Initial Ivy Bridge support

Initial Ivy Bridge support

[Jesse Barnes]

This set of patches enables basic Ivy Bridge support, and has been
tested with early hardware.  VGA is known to work, but other outputs are
likely to work as well given that IVB uses CougarPoint or compatible PCH
chips, which contain most of the display logic.

Page flipping was buggy when last tested, it seems we're missing flip
complete interrupts.  I'll fix that up once I get some new hardware (as
it could have been a hw issue with early boards).

Thanks,
Jesse

[PATCH 01/16] drm/i915: make FDI training a display function

[Jesse Barnes]

Rather than branching in ironlake_pch_enable, add a new train_fdi
function to the display function pointer struct and use it instead.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_drv.h      |    2 +-
 drivers/gpu/drm/i915/intel_display.c |    7 +++----
 2 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0296967..c10d7e9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -209,7 +209,7 @@ struct drm_i915_display_funcs {
 			     struct drm_display_mode *adjusted_mode,
 			     int x, int y,
 			     struct drm_framebuffer *old_fb);
-
+	void (*train_fdi)(struct drm_crtc *crtc);
 	/* clock updates for mode set */
 	/* cursor updates */
 	/* render clock increase/decrease */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 62f9e52..6455e0e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2465,10 +2465,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
 	u32 reg, temp;
 
 	/* For PCH output, training FDI link */
-	if (IS_GEN6(dev))
-		gen6_fdi_link_train(crtc);
-	else
-		ironlake_fdi_link_train(crtc);
+	dev_priv->display.train_fdi(crtc);
 
 	intel_enable_pch_pll(dev_priv, pipe);
 
@@ -7290,6 +7287,7 @@ static void intel_init_display(struct drm_device *dev)
 					      "Disable CxSR\n");
 				dev_priv->display.update_wm = NULL;
 			}
+			dev_priv->display.train_fdi = ironlake_fdi_link_train;
 		} else if (IS_GEN6(dev)) {
 			if (SNB_READ_WM0_LATENCY()) {
 				dev_priv->display.update_wm = sandybridge_update_wm;
@@ -7298,6 +7296,7 @@ static void intel_init_display(struct drm_device *dev)
 					      "Disable CxSR\n");
 				dev_priv->display.update_wm = NULL;
 			}
+			dev_priv->display.train_fdi = gen6_fdi_link_train;
 		} else
 			dev_priv->display.update_wm = NULL;
 	} else if (IS_PINEVIEW(dev)) {
-- 
1.7.4.1

[PATCH 02/16] drm/i915: split irq handling into per-chipset functions

[Jesse Barnes]

Set the IRQ handling functions in driver load so they'll just be used
directly, rather than branching over most of the code in the chipset
functions.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_dma.c |   12 ++++++++++
 drivers/gpu/drm/i915/i915_drv.h |    6 +++++
 drivers/gpu/drm/i915/i915_irq.c |   45 +++++++++++++++++++++-----------------
 3 files changed, 43 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 3b69f38..2f653c2 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1253,6 +1253,18 @@ static int i915_load_modeset_init(struct drm_device *dev)
 
 	intel_modeset_init(dev);
 
+	if (HAS_PCH_SPLIT(dev)) {
+		dev->driver->irq_handler = ironlake_irq_handler;
+		dev->driver->irq_preinstall = ironlake_irq_preinstall;
+		dev->driver->irq_postinstall = ironlake_irq_postinstall;
+		dev->driver->irq_uninstall = ironlake_irq_uninstall;
+	} else {
+		dev->driver->irq_preinstall = i915_driver_irq_preinstall;
+		dev->driver->irq_postinstall = i915_driver_irq_postinstall;
+		dev->driver->irq_uninstall = i915_driver_irq_uninstall;
+		dev->driver->irq_handler = i915_driver_irq_handler;
+	}
+
 	ret = drm_irq_install(dev);
 	if (ret)
 		goto cleanup_vga_switcheroo;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c10d7e9..44d24fb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1024,6 +1024,12 @@ extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
 extern void i915_driver_irq_preinstall(struct drm_device * dev);
 extern int i915_driver_irq_postinstall(struct drm_device *dev);
 extern void i915_driver_irq_uninstall(struct drm_device * dev);
+
+extern irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS);
+extern void ironlake_irq_preinstall(struct drm_device *dev);
+extern int ironlake_irq_postinstall(struct drm_device *dev);
+extern void ironlake_irq_uninstall(struct drm_device *dev);
+
 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
 				struct drm_file *file_priv);
 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 5c0466e..a58d477 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -448,8 +448,9 @@ static void pch_irq_handler(struct drm_device *dev)
 		DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
 }
 
-static irqreturn_t ironlake_irq_handler(struct drm_device *dev)
+irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
 {
+	struct drm_device *dev = (struct drm_device *) arg;
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	int ret = IRQ_NONE;
 	u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
@@ -457,6 +458,8 @@ static irqreturn_t ironlake_irq_handler(struct drm_device *dev)
 	struct drm_i915_master_private *master_priv;
 	u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT;
 
+	atomic_inc(&dev_priv->irq_received);
+
 	if (IS_GEN6(dev))
 		bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT;
 
@@ -1103,9 +1106,6 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 
 	atomic_inc(&dev_priv->irq_received);
 
-	if (HAS_PCH_SPLIT(dev))
-		return ironlake_irq_handler(dev);
-
 	iir = I915_READ(IIR);
 
 	if (INTEL_INFO(dev)->gen >= 4)
@@ -1562,10 +1562,15 @@ repeat:
 
 /* drm_dma.h hooks
 */
-static void ironlake_irq_preinstall(struct drm_device *dev)
+void ironlake_irq_preinstall(struct drm_device *dev)
 {
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 
+	atomic_set(&dev_priv->irq_received, 0);
+
+	INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
+	INIT_WORK(&dev_priv->error_work, i915_error_work_func);
+
 	I915_WRITE(HWSTAM, 0xeffe);
 
 	/* XXX hotplug from PCH */
@@ -1585,7 +1590,7 @@ static void ironlake_irq_preinstall(struct drm_device *dev)
 	POSTING_READ(SDEIER);
 }
 
-static int ironlake_irq_postinstall(struct drm_device *dev)
+int ironlake_irq_postinstall(struct drm_device *dev)
 {
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	/* enable kind of interrupts always enabled */
@@ -1594,6 +1599,13 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
 	u32 render_irqs;
 	u32 hotplug_mask;
 
+	DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
+	if (HAS_BSD(dev))
+		DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
+	if (HAS_BLT(dev))
+		DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
+
+	dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 	dev_priv->irq_mask = ~display_mask;
 
 	/* should always can generate irq */
@@ -1660,11 +1672,6 @@ void i915_driver_irq_preinstall(struct drm_device * dev)
 	INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
 	INIT_WORK(&dev_priv->error_work, i915_error_work_func);
 
-	if (HAS_PCH_SPLIT(dev)) {
-		ironlake_irq_preinstall(dev);
-		return;
-	}
-
 	if (I915_HAS_HOTPLUG(dev)) {
 		I915_WRITE(PORT_HOTPLUG_EN, 0);
 		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
@@ -1696,9 +1703,6 @@ int i915_driver_irq_postinstall(struct drm_device *dev)
 
 	dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 
-	if (HAS_PCH_SPLIT(dev))
-		return ironlake_irq_postinstall(dev);
-
 	/* Unmask the interrupts that we always want on. */
 	dev_priv->irq_mask = ~I915_INTERRUPT_ENABLE_FIX;
 
@@ -1767,9 +1771,15 @@ int i915_driver_irq_postinstall(struct drm_device *dev)
 	return 0;
 }
 
-static void ironlake_irq_uninstall(struct drm_device *dev)
+void ironlake_irq_uninstall(struct drm_device *dev)
 {
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+
+	if (!dev_priv)
+		return;
+
+	dev_priv->vblank_pipe = 0;
+
 	I915_WRITE(HWSTAM, 0xffffffff);
 
 	I915_WRITE(DEIMR, 0xffffffff);
@@ -1791,11 +1801,6 @@ void i915_driver_irq_uninstall(struct drm_device * dev)
 
 	dev_priv->vblank_pipe = 0;
 
-	if (HAS_PCH_SPLIT(dev)) {
-		ironlake_irq_uninstall(dev);
-		return;
-	}
-
 	if (I915_HAS_HOTPLUG(dev)) {
 		I915_WRITE(PORT_HOTPLUG_EN, 0);
 		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
-- 
1.7.4.1

[PATCH 03/16] drm/i915: split enable/disable vblank code into chipset specific functions

[Jesse Barnes]

This makes the Ironlake+ code trivial and generally simplifies things.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_dma.c |    4 +++
 drivers/gpu/drm/i915/i915_drv.h |    2 +
 drivers/gpu/drm/i915/i915_irq.c |   42 ++++++++++++++++++++++++++++----------
 3 files changed, 37 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 2f653c2..d124f0e 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1258,11 +1258,15 @@ static int i915_load_modeset_init(struct drm_device *dev)
 		dev->driver->irq_preinstall = ironlake_irq_preinstall;
 		dev->driver->irq_postinstall = ironlake_irq_postinstall;
 		dev->driver->irq_uninstall = ironlake_irq_uninstall;
+		dev->driver->enable_vblank = ironlake_enable_vblank;
+		dev->driver->disable_vblank = ironlake_disable_vblank;
 	} else {
 		dev->driver->irq_preinstall = i915_driver_irq_preinstall;
 		dev->driver->irq_postinstall = i915_driver_irq_postinstall;
 		dev->driver->irq_uninstall = i915_driver_irq_uninstall;
 		dev->driver->irq_handler = i915_driver_irq_handler;
+		dev->driver->enable_vblank = i915_enable_vblank;
+		dev->driver->disable_vblank = i915_disable_vblank;
 	}
 
 	ret = drm_irq_install(dev);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 44d24fb..2a41118 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1036,6 +1036,8 @@ extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 				struct drm_file *file_priv);
 extern int i915_enable_vblank(struct drm_device *dev, int crtc);
 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
+extern int ironlake_enable_vblank(struct drm_device *dev, int crtc);
+extern void ironlake_disable_vblank(struct drm_device *dev, int crtc);
 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
 extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
 extern int i915_vblank_swap(struct drm_device *dev, void *data,
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index a58d477..d5dcb8f 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1344,10 +1344,7 @@ int i915_enable_vblank(struct drm_device *dev, int pipe)
 		return -EINVAL;
 
 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
-	if (HAS_PCH_SPLIT(dev))
-		ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
-					    DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
-	else if (INTEL_INFO(dev)->gen >= 4)
+	if (INTEL_INFO(dev)->gen >= 4)
 		i915_enable_pipestat(dev_priv, pipe,
 				     PIPE_START_VBLANK_INTERRUPT_ENABLE);
 	else
@@ -1362,6 +1359,22 @@ int i915_enable_vblank(struct drm_device *dev, int pipe)
 	return 0;
 }
 
+int ironlake_enable_vblank(struct drm_device *dev, int pipe)
+{
+	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+	unsigned long irqflags;
+
+	if (!i915_pipe_enabled(dev, pipe))
+		return -EINVAL;
+
+	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+	ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
+				    DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
+	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+
+	return 0;
+}
+
 /* Called from drm generic code, passed 'crtc' which
  * we use as a pipe index
  */
@@ -1375,13 +1388,20 @@ void i915_disable_vblank(struct drm_device *dev, int pipe)
 		I915_WRITE(INSTPM,
 			   INSTPM_AGPBUSY_DIS << 16 | INSTPM_AGPBUSY_DIS);
 
-	if (HAS_PCH_SPLIT(dev))
-		ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
-					     DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
-	else
-		i915_disable_pipestat(dev_priv, pipe,
-				      PIPE_VBLANK_INTERRUPT_ENABLE |
-				      PIPE_START_VBLANK_INTERRUPT_ENABLE);
+	i915_disable_pipestat(dev_priv, pipe,
+			      PIPE_VBLANK_INTERRUPT_ENABLE |
+			      PIPE_START_VBLANK_INTERRUPT_ENABLE);
+	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+}
+
+void ironlake_disable_vblank(struct drm_device *dev, int pipe)
+{
+	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+	unsigned long irqflags;
+
+	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+	ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
+				     DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 }
 
-- 
1.7.4.1

[PATCH 04/16] drm/i915: add Ivy Bridge PCI IDs and flags

[Jesse Barnes]

Check for IVB desktop, mobile and other SKUs and set flags
appropriately.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_drv.c |   19 +++++++++++++++++++
 drivers/gpu/drm/i915/i915_drv.h |    2 ++
 2 files changed, 21 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5d0d28c..016290e 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -188,6 +188,20 @@ static const struct intel_device_info intel_sandybridge_m_info = {
 	.has_blt_ring = 1,
 };
 
+static const struct intel_device_info intel_ivybridge_d_info = {
+	.is_ivybridge = 1, .gen = 7,
+	.need_gfx_hws = 1, .has_hotplug = 1,
+	.has_bsd_ring = 1,
+	.has_blt_ring = 1,
+};
+
+static const struct intel_device_info intel_ivybridge_m_info = {
+	.is_ivybridge = 1, .gen = 7, .is_mobile = 1,
+	.need_gfx_hws = 1, .has_hotplug = 1,
+	.has_bsd_ring = 1,
+	.has_blt_ring = 1,
+};
+
 static const struct pci_device_id pciidlist[] = {		/* aka */
 	INTEL_VGA_DEVICE(0x3577, &intel_i830_info),		/* I830_M */
 	INTEL_VGA_DEVICE(0x2562, &intel_845g_info),		/* 845_G */
@@ -227,6 +241,11 @@ static const struct pci_device_id pciidlist[] = {		/* aka */
 	INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
 	INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
 	INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
+	INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
+	INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
+	INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
+	INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
+	INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
 	{0, 0, 0}
 };
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2a41118..0b5e263 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -230,6 +230,7 @@ struct intel_device_info {
 	u8 is_pineview : 1;
 	u8 is_broadwater : 1;
 	u8 is_crestline : 1;
+	u8 is_ivybridge : 1;
 	u8 has_fbc : 1;
 	u8 has_pipe_cxsr : 1;
 	u8 has_hotplug : 1;
@@ -929,6 +930,7 @@ enum intel_chip_family {
 #define IS_G33(dev)		(INTEL_INFO(dev)->is_g33)
 #define IS_IRONLAKE_D(dev)	((dev)->pci_device == 0x0042)
 #define IS_IRONLAKE_M(dev)	((dev)->pci_device == 0x0046)
+#define IS_IVYBRIDGE(dev)	(INTEL_INFO(dev)->is_ivybridge)
 #define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)
 
 #define IS_GEN2(dev)	(INTEL_INFO(dev)->gen == 2)
-- 
1.7.4.1

[PATCH 05/16] drm/i915: add IS_GEN7 macro to cover Ivy Bridge and later

[Jesse Barnes]

Note: IS_GEN* are for render related checks.  Display and other checks
should use IS_MOBILE, IS_$CHIPSET or test for specific features.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_drv.h |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0b5e263..9fbb6fe 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -938,6 +938,7 @@ enum intel_chip_family {
 #define IS_GEN4(dev)	(INTEL_INFO(dev)->gen == 4)
 #define IS_GEN5(dev)	(INTEL_INFO(dev)->gen == 5)
 #define IS_GEN6(dev)	(INTEL_INFO(dev)->gen == 6)
+#define IS_GEN7(dev)	(INTEL_INFO(dev)->gen == 7)
 
 #define HAS_BSD(dev)            (INTEL_INFO(dev)->has_bsd_ring)
 #define HAS_BLT(dev)            (INTEL_INFO(dev)->has_blt_ring)
-- 
1.7.4.1

[PATCH 06/16] agp/intel: add Ivy Bridge support

[Jesse Barnes]

Just use the Sandy Bridge routines.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/char/agp/intel-agp.c |    3 +++
 drivers/char/agp/intel-agp.h |    8 ++++++++
 drivers/char/agp/intel-gtt.c |   10 ++++++++++
 3 files changed, 21 insertions(+), 0 deletions(-)

diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
index b0a0dcc..b427711 100644
--- a/drivers/char/agp/intel-agp.c
+++ b/drivers/char/agp/intel-agp.c
@@ -903,6 +903,9 @@ static struct pci_device_id agp_intel_pci_table[] = {
 	ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB),
 	ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB),
 	ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB),
+	ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_HB),
+	ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_HB),
+	ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_HB),
 	{ }
 };
 
diff --git a/drivers/char/agp/intel-agp.h b/drivers/char/agp/intel-agp.h
index 5feebe2..999803c 100644
--- a/drivers/char/agp/intel-agp.h
+++ b/drivers/char/agp/intel-agp.h
@@ -225,6 +225,14 @@
 #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG	0x0126
 #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB		0x0108  /* Server */
 #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG		0x010A
+#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_HB		0x0150  /* Desktop */
+#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT1_IG		0x0152
+#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT2_IG		0x0162
+#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_HB		0x0154  /* Mobile */
+#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT1_IG		0x0156
+#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG		0x0166
+#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_HB		0x0158  /* Server */
+#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG		0x015A
 
 int intel_gmch_probe(struct pci_dev *pdev,
 			       struct agp_bridge_data *bridge);
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 0d09b53..8515101 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -1420,6 +1420,16 @@ static const struct intel_gtt_driver_description {
 	    "Sandybridge", &sandybridge_gtt_driver },
 	{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG,
 	    "Sandybridge", &sandybridge_gtt_driver },
+	{ PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT1_IG,
+	    "Ivybridge", &sandybridge_gtt_driver },
+	{ PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT2_IG,
+	    "Ivybridge", &sandybridge_gtt_driver },
+	{ PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT1_IG,
+	    "Ivybridge", &sandybridge_gtt_driver },
+	{ PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG,
+	    "Ivybridge", &sandybridge_gtt_driver },
+	{ PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG,
+	    "Ivybridge", &sandybridge_gtt_driver },
 	{ 0, NULL, NULL }
 };
 
-- 
1.7.4.1

[PATCH 07/16] drm/i915: add PantherPoint PCH ID

[Jesse Barnes]

We can treat PantherPoint as CougarPoint as far as display goes.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_drv.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 016290e..53f4f14 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -255,6 +255,7 @@ MODULE_DEVICE_TABLE(pci, pciidlist);
 
 #define INTEL_PCH_DEVICE_ID_MASK	0xff00
 #define INTEL_PCH_CPT_DEVICE_ID_TYPE	0x1c00
+#define INTEL_PCH_PPT_DEVICE_ID_TYPE	0x1e00
 
 void intel_detect_pch (struct drm_device *dev)
 {
@@ -276,6 +277,9 @@ void intel_detect_pch (struct drm_device *dev)
 			if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 				dev_priv->pch_type = PCH_CPT;
 				DRM_DEBUG_KMS("Found CougarPoint PCH\n");
+			} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
+				dev_priv->pch_type = PCH_CPT;
+				DRM_ERROR("Found PatherPoint PCH\n");
 			}
 		}
 		pci_dev_put(pch);
-- 
1.7.4.1

[PATCH 08/16] drm/i915: Ivy Bridge has split display and pipe control

[Jesse Barnes]

Ivy Bridge has a similar split display controller to Sandy Bridge, so
use HAS_PCH_SPLIT.  And gen7 also has the pipe control instruction, so
use HAS_PIPE_CONTROL as well.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_drv.h |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9fbb6fe..e596c10 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -965,8 +965,8 @@ enum intel_chip_family {
 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
 
-#define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev))
-#define HAS_PIPE_CONTROL(dev) (IS_GEN5(dev) || IS_GEN6(dev))
+#define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev))
+#define HAS_PIPE_CONTROL(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_GEN7(dev))
 
 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
-- 
1.7.4.1

[PATCH 09/16] drm/i915: add swizzle/tiling support for Ivy Bridge

[Jesse Barnes]

Treat it like Ironlake and Sandy Bridge.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_gem_tiling.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index dfb682b..418015f 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -92,7 +92,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
 	uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
 	uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
 
-	if (IS_GEN5(dev) || IS_GEN6(dev)) {
+	if (IS_GEN5(dev) || IS_GEN6(dev) || IS_GEN7(dev)) {
 		/* On Ironlake whatever DRAM config, GPU always do
 		 * same swizzling setup.
 		 */
-- 
1.7.4.1

[PATCH 10/16] drm/i915: automatic FDI training support for Ivy Bridge

[Jesse Barnes]

Ivy Bridge supports auto-training on the CPU side, so add a separate
training function to handle it.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_reg.h      |    2 +
 drivers/gpu/drm/i915/intel_display.c |   81 +++++++++++++++++++++++++++++++--
 2 files changed, 78 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8848411..b77bd49 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3108,6 +3108,8 @@
 /* both Tx and Rx */
 #define  FDI_SCRAMBLING_ENABLE          (0<<7)
 #define  FDI_SCRAMBLING_DISABLE         (1<<7)
+/* Ivybridge */
+#define  FDI_AUTO_TRAIN_DONE		(1<<1)
 
 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
 #define _FDI_RXA_CTL             0xf000c
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6455e0e..db46e4f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2292,7 +2292,76 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
 	DRM_DEBUG_KMS("FDI train done.\n");
 }
 
-static void ironlake_fdi_enable(struct drm_crtc *crtc)
+/* On Ivybridge we can use auto training */
+static void ivb_fdi_link_train(struct drm_crtc *crtc)
+{
+	struct drm_device *dev = crtc->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	unsigned long start = jiffies_to_msecs(jiffies);
+	int pipe = intel_crtc->pipe;
+	u32 reg, temp, i, j;
+
+	/* Can't pair IVB & Ibex Peak */
+	BUG_ON(HAS_PCH_IBX(dev));
+
+	reg = FDI_TX_CTL(pipe);
+	temp = I915_READ(reg);
+	temp &= ~(7 << 19);
+	temp |= (intel_crtc->fdi_lanes - 1) << 19;
+	temp &= ~FDI_LINK_TRAIN_NONE;
+	I915_WRITE(reg, temp);
+
+	/* Enable auto training on TX and RX */
+	for (i = 0; i < ARRAY_SIZE(snb_b_fdi_train_param); i++) {
+		/* Try each vswing/pre-emphasis pair twice */
+		for (j = 0; j < 2; j++) {
+			reg = FDI_TX_CTL(pipe);
+			temp = I915_READ(reg);
+			temp |= FDI_AUTO_TRAINING;
+			temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
+			temp |= snb_b_fdi_train_param[i];
+			I915_WRITE(reg, temp | FDI_TX_ENABLE);
+
+			reg = FDI_RX_CTL(pipe);
+			temp = I915_READ(reg);
+			I915_WRITE(reg, temp | FDI_RX_ENABLE);
+			POSTING_READ(reg);
+
+			udelay(5);
+
+			reg = FDI_TX_CTL(pipe);
+			temp = I915_READ(reg);
+			if ((temp & FDI_AUTO_TRAIN_DONE) ||
+			    (I915_READ(reg) & FDI_AUTO_TRAIN_DONE)) {
+				DRM_DEBUG_KMS("FDI auto train complete in %d ms\n",
+					      jiffies_to_msecs(jiffies) - start);
+				goto done;
+			}
+
+			reg = FDI_TX_CTL(pipe);
+			temp = I915_READ(reg);
+			I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
+
+			reg = FDI_RX_CTL(pipe);
+			temp = I915_READ(reg);
+			I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
+			POSTING_READ(reg);
+			udelay(31); /* wait idle time before retrying */
+		}
+	}
+	DRM_ERROR("FDI auto train failed\n");
+	return;
+
+done:
+	reg = FDI_RX_CTL(pipe);
+	temp = I915_READ(reg);
+	temp |= FDI_FS_ERR_CORRECT_ENABLE | FDI_FE_ERR_CORRECT_ENABLE;
+	I915_WRITE(reg, temp);
+	POSTING_READ(reg);
+}
+
+static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -2333,7 +2402,7 @@ static void ironlake_fdi_enable(struct drm_crtc *crtc)
 	}
 }
 
-static void ironlake_fdi_disable(struct drm_crtc *crtc)
+static void ironlake_fdi_pll_disable(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -2555,9 +2624,9 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
 	is_pch_port = intel_crtc_driving_pch(crtc);
 
 	if (is_pch_port)
-		ironlake_fdi_enable(crtc);
+		ironlake_fdi_pll_enable(crtc);
 	else
-		ironlake_fdi_disable(crtc);
+		ironlake_fdi_pll_disable(crtc);
 
 	/* Enable panel fitting for LVDS */
 	if (dev_priv->pch_pf_size &&
@@ -2610,7 +2679,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
 	I915_WRITE(PF_CTL(pipe), 0);
 	I915_WRITE(PF_WIN_SZ(pipe), 0);
 
-	ironlake_fdi_disable(crtc);
+	ironlake_fdi_pll_disable(crtc);
 
 	/* This is a horrible layering violation; we should be doing this in
 	 * the connector/encoder ->prepare instead, but we don't always have
@@ -7297,6 +7366,8 @@ static void intel_init_display(struct drm_device *dev)
 				dev_priv->display.update_wm = NULL;
 			}
 			dev_priv->display.train_fdi = gen6_fdi_link_train;
+		} else if (IS_IVYBRIDGE(dev)) {
+			dev_priv->display.train_fdi = ivb_fdi_link_train;
 		} else
 			dev_priv->display.update_wm = NULL;
 	} else if (IS_PINEVIEW(dev)) {
-- 
1.7.4.1

[PATCH 11/16] drm/i915: manual FDI training for Ivy Bridge

[Jesse Barnes]

A0 stepping chips need to use manual training, but the bits have all
moved.  So fix things up so we can at least train FDI for VGA links.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_reg.h      |   10 +++
 drivers/gpu/drm/i915/intel_display.c |  129 +++++++++++++++++++++++++++++++++-
 2 files changed, 136 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b77bd49..03c99ed 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3105,7 +3105,15 @@
 #define  FDI_TX_ENHANCE_FRAME_ENABLE    (1<<18)
 /* Ironlake: hardwired to 1 */
 #define  FDI_TX_PLL_ENABLE              (1<<14)
+
+/* Ivybridge has different bits for lolz */
+#define  FDI_LINK_TRAIN_PATTERN_1_IVB       (0<<8)
+#define  FDI_LINK_TRAIN_PATTERN_2_IVB       (1<<8)
+#define  FDI_LINK_TRAIN_PATTERN_IDLE_IVB    (2<<8)
+#define  FDI_LINK_TRAIN_NONE_IVB            (3<<8)
+
 /* both Tx and Rx */
+#define  FDI_LINK_TRAIN_AUTO		(1<<10)
 #define  FDI_SCRAMBLING_ENABLE          (0<<7)
 #define  FDI_SCRAMBLING_DISABLE         (1<<7)
 /* Ivybridge */
@@ -3117,6 +3125,8 @@
 #define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
 #define  FDI_RX_ENABLE          (1<<31)
 /* train, dp width same as FDI_TX */
+#define  FDI_FS_ERRC_ENABLE		(1<<27)
+#define  FDI_FE_ERRC_ENABLE		(1<<26)
 #define  FDI_DP_PORT_WIDTH_X8           (7<<19)
 #define  FDI_8BPC                       (0<<16)
 #define  FDI_10BPC                      (1<<16)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index db46e4f..866abe5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2047,8 +2047,13 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
 	/* enable normal train */
 	reg = FDI_TX_CTL(pipe);
 	temp = I915_READ(reg);
-	temp &= ~FDI_LINK_TRAIN_NONE;
-	temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
+	if (IS_GEN6(dev)) {
+		temp &= ~FDI_LINK_TRAIN_NONE;
+		temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
+	} else if (IS_IVYBRIDGE(dev)) {
+		temp &= ~FDI_LINK_TRAIN_NONE_IVB;
+		temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
+	}
 	I915_WRITE(reg, temp);
 
 	reg = FDI_RX_CTL(pipe);
@@ -2065,6 +2070,11 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
 	/* wait one idle pattern time */
 	POSTING_READ(reg);
 	udelay(1000);
+
+	/* IVB wants error correction enabled */
+	if (IS_IVYBRIDGE(dev))
+		I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
+			   FDI_FE_ERRC_ENABLE);
 }
 
 /* The FDI link training functions for ILK/Ibexpeak. */
@@ -2292,6 +2302,115 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
 	DRM_DEBUG_KMS("FDI train done.\n");
 }
 
+/* Manual link training for Ivy Bridge A0 parts */
+static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
+{
+	struct drm_device *dev = crtc->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	int pipe = intel_crtc->pipe;
+	u32 reg, temp, i;
+
+	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
+	   for train result */
+	reg = FDI_RX_IMR(pipe);
+	temp = I915_READ(reg);
+	temp &= ~FDI_RX_SYMBOL_LOCK;
+	temp &= ~FDI_RX_BIT_LOCK;
+	I915_WRITE(reg, temp);
+
+	POSTING_READ(reg);
+	udelay(150);
+
+	/* enable CPU FDI TX and PCH FDI RX */
+	reg = FDI_TX_CTL(pipe);
+	temp = I915_READ(reg);
+	temp &= ~(7 << 19);
+	temp |= (intel_crtc->fdi_lanes - 1) << 19;
+	temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
+	temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
+	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
+	temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
+	I915_WRITE(reg, temp | FDI_TX_ENABLE);
+
+	reg = FDI_RX_CTL(pipe);
+	temp = I915_READ(reg);
+	temp &= ~FDI_LINK_TRAIN_AUTO;
+	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
+	temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
+	I915_WRITE(reg, temp | FDI_RX_ENABLE);
+
+	POSTING_READ(reg);
+	udelay(150);
+
+	for (i = 0; i < 4; i++ ) {
+		reg = FDI_TX_CTL(pipe);
+		temp = I915_READ(reg);
+		temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
+		temp |= snb_b_fdi_train_param[i];
+		I915_WRITE(reg, temp);
+
+		POSTING_READ(reg);
+		udelay(500);
+
+		reg = FDI_RX_IIR(pipe);
+		temp = I915_READ(reg);
+		DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
+
+		if (temp & FDI_RX_BIT_LOCK ||
+		    (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
+			I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
+			DRM_DEBUG_KMS("FDI train 1 done.\n");
+			break;
+		}
+	}
+	if (i == 4)
+		DRM_ERROR("FDI train 1 fail!\n");
+
+	/* Train 2 */
+	reg = FDI_TX_CTL(pipe);
+	temp = I915_READ(reg);
+	temp &= ~FDI_LINK_TRAIN_NONE_IVB;
+	temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
+	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
+	temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
+	I915_WRITE(reg, temp);
+
+	reg = FDI_RX_CTL(pipe);
+	temp = I915_READ(reg);
+	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
+	temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
+	I915_WRITE(reg, temp);
+
+	POSTING_READ(reg);
+	udelay(150);
+
+	for (i = 0; i < 4; i++ ) {
+		reg = FDI_TX_CTL(pipe);
+		temp = I915_READ(reg);
+		temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
+		temp |= snb_b_fdi_train_param[i];
+		I915_WRITE(reg, temp);
+
+		POSTING_READ(reg);
+		udelay(500);
+
+		reg = FDI_RX_IIR(pipe);
+		temp = I915_READ(reg);
+		DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
+
+		if (temp & FDI_RX_SYMBOL_LOCK) {
+			I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
+			DRM_DEBUG_KMS("FDI train 2 done.\n");
+			break;
+		}
+	}
+	if (i == 4)
+		DRM_ERROR("FDI train 2 fail!\n");
+
+	DRM_DEBUG_KMS("FDI train done.\n");
+}
+
 /* On Ivybridge we can use auto training */
 static void ivb_fdi_link_train(struct drm_crtc *crtc)
 {
@@ -7367,7 +7486,11 @@ static void intel_init_display(struct drm_device *dev)
 			}
 			dev_priv->display.train_fdi = gen6_fdi_link_train;
 		} else if (IS_IVYBRIDGE(dev)) {
-			dev_priv->display.train_fdi = ivb_fdi_link_train;
+			/* FIXME: detect B0+ stepping and use auto training */
+			if (0)
+				dev_priv->display.train_fdi = ivb_fdi_link_train;
+			else
+				dev_priv->display.train_fdi = ivb_manual_fdi_link_train;
 		} else
 			dev_priv->display.update_wm = NULL;
 	} else if (IS_PINEVIEW(dev)) {
-- 
1.7.4.1

[PATCH 12/16] drm/i915: treat Ivy Bridge watermarks like Sandy Bridge

[Jesse Barnes]

Not fully tested.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_display.c |    9 ++++++++-
 1 files changed, 8 insertions(+), 1 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 866abe5..908c4d9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7229,7 +7229,7 @@ void intel_enable_clock_gating(struct drm_device *dev)
 				   _3D_CHICKEN2_WM_READ_PIPELINED);
 		}
 
-		if (IS_GEN6(dev)) {
+		if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
 			I915_WRITE(WM3_LP_ILK, 0);
 			I915_WRITE(WM2_LP_ILK, 0);
 			I915_WRITE(WM1_LP_ILK, 0);
@@ -7491,6 +7491,13 @@ static void intel_init_display(struct drm_device *dev)
 				dev_priv->display.train_fdi = ivb_fdi_link_train;
 			else
 				dev_priv->display.train_fdi = ivb_manual_fdi_link_train;
+			if (SNB_READ_WM0_LATENCY()) {
+				dev_priv->display.update_wm = sandybridge_update_wm;
+			} else {
+				DRM_DEBUG_KMS("Failed to read display plane latency. "
+					      "Disable CxSR\n");
+				dev_priv->display.update_wm = NULL;
+			}
 		} else
 			dev_priv->display.update_wm = NULL;
 	} else if (IS_PINEVIEW(dev)) {
-- 
1.7.4.1

[PATCH 13/16] drm/i915: interrupt & vblank support for Ivy Bridge

[Jesse Barnes]

Add new interrupt handling functions for Ivy Bridge.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_dma.c |   12 +++-
 drivers/gpu/drm/i915/i915_drv.h |    7 ++
 drivers/gpu/drm/i915/i915_irq.c |  156 +++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h |   13 +++
 4 files changed, 186 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index d124f0e..8e27bc4 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1253,7 +1253,15 @@ static int i915_load_modeset_init(struct drm_device *dev)
 
 	intel_modeset_init(dev);
 
-	if (HAS_PCH_SPLIT(dev)) {
+	if (IS_IVYBRIDGE(dev)) {
+		/* Share pre & uninstall handlers with ILK/SNB */
+		dev->driver->irq_handler = ivybridge_irq_handler;
+		dev->driver->irq_preinstall = ironlake_irq_preinstall;
+		dev->driver->irq_postinstall = ivybridge_irq_postinstall;
+		dev->driver->irq_uninstall = ironlake_irq_uninstall;
+		dev->driver->enable_vblank = ivybridge_enable_vblank;
+		dev->driver->disable_vblank = ivybridge_disable_vblank;
+	} else if (HAS_PCH_SPLIT(dev)) {
 		dev->driver->irq_handler = ironlake_irq_handler;
 		dev->driver->irq_preinstall = ironlake_irq_preinstall;
 		dev->driver->irq_postinstall = ironlake_irq_postinstall;
@@ -1998,7 +2006,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 
 	dev->driver->get_vblank_counter = i915_get_vblank_counter;
 	dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
-	if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev)) {
+	if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
 		dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
 		dev->driver->get_vblank_counter = gm45_get_vblank_counter;
 	}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e596c10..7be7893 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1033,6 +1033,11 @@ extern void ironlake_irq_preinstall(struct drm_device *dev);
 extern int ironlake_irq_postinstall(struct drm_device *dev);
 extern void ironlake_irq_uninstall(struct drm_device *dev);
 
+extern irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS);
+extern void ivybridge_irq_preinstall(struct drm_device *dev);
+extern int ivybridge_irq_postinstall(struct drm_device *dev);
+extern void ivybridge_irq_uninstall(struct drm_device *dev);
+
 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
 				struct drm_file *file_priv);
 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
@@ -1041,6 +1046,8 @@ extern int i915_enable_vblank(struct drm_device *dev, int crtc);
 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
 extern int ironlake_enable_vblank(struct drm_device *dev, int crtc);
 extern void ironlake_disable_vblank(struct drm_device *dev, int crtc);
+extern int ivybridge_enable_vblank(struct drm_device *dev, int crtc);
+extern void ivybridge_disable_vblank(struct drm_device *dev, int crtc);
 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
 extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
 extern int i915_vblank_swap(struct drm_device *dev, void *data,
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d5dcb8f..a025002 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -448,6 +448,85 @@ static void pch_irq_handler(struct drm_device *dev)
 		DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
 }
 
+irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
+{
+	struct drm_device *dev = (struct drm_device *) arg;
+	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+	int ret = IRQ_NONE;
+	u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
+	struct drm_i915_master_private *master_priv;
+
+	atomic_inc(&dev_priv->irq_received);
+
+	/* disable master interrupt before clearing iir  */
+	de_ier = I915_READ(DEIER);
+	I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
+	POSTING_READ(DEIER);
+
+	de_iir = I915_READ(DEIIR);
+	gt_iir = I915_READ(GTIIR);
+	pch_iir = I915_READ(SDEIIR);
+	pm_iir = I915_READ(GEN6_PMIIR);
+
+	if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && pm_iir == 0)
+		goto done;
+
+	ret = IRQ_HANDLED;
+
+	if (dev->primary->master) {
+		master_priv = dev->primary->master->driver_priv;
+		if (master_priv->sarea_priv)
+			master_priv->sarea_priv->last_dispatch =
+				READ_BREADCRUMB(dev_priv);
+	}
+
+	if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
+		notify_ring(dev, &dev_priv->ring[RCS]);
+	if (gt_iir & GT_GEN6_BSD_USER_INTERRUPT)
+		notify_ring(dev, &dev_priv->ring[VCS]);
+	if (gt_iir & GT_BLT_USER_INTERRUPT)
+		notify_ring(dev, &dev_priv->ring[BCS]);
+
+	if (de_iir & DE_GSE_IVB)
+		intel_opregion_gse_intr(dev);
+
+	if (de_iir & DE_PLANEA_FLIP_DONE_IVB) {
+		intel_prepare_page_flip(dev, 0);
+		intel_finish_page_flip_plane(dev, 0);
+	}
+
+	if (de_iir & DE_PLANEB_FLIP_DONE_IVB) {
+		intel_prepare_page_flip(dev, 1);
+		intel_finish_page_flip_plane(dev, 1);
+	}
+
+	if (de_iir & DE_PIPEA_VBLANK_IVB)
+		drm_handle_vblank(dev, 0);
+
+	if (de_iir & DE_PIPEB_VBLANK_IVB);
+		drm_handle_vblank(dev, 1);
+
+	/* check event from PCH */
+	if (de_iir & DE_PCH_EVENT_IVB) {
+		if (pch_iir & SDE_HOTPLUG_MASK_CPT)
+			queue_work(dev_priv->wq, &dev_priv->hotplug_work);
+		pch_irq_handler(dev);
+	}
+
+	gen6_pm_irq_handler(dev);
+
+	/* should clear PCH hotplug event before clear CPU irq */
+	I915_WRITE(SDEIIR, pch_iir);
+	I915_WRITE(GTIIR, gt_iir);
+	I915_WRITE(DEIIR, de_iir);
+
+done:
+	I915_WRITE(DEIER, de_ier);
+	POSTING_READ(DEIER);
+
+	return ret;
+}
+
 irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
 {
 	struct drm_device *dev = (struct drm_device *) arg;
@@ -1375,6 +1454,22 @@ int ironlake_enable_vblank(struct drm_device *dev, int pipe)
 	return 0;
 }
 
+int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
+{
+	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+	unsigned long irqflags;
+
+	if (!i915_pipe_enabled(dev, pipe))
+		return -EINVAL;
+
+	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+	ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
+				    DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
+	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+
+	return 0;
+}
+
 /* Called from drm generic code, passed 'crtc' which
  * we use as a pipe index
  */
@@ -1405,6 +1500,17 @@ void ironlake_disable_vblank(struct drm_device *dev, int pipe)
 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 }
 
+void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
+{
+	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+	unsigned long irqflags;
+
+	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+	ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
+				     DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
+	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+}
+
 /* Set the vblank monitor pipe
  */
 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
@@ -1682,6 +1788,56 @@ int ironlake_irq_postinstall(struct drm_device *dev)
 	return 0;
 }
 
+int ivybridge_irq_postinstall(struct drm_device *dev)
+{
+	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+	/* enable kind of interrupts always enabled */
+	u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
+		DE_PCH_EVENT_IVB | DE_PLANEA_FLIP_DONE_IVB |
+		DE_PLANEB_FLIP_DONE_IVB;
+	u32 render_irqs;
+	u32 hotplug_mask;
+
+	DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
+	if (HAS_BSD(dev))
+		DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
+	if (HAS_BLT(dev))
+		DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
+
+	dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
+	dev_priv->irq_mask = ~display_mask;
+
+	/* should always can generate irq */
+	I915_WRITE(DEIIR, I915_READ(DEIIR));
+	I915_WRITE(DEIMR, dev_priv->irq_mask);
+	I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK_IVB |
+		   DE_PIPEB_VBLANK_IVB);
+	POSTING_READ(DEIER);
+
+	dev_priv->gt_irq_mask = ~0;
+
+	I915_WRITE(GTIIR, I915_READ(GTIIR));
+	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
+
+	render_irqs = GT_USER_INTERRUPT | GT_GEN6_BSD_USER_INTERRUPT |
+		GT_BLT_USER_INTERRUPT;
+	I915_WRITE(GTIER, render_irqs);
+	POSTING_READ(GTIER);
+
+	hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
+			SDE_PORTB_HOTPLUG_CPT |
+			SDE_PORTC_HOTPLUG_CPT |
+			SDE_PORTD_HOTPLUG_CPT);
+	dev_priv->pch_irq_mask = ~hotplug_mask;
+
+	I915_WRITE(SDEIIR, I915_READ(SDEIIR));
+	I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
+	I915_WRITE(SDEIER, hotplug_mask);
+	POSTING_READ(SDEIER);
+
+	return 0;
+}
+
 void i915_driver_irq_preinstall(struct drm_device * dev)
 {
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 03c99ed..6d4e671 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2779,6 +2779,19 @@
 #define DE_PIPEA_VSYNC          (1 << 3)
 #define DE_PIPEA_FIFO_UNDERRUN  (1 << 0)
 
+/* More Ivybridge lolz */
+#define DE_ERR_DEBUG_IVB		(1<<30)
+#define DE_GSE_IVB			(1<<29)
+#define DE_PCH_EVENT_IVB		(1<<28)
+#define DE_DP_A_HOTPLUG_IVB		(1<<27)
+#define DE_AUX_CHANNEL_A_IVB		(1<<26)
+#define DE_SPRITEB_FLIP_DONE_IVB	(1<<9)
+#define DE_SPRITEA_FLIP_DONE_IVB	(1<<4)
+#define DE_PLANEB_FLIP_DONE_IVB		(1<<8)
+#define DE_PLANEA_FLIP_DONE_IVB		(1<<3)
+#define DE_PIPEB_VBLANK_IVB		(1<<5)
+#define DE_PIPEA_VBLANK_IVB		(1<<0)
+
 #define DEISR   0x44000
 #define DEIMR   0x44004
 #define DEIIR   0x44008
-- 
1.7.4.1

[PATCH 14/16] drm/i915: page flip support for Ivy Bridge

[Jesse Barnes]

Treat Ivy Bridge like previous chips as far as flip submission is
concerned.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_display.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 908c4d9..6b24947 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6362,6 +6362,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
 		break;
 
 	case 6:
+	case 7:
 		OUT_RING(MI_DISPLAY_FLIP |
 			 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
 		OUT_RING(fb->pitch | obj->tiling_mode);
-- 
1.7.4.1

[PATCH 15/16] drm/i915: untested DP support for Ivy Bridge

[Jesse Barnes]

Treat it like Sandy Bridge in a few places.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_dp.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 0daefca..1d0eccd 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -312,7 +312,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
 	else
 		aux_clock_divider = intel_hrawclk(dev) / 2;
 
-	if (IS_GEN6(dev))
+	if (IS_GEN6(dev) || IS_GEN7(dev))
 		precharge = 3;
 	else
 		precharge = 5;
@@ -1302,7 +1302,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
 	for (;;) {
 		/* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
 		uint32_t    signal_levels;
-		if (IS_GEN6(dev) && is_edp(intel_dp)) {
+		if ((IS_GEN6(dev) || IS_GEN7(dev)) && is_edp(intel_dp)) {
 			signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
 			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
 		} else {
@@ -1376,7 +1376,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
 			break;
 		}
 
-		if (IS_GEN6(dev) && is_edp(intel_dp)) {
+		if ((IS_GEN6(dev) || IS_GEN7(dev)) && is_edp(intel_dp)) {
 			signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
 			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
 		} else {
-- 
1.7.4.1

[PATCH 16/16] drm/i915: ring support for Ivy Bridge

[Jesse Barnes]

Use Sandy Bridge paths in a few places.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index f15d80f..9bcfb9b 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -287,7 +287,7 @@ static int init_render_ring(struct intel_ring_buffer *ring)
 
 	if (INTEL_INFO(dev)->gen > 3) {
 		int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
-		if (IS_GEN6(dev))
+		if (IS_GEN6(dev) || IS_GEN7(dev))
 			mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
 		I915_WRITE(MI_MODE, mode);
 	}
@@ -553,7 +553,7 @@ render_ring_put_irq(struct intel_ring_buffer *ring)
 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
 {
 	drm_i915_private_t *dev_priv = ring->dev->dev_private;
-	u32 mmio = IS_GEN6(ring->dev) ?
+	u32 mmio = (IS_GEN6(ring->dev) || IS_GEN7(ring->dev)) ?
 		RING_HWS_PGA_GEN6(ring->mmio_base) :
 		RING_HWS_PGA(ring->mmio_base);
 	I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
@@ -1335,7 +1335,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
 
-	if (IS_GEN6(dev))
+	if (IS_GEN6(dev) || IS_GEN7(dev))
 		*ring = gen6_bsd_ring;
 	else
 		*ring = bsd_ring;
-- 
1.7.4.1

Re: Initial Ivy Bridge support

[Jesse Barnes]

On Tue, 26 Apr 2011 16:38:38 -0700
Jesse Barnes <jbarnes@virtuousgeek.org> wrote:

> This set of patches enables basic Ivy Bridge support, and has been
> tested with early hardware.  VGA is known to work, but other outputs are
> likely to work as well given that IVB uses CougarPoint or compatible PCH
> chips, which contain most of the display logic.
> 
> Page flipping was buggy when last tested, it seems we're missing flip
> complete interrupts.  I'll fix that up once I get some new hardware (as
> it could have been a hw issue with early boards).

Arg my ISP is eating or delaying these messages.  Maybe they'll come
through eventually.

-- 
Jesse Barnes, Intel Open Source Technology Center

Re: [PATCH 04/16] drm/i915: add Ivy Bridge PCI IDs and flags

[Chris Wilson]

On Tue, 26 Apr 2011 16:38:42 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> Check for IVB desktop, mobile and other SKUs and set flags
> appropriately.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 2a41118..0b5e263 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -230,6 +230,7 @@ struct intel_device_info {
>  	u8 is_pineview : 1;
>  	u8 is_broadwater : 1;
>  	u8 is_crestline : 1;
> +	u8 is_ivybridge : 1;

Since ivybridge is synonymous with GEN7, we have been going with the
latter. I want to reserve the capability bits for instances where we
either have a workaround for a few chipsets (and so I have a patch to
strip out the is_broadwater and is_crestline since they are just a single
pci-id each) or otherwise describing a feature across chipsets. 

So I think we just want IS_GEN7() for IVB code.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH 08/16] drm/i915: Ivy Bridge has split display and pipe control

[Chris Wilson]

On Tue, 26 Apr 2011 16:38:46 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> Ivy Bridge has a similar split display controller to Sandy Bridge, so
> use HAS_PCH_SPLIT.  And gen7 also has the pipe control instruction, so
> use HAS_PIPE_CONTROL as well.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/i915_drv.h |    4 ++--
>  1 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 9fbb6fe..e596c10 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -965,8 +965,8 @@ enum intel_chip_family {
>  #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
>  #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
>  
> -#define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev))
> -#define HAS_PIPE_CONTROL(dev) (IS_GEN5(dev) || IS_GEN6(dev))
> +#define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev))
> +#define HAS_PIPE_CONTROL(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_GEN7(dev))
>  
>  #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
>  #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)

So either we are confident that every future ILK+ continues with the split
and keeps pipe_control, in which case we do the obvious simplification or
we make these an actual capability bit before the code becomes a deep
nesting of predicates again...
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH 04/16] drm/i915: add Ivy Bridge PCI IDs and flags

[Chris Wilson]

On Tue, 26 Apr 2011 16:38:42 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> Check for IVB desktop, mobile and other SKUs and set flags
> appropriately.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  static const struct pci_device_id pciidlist[] = {		/* aka */
>  	INTEL_VGA_DEVICE(0x3577, &intel_i830_info),		/* I830_M */
>  	INTEL_VGA_DEVICE(0x2562, &intel_845g_info),		/* 845_G */
> @@ -227,6 +241,11 @@ static const struct pci_device_id pciidlist[] = {		/* aka */
>  	INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
>  	INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
>  	INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
> +	INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
> +	INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
> +	INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
> +	INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
> +	INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */

Shouldn't this chunk be the last patch in the series? (First for testing,
last for deployment.)
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH 07/16] drm/i915: add PantherPoint PCH ID

[Keith Packard]

[-- Attachment #1.1: Type: text/plain, Size: 303 bytes --]

On Tue, 26 Apr 2011 16:38:45 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:

> We can treat PantherPoint as CougarPoint as far as display goes.

I'll note in passing that pch_type is never set to PCH_IBX explicitly,
which only works because PCH_IBX is zero.

-- 
keith.packard@intel.com

[-- Attachment #1.2: Type: application/pgp-signature, Size: 189 bytes --]

[-- Attachment #2: Type: text/plain, Size: 159 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 11/16] drm/i915: manual FDI training for Ivy Bridge

[Keith Packard]

[-- Attachment #1.1: Type: text/plain, Size: 7228 bytes --]

On Tue, 26 Apr 2011 16:38:49 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> A0 stepping chips need to use manual training, but the bits have all
> moved.  So fix things up so we can at least train FDI for VGA links.

This patch should be before the auto-train patch so that we don't have
a broken driver between them.

> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      |   10 +++
>  drivers/gpu/drm/i915/intel_display.c |  129 +++++++++++++++++++++++++++++++++-
>  2 files changed, 136 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b77bd49..03c99ed 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3105,7 +3105,15 @@
>  #define  FDI_TX_ENHANCE_FRAME_ENABLE    (1<<18)
>  /* Ironlake: hardwired to 1 */
>  #define  FDI_TX_PLL_ENABLE              (1<<14)
> +
> +/* Ivybridge has different bits for lolz */
> +#define  FDI_LINK_TRAIN_PATTERN_1_IVB       (0<<8)
> +#define  FDI_LINK_TRAIN_PATTERN_2_IVB       (1<<8)
> +#define  FDI_LINK_TRAIN_PATTERN_IDLE_IVB    (2<<8)
> +#define  FDI_LINK_TRAIN_NONE_IVB            (3<<8)
> +
>  /* both Tx and Rx */
> +#define  FDI_LINK_TRAIN_AUTO		(1<<10)
>  #define  FDI_SCRAMBLING_ENABLE          (0<<7)
>  #define  FDI_SCRAMBLING_DISABLE         (1<<7)
>  /* Ivybridge */
> @@ -3117,6 +3125,8 @@
>  #define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
>  #define  FDI_RX_ENABLE          (1<<31)
>  /* train, dp width same as FDI_TX */
> +#define  FDI_FS_ERRC_ENABLE		(1<<27)
> +#define  FDI_FE_ERRC_ENABLE		(1<<26)
>  #define  FDI_DP_PORT_WIDTH_X8           (7<<19)
>  #define  FDI_8BPC                       (0<<16)
>  #define  FDI_10BPC                      (1<<16)
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index db46e4f..866abe5 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2047,8 +2047,13 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
>  	/* enable normal train */
>  	reg = FDI_TX_CTL(pipe);
>  	temp = I915_READ(reg);
> -	temp &= ~FDI_LINK_TRAIN_NONE;
> -	temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
> +	if (IS_GEN6(dev)) {
> +		temp &= ~FDI_LINK_TRAIN_NONE;
> +		temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
> +	} else if (IS_IVYBRIDGE(dev)) {
> +		temp &= ~FDI_LINK_TRAIN_NONE_IVB;
> +		temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
> +	}
>  	I915_WRITE(reg, temp);
>  
>  	reg = FDI_RX_CTL(pipe);
> @@ -2065,6 +2070,11 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
>  	/* wait one idle pattern time */
>  	POSTING_READ(reg);
>  	udelay(1000);
> +
> +	/* IVB wants error correction enabled */
> +	if (IS_IVYBRIDGE(dev))
> +		I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
> +			   FDI_FE_ERRC_ENABLE);
>  }
>  
>  /* The FDI link training functions for ILK/Ibexpeak. */
> @@ -2292,6 +2302,115 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
>  	DRM_DEBUG_KMS("FDI train done.\n");
>  }
>  
> +/* Manual link training for Ivy Bridge A0 parts */
> +static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
> +{
> +	struct drm_device *dev = crtc->dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +	int pipe = intel_crtc->pipe;
> +	u32 reg, temp, i;
> +
> +	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
> +	   for train result */
> +	reg = FDI_RX_IMR(pipe);
> +	temp = I915_READ(reg);
> +	temp &= ~FDI_RX_SYMBOL_LOCK;
> +	temp &= ~FDI_RX_BIT_LOCK;
> +	I915_WRITE(reg, temp);
> +
> +	POSTING_READ(reg);
> +	udelay(150);
> +
> +	/* enable CPU FDI TX and PCH FDI RX */
> +	reg = FDI_TX_CTL(pipe);
> +	temp = I915_READ(reg);
> +	temp &= ~(7 << 19);
> +	temp |= (intel_crtc->fdi_lanes - 1) << 19;
> +	temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
> +	temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
> +	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
> +	temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
> +	I915_WRITE(reg, temp | FDI_TX_ENABLE);
> +
> +	reg = FDI_RX_CTL(pipe);
> +	temp = I915_READ(reg);
> +	temp &= ~FDI_LINK_TRAIN_AUTO;
> +	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
> +	temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
> +	I915_WRITE(reg, temp | FDI_RX_ENABLE);
> +
> +	POSTING_READ(reg);
> +	udelay(150);
> +
> +	for (i = 0; i < 4; i++ ) {
> +		reg = FDI_TX_CTL(pipe);
> +		temp = I915_READ(reg);
> +		temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
> +		temp |= snb_b_fdi_train_param[i];
> +		I915_WRITE(reg, temp);
> +
> +		POSTING_READ(reg);
> +		udelay(500);
> +
> +		reg = FDI_RX_IIR(pipe);
> +		temp = I915_READ(reg);
> +		DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
> +
> +		if (temp & FDI_RX_BIT_LOCK ||
> +		    (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
> +			I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
> +			DRM_DEBUG_KMS("FDI train 1 done.\n");
> +			break;
> +		}
> +	}
> +	if (i == 4)
> +		DRM_ERROR("FDI train 1 fail!\n");
> +
> +	/* Train 2 */
> +	reg = FDI_TX_CTL(pipe);
> +	temp = I915_READ(reg);
> +	temp &= ~FDI_LINK_TRAIN_NONE_IVB;
> +	temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
> +	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
> +	temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
> +	I915_WRITE(reg, temp);
> +
> +	reg = FDI_RX_CTL(pipe);
> +	temp = I915_READ(reg);
> +	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
> +	temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
> +	I915_WRITE(reg, temp);
> +
> +	POSTING_READ(reg);
> +	udelay(150);
> +
> +	for (i = 0; i < 4; i++ ) {
> +		reg = FDI_TX_CTL(pipe);
> +		temp = I915_READ(reg);
> +		temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
> +		temp |= snb_b_fdi_train_param[i];
> +		I915_WRITE(reg, temp);
> +
> +		POSTING_READ(reg);
> +		udelay(500);
> +
> +		reg = FDI_RX_IIR(pipe);
> +		temp = I915_READ(reg);
> +		DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
> +
> +		if (temp & FDI_RX_SYMBOL_LOCK) {
> +			I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
> +			DRM_DEBUG_KMS("FDI train 2 done.\n");
> +			break;
> +		}
> +	}
> +	if (i == 4)
> +		DRM_ERROR("FDI train 2 fail!\n");
> +
> +	DRM_DEBUG_KMS("FDI train done.\n");
> +}
> +
>  /* On Ivybridge we can use auto training */
>  static void ivb_fdi_link_train(struct drm_crtc *crtc)
>  {
> @@ -7367,7 +7486,11 @@ static void intel_init_display(struct drm_device *dev)
>  			}
>  			dev_priv->display.train_fdi = gen6_fdi_link_train;
>  		} else if (IS_IVYBRIDGE(dev)) {
> -			dev_priv->display.train_fdi = ivb_fdi_link_train;
> +			/* FIXME: detect B0+ stepping and use auto training */
> +			if (0)
> +				dev_priv->display.train_fdi = ivb_fdi_link_train;
> +			else
> +				dev_priv->display.train_fdi = ivb_manual_fdi_link_train;
>  		} else
>  			dev_priv->display.update_wm = NULL;
>  	} else if (IS_PINEVIEW(dev)) {
> -- 
> 1.7.4.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
keith.packard@intel.com

[-- Attachment #1.2: Type: application/pgp-signature, Size: 189 bytes --]

[-- Attachment #2: Type: text/plain, Size: 159 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 01/16] drm/i915: make FDI training a display function

[Ben Widawsky]

On Tue, Apr 26, 2011 at 04:38:39PM -0700, Jesse Barnes wrote:
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 0296967..c10d7e9 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -209,7 +209,7 @@ struct drm_i915_display_funcs {
>  			     struct drm_display_mode *adjusted_mode,
>  			     int x, int y,
>  			     struct drm_framebuffer *old_fb);
> -
> +	void (*train_fdi)(struct drm_crtc *crtc);
>  	/* clock updates for mode set */
>  	/* cursor updates */
>  	/* render clock increase/decrease */

I was hoping for:
void (*fdi_link_train)(struct drm_crtc *crtc);

Ben

Re: [PATCH 08/16] drm/i915: Ivy Bridge has split display and pipe control

[Daniel Vetter]

On Wed, Apr 27, 2011 at 08:19:21AM +0100, Chris Wilson wrote:
> On Tue, 26 Apr 2011 16:38:46 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> > Ivy Bridge has a similar split display controller to Sandy Bridge, so
> > use HAS_PCH_SPLIT.  And gen7 also has the pipe control instruction, so
> > use HAS_PIPE_CONTROL as well.
> > 
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h |    4 ++--
> >  1 files changed, 2 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 9fbb6fe..e596c10 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -965,8 +965,8 @@ enum intel_chip_family {
> >  #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
> >  #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
> >  
> > -#define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev))
> > -#define HAS_PIPE_CONTROL(dev) (IS_GEN5(dev) || IS_GEN6(dev))
> > +#define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev))
> > +#define HAS_PIPE_CONTROL(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_GEN7(dev))
> >  
> >  #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
> >  #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
> 
> So either we are confident that every future ILK+ continues with the split
> and keeps pipe_control, in which case we do the obvious simplification or
> we make these an actual capability bit before the code becomes a deep
> nesting of predicates again...

HAS_PIPE_CONTROL is currently unused in the kernel. We might as well kill
it. Unreleated style critique that also applies to other patches: I think
checks of the from (gen >= 5) would be easier to read - using IS_FOO
macros always looks a bit like a special case ...
-Daniel
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 01/16] drm/i915: make FDI training a display function

[Jesse Barnes]

On Wed, 27 Apr 2011 08:58:38 -0700
Ben Widawsky <ben@bwidawsk.net> wrote:

> On Tue, Apr 26, 2011 at 04:38:39PM -0700, Jesse Barnes wrote:
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 0296967..c10d7e9 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -209,7 +209,7 @@ struct drm_i915_display_funcs {
> >  			     struct drm_display_mode *adjusted_mode,
> >  			     int x, int y,
> >  			     struct drm_framebuffer *old_fb);
> > -
> > +	void (*train_fdi)(struct drm_crtc *crtc);
> >  	/* clock updates for mode set */
> >  	/* cursor updates */
> >  	/* render clock increase/decrease */
> 
> I was hoping for:
> void (*fdi_link_train)(struct drm_crtc *crtc);

Oh right, I forgot to update this before I sent it out; will fix.

Thanks,
Jesse

Re: [PATCH 04/16] drm/i915: add Ivy Bridge PCI IDs and flags

[Jesse Barnes]

On Wed, 27 Apr 2011 07:59:17 +0100
Chris Wilson <chris@chris-wilson.co.uk> wrote:

> On Tue, 26 Apr 2011 16:38:42 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> > Check for IVB desktop, mobile and other SKUs and set flags
> > appropriately.
> > 
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 2a41118..0b5e263 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -230,6 +230,7 @@ struct intel_device_info {
> >  	u8 is_pineview : 1;
> >  	u8 is_broadwater : 1;
> >  	u8 is_crestline : 1;
> > +	u8 is_ivybridge : 1;
> 
> Since ivybridge is synonymous with GEN7, we have been going with the
> latter. I want to reserve the capability bits for instances where we
> either have a workaround for a few chipsets (and so I have a patch to
> strip out the is_broadwater and is_crestline since they are just a single
> pci-id each) or otherwise describing a feature across chipsets. 
> 
> So I think we just want IS_GEN7() for IVB code.

I'd rather keep them separate since we know we'll have gen7 chips with
different display engines in the future.  I've been trying to use
IS_GEN for render related checks, IS_IVB for specific display checks,
and HAS_PCH for the ilk+ split (though for the most part that should go
away with proper function call backs).

But I'll take a look at them again and see what's most appropriate.

Jesse

Re: [PATCH 04/16] drm/i915: add Ivy Bridge PCI IDs and flags

[Jesse Barnes]

On Wed, 27 Apr 2011 08:23:33 +0100
Chris Wilson <chris@chris-wilson.co.uk> wrote:

> On Tue, 26 Apr 2011 16:38:42 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> > Check for IVB desktop, mobile and other SKUs and set flags
> > appropriately.
> > 
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > ---
> >  static const struct pci_device_id pciidlist[] = {		/* aka */
> >  	INTEL_VGA_DEVICE(0x3577, &intel_i830_info),		/* I830_M */
> >  	INTEL_VGA_DEVICE(0x2562, &intel_845g_info),		/* 845_G */
> > @@ -227,6 +241,11 @@ static const struct pci_device_id pciidlist[] = {		/* aka */
> >  	INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
> >  	INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
> >  	INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
> > +	INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
> > +	INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
> > +	INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
> > +	INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
> > +	INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
> 
> Shouldn't this chunk be the last patch in the series? (First for testing,
> last for deployment.)

Sure, this one's easy to move around.  Likewise with the AGP patch.

Jesse

Re: [PATCH 08/16] drm/i915: Ivy Bridge has split display and pipe control

[Jesse Barnes]

On Wed, 27 Apr 2011 08:19:21 +0100
Chris Wilson <chris@chris-wilson.co.uk> wrote:

> On Tue, 26 Apr 2011 16:38:46 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> > Ivy Bridge has a similar split display controller to Sandy Bridge, so
> > use HAS_PCH_SPLIT.  And gen7 also has the pipe control instruction, so
> > use HAS_PIPE_CONTROL as well.
> > 
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h |    4 ++--
> >  1 files changed, 2 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 9fbb6fe..e596c10 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -965,8 +965,8 @@ enum intel_chip_family {
> >  #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
> >  #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
> >  
> > -#define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev))
> > -#define HAS_PIPE_CONTROL(dev) (IS_GEN5(dev) || IS_GEN6(dev))
> > +#define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev))
> > +#define HAS_PIPE_CONTROL(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_GEN7(dev))
> >  
> >  #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
> >  #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
> 
> So either we are confident that every future ILK+ continues with the split
> and keeps pipe_control, in which case we do the obvious simplification or
> we make these an actual capability bit before the code becomes a deep
> nesting of predicates again...

No, I expect HAS_PCH_SPLIT won't apply to upcoming gen7 chipsets.  The
cantiga display controller is even used in GMA500, so it really is
separate from render related checks.  We could probably come up with
better names though to make things more readable and consistent.

Jesse

Re: [PATCH 07/16] drm/i915: add PantherPoint PCH ID

[Jesse Barnes]

On Wed, 27 Apr 2011 08:05:37 -0700
Keith Packard <keithp@keithp.com> wrote:

> On Tue, 26 Apr 2011 16:38:45 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> 
> > We can treat PantherPoint as CougarPoint as far as display goes.
> 
> I'll note in passing that pch_type is never set to PCH_IBX explicitly,
> which only works because PCH_IBX is zero.

Yeah, I don't like that either, I can fix that up in a separate patch.

Jesse

Re: [PATCH 11/16] drm/i915: manual FDI training for Ivy Bridge

[Jesse Barnes]

On Wed, 27 Apr 2011 08:10:29 -0700
Keith Packard <keithp@keithp.com> wrote:

> On Tue, 26 Apr 2011 16:38:49 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> > A0 stepping chips need to use manual training, but the bits have all
> > moved.  So fix things up so we can at least train FDI for VGA links.
> 
> This patch should be before the auto-train patch so that we don't have
> a broken driver between them.

Ok, will re-order.

Jesse

Re: [PATCH 04/16] drm/i915: add Ivy Bridge PCI IDs and flags

[Chris Wilson]

On Wed, 27 Apr 2011 14:01:50 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> On Wed, 27 Apr 2011 07:59:17 +0100
> Chris Wilson <chris@chris-wilson.co.uk> wrote:
> > So I think we just want IS_GEN7() for IVB code.
> 
> I'd rather keep them separate since we know we'll have gen7 chips with
> different display engines in the future.  I've been trying to use
> IS_GEN for render related checks, IS_IVB for specific display checks,
> and HAS_PCH for the ilk+ split (though for the most part that should go
> away with proper function call backs).

If there is method to the madness, fine. I like the explanation and so
perhaps we should include that in the code somewhere. And we just need to
make sure we are consistent in our usage.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre