* [PATCH 1/2] i965: Stop caching the combined depth/stencil region in brw_context.c.
@ 2011-05-14 21:15 Eric Anholt
2011-05-14 21:15 ` [PATCH 2/2] i965: Add support for rendering to depthbuffer mipmap levels > 0 Eric Anholt
0 siblings, 1 reply; 2+ messages in thread
From: Eric Anholt @ 2011-05-14 21:15 UTC (permalink / raw)
To: intel-gfx
This was going to get in the way of separate depth/stencil (which
wants to know about both, and whether they are the same rb), and also
wasn't a sufficient flag for the fix in the following commit.
---
src/mesa/drivers/dri/i965/brw_context.h | 24 -----------------
src/mesa/drivers/dri/i965/brw_misc_state.c | 36 ++++++++++++++++++--------
src/mesa/drivers/dri/i965/brw_state_upload.c | 1 -
src/mesa/drivers/dri/i965/brw_vtbl.c | 9 ------
src/mesa/drivers/dri/i965/brw_wm_state.c | 6 ++--
5 files changed, 28 insertions(+), 48 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 26cd820..f351bcd 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -139,8 +139,6 @@ struct brw_context;
* by any 3D rendering.
*/
#define BRW_NEW_BATCH 0x10000
-/** \see brw.state.depth_region */
-#define BRW_NEW_DEPTH_BUFFER 0x20000
#define BRW_NEW_NR_WM_SURFACES 0x40000
#define BRW_NEW_NR_VS_SURFACES 0x80000
#define BRW_NEW_INDEX_BUFFER 0x100000
@@ -462,28 +460,6 @@ struct brw_context
struct {
struct brw_state_flags dirty;
-
- /**
- * \name Cached region pointers
- *
- * When the draw buffer is updated, often the depth buffer is not
- * changed. Caching the pointer to the buffer's region allows us to
- * detect when the buffer has in fact changed, and allows us to avoid
- * updating the buffer's GPU state when it has not.
- *
- * The original of each cached pointer is an instance of
- * \c intel_renderbuffer.region.
- *
- * \see brw_set_draw_region()
- *
- * \{
- */
-
- /** \see struct brw_tracked_state brw_depthbuffer */
- struct intel_region *depth_region;
-
- /** \} */
-
/**
* List of buffers accumulated in brw_validate_state to receive
* drm_intel_bo_check_aperture treatment before exec, so we can
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 7119786..e8c8b81 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -32,6 +32,7 @@
#include "intel_batchbuffer.h"
+#include "intel_fbo.h"
#include "intel_regions.h"
#include "brw_context.h"
@@ -187,18 +188,33 @@ const struct brw_tracked_state brw_psp_urb_cbs = {
static void prepare_depthbuffer(struct brw_context *brw)
{
- struct intel_region *region = brw->state.depth_region;
-
- if (region != NULL)
- brw_add_validated_bo(brw, region->buffer);
+ struct intel_context *intel = &brw->intel;
+ struct gl_context *ctx = &intel->ctx;
+ struct gl_framebuffer *fb = ctx->DrawBuffer;
+ struct intel_renderbuffer *drb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
+ struct intel_renderbuffer *srb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
+
+ if (drb)
+ brw_add_validated_bo(brw, drb->region->buffer);
+ if (srb)
+ brw_add_validated_bo(brw, srb->region->buffer);
}
static void emit_depthbuffer(struct brw_context *brw)
{
struct intel_context *intel = &brw->intel;
- struct intel_region *region = brw->state.depth_region;
+ struct gl_context *ctx = &intel->ctx;
+ struct gl_framebuffer *fb = ctx->DrawBuffer;
+ /* _NEW_BUFFERS */
+ struct intel_renderbuffer *irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
unsigned int len;
+ /* If we're combined depth stencil but no depth is attached, look
+ * up stencil.
+ */
+ if (!irb)
+ irb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
+
if (intel->gen >= 6)
len = 7;
else if (intel->is_g4x || intel->gen == 5)
@@ -206,7 +222,7 @@ static void emit_depthbuffer(struct brw_context *brw)
else
len = 5;
- if (region == NULL) {
+ if (!irb) {
BEGIN_BATCH(len);
OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) |
@@ -223,6 +239,7 @@ static void emit_depthbuffer(struct brw_context *brw)
ADVANCE_BATCH();
} else {
+ struct intel_region *region = irb->region;
unsigned int format;
switch (region->cpp) {
@@ -276,13 +293,10 @@ static void emit_depthbuffer(struct brw_context *brw)
}
}
-/**
- * \see brw_context.state.depth_region
- */
const struct brw_tracked_state brw_depthbuffer = {
.dirty = {
- .mesa = 0,
- .brw = BRW_NEW_DEPTH_BUFFER | BRW_NEW_BATCH,
+ .mesa = _NEW_BUFFERS,
+ .brw = BRW_NEW_BATCH,
.cache = 0,
},
.prepare = prepare_depthbuffer,
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 008aceb..0bd36a0 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -304,7 +304,6 @@ static struct dirty_bit_map brw_bits[] = {
DEFINE_BIT(BRW_NEW_INDEX_BUFFER),
DEFINE_BIT(BRW_NEW_VERTICES),
DEFINE_BIT(BRW_NEW_BATCH),
- DEFINE_BIT(BRW_NEW_DEPTH_BUFFER),
DEFINE_BIT(BRW_NEW_NR_WM_SURFACES),
DEFINE_BIT(BRW_NEW_NR_VS_SURFACES),
DEFINE_BIT(BRW_NEW_VS_CONSTBUF),
diff --git a/src/mesa/drivers/dri/i965/brw_vtbl.c b/src/mesa/drivers/dri/i965/brw_vtbl.c
index f2c417d..5515038 100644
--- a/src/mesa/drivers/dri/i965/brw_vtbl.c
+++ b/src/mesa/drivers/dri/i965/brw_vtbl.c
@@ -72,8 +72,6 @@ static void brw_destroy_context( struct intel_context *intel )
free(brw->wm.compile_data);
}
- intel_region_release(&brw->state.depth_region);
-
dri_bo_release(&brw->curbe.curbe_bo);
dri_bo_release(&brw->vs.prog_bo);
dri_bo_release(&brw->vs.const_bo);
@@ -97,13 +95,6 @@ static void brw_set_draw_region( struct intel_context *intel,
struct intel_region *depth_region,
GLuint num_color_regions)
{
- struct brw_context *brw = brw_context(&intel->ctx);
-
- if (brw->state.depth_region != depth_region) {
- brw->state.dirty.brw |= BRW_NEW_DEPTH_BUFFER;
- intel_region_release(&brw->state.depth_region);
- intel_region_reference(&brw->state.depth_region, depth_region);
- }
}
diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c
index a91ae51..a356711 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
@@ -31,6 +31,7 @@
+#include "intel_fbo.h"
#include "brw_context.h"
#include "brw_state.h"
#include "brw_defines.h"
@@ -144,11 +145,11 @@ brw_prepare_wm_unit(struct brw_context *brw)
(1 << FRAG_ATTRIB_WPOS)) != 0;
wm->wm5.program_computes_depth = (fp->Base.OutputsWritten &
BITFIELD64_BIT(FRAG_RESULT_DEPTH)) != 0;
- /* BRW_NEW_DEPTH_BUFFER
+ /* _NEW_BUFFERS
* Override for NULL depthbuffer case, required by the Pixel Shader Computed
* Depth field.
*/
- if (brw->state.depth_region == NULL)
+ if (!intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH))
wm->wm5.program_computes_depth = 0;
/* _NEW_COLOR */
@@ -266,7 +267,6 @@ const struct brw_tracked_state brw_wm_unit = {
.brw = (BRW_NEW_BATCH |
BRW_NEW_FRAGMENT_PROGRAM |
BRW_NEW_CURBE_OFFSETS |
- BRW_NEW_DEPTH_BUFFER |
BRW_NEW_NR_WM_SURFACES),
.cache = (CACHE_NEW_WM_PROG |
--
1.7.5.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* [PATCH 2/2] i965: Add support for rendering to depthbuffer mipmap levels > 0.
2011-05-14 21:15 [PATCH 1/2] i965: Stop caching the combined depth/stencil region in brw_context.c Eric Anholt
@ 2011-05-14 21:15 ` Eric Anholt
0 siblings, 0 replies; 2+ messages in thread
From: Eric Anholt @ 2011-05-14 21:15 UTC (permalink / raw)
To: intel-gfx
Fixes
GL_ARB_depth_texture/fbo-clear-formats
GL_EXT_packed_depth_stencil/fbo-clear-formats
---
src/mesa/drivers/dri/i965/brw_misc_state.c | 10 ++++--
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 41 ++++++---------------
src/mesa/drivers/dri/intel/intel_regions.c | 35 ++++++++++++++++++
src/mesa/drivers/dri/intel/intel_regions.h | 4 ++
4 files changed, 58 insertions(+), 32 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index e8c8b81..0d2f5da 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -241,6 +241,7 @@ static void emit_depthbuffer(struct brw_context *brw)
} else {
struct intel_region *region = irb->region;
unsigned int format;
+ uint32_t tile_x, tile_y, offset;
switch (region->cpp) {
case 2:
@@ -257,7 +258,8 @@ static void emit_depthbuffer(struct brw_context *brw)
return;
}
- assert(region->tiling != I915_TILING_X);
+ offset = intel_region_tile_offsets(region, &tile_x, &tile_y);
+
assert(intel->gen < 6 || region->tiling == I915_TILING_Y);
BEGIN_BATCH(len);
@@ -269,14 +271,16 @@ static void emit_depthbuffer(struct brw_context *brw)
(BRW_SURFACE_2D << 29));
OUT_RELOC(region->buffer,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- 0);
+ offset);
OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1) |
((region->width - 1) << 6) |
((region->height - 1) << 19));
OUT_BATCH(0);
if (intel->is_g4x || intel->gen >= 5)
- OUT_BATCH(0);
+ OUT_BATCH(tile_x | (tile_y << 16));
+ else
+ assert(tile_x == 0 && tile_y == 0);
if (intel->gen >= 6)
OUT_BATCH(0);
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 9b2072a..650e261 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -442,6 +442,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
struct intel_renderbuffer *irb = intel_renderbuffer(rb);
struct intel_region *region = irb->region;
struct brw_surface_state *surf;
+ uint32_t tile_x, tile_y;
surf = brw_state_batch(brw, sizeof(*surf), 32,
&brw->wm.surf_offset[unit]);
@@ -480,37 +481,19 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
}
surf->ss0.surface_type = BRW_SURFACE_2D;
- if (region->tiling == I915_TILING_NONE) {
- surf->ss1.base_addr = (region->draw_x +
- region->draw_y * region->pitch) * region->cpp;
- } else {
- uint32_t tile_base, tile_x, tile_y;
- uint32_t pitch = region->pitch * region->cpp;
-
- if (region->tiling == I915_TILING_X) {
- tile_x = region->draw_x % (512 / region->cpp);
- tile_y = region->draw_y % 8;
- tile_base = ((region->draw_y / 8) * (8 * pitch));
- tile_base += (region->draw_x - tile_x) / (512 / region->cpp) * 4096;
- } else {
- /* Y */
- tile_x = region->draw_x % (128 / region->cpp);
- tile_y = region->draw_y % 32;
- tile_base = ((region->draw_y / 32) * (32 * pitch));
- tile_base += (region->draw_x - tile_x) / (128 / region->cpp) * 4096;
- }
- assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
- assert(tile_x % 4 == 0);
- assert(tile_y % 2 == 0);
- /* Note that the low bits of these fields are missing, so
- * there's the possibility of getting in trouble.
- */
- surf->ss1.base_addr = tile_base;
- surf->ss5.x_offset = tile_x / 4;
- surf->ss5.y_offset = tile_y / 2;
- }
+ /* reloc */
+ surf->ss1.base_addr = intel_region_tile_offsets(region, &tile_x, &tile_y);
surf->ss1.base_addr += region->buffer->offset; /* reloc */
+ assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
+ /* Note that the low bits of these fields are missing, so
+ * there's the possibility of getting in trouble.
+ */
+ assert(tile_x % 4 == 0);
+ assert(tile_y % 2 == 0);
+ surf->ss5.x_offset = tile_x / 4;
+ surf->ss5.y_offset = tile_y / 2;
+
surf->ss2.width = rb->Width - 1;
surf->ss2.height = rb->Height - 1;
brw_set_surface_tiling(surf, region->tiling);
diff --git a/src/mesa/drivers/dri/intel/intel_regions.c b/src/mesa/drivers/dri/intel/intel_regions.c
index a4da1ce..0253bbc 100644
--- a/src/mesa/drivers/dri/intel/intel_regions.c
+++ b/src/mesa/drivers/dri/intel/intel_regions.c
@@ -524,3 +524,38 @@ intel_region_buffer(struct intel_context *intel,
return region->buffer;
}
+
+/**
+ * Rendering to tiled buffers requires that the base address of the
+ * buffer be aligned to a page boundary. We generally render to
+ * textures by pointing the surface at the mipmap image level, which
+ * may not be aligned to a tile boundary.
+ *
+ * This function returns an appropriately-aligned base offset
+ * according to the tiling restrictions, plus any required x/y offset
+ * from there.
+ */
+uint32_t
+intel_region_tile_offsets(struct intel_region *region,
+ uint32_t *tile_x,
+ uint32_t *tile_y)
+{
+ uint32_t pitch = region->pitch * region->cpp;
+
+ if (region->tiling == I915_TILING_NONE) {
+ *tile_x = 0;
+ *tile_y = 0;
+ return region->draw_x * region->cpp + region->draw_y * pitch;
+ } else if (region->tiling == I915_TILING_X) {
+ *tile_x = region->draw_x % (512 / region->cpp);
+ *tile_y = region->draw_y % 8;
+ return ((region->draw_y / 8) * (8 * pitch) +
+ (region->draw_x - *tile_x) / (512 / region->cpp) * 4096);
+ } else {
+ assert(region->tiling == I915_TILING_Y);
+ *tile_x = region->draw_x % (128 / region->cpp);
+ *tile_y = region->draw_y % 32;
+ return ((region->draw_y / 32) * (32 * pitch) +
+ (region->draw_x - *tile_x) / (128 / region->cpp) * 4096);
+ }
+}
diff --git a/src/mesa/drivers/dri/intel/intel_regions.h b/src/mesa/drivers/dri/intel/intel_regions.h
index 8464a5e..a8a300d 100644
--- a/src/mesa/drivers/dri/intel/intel_regions.h
+++ b/src/mesa/drivers/dri/intel/intel_regions.h
@@ -142,6 +142,10 @@ drm_intel_bo *intel_region_buffer(struct intel_context *intel,
struct intel_region *region,
GLuint flag);
+uint32_t intel_region_tile_offsets(struct intel_region *region,
+ uint32_t *tile_x,
+ uint32_t *tile_y);
+
void _mesa_copy_rect(GLubyte * dst,
GLuint cpp,
GLuint dst_pitch,
--
1.7.5.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
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