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* [PATCH 1/2] drm/i915: Control gen6 ring interrupts through a single mask field.
@ 2011-06-02  0:41 Eric Anholt
  2011-06-02  0:41 ` [PATCH 2/2] drm/i915: Fix missed interrupts on gen6 blit ring by holding FORCEWAKE up Eric Anholt
  0 siblings, 1 reply; 2+ messages in thread
From: Eric Anholt @ 2011-06-02  0:41 UTC (permalink / raw)
  To: intel-gfx

The BSpec says that the GTIMR is not to be used for masking
interrupts.  Regardless, writing one register should be better than
writing two registers.

Signed-off-by: Eric Anholt <eric@anholt.net>
---
 drivers/gpu/drm/i915/i915_irq.c         |   19 +++++++++++++----
 drivers/gpu/drm/i915/intel_ringbuffer.c |   32 +++++++++---------------------
 2 files changed, 24 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b79619a..0f8af27 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1782,21 +1782,30 @@ int ironlake_irq_postinstall(struct drm_device *dev)
 	I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
 	POSTING_READ(DEIER);
 
-	dev_priv->gt_irq_mask = ~0;
-
 	I915_WRITE(GTIIR, I915_READ(GTIIR));
-	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 
-	if (IS_GEN6(dev))
+	if (IS_GEN6(dev)) {
 		render_irqs =
 			GT_USER_INTERRUPT |
 			GT_GEN6_BSD_USER_INTERRUPT |
 			GT_BLT_USER_INTERRUPT;
-	else
+
+		/* The GTIMR is not supposed to be used for command streamer
+		 * interrupt events.  They are masked out in the per-ring
+		 * interrupt masks.
+		 */
+		dev_priv->gt_irq_mask = ~render_irqs;
+	} else {
 		render_irqs =
 			GT_USER_INTERRUPT |
 			GT_PIPE_NOTIFY |
 			GT_BSD_USER_INTERRUPT;
+
+		dev_priv->gt_irq_mask = ~0;
+	}
+
+	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
+
 	I915_WRITE(GTIER, render_irqs);
 	POSTING_READ(GTIER);
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 95c4b14..c6c4d23 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -621,7 +621,7 @@ ring_add_request(struct intel_ring_buffer *ring,
 }
 
 static bool
-gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
+gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 rflag)
 {
 	struct drm_device *dev = ring->dev;
 	drm_i915_private_t *dev_priv = dev->dev_private;
@@ -633,7 +633,7 @@ gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
 	if (ring->irq_refcount++ == 0) {
 		ring->irq_mask &= ~rflag;
 		I915_WRITE_IMR(ring, ring->irq_mask);
-		ironlake_enable_irq(dev_priv, gflag);
+		POSTING_READ(RING_IMR(ring->mmio_base));
 	}
 	spin_unlock(&ring->irq_lock);
 
@@ -641,7 +641,7 @@ gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
 }
 
 static void
-gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
+gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 rflag)
 {
 	struct drm_device *dev = ring->dev;
 	drm_i915_private_t *dev_priv = dev->dev_private;
@@ -650,7 +650,7 @@ gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
 	if (--ring->irq_refcount == 0) {
 		ring->irq_mask |= rflag;
 		I915_WRITE_IMR(ring, ring->irq_mask);
-		ironlake_disable_irq(dev_priv, gflag);
+		POSTING_READ(RING_IMR(ring->mmio_base));
 	}
 	spin_unlock(&ring->irq_lock);
 }
@@ -1105,33 +1105,25 @@ gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
 static bool
 gen6_render_ring_get_irq(struct intel_ring_buffer *ring)
 {
-	return gen6_ring_get_irq(ring,
-				 GT_USER_INTERRUPT,
-				 GEN6_RENDER_USER_INTERRUPT);
+	return gen6_ring_get_irq(ring, GEN6_RENDER_USER_INTERRUPT);
 }
 
 static void
 gen6_render_ring_put_irq(struct intel_ring_buffer *ring)
 {
-	return gen6_ring_put_irq(ring,
-				 GT_USER_INTERRUPT,
-				 GEN6_RENDER_USER_INTERRUPT);
+	return gen6_ring_put_irq(ring, GEN6_RENDER_USER_INTERRUPT);
 }
 
 static bool
 gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring)
 {
-	return gen6_ring_get_irq(ring,
-				 GT_GEN6_BSD_USER_INTERRUPT,
-				 GEN6_BSD_USER_INTERRUPT);
+	return gen6_ring_get_irq(ring, GEN6_BSD_USER_INTERRUPT);
 }
 
 static void
 gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring)
 {
-	return gen6_ring_put_irq(ring,
-				 GT_GEN6_BSD_USER_INTERRUPT,
-				 GEN6_BSD_USER_INTERRUPT);
+	return gen6_ring_put_irq(ring, GEN6_BSD_USER_INTERRUPT);
 }
 
 /* ring buffer for Video Codec for Gen6+ */
@@ -1155,17 +1147,13 @@ static const struct intel_ring_buffer gen6_bsd_ring = {
 static bool
 blt_ring_get_irq(struct intel_ring_buffer *ring)
 {
-	return gen6_ring_get_irq(ring,
-				 GT_BLT_USER_INTERRUPT,
-				 GEN6_BLITTER_USER_INTERRUPT);
+	return gen6_ring_get_irq(ring, GEN6_BLITTER_USER_INTERRUPT);
 }
 
 static void
 blt_ring_put_irq(struct intel_ring_buffer *ring)
 {
-	gen6_ring_put_irq(ring,
-			  GT_BLT_USER_INTERRUPT,
-			  GEN6_BLITTER_USER_INTERRUPT);
+	gen6_ring_put_irq(ring, GEN6_BLITTER_USER_INTERRUPT);
 }
 
 
-- 
1.7.5.1

^ permalink raw reply related	[flat|nested] 2+ messages in thread
* [PATCH 2/2] drm/i915: Fix missed interrupts on gen6 blit ring by holding FORCEWAKE up.
  2011-06-02  0:41 [PATCH 1/2] drm/i915: Control gen6 ring interrupts through a single mask field Eric Anholt
@ 2011-06-02  0:41 ` Eric Anholt
  0 siblings, 0 replies; 2+ messages in thread
From: Eric Anholt @ 2011-06-02  0:41 UTC (permalink / raw)
  To: intel-gfx

Before this patch, I was experiencing missed IRQs (hang, then dmesg
saying IRQ missed, then continuing) when running piglit
copypixels-sync about 0.5% of the time (no single run series I've done
so far got beyond 400 consecutive successes).  With this patch, I'm over
3200 consecutive successes with no missed IRQs.

---

This patch seems like a pretty clear indication that our understanding
of what requires FORCEWAKE is incorrect.  The only other patch I got
to succeed like this one was when I just left BLT IRQs on forever.

Can anyone cite where 0x40000 came from?

 drivers/gpu/drm/i915/intel_ringbuffer.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index c6c4d23..ef22e9b 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -631,9 +631,11 @@ gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 rflag)
 
 	spin_lock(&ring->irq_lock);
 	if (ring->irq_refcount++ == 0) {
+		gen6_gt_force_wake_get(dev_priv);
 		ring->irq_mask &= ~rflag;
 		I915_WRITE_IMR(ring, ring->irq_mask);
 		POSTING_READ(RING_IMR(ring->mmio_base));
+		gen6_gt_force_wake_put(dev_priv);
 	}
 	spin_unlock(&ring->irq_lock);
 
@@ -648,9 +650,11 @@ gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 rflag)
 
 	spin_lock(&ring->irq_lock);
 	if (--ring->irq_refcount == 0) {
+		gen6_gt_force_wake_get(dev_priv);
 		ring->irq_mask |= rflag;
 		I915_WRITE_IMR(ring, ring->irq_mask);
 		POSTING_READ(RING_IMR(ring->mmio_base));
+		gen6_gt_force_wake_put(dev_priv);
 	}
 	spin_unlock(&ring->irq_lock);
 }
-- 
1.7.5.1

^ permalink raw reply related	[flat|nested] 2+ messages in thread
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2011-06-02  0:41 [PATCH 1/2] drm/i915: Control gen6 ring interrupts through a single mask field Eric Anholt
2011-06-02  0:41 ` [PATCH 2/2] drm/i915: Fix missed interrupts on gen6 blit ring by holding FORCEWAKE up Eric Anholt

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