[PATCH 1/2] Add bare-metal interface to adjust cacheing (i.e. snoop status) of a bo

[PATCH 1/2] Add bare-metal interface to adjust cacheing (i.e. snoop status) of a bo

[Chris Wilson]

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 lib/drmtest.c |   52 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 lib/drmtest.h |    3 +++
 2 files changed, 55 insertions(+)

diff --git a/lib/drmtest.c b/lib/drmtest.c
index 871c1d0..66f2887 100644
--- a/lib/drmtest.c
+++ b/lib/drmtest.c
@@ -252,6 +252,58 @@ void gem_set_tiling(int fd, uint32_t handle, int tiling, int stride)
 	assert(st.tiling_mode == tiling);
 }
 
+struct local_drm_i915_gem_cacheing {
+	uint32_t handle;
+	uint32_t cacheing;
+};
+
+#define LOCAL_DRM_I915_GEM_SET_CACHEING    0x2f
+#define LOCAL_DRM_I915_GEM_GET_CACHEING    0x30
+#define LOCAL_DRM_IOCTL_I915_GEM_SET_CACHEING \
+	DRM_IOW(DRM_COMMAND_BASE + LOCAL_DRM_I915_GEM_SET_CACHEING, struct local_drm_i915_gem_cacheing)
+#define LOCAL_DRM_IOCTL_I915_GEM_GET_CACHEING \
+	DRM_IOWR(DRM_COMMAND_BASE + LOCAL_DRM_I915_GEM_GET_CACHEING, struct local_drm_i915_gem_cacheing)
+
+int gem_has_cacheing(int fd)
+{
+	struct local_drm_i915_gem_cacheing arg;
+	int ret;
+
+	arg.handle = gem_create(fd, 4096);
+	if (arg.handle == 0)
+		return 0;
+
+	arg.cacheing = 0;
+	ret = ioctl(fd, LOCAL_DRM_IOCTL_I915_GEM_SET_CACHEING, &arg);
+	gem_close(fd, arg.handle);
+
+	return ret == 0;
+}
+
+void gem_set_cacheing(int fd, uint32_t handle, int cacheing)
+{
+	struct local_drm_i915_gem_cacheing arg;
+	int ret;
+
+	arg.handle = handle;
+	arg.cacheing = cacheing;
+	ret = ioctl(fd, LOCAL_DRM_IOCTL_I915_GEM_SET_CACHEING, &arg);
+	assert(ret == 0);
+}
+
+int gem_get_cacheing(int fd, uint32_t handle)
+{
+	struct local_drm_i915_gem_cacheing arg;
+	int ret;
+
+	arg.handle = handle;
+	arg.cacheing = 0;
+	ret = ioctl(fd, LOCAL_DRM_IOCTL_I915_GEM_GET_CACHEING, &arg);
+	assert(ret == 0);
+
+	return arg.cacheing;
+}
+
 void gem_close(int fd, uint32_t handle)
 {
 	struct drm_gem_close close_bo;
diff --git a/lib/drmtest.h b/lib/drmtest.h
index 4021104..0208559 100644
--- a/lib/drmtest.h
+++ b/lib/drmtest.h
@@ -45,6 +45,9 @@ void gem_quiescent_gpu(int fd);
 
 /* ioctl wrappers and similar stuff for bare metal testing */
 void gem_set_tiling(int fd, uint32_t handle, int tiling, int stride);
+int gem_has_cacheing(int fd);
+void gem_set_cacheing(int fd, uint32_t handle, int cacheing);
+int gem_get_cacheing(int fd, uint32_t handle);
 void gem_close(int fd, uint32_t handle);
 void gem_write(int fd, uint32_t handle, uint32_t offset,  const void *buf, uint32_t size);
 void gem_read(int fd, uint32_t handle, uint32_t offset, void *buf, uint32_t size);
-- 
1.7.10.4

[PATCH 2/2] tests/gem_cacheing: Exercise snoop coherency

[Chris Wilson]

This is based on tests/gem_partial_pwrite_pread which aims to detect
incoherency between CPU reads and writes to a bo whilst using it as a
source and target for GPU writes.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/.gitignore     |    1 +
 tests/Makefile.am    |    1 +
 tests/gem_cacheing.c |  274 ++++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 276 insertions(+)
 create mode 100644 tests/gem_cacheing.c

diff --git a/tests/.gitignore b/tests/.gitignore
index f486a87..d360a02 100644
--- a/tests/.gitignore
+++ b/tests/.gitignore
@@ -8,6 +8,7 @@ gem_bad_batch
 gem_bad_blit
 gem_bad_length
 gem_basic
+gem_cacheing
 gem_cs_prefetch
 gem_cpu_concurrent_blit
 gem_double_irq_loop
diff --git a/tests/Makefile.am b/tests/Makefile.am
index 1f55912..a7da761 100644
--- a/tests/Makefile.am
+++ b/tests/Makefile.am
@@ -9,6 +9,7 @@ TESTS_progs = \
 	getclient \
 	getstats \
 	gem_basic \
+	gem_cacheing \
 	gem_cpu_concurrent_blit \
 	gem_gtt_concurrent_blit \
 	gem_exec_nop \
diff --git a/tests/gem_cacheing.c b/tests/gem_cacheing.c
new file mode 100644
index 0000000..b94ab70
--- /dev/null
+++ b/tests/gem_cacheing.c
@@ -0,0 +1,274 @@
+/*
+ * Copyright © 2012 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Daniel Vetter <daniel.vetter@ffwll.ch>
+ *    Chris Wilson <chris@chris-wilson.co.uk>
+ *
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <assert.h>
+#include <fcntl.h>
+#include <inttypes.h>
+#include <errno.h>
+#include <sys/stat.h>
+#include <sys/time.h>
+#include "drm.h"
+#include "i915_drm.h"
+#include "drmtest.h"
+#include "intel_bufmgr.h"
+#include "intel_batchbuffer.h"
+#include "intel_gpu_tools.h"
+
+/*
+ * Testcase: snoop consistency when touching partial cachelines
+ *
+ */
+
+static drm_intel_bufmgr *bufmgr;
+struct intel_batchbuffer *batch;
+
+drm_intel_bo *scratch_bo;
+drm_intel_bo *staging_bo;
+#define BO_SIZE (4*4096)
+uint32_t devid;
+uint64_t mappable_gtt_limit;
+int fd;
+
+static void
+copy_bo(drm_intel_bo *src, drm_intel_bo *dst)
+{
+	BEGIN_BATCH(8);
+	OUT_BATCH(XY_SRC_COPY_BLT_CMD |
+		  XY_SRC_COPY_BLT_WRITE_ALPHA |
+		  XY_SRC_COPY_BLT_WRITE_RGB);
+	OUT_BATCH((3 << 24) | /* 32 bits */
+		  (0xcc << 16) | /* copy ROP */
+		  4096);
+	OUT_BATCH(0 << 16 | 0);
+	OUT_BATCH((BO_SIZE/4096) << 16 | 1024);
+	OUT_RELOC_FENCED(dst, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
+	OUT_BATCH(0 << 16 | 0);
+	OUT_BATCH(4096);
+	OUT_RELOC_FENCED(src, I915_GEM_DOMAIN_RENDER, 0, 0);
+	ADVANCE_BATCH();
+
+	intel_batchbuffer_flush(batch);
+}
+
+static void
+blt_bo_fill(drm_intel_bo *tmp_bo, drm_intel_bo *bo, uint8_t val)
+{
+	uint8_t *gtt_ptr;
+	int i;
+
+	do_or_die(drm_intel_gem_bo_map_gtt(tmp_bo));
+	gtt_ptr = tmp_bo->virtual;
+
+	for (i = 0; i < BO_SIZE; i++)
+		gtt_ptr[i] = val;
+
+	drm_intel_gem_bo_unmap_gtt(tmp_bo);
+
+	if (bo->offset < mappable_gtt_limit &&
+	    (IS_G33(devid) || intel_gen(devid) >= 4))
+		drmtest_trash_aperture();
+
+	copy_bo(tmp_bo, bo);
+}
+
+#define MAX_BLT_SIZE 128
+#define ROUNDS 1000
+int main(int argc, char **argv)
+{
+	int i, j;
+	uint8_t *cpu_ptr;
+	uint8_t *gtt_ptr;
+
+	srandom(0xdeadbeef);
+
+	fd = drm_open_any();
+
+	if (!gem_has_cacheing(fd))
+		return 77;
+
+	bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
+	//drm_intel_bufmgr_gem_enable_reuse(bufmgr);
+	devid = intel_get_drm_devid(fd);
+	batch = intel_batchbuffer_alloc(bufmgr, devid);
+
+	/* overallocate the buffers we're actually using because */
+	scratch_bo = drm_intel_bo_alloc(bufmgr, "scratch bo", BO_SIZE, 4096);
+	gem_set_cacheing(fd, scratch_bo->handle, 1);
+
+	staging_bo = drm_intel_bo_alloc(bufmgr, "staging bo", BO_SIZE, 4096);
+
+	drmtest_init_aperture_trashers(bufmgr);
+	mappable_gtt_limit = gem_mappable_aperture_size();
+
+	printf("checking partial reads\n");
+	for (i = 0; i < ROUNDS; i++) {
+		uint8_t val0 = i;
+		int start, len;
+
+		blt_bo_fill(staging_bo, scratch_bo, i);
+
+		start = random() % BO_SIZE;
+		len = random() % (BO_SIZE-start) + 1;
+
+		drm_intel_bo_map(scratch_bo, false);
+		cpu_ptr = scratch_bo->virtual;
+		for (j = 0; j < len; j++) {
+			if (cpu_ptr[j] != val0) {
+				printf("mismatch at %i, got: %i, expected: %i\n",
+				       j, cpu_ptr[j], val0);
+				exit(1);
+			}
+		}
+		drm_intel_bo_unmap(scratch_bo);
+
+		drmtest_progress("partial reads test: ", i, ROUNDS);
+	}
+
+	printf("checking partial writes\n");
+	for (i = 0; i < ROUNDS; i++) {
+		uint8_t val0 = i, val1;
+		int start, len;
+
+		blt_bo_fill(staging_bo, scratch_bo, val0);
+
+		start = random() % BO_SIZE;
+		len = random() % (BO_SIZE-start) + 1;
+
+		val1 = val0 + 63;
+		drm_intel_bo_map(scratch_bo, true);
+		cpu_ptr = scratch_bo->virtual;
+		memset(cpu_ptr + start, val1, len);
+		drm_intel_bo_unmap(scratch_bo);
+
+		copy_bo(scratch_bo, staging_bo);
+		do_or_die(drm_intel_gem_bo_map_gtt(staging_bo));
+		gtt_ptr = staging_bo->virtual;
+
+		for (j = 0; j < start; j++) {
+			if (gtt_ptr[j] != val0) {
+				printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
+				       j, start, len, gtt_ptr[j], val0);
+				exit(1);
+			}
+		}
+		for (; j < start + len; j++) {
+			if (gtt_ptr[j] != val1) {
+				printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
+				       j, start, len, gtt_ptr[j], val1);
+				exit(1);
+			}
+		}
+		for (; j < BO_SIZE; j++) {
+			if (gtt_ptr[j] != val0) {
+				printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
+				       j, start, len, gtt_ptr[j], val0);
+				exit(1);
+			}
+		}
+		drm_intel_gem_bo_unmap_gtt(staging_bo);
+
+		drmtest_progress("partial writes test: ", i, ROUNDS);
+	}
+
+	printf("checking partial writes after partial reads\n");
+	for (i = 0; i < ROUNDS; i++) {
+		uint8_t val0 = i, val1, val2;
+		int start, len;
+
+		blt_bo_fill(staging_bo, scratch_bo, val0);
+
+		/* partial read */
+		start = random() % BO_SIZE;
+		len = random() % (BO_SIZE-start) + 1;
+
+		do_or_die(drm_intel_bo_map(scratch_bo, false));
+		cpu_ptr = scratch_bo->virtual;
+		for (j = 0; j < len; j++) {
+			if (cpu_ptr[j] != val0) {
+				printf("mismatch in read at %i, got: %i, expected: %i\n",
+				       j, cpu_ptr[j], val0);
+				exit(1);
+			}
+		}
+		drm_intel_bo_unmap(scratch_bo);
+
+		/* Change contents through gtt to make the pread cachelines
+		 * stale. */
+		val1 = i + 17;
+		blt_bo_fill(staging_bo, scratch_bo, val1);
+
+		/* partial write */
+		start = random() % BO_SIZE;
+		len = random() % (BO_SIZE-start) + 1;
+
+		val2 = i + 63;
+		do_or_die(drm_intel_bo_map(scratch_bo, false));
+		cpu_ptr = scratch_bo->virtual;
+		memset(cpu_ptr + start, val2, len);
+
+		copy_bo(scratch_bo, staging_bo);
+		do_or_die(drm_intel_gem_bo_map_gtt(staging_bo));
+		gtt_ptr = staging_bo->virtual;
+
+		for (j = 0; j < start; j++) {
+			if (gtt_ptr[j] != val1) {
+				printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
+				       j, start, len, gtt_ptr[j], val1);
+				exit(1);
+			}
+		}
+		for (; j < start + len; j++) {
+			if (gtt_ptr[j] != val2) {
+				printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
+				       j, start, len, gtt_ptr[j], val2);
+				exit(1);
+			}
+		}
+		for (; j < BO_SIZE; j++) {
+			if (gtt_ptr[j] != val1) {
+				printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
+				       j, start, len, gtt_ptr[j], val1);
+				exit(1);
+			}
+		}
+		drm_intel_gem_bo_unmap_gtt(staging_bo);
+		drm_intel_bo_unmap(scratch_bo);
+
+		drmtest_progress("partial read/writes test: ", i, ROUNDS);
+	}
+
+	drmtest_cleanup_aperture_trashers();
+	drm_intel_bufmgr_destroy(bufmgr);
+
+	close(fd);
+
+	return 0;
+}
-- 
1.7.10.4

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