* [PATCH 1/3] drm/i915: Add contexts for HSW @ 2012-07-25 3:47 Ben Widawsky 2012-07-25 3:47 ` [PATCH 2/3] drm/i915: Macro to determine DPF support Ben Widawsky 2012-07-25 3:47 ` [PATCH 3/3] drm/i915: Expand DPF support to Haswell Ben Widawsky 0 siblings, 2 replies; 4+ messages in thread From: Ben Widawsky @ 2012-07-25 3:47 UTC (permalink / raw) To: intel-gfx; +Cc: Ben Widawsky Basic context support on HSW is no different than previous generations. The size of the context object changes, but that's about it. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> --- drivers/gpu/drm/i915/i915_gem_context.c | 5 ++++- drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++ 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 5d0d6ad..5c2d354 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -112,7 +112,10 @@ static int get_context_size(struct drm_device *dev) break; case 7: reg = I915_READ(GEN7_CXT_SIZE); - ret = GEN7_CXT_TOTAL_SIZE(reg) * 64; + if (IS_HASWELL(dev)) + ret = HSW_CXT_TOTAL_SIZE(reg) * 64; + else + ret = GEN7_CXT_TOTAL_SIZE(reg) * 64; break; default: BUG(); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 81a3de6..1310caa 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1498,6 +1498,14 @@ GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \ GEN7_CXT_GT1_SIZE(ctx_reg) + \ GEN7_CXT_VFSTATE_SIZE(ctx_reg)) +#define HSW_CXT_POWER_SIZE(ctx_reg) ((ctx_reg >> 26) & 0x3f) +#define HSW_CXT_RING_SIZE(ctx_reg) ((ctx_reg >> 23) & 0x7) +#define HSW_CXT_RENDER_SIZE(ctx_reg) ((ctx_reg >> 15) & 0xff) +#define HSW_CXT_TOTAL_SIZE(ctx_reg) (HSW_CXT_POWER_SIZE(ctx_reg) + \ + HSW_CXT_RING_SIZE(ctx_reg) + \ + HSW_CXT_RENDER_SIZE(ctx_reg) + \ + GEN7_CXT_VFSTATE_SIZE(ctx_reg)) + /* * Overlay regs -- 1.7.11.3 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/3] drm/i915: Macro to determine DPF support 2012-07-25 3:47 [PATCH 1/3] drm/i915: Add contexts for HSW Ben Widawsky @ 2012-07-25 3:47 ` Ben Widawsky 2012-07-25 3:47 ` [PATCH 3/3] drm/i915: Expand DPF support to Haswell Ben Widawsky 1 sibling, 0 replies; 4+ messages in thread From: Ben Widawsky @ 2012-07-25 3:47 UTC (permalink / raw) To: intel-gfx; +Cc: Ben Widawsky, Ben Widawsky From: Ben Widawsky <benjamin.widawsky@intel.com> Originally I had a macro specifically for DPF support, and Daniel, with good reason asked me to change it to this. It's not the way I would have gone (and indeed I didn't), but for now there is no distinction as all platforms with L3 also have DPF. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_irq.c | 2 +- drivers/gpu/drm/i915/i915_sysfs.c | 2 +- drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +++--- 4 files changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 700dc83..001f8fb 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1117,6 +1117,8 @@ struct drm_i915_file_private { #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake) +#define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev)) + #include "i915_trace.h" /** diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 41ed41d..440c905 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -444,7 +444,7 @@ static void ivybridge_handle_parity_error(struct drm_device *dev) drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; unsigned long flags; - if (!IS_IVYBRIDGE(dev)) + if (!HAS_L3_GPU_CACHE(dev)) return; spin_lock_irqsave(&dev_priv->irq_lock, flags); diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c index 2f5388a..77a97bf 100644 --- a/drivers/gpu/drm/i915/i915_sysfs.c +++ b/drivers/gpu/drm/i915/i915_sysfs.c @@ -212,7 +212,7 @@ void i915_setup_sysfs(struct drm_device *dev) DRM_ERROR("RC6 residency sysfs setup failed\n"); } - if (IS_IVYBRIDGE(dev)) { + if (HAS_L3_GPU_CACHE(dev)) { ret = device_create_bin_file(&dev->primary->kdev, &dpf_attrs); if (ret) DRM_ERROR("l3 parity sysfs setup failed\n"); diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 8b7085e..c58f1b9 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -454,7 +454,7 @@ static int init_render_ring(struct intel_ring_buffer *ring) if (INTEL_INFO(dev)->gen >= 6) I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); - if (IS_IVYBRIDGE(dev)) + if (HAS_L3_GPU_CACHE(dev)) I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR); return ret; @@ -844,7 +844,7 @@ gen6_ring_get_irq(struct intel_ring_buffer *ring) spin_lock_irqsave(&dev_priv->irq_lock, flags); if (ring->irq_refcount++ == 0) { - if (IS_IVYBRIDGE(dev) && ring->id == RCS) + if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS) I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | GEN6_RENDER_L3_PARITY_ERROR)); else @@ -867,7 +867,7 @@ gen6_ring_put_irq(struct intel_ring_buffer *ring) spin_lock_irqsave(&dev_priv->irq_lock, flags); if (--ring->irq_refcount == 0) { - if (IS_IVYBRIDGE(dev) && ring->id == RCS) + if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS) I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR); else I915_WRITE_IMR(ring, ~0); -- 1.7.11.3 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 3/3] drm/i915: Expand DPF support to Haswell 2012-07-25 3:47 [PATCH 1/3] drm/i915: Add contexts for HSW Ben Widawsky 2012-07-25 3:47 ` [PATCH 2/3] drm/i915: Macro to determine DPF support Ben Widawsky @ 2012-07-25 3:47 ` Ben Widawsky 2012-07-25 16:09 ` Daniel Vetter 1 sibling, 1 reply; 4+ messages in thread From: Ben Widawsky @ 2012-07-25 3:47 UTC (permalink / raw) To: intel-gfx; +Cc: Ben Widawsky, Ben Widawsky From: Ben Widawsky <benjamin.widawsky@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> --- drivers/gpu/drm/i915/i915_drv.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 001f8fb..f6a44d4 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1117,7 +1117,7 @@ struct drm_i915_file_private { #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake) -#define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev)) +#define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) #include "i915_trace.h" -- 1.7.11.3 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 3/3] drm/i915: Expand DPF support to Haswell 2012-07-25 3:47 ` [PATCH 3/3] drm/i915: Expand DPF support to Haswell Ben Widawsky @ 2012-07-25 16:09 ` Daniel Vetter 0 siblings, 0 replies; 4+ messages in thread From: Daniel Vetter @ 2012-07-25 16:09 UTC (permalink / raw) To: Ben Widawsky; +Cc: intel-gfx, Ben Widawsky On Tue, Jul 24, 2012 at 08:47:32PM -0700, Ben Widawsky wrote: > From: Ben Widawsky <benjamin.widawsky@intel.com> > > Signed-off-by: Ben Widawsky <ben@bwidawsk.net> I've queued up the entire series, thanks. -Daniel -- Daniel Vetter Mail: daniel@ffwll.ch Mobile: +41 (0)79 365 57 48 ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2012-07-25 16:09 UTC | newest] Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2012-07-25 3:47 [PATCH 1/3] drm/i915: Add contexts for HSW Ben Widawsky 2012-07-25 3:47 ` [PATCH 2/3] drm/i915: Macro to determine DPF support Ben Widawsky 2012-07-25 3:47 ` [PATCH 3/3] drm/i915: Expand DPF support to Haswell Ben Widawsky 2012-07-25 16:09 ` Daniel Vetter
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