* [PATCH 01/14] drm/i915: add DP support to intel_ddi_enable_pipe_func
2012-10-15 18:51 [PATCH 00/14] Haswell DP enablement Paulo Zanoni
@ 2012-10-15 18:51 ` Paulo Zanoni
2012-10-16 10:04 ` Jani Nikula
2012-10-15 18:51 ` [PATCH 02/14] drm/i915: add intel_ddi_set_pipe_settings Paulo Zanoni
` (12 subsequent siblings)
13 siblings, 1 reply; 34+ messages in thread
From: Paulo Zanoni @ 2012-10-15 18:51 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 34 ++++++++++++++++++++++++++++++----
drivers/gpu/drm/i915/intel_dp.c | 5 -----
drivers/gpu/drm/i915/intel_drv.h | 5 +++++
3 files changed, 35 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index a78860a..9659c227 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -831,8 +831,10 @@ void intel_ddi_enable_pipe_func(struct drm_crtc *crtc)
{
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
+ struct drm_encoder *encoder = &intel_encoder->base;
struct drm_i915_private *dev_priv = crtc->dev->dev_private;
enum pipe pipe = intel_crtc->pipe;
+ int type = intel_encoder->type;
uint32_t temp;
/* Enable PIPE_DDI_FUNC_CTL for the pipe to work in HDMI mode */
@@ -861,9 +863,8 @@ void intel_ddi_enable_pipe_func(struct drm_crtc *crtc)
if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
temp |= PIPE_DDI_PHSYNC;
- if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
- struct intel_hdmi *intel_hdmi =
- enc_to_intel_hdmi(&intel_encoder->base);
+ if (type == INTEL_OUTPUT_HDMI) {
+ struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
if (intel_hdmi->has_hdmi_sink)
temp |= PIPE_DDI_MODE_SELECT_HDMI;
@@ -871,9 +872,34 @@ void intel_ddi_enable_pipe_func(struct drm_crtc *crtc)
temp |= PIPE_DDI_MODE_SELECT_DVI;
temp |= PIPE_DDI_SELECT_PORT(intel_hdmi->ddi_port);
- } else if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
+
+ } else if (type == INTEL_OUTPUT_ANALOG) {
temp |= PIPE_DDI_MODE_SELECT_FDI;
temp |= PIPE_DDI_SELECT_PORT(PORT_E);
+
+ } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
+ type == INTEL_OUTPUT_EDP) {
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ temp |= PIPE_DDI_MODE_SELECT_DP_SST;
+ temp |= PIPE_DDI_SELECT_PORT(intel_dp->port);
+
+ switch (intel_dp->lane_count) {
+ case 1:
+ temp |= PIPE_DDI_PORT_WIDTH_X1;
+ break;
+ case 2:
+ temp |= PIPE_DDI_PORT_WIDTH_X2;
+ break;
+ case 4:
+ temp |= PIPE_DDI_PORT_WIDTH_X4;
+ break;
+ default:
+ temp |= PIPE_DDI_PORT_WIDTH_X4;
+ WARN(1, "Unsupported lane count %d\n",
+ intel_dp->lane_count);
+ }
+
} else {
WARN(1, "Invalid encoder type %d for pipe %d\n",
intel_encoder->type, pipe);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index fcce392..871bc17 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -77,11 +77,6 @@ static bool is_cpu_edp(struct intel_dp *intel_dp)
return is_edp(intel_dp) && !is_pch_edp(intel_dp);
}
-static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
-{
- return container_of(encoder, struct intel_dp, base.base);
-}
-
static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
{
return container_of(intel_attached_encoder(connector),
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 245319a..7e1e670 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -474,6 +474,11 @@ static inline struct intel_encoder *intel_attached_encoder(struct drm_connector
return to_intel_connector(connector)->encoder;
}
+static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
+{
+ return container_of(encoder, struct intel_dp, base.base);
+}
+
extern void intel_connector_attach_encoder(struct intel_connector *connector,
struct intel_encoder *encoder);
extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
--
1.7.11.4
^ permalink raw reply related [flat|nested] 34+ messages in thread
* Re: [PATCH 01/14] drm/i915: add DP support to intel_ddi_enable_pipe_func
2012-10-15 18:51 ` [PATCH 01/14] drm/i915: add DP support to intel_ddi_enable_pipe_func Paulo Zanoni
@ 2012-10-16 10:04 ` Jani Nikula
0 siblings, 0 replies; 34+ messages in thread
From: Jani Nikula @ 2012-10-16 10:04 UTC (permalink / raw)
To: Paulo Zanoni, intel-gfx; +Cc: Paulo Zanoni
On Mon, 15 Oct 2012, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 34 ++++++++++++++++++++++++++++++----
> drivers/gpu/drm/i915/intel_dp.c | 5 -----
> drivers/gpu/drm/i915/intel_drv.h | 5 +++++
> 3 files changed, 35 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index a78860a..9659c227 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -831,8 +831,10 @@ void intel_ddi_enable_pipe_func(struct drm_crtc *crtc)
> {
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
> + struct drm_encoder *encoder = &intel_encoder->base;
> struct drm_i915_private *dev_priv = crtc->dev->dev_private;
> enum pipe pipe = intel_crtc->pipe;
> + int type = intel_encoder->type;
> uint32_t temp;
>
> /* Enable PIPE_DDI_FUNC_CTL for the pipe to work in HDMI mode */
> @@ -861,9 +863,8 @@ void intel_ddi_enable_pipe_func(struct drm_crtc *crtc)
> if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
> temp |= PIPE_DDI_PHSYNC;
>
> - if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
> - struct intel_hdmi *intel_hdmi =
> - enc_to_intel_hdmi(&intel_encoder->base);
> + if (type == INTEL_OUTPUT_HDMI) {
> + struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
>
> if (intel_hdmi->has_hdmi_sink)
> temp |= PIPE_DDI_MODE_SELECT_HDMI;
> @@ -871,9 +872,34 @@ void intel_ddi_enable_pipe_func(struct drm_crtc *crtc)
> temp |= PIPE_DDI_MODE_SELECT_DVI;
>
> temp |= PIPE_DDI_SELECT_PORT(intel_hdmi->ddi_port);
> - } else if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
> +
> + } else if (type == INTEL_OUTPUT_ANALOG) {
> temp |= PIPE_DDI_MODE_SELECT_FDI;
> temp |= PIPE_DDI_SELECT_PORT(PORT_E);
> +
> + } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
> + type == INTEL_OUTPUT_EDP) {
> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
> + temp |= PIPE_DDI_MODE_SELECT_DP_SST;
> + temp |= PIPE_DDI_SELECT_PORT(intel_dp->port);
> +
> + switch (intel_dp->lane_count) {
> + case 1:
> + temp |= PIPE_DDI_PORT_WIDTH_X1;
> + break;
> + case 2:
> + temp |= PIPE_DDI_PORT_WIDTH_X2;
> + break;
> + case 4:
> + temp |= PIPE_DDI_PORT_WIDTH_X4;
> + break;
> + default:
> + temp |= PIPE_DDI_PORT_WIDTH_X4;
> + WARN(1, "Unsupported lane count %d\n",
> + intel_dp->lane_count);
> + }
> +
> } else {
> WARN(1, "Invalid encoder type %d for pipe %d\n",
> intel_encoder->type, pipe);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index fcce392..871bc17 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -77,11 +77,6 @@ static bool is_cpu_edp(struct intel_dp *intel_dp)
> return is_edp(intel_dp) && !is_pch_edp(intel_dp);
> }
>
> -static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
> -{
> - return container_of(encoder, struct intel_dp, base.base);
> -}
> -
> static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
> {
> return container_of(intel_attached_encoder(connector),
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 245319a..7e1e670 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -474,6 +474,11 @@ static inline struct intel_encoder *intel_attached_encoder(struct drm_connector
> return to_intel_connector(connector)->encoder;
> }
>
> +static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
> +{
> + return container_of(encoder, struct intel_dp, base.base);
> +}
> +
> extern void intel_connector_attach_encoder(struct intel_connector *connector,
> struct intel_encoder *encoder);
> extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
> --
> 1.7.11.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH 02/14] drm/i915: add intel_ddi_set_pipe_settings
2012-10-15 18:51 [PATCH 00/14] Haswell DP enablement Paulo Zanoni
2012-10-15 18:51 ` [PATCH 01/14] drm/i915: add DP support to intel_ddi_enable_pipe_func Paulo Zanoni
@ 2012-10-15 18:51 ` Paulo Zanoni
2012-10-16 8:05 ` Jani Nikula
2012-10-15 18:51 ` [PATCH 03/14] drm/i915: add DP support to intel_ddi_pll_mode_set Paulo Zanoni
` (11 subsequent siblings)
13 siblings, 1 reply; 34+ messages in thread
From: Paulo Zanoni @ 2012-10-15 18:51 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
In theory, all the DDI pipe settings should be set here, including
timing and M/N registers. For now, let's just set the DP MSA
attributes.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 10 ++++++++++
drivers/gpu/drm/i915/intel_ddi.c | 34 ++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_display.c | 4 +++-
drivers/gpu/drm/i915/intel_drv.h | 1 +
4 files changed, 48 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8200c31..7ca8b7d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4533,6 +4533,16 @@
#define PIPE_CLK_SEL_DISABLED (0x0<<29)
#define PIPE_CLK_SEL_PORT(x) ((x+1)<<29)
+#define _PIPEA_MSA_MISC 0x60410
+#define _PIPEB_MSA_MISC 0x61410
+#define PIPE_MSA_MISC(pipe) _PIPE(pipe, _PIPEA_MSA_MISC, _PIPEB_MSA_MISC)
+#define PIPE_MSA_SYNC_CLK (1<<0)
+#define PIPE_MSA_6_BPC (0<<5)
+#define PIPE_MSA_8_BPC (1<<5)
+#define PIPE_MSA_10_BPC (2<<5)
+#define PIPE_MSA_12_BPC (3<<5)
+#define PIPE_MSA_16_BPC (3<<5)
+
/* LCPLL Control */
#define LCPLL_CTL 0x130040
#define LCPLL_PLL_DISABLE (1<<31)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 9659c227..e58df71 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -827,6 +827,40 @@ bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock)
return true;
}
+void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = crtc->dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
+ enum pipe pipe = intel_crtc->pipe;
+ int type = intel_encoder->type;
+ uint32_t temp;
+
+ if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
+
+ temp = PIPE_MSA_SYNC_CLK;
+ switch (intel_crtc->bpp) {
+ case 18:
+ temp |= PIPE_MSA_6_BPC;
+ break;
+ case 24:
+ temp |= PIPE_MSA_8_BPC;
+ break;
+ case 30:
+ temp |= PIPE_MSA_10_BPC;
+ break;
+ case 36:
+ temp |= PIPE_MSA_12_BPC;
+ break;
+ default:
+ temp |= PIPE_MSA_8_BPC;
+ WARN(1, "%d bpp unsupported by pipe DDI function\n",
+ intel_crtc->bpp);
+ }
+ I915_WRITE(PIPE_MSA_MISC(pipe), temp);
+ }
+}
+
void intel_ddi_enable_pipe_func(struct drm_crtc *crtc)
{
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 705ed80..f48986b9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3218,8 +3218,10 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
*/
intel_crtc_load_lut(crtc);
- if (IS_HASWELL(dev))
+ if (IS_HASWELL(dev)) {
+ intel_ddi_set_pipe_settings(crtc);
intel_ddi_enable_pipe_func(crtc);
+ }
intel_enable_pipe(dev_priv, pipe, is_pch_port);
intel_enable_plane(dev_priv, plane, pipe);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 7e1e670..ed75a36 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -597,5 +597,6 @@ extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock);
extern void intel_ddi_pre_enable(struct intel_encoder *intel_encoder);
extern void intel_ddi_post_disable(struct intel_encoder *intel_encoder);
extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
+extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
#endif /* __INTEL_DRV_H__ */
--
1.7.11.4
^ permalink raw reply related [flat|nested] 34+ messages in thread
* Re: [PATCH 02/14] drm/i915: add intel_ddi_set_pipe_settings
2012-10-15 18:51 ` [PATCH 02/14] drm/i915: add intel_ddi_set_pipe_settings Paulo Zanoni
@ 2012-10-16 8:05 ` Jani Nikula
0 siblings, 0 replies; 34+ messages in thread
From: Jani Nikula @ 2012-10-16 8:05 UTC (permalink / raw)
To: Paulo Zanoni, intel-gfx; +Cc: Paulo Zanoni
On Mon, 15 Oct 2012, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> In theory, all the DDI pipe settings should be set here, including
> timing and M/N registers. For now, let's just set the DP MSA
> attributes.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 10 ++++++++++
> drivers/gpu/drm/i915/intel_ddi.c | 34 ++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_display.c | 4 +++-
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> 4 files changed, 48 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8200c31..7ca8b7d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4533,6 +4533,16 @@
> #define PIPE_CLK_SEL_DISABLED (0x0<<29)
> #define PIPE_CLK_SEL_PORT(x) ((x+1)<<29)
>
> +#define _PIPEA_MSA_MISC 0x60410
> +#define _PIPEB_MSA_MISC 0x61410
> +#define PIPE_MSA_MISC(pipe) _PIPE(pipe, _PIPEA_MSA_MISC, _PIPEB_MSA_MISC)
> +#define PIPE_MSA_SYNC_CLK (1<<0)
> +#define PIPE_MSA_6_BPC (0<<5)
> +#define PIPE_MSA_8_BPC (1<<5)
> +#define PIPE_MSA_10_BPC (2<<5)
> +#define PIPE_MSA_12_BPC (3<<5)
> +#define PIPE_MSA_16_BPC (3<<5)
This should be (4<<5) per DP 1.2a. Not that it matters now, unused as it
is.
BR,
Jani.
> +
> /* LCPLL Control */
> #define LCPLL_CTL 0x130040
> #define LCPLL_PLL_DISABLE (1<<31)
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 9659c227..e58df71 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -827,6 +827,40 @@ bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock)
> return true;
> }
>
> +void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
> +{
> + struct drm_i915_private *dev_priv = crtc->dev->dev_private;
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> + struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
> + enum pipe pipe = intel_crtc->pipe;
> + int type = intel_encoder->type;
> + uint32_t temp;
> +
> + if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
> +
> + temp = PIPE_MSA_SYNC_CLK;
> + switch (intel_crtc->bpp) {
> + case 18:
> + temp |= PIPE_MSA_6_BPC;
> + break;
> + case 24:
> + temp |= PIPE_MSA_8_BPC;
> + break;
> + case 30:
> + temp |= PIPE_MSA_10_BPC;
> + break;
> + case 36:
> + temp |= PIPE_MSA_12_BPC;
> + break;
> + default:
> + temp |= PIPE_MSA_8_BPC;
> + WARN(1, "%d bpp unsupported by pipe DDI function\n",
> + intel_crtc->bpp);
> + }
> + I915_WRITE(PIPE_MSA_MISC(pipe), temp);
> + }
> +}
> +
> void intel_ddi_enable_pipe_func(struct drm_crtc *crtc)
> {
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 705ed80..f48986b9 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3218,8 +3218,10 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
> */
> intel_crtc_load_lut(crtc);
>
> - if (IS_HASWELL(dev))
> + if (IS_HASWELL(dev)) {
> + intel_ddi_set_pipe_settings(crtc);
> intel_ddi_enable_pipe_func(crtc);
> + }
>
> intel_enable_pipe(dev_priv, pipe, is_pch_port);
> intel_enable_plane(dev_priv, plane, pipe);
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 7e1e670..ed75a36 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -597,5 +597,6 @@ extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock);
> extern void intel_ddi_pre_enable(struct intel_encoder *intel_encoder);
> extern void intel_ddi_post_disable(struct intel_encoder *intel_encoder);
> extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
> +extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
>
> #endif /* __INTEL_DRV_H__ */
> --
> 1.7.11.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH 03/14] drm/i915: add DP support to intel_ddi_pll_mode_set
2012-10-15 18:51 [PATCH 00/14] Haswell DP enablement Paulo Zanoni
2012-10-15 18:51 ` [PATCH 01/14] drm/i915: add DP support to intel_ddi_enable_pipe_func Paulo Zanoni
2012-10-15 18:51 ` [PATCH 02/14] drm/i915: add intel_ddi_set_pipe_settings Paulo Zanoni
@ 2012-10-15 18:51 ` Paulo Zanoni
2012-10-15 18:51 ` [PATCH 04/14] drm/i915: add DP support to intel_ddi_disable_port Paulo Zanoni
` (10 subsequent siblings)
13 siblings, 0 replies; 34+ messages in thread
From: Paulo Zanoni @ 2012-10-15 18:51 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 25 ++++++++++++++++++++++++-
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index e58df71..5071370 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -763,6 +763,7 @@ bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock)
{
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
+ struct drm_encoder *encoder = &intel_encoder->base;
struct drm_i915_private *dev_priv = crtc->dev->dev_private;
struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
int type = intel_encoder->type;
@@ -773,7 +774,29 @@ bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock)
intel_ddi_put_crtc_pll(crtc);
- if (type == INTEL_OUTPUT_HDMI) {
+ if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ switch (intel_dp->link_bw) {
+ case DP_LINK_BW_1_62:
+ intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
+ break;
+ case DP_LINK_BW_2_7:
+ intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
+ break;
+ case DP_LINK_BW_5_4:
+ intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
+ break;
+ default:
+ DRM_ERROR("Link bandwidth %d unsupported\n",
+ intel_dp->link_bw);
+ return false;
+ }
+
+ /* We don't need to turn any PLL on because we'll use LCPLL. */
+ return true;
+
+ } else if (type == INTEL_OUTPUT_HDMI) {
int p, n2, r2;
if (plls->wrpll1_refcount == 0) {
--
1.7.11.4
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 04/14] drm/i915: add DP support to intel_ddi_disable_port
2012-10-15 18:51 [PATCH 00/14] Haswell DP enablement Paulo Zanoni
` (2 preceding siblings ...)
2012-10-15 18:51 ` [PATCH 03/14] drm/i915: add DP support to intel_ddi_pll_mode_set Paulo Zanoni
@ 2012-10-15 18:51 ` Paulo Zanoni
2012-10-16 10:05 ` Jani Nikula
2012-10-15 18:51 ` [PATCH 05/14] drm/i915: add DP support to intel_ddi_mode_set Paulo Zanoni
` (9 subsequent siblings)
13 siblings, 1 reply; 34+ messages in thread
From: Paulo Zanoni @ 2012-10-15 18:51 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Just a missing register. There is no problem to run this code when the
output is HDMI.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 5071370..4f03b1b 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1105,14 +1105,23 @@ void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
struct drm_i915_private *dev_priv = encoder->dev->dev_private;
enum port port = intel_ddi_get_encoder_port(intel_encoder);
uint32_t val;
+ bool wait = false;
val = I915_READ(DDI_BUF_CTL(port));
if (val & DDI_BUF_CTL_ENABLE) {
val &= ~DDI_BUF_CTL_ENABLE;
I915_WRITE(DDI_BUF_CTL(port), val);
- intel_wait_ddi_buf_idle(dev_priv, port);
+ wait = true;
}
+ val = I915_READ(DP_TP_CTL(port));
+ val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
+ val |= DP_TP_CTL_LINK_TRAIN_PAT1;
+ I915_WRITE(DP_TP_CTL(port), val);
+
+ if (wait)
+ intel_wait_ddi_buf_idle(dev_priv, port);
+
I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
}
--
1.7.11.4
^ permalink raw reply related [flat|nested] 34+ messages in thread
* Re: [PATCH 04/14] drm/i915: add DP support to intel_ddi_disable_port
2012-10-15 18:51 ` [PATCH 04/14] drm/i915: add DP support to intel_ddi_disable_port Paulo Zanoni
@ 2012-10-16 10:05 ` Jani Nikula
0 siblings, 0 replies; 34+ messages in thread
From: Jani Nikula @ 2012-10-16 10:05 UTC (permalink / raw)
To: Paulo Zanoni, intel-gfx; +Cc: Paulo Zanoni
On Mon, 15 Oct 2012, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Just a missing register. There is no problem to run this code when the
> output is HDMI.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 11 ++++++++++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 5071370..4f03b1b 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1105,14 +1105,23 @@ void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
> struct drm_i915_private *dev_priv = encoder->dev->dev_private;
> enum port port = intel_ddi_get_encoder_port(intel_encoder);
> uint32_t val;
> + bool wait = false;
>
> val = I915_READ(DDI_BUF_CTL(port));
> if (val & DDI_BUF_CTL_ENABLE) {
> val &= ~DDI_BUF_CTL_ENABLE;
> I915_WRITE(DDI_BUF_CTL(port), val);
> - intel_wait_ddi_buf_idle(dev_priv, port);
> + wait = true;
> }
>
> + val = I915_READ(DP_TP_CTL(port));
> + val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
> + val |= DP_TP_CTL_LINK_TRAIN_PAT1;
> + I915_WRITE(DP_TP_CTL(port), val);
> +
> + if (wait)
> + intel_wait_ddi_buf_idle(dev_priv, port);
> +
> I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
> }
>
> --
> 1.7.11.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH 05/14] drm/i915: add DP support to intel_ddi_mode_set
2012-10-15 18:51 [PATCH 00/14] Haswell DP enablement Paulo Zanoni
` (3 preceding siblings ...)
2012-10-15 18:51 ` [PATCH 04/14] drm/i915: add DP support to intel_ddi_disable_port Paulo Zanoni
@ 2012-10-15 18:51 ` Paulo Zanoni
2012-10-18 18:00 ` Lespiau, Damien
2012-10-15 18:51 ` [PATCH 06/14] drm/i915: add basic Haswell DP link train bits Paulo Zanoni
` (8 subsequent siblings)
13 siblings, 1 reply; 34+ messages in thread
From: Paulo Zanoni @ 2012-10-15 18:51 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 61 +++++++++++++++++++++++++++++-----------
drivers/gpu/drm/i915/intel_dp.c | 28 ++++++++++--------
drivers/gpu/drm/i915/intel_drv.h | 1 +
3 files changed, 62 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 4f03b1b..c6ddba9 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -644,28 +644,55 @@ void intel_ddi_mode_set(struct drm_encoder *encoder,
{
struct drm_crtc *crtc = encoder->crtc;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
- int port = intel_hdmi->ddi_port;
+ struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
+ int port = intel_ddi_get_encoder_port(intel_encoder);
int pipe = intel_crtc->pipe;
+ int type = intel_encoder->type;
- /* On Haswell, we need to enable the clocks and prepare DDI function to
- * work in HDMI mode for this pipe.
- */
- DRM_DEBUG_KMS("Preparing HDMI DDI mode for Haswell on port %c, pipe %c\n", port_name(port), pipe_name(pipe));
+ DRM_DEBUG_KMS("Preparing DDI mode for Haswell on port %c, pipe %c\n",
+ port_name(port), pipe_name(pipe));
- if (intel_hdmi->has_audio) {
- /* Proper support for digital audio needs a new logic and a new set
- * of registers, so we leave it for future patch bombing.
- */
- DRM_DEBUG_DRIVER("HDMI audio on pipe %c on DDI\n",
- pipe_name(intel_crtc->pipe));
+ if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
- /* write eld */
- DRM_DEBUG_DRIVER("HDMI audio: write eld information\n");
- intel_write_eld(encoder, adjusted_mode);
- }
+ intel_dp->DP = DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW;
+ switch (intel_dp->lane_count) {
+ case 1:
+ intel_dp->DP |= DDI_PORT_WIDTH_X1;
+ break;
+ case 2:
+ intel_dp->DP |= DDI_PORT_WIDTH_X2;
+ break;
+ case 4:
+ intel_dp->DP |= DDI_PORT_WIDTH_X4;
+ break;
+ default:
+ intel_dp->DP |= DDI_PORT_WIDTH_X4;
+ WARN(1, "Unexpected DP lane count %d\n",
+ intel_dp->lane_count);
+ break;
+ }
+
+ intel_dp_init_link_config(intel_dp);
- intel_hdmi->set_infoframes(encoder, adjusted_mode);
+ } else if (type == INTEL_OUTPUT_HDMI) {
+ struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
+
+ if (intel_hdmi->has_audio) {
+ /* Proper support for digital audio needs a new logic
+ * and a new set of registers, so we leave it for future
+ * patch bombing.
+ */
+ DRM_DEBUG_DRIVER("HDMI audio on pipe %c on DDI\n",
+ pipe_name(intel_crtc->pipe));
+
+ /* write eld */
+ DRM_DEBUG_DRIVER("HDMI audio: write eld information\n");
+ intel_write_eld(encoder, adjusted_mode);
+ }
+
+ intel_hdmi->set_infoframes(encoder, adjusted_mode);
+ }
}
static struct intel_encoder *
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 871bc17..3fa71cd 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -815,6 +815,21 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
}
}
+void intel_dp_init_link_config(struct intel_dp *intel_dp)
+{
+ memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
+ intel_dp->link_configuration[0] = intel_dp->link_bw;
+ intel_dp->link_configuration[1] = intel_dp->lane_count;
+ intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
+ /*
+ * Check for DPCD version > 1.1 and enhanced framing support
+ */
+ if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
+ (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
+ intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
+ }
+}
+
static void
intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
@@ -867,17 +882,8 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
intel_write_eld(encoder, adjusted_mode);
}
- memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
- intel_dp->link_configuration[0] = intel_dp->link_bw;
- intel_dp->link_configuration[1] = intel_dp->lane_count;
- intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
- /*
- * Check for DPCD version > 1.1 and enhanced framing support
- */
- if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
- (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
- intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
- }
+
+ intel_dp_init_link_config(intel_dp);
/* Split out the IBX/CPU vs CPT settings */
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index ed75a36..d89d428 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -422,6 +422,7 @@ extern void intel_dp_init(struct drm_device *dev, int output_reg,
void
intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode);
+extern void intel_dp_init_link_config(struct intel_dp *intel_dp);
extern bool intel_dpd_is_edp(struct drm_device *dev);
extern void intel_edp_link_config(struct intel_encoder *, int *, int *);
extern int intel_edp_target_clock(struct intel_encoder *,
--
1.7.11.4
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 06/14] drm/i915: add basic Haswell DP link train bits
2012-10-15 18:51 [PATCH 00/14] Haswell DP enablement Paulo Zanoni
` (4 preceding siblings ...)
2012-10-15 18:51 ` [PATCH 05/14] drm/i915: add DP support to intel_ddi_mode_set Paulo Zanoni
@ 2012-10-15 18:51 ` Paulo Zanoni
2012-10-16 11:47 ` Jani Nikula
2012-10-15 18:51 ` [PATCH 07/14] drm/i915: use TU_SIZE macro at intel_dp_set_m_n Paulo Zanoni
` (7 subsequent siblings)
13 siblings, 1 reply; 34+ messages in thread
From: Paulo Zanoni @ 2012-10-15 18:51 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Previously, the DP register was used for everything. On Haswell, it
was split into DDI_BUF_CTL (which is the new intel_dp->DP register)
and DP_TP_CTL.
The logic behind this patch is based on a patch written by Shobhit
Kumar, but the way the code was written is very different.
Credits-to: Shobhit Kumar <shobhit.kumar@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 4 ++
drivers/gpu/drm/i915/intel_dp.c | 104 +++++++++++++++++++++++++++++++++++++---
2 files changed, 102 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7ca8b7d..68ce163 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4426,12 +4426,16 @@
#define DP_TP_CTL_LINK_TRAIN_MASK (7<<8)
#define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8)
#define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8)
+#define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8)
+#define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8)
#define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8)
+#define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7)
/* DisplayPort Transport Status */
#define DP_TP_STATUS_A 0x64044
#define DP_TP_STATUS_B 0x64144
#define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B)
+#define DP_TP_STATUS_IDLE_DONE (1<<25)
#define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12)
/* DDI Buffer Control */
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 3fa71cd..b10f35b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1476,7 +1476,19 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
{
struct drm_device *dev = intel_dp->base.base.dev;
- if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
+ if (IS_HASWELL(dev)) {
+ switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
+ case DP_TRAIN_VOLTAGE_SWING_400:
+ return DP_TRAIN_PRE_EMPHASIS_9_5;
+ case DP_TRAIN_VOLTAGE_SWING_600:
+ return DP_TRAIN_PRE_EMPHASIS_6;
+ case DP_TRAIN_VOLTAGE_SWING_800:
+ return DP_TRAIN_PRE_EMPHASIS_3_5;
+ case DP_TRAIN_VOLTAGE_SWING_1200:
+ default:
+ return DP_TRAIN_PRE_EMPHASIS_0;
+ }
+ } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
case DP_TRAIN_VOLTAGE_SWING_400:
return DP_TRAIN_PRE_EMPHASIS_6;
@@ -1630,6 +1642,40 @@ intel_gen7_edp_signal_levels(uint8_t train_set)
}
}
+/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
+static uint32_t
+intel_dp_signal_levels_hsw(uint8_t train_set)
+{
+ int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
+ DP_TRAIN_PRE_EMPHASIS_MASK);
+ switch (signal_levels) {
+ case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
+ return DDI_BUF_EMP_400MV_0DB_HSW;
+ case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
+ return DDI_BUF_EMP_400MV_3_5DB_HSW;
+ case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
+ return DDI_BUF_EMP_400MV_6DB_HSW;
+ case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
+ return DDI_BUF_EMP_400MV_9_5DB_HSW;
+
+ case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
+ return DDI_BUF_EMP_600MV_0DB_HSW;
+ case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
+ return DDI_BUF_EMP_600MV_3_5DB_HSW;
+ case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
+ return DDI_BUF_EMP_600MV_6DB_HSW;
+
+ case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
+ return DDI_BUF_EMP_800MV_0DB_HSW;
+ case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
+ return DDI_BUF_EMP_800MV_3_5DB_HSW;
+ default:
+ DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
+ "0x%x\n", signal_levels);
+ return DDI_BUF_EMP_400MV_0DB_HSW;
+ }
+}
+
static uint8_t
intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
int lane)
@@ -1686,8 +1732,44 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
struct drm_device *dev = intel_dp->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
int ret;
+ uint32_t temp;
- if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
+ if (IS_HASWELL(dev)) {
+ temp = I915_READ(DP_TP_CTL(intel_dp->port));
+
+ if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
+ temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
+ else
+ temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
+
+ temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
+ switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
+ case DP_TRAINING_PATTERN_DISABLE:
+ temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
+ I915_WRITE(DP_TP_CTL(intel_dp->port), temp);
+
+ if (wait_for((I915_READ(DP_TP_STATUS(intel_dp->port)) &
+ DP_TP_STATUS_IDLE_DONE) == 0, 1))
+ DRM_ERROR("Timed out waiting for DP idle patterns\n");
+
+ temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
+ temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
+
+ break;
+ case DP_TRAINING_PATTERN_1:
+ temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
+ break;
+ case DP_TRAINING_PATTERN_2:
+ temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
+ break;
+ case DP_TRAINING_PATTERN_3:
+ temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
+ break;
+ }
+ I915_WRITE(DP_TP_CTL(intel_dp->port), temp);
+
+ } else if (HAS_PCH_CPT(dev) &&
+ (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
@@ -1774,8 +1856,11 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
uint8_t link_status[DP_LINK_STATUS_SIZE];
uint32_t signal_levels;
-
- if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
+ if (IS_HASWELL(dev)) {
+ signal_levels = intel_dp_signal_levels_hsw(
+ intel_dp->train_set[0]);
+ DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
+ } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
@@ -1783,9 +1868,10 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
} else {
signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
- DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);
DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
}
+ DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n",
+ signal_levels);
if (!intel_dp_set_link_train(intel_dp, DP,
DP_TRAINING_PATTERN_1 |
@@ -1861,7 +1947,10 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
break;
}
- if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
+ if (IS_HASWELL(dev)) {
+ signal_levels = intel_dp_signal_levels_hsw(intel_dp->train_set[0]);
+ DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
+ } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
@@ -1908,6 +1997,9 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
++tries;
}
+ if (channel_eq)
+ DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
+
intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
}
--
1.7.11.4
^ permalink raw reply related [flat|nested] 34+ messages in thread
* Re: [PATCH 06/14] drm/i915: add basic Haswell DP link train bits
2012-10-15 18:51 ` [PATCH 06/14] drm/i915: add basic Haswell DP link train bits Paulo Zanoni
@ 2012-10-16 11:47 ` Jani Nikula
0 siblings, 0 replies; 34+ messages in thread
From: Jani Nikula @ 2012-10-16 11:47 UTC (permalink / raw)
To: Paulo Zanoni, intel-gfx; +Cc: Paulo Zanoni
On Mon, 15 Oct 2012, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Previously, the DP register was used for everything. On Haswell, it
> was split into DDI_BUF_CTL (which is the new intel_dp->DP register)
> and DP_TP_CTL.
>
> The logic behind this patch is based on a patch written by Shobhit
> Kumar, but the way the code was written is very different.
>
> Credits-to: Shobhit Kumar <shobhit.kumar@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 ++
> drivers/gpu/drm/i915/intel_dp.c | 104 +++++++++++++++++++++++++++++++++++++---
> 2 files changed, 102 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7ca8b7d..68ce163 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4426,12 +4426,16 @@
> #define DP_TP_CTL_LINK_TRAIN_MASK (7<<8)
> #define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8)
> #define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8)
> +#define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8)
> +#define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8)
> #define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8)
> +#define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7)
>
> /* DisplayPort Transport Status */
> #define DP_TP_STATUS_A 0x64044
> #define DP_TP_STATUS_B 0x64144
> #define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B)
> +#define DP_TP_STATUS_IDLE_DONE (1<<25)
> #define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12)
>
> /* DDI Buffer Control */
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 3fa71cd..b10f35b 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1476,7 +1476,19 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
> {
> struct drm_device *dev = intel_dp->base.base.dev;
>
> - if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
> + if (IS_HASWELL(dev)) {
> + switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> + case DP_TRAIN_VOLTAGE_SWING_400:
> + return DP_TRAIN_PRE_EMPHASIS_9_5;
> + case DP_TRAIN_VOLTAGE_SWING_600:
> + return DP_TRAIN_PRE_EMPHASIS_6;
> + case DP_TRAIN_VOLTAGE_SWING_800:
> + return DP_TRAIN_PRE_EMPHASIS_3_5;
> + case DP_TRAIN_VOLTAGE_SWING_1200:
> + default:
> + return DP_TRAIN_PRE_EMPHASIS_0;
> + }
> + } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
> switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> case DP_TRAIN_VOLTAGE_SWING_400:
> return DP_TRAIN_PRE_EMPHASIS_6;
> @@ -1630,6 +1642,40 @@ intel_gen7_edp_signal_levels(uint8_t train_set)
> }
> }
>
> +/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
> +static uint32_t
> +intel_dp_signal_levels_hsw(uint8_t train_set)
> +{
> + int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
> + DP_TRAIN_PRE_EMPHASIS_MASK);
> + switch (signal_levels) {
> + case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
> + return DDI_BUF_EMP_400MV_0DB_HSW;
> + case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
> + return DDI_BUF_EMP_400MV_3_5DB_HSW;
> + case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
> + return DDI_BUF_EMP_400MV_6DB_HSW;
> + case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
> + return DDI_BUF_EMP_400MV_9_5DB_HSW;
> +
> + case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
> + return DDI_BUF_EMP_600MV_0DB_HSW;
> + case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
> + return DDI_BUF_EMP_600MV_3_5DB_HSW;
> + case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
> + return DDI_BUF_EMP_600MV_6DB_HSW;
> +
> + case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
> + return DDI_BUF_EMP_800MV_0DB_HSW;
> + case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
> + return DDI_BUF_EMP_800MV_3_5DB_HSW;
> + default:
> + DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
> + "0x%x\n", signal_levels);
> + return DDI_BUF_EMP_400MV_0DB_HSW;
> + }
> +}
> +
> static uint8_t
> intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
> int lane)
> @@ -1686,8 +1732,44 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
> struct drm_device *dev = intel_dp->base.base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> int ret;
> + uint32_t temp;
>
> - if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
> + if (IS_HASWELL(dev)) {
> + temp = I915_READ(DP_TP_CTL(intel_dp->port));
> +
> + if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
> + temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
> + else
> + temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
> +
> + temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
> + switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
> + case DP_TRAINING_PATTERN_DISABLE:
> + temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
> + I915_WRITE(DP_TP_CTL(intel_dp->port), temp);
> +
> + if (wait_for((I915_READ(DP_TP_STATUS(intel_dp->port)) &
> + DP_TP_STATUS_IDLE_DONE) == 0, 1))
Shouldn't this wait for DP_TP_STATUS_IDLE_DONE to be set?
Otherwise,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> + DRM_ERROR("Timed out waiting for DP idle patterns\n");
> +
> + temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
> + temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
> +
> + break;
> + case DP_TRAINING_PATTERN_1:
> + temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
> + break;
> + case DP_TRAINING_PATTERN_2:
> + temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
> + break;
> + case DP_TRAINING_PATTERN_3:
> + temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
> + break;
> + }
> + I915_WRITE(DP_TP_CTL(intel_dp->port), temp);
> +
> + } else if (HAS_PCH_CPT(dev) &&
> + (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
> dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
>
> switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
> @@ -1774,8 +1856,11 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
> uint8_t link_status[DP_LINK_STATUS_SIZE];
> uint32_t signal_levels;
>
> -
> - if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
> + if (IS_HASWELL(dev)) {
> + signal_levels = intel_dp_signal_levels_hsw(
> + intel_dp->train_set[0]);
> + DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
> + } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
> signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
> DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
> } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
> @@ -1783,9 +1868,10 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
> DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
> } else {
> signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
> - DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);
> DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
> }
> + DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n",
> + signal_levels);
>
> if (!intel_dp_set_link_train(intel_dp, DP,
> DP_TRAINING_PATTERN_1 |
> @@ -1861,7 +1947,10 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
> break;
> }
>
> - if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
> + if (IS_HASWELL(dev)) {
> + signal_levels = intel_dp_signal_levels_hsw(intel_dp->train_set[0]);
> + DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
> + } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
> signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
> DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
> } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
> @@ -1908,6 +1997,9 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
> ++tries;
> }
>
> + if (channel_eq)
> + DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
> +
> intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
> }
>
> --
> 1.7.11.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH 07/14] drm/i915: use TU_SIZE macro at intel_dp_set_m_n
2012-10-15 18:51 [PATCH 00/14] Haswell DP enablement Paulo Zanoni
` (5 preceding siblings ...)
2012-10-15 18:51 ` [PATCH 06/14] drm/i915: add basic Haswell DP link train bits Paulo Zanoni
@ 2012-10-15 18:51 ` Paulo Zanoni
2012-10-16 11:49 ` Jani Nikula
2012-10-15 18:51 ` [PATCH 08/14] drm/i915: fix Haswell DP M/N registers Paulo Zanoni
` (6 subsequent siblings)
13 siblings, 1 reply; 34+ messages in thread
From: Paulo Zanoni @ 2012-10-15 18:51 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Much simpler and looks more like the M/N code inside intel_display.c.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b10f35b..52b5453 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -794,9 +794,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
mode->clock, adjusted_mode->clock, &m_n);
if (HAS_PCH_SPLIT(dev)) {
- I915_WRITE(TRANSDATA_M1(pipe),
- ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
- m_n.gmch_m);
+ I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
@@ -807,8 +805,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
} else {
I915_WRITE(PIPE_GMCH_DATA_M(pipe),
- ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
- m_n.gmch_m);
+ TU_SIZE(m_n.tu) | m_n.gmch_m);
I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
--
1.7.11.4
^ permalink raw reply related [flat|nested] 34+ messages in thread
* Re: [PATCH 07/14] drm/i915: use TU_SIZE macro at intel_dp_set_m_n
2012-10-15 18:51 ` [PATCH 07/14] drm/i915: use TU_SIZE macro at intel_dp_set_m_n Paulo Zanoni
@ 2012-10-16 11:49 ` Jani Nikula
2012-10-17 20:27 ` Daniel Vetter
0 siblings, 1 reply; 34+ messages in thread
From: Jani Nikula @ 2012-10-16 11:49 UTC (permalink / raw)
To: Paulo Zanoni, intel-gfx; +Cc: Paulo Zanoni
On Mon, 15 Oct 2012, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Much simpler and looks more like the M/N code inside intel_display.c.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 7 ++-----
> 1 file changed, 2 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index b10f35b..52b5453 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -794,9 +794,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
> mode->clock, adjusted_mode->clock, &m_n);
>
> if (HAS_PCH_SPLIT(dev)) {
> - I915_WRITE(TRANSDATA_M1(pipe),
> - ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
> - m_n.gmch_m);
> + I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
> I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
> I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
> I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
> @@ -807,8 +805,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
> I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
> } else {
> I915_WRITE(PIPE_GMCH_DATA_M(pipe),
> - ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
> - m_n.gmch_m);
> + TU_SIZE(m_n.tu) | m_n.gmch_m);
> I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
> I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
> I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
> --
> 1.7.11.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 07/14] drm/i915: use TU_SIZE macro at intel_dp_set_m_n
2012-10-16 11:49 ` Jani Nikula
@ 2012-10-17 20:27 ` Daniel Vetter
2012-10-18 17:14 ` Paulo Zanoni
0 siblings, 1 reply; 34+ messages in thread
From: Daniel Vetter @ 2012-10-17 20:27 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, Paulo Zanoni
On Tue, Oct 16, 2012 at 02:49:58PM +0300, Jani Nikula wrote:
> On Mon, 15 Oct 2012, Paulo Zanoni <przanoni@gmail.com> wrote:
> > From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> >
> > Much simpler and looks more like the M/N code inside intel_display.c.
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Merged up to this patch, thanks.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 07/14] drm/i915: use TU_SIZE macro at intel_dp_set_m_n
2012-10-17 20:27 ` Daniel Vetter
@ 2012-10-18 17:14 ` Paulo Zanoni
2012-10-18 19:36 ` Daniel Vetter
0 siblings, 1 reply; 34+ messages in thread
From: Paulo Zanoni @ 2012-10-18 17:14 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx, Paulo Zanoni
Hi
2012/10/17 Daniel Vetter <daniel@ffwll.ch>:
> On Tue, Oct 16, 2012 at 02:49:58PM +0300, Jani Nikula wrote:
>> On Mon, 15 Oct 2012, Paulo Zanoni <przanoni@gmail.com> wrote:
>> > From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>> >
>> > Much simpler and looks more like the M/N code inside intel_display.c.
>>
>> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
> Merged up to this patch, thanks.
No. Actually I think we're missing patches 4 and 5. Patch 4 has a R-B,
but 5 doesn't.
After this, we still need 9 (just resent), then 13 and 14.
> -Daniel
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
--
Paulo Zanoni
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 07/14] drm/i915: use TU_SIZE macro at intel_dp_set_m_n
2012-10-18 17:14 ` Paulo Zanoni
@ 2012-10-18 19:36 ` Daniel Vetter
0 siblings, 0 replies; 34+ messages in thread
From: Daniel Vetter @ 2012-10-18 19:36 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx, Paulo Zanoni
On Thu, Oct 18, 2012 at 02:14:52PM -0300, Paulo Zanoni wrote:
> Hi
>
> 2012/10/17 Daniel Vetter <daniel@ffwll.ch>:
> > On Tue, Oct 16, 2012 at 02:49:58PM +0300, Jani Nikula wrote:
> >> On Mon, 15 Oct 2012, Paulo Zanoni <przanoni@gmail.com> wrote:
> >> > From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> >> >
> >> > Much simpler and looks more like the M/N code inside intel_display.c.
> >>
> >> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> >
> > Merged up to this patch, thanks.
>
> No. Actually I think we're missing patches 4 and 5. Patch 4 has a R-B,
> but 5 doesn't.
Yeah, I've made a bit a mess ;-) Should be all merged now, thanks for
patches and review.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH 08/14] drm/i915: fix Haswell DP M/N registers
2012-10-15 18:51 [PATCH 00/14] Haswell DP enablement Paulo Zanoni
` (6 preceding siblings ...)
2012-10-15 18:51 ` [PATCH 07/14] drm/i915: use TU_SIZE macro at intel_dp_set_m_n Paulo Zanoni
@ 2012-10-15 18:51 ` Paulo Zanoni
2012-10-15 20:29 ` Adam Jackson
2012-10-18 15:42 ` [PATCH 08/83] " Paulo Zanoni
2012-10-15 18:51 ` [PATCH 09/14] drm/i915: fix DP AUX register definitions on Haswell Paulo Zanoni
` (5 subsequent siblings)
13 siblings, 2 replies; 34+ messages in thread
From: Paulo Zanoni @ 2012-10-15 18:51 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
We have to write the correct values inside intel_dp_set_m_n and then
prevent these values from being overwritten later.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 3 ++-
drivers/gpu/drm/i915/intel_dp.c | 7 ++++++-
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f48986b9..ba40aa7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5356,7 +5356,8 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
- ironlake_set_m_n(crtc, mode, adjusted_mode);
+ if (!(is_dp && !is_cpu_edp))
+ ironlake_set_m_n(crtc, mode, adjusted_mode);
if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
if (is_cpu_edp)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 52b5453..22702df 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -793,7 +793,12 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
mode->clock, adjusted_mode->clock, &m_n);
- if (HAS_PCH_SPLIT(dev)) {
+ if (IS_HASWELL(dev)) {
+ I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
+ I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
+ I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
+ I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
+ } else if (HAS_PCH_SPLIT(dev)) {
I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
--
1.7.11.4
^ permalink raw reply related [flat|nested] 34+ messages in thread
* Re: [PATCH 08/14] drm/i915: fix Haswell DP M/N registers
2012-10-15 18:51 ` [PATCH 08/14] drm/i915: fix Haswell DP M/N registers Paulo Zanoni
@ 2012-10-15 20:29 ` Adam Jackson
2012-10-15 20:39 ` Daniel Vetter
2012-10-18 15:42 ` [PATCH 08/83] " Paulo Zanoni
1 sibling, 1 reply; 34+ messages in thread
From: Adam Jackson @ 2012-10-15 20:29 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx, Paulo Zanoni
On 10/15/12 2:51 PM, Paulo Zanoni wrote:
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index f48986b9..ba40aa7 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5356,7 +5356,8 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
>
> intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
>
> - ironlake_set_m_n(crtc, mode, adjusted_mode);
> + if (!(is_dp && !is_cpu_edp))
> + ironlake_set_m_n(crtc, mode, adjusted_mode);
The double-negation here hurts my brain. I think this would be clearer
and equivalent phrased positively:
if (!is_dp || is_pch_edp)
ironlake_set_m_n(crtc, mode, adjusted_mode);
- ajax
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 08/14] drm/i915: fix Haswell DP M/N registers
2012-10-15 20:29 ` Adam Jackson
@ 2012-10-15 20:39 ` Daniel Vetter
2012-10-15 20:45 ` Paulo Zanoni
0 siblings, 1 reply; 34+ messages in thread
From: Daniel Vetter @ 2012-10-15 20:39 UTC (permalink / raw)
To: Adam Jackson; +Cc: intel-gfx, Paulo Zanoni
On Mon, Oct 15, 2012 at 10:29 PM, Adam Jackson <ajax@redhat.com> wrote:
> On 10/15/12 2:51 PM, Paulo Zanoni wrote:
>
>> diff --git a/drivers/gpu/drm/i915/intel_display.c
>> b/drivers/gpu/drm/i915/intel_display.c
>> index f48986b9..ba40aa7 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -5356,7 +5356,8 @@ static int haswell_crtc_mode_set(struct drm_crtc
>> *crtc,
>>
>> intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
>>
>> - ironlake_set_m_n(crtc, mode, adjusted_mode);
>> + if (!(is_dp && !is_cpu_edp))
>> + ironlake_set_m_n(crtc, mode, adjusted_mode);
>
>
> The double-negation here hurts my brain. I think this would be clearer and
> equivalent phrased positively:
>
> if (!is_dp || is_pch_edp)
> ironlake_set_m_n(crtc, mode, adjusted_mode);
pch_edp doesn't really exist (since nothing much is still on the pch,
only the vga port is left), so not really clearer. I suspect we
actually want a !is_dp check in there - since the eDP enabling is
later in the series all edp checks don't really matter anyway.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 08/14] drm/i915: fix Haswell DP M/N registers
2012-10-15 20:39 ` Daniel Vetter
@ 2012-10-15 20:45 ` Paulo Zanoni
0 siblings, 0 replies; 34+ messages in thread
From: Paulo Zanoni @ 2012-10-15 20:45 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx, Paulo Zanoni
Hi
2012/10/15 Daniel Vetter <daniel@ffwll.ch>:
> On Mon, Oct 15, 2012 at 10:29 PM, Adam Jackson <ajax@redhat.com> wrote:
>> On 10/15/12 2:51 PM, Paulo Zanoni wrote:
>>
>>> diff --git a/drivers/gpu/drm/i915/intel_display.c
>>> b/drivers/gpu/drm/i915/intel_display.c
>>> index f48986b9..ba40aa7 100644
>>> --- a/drivers/gpu/drm/i915/intel_display.c
>>> +++ b/drivers/gpu/drm/i915/intel_display.c
>>> @@ -5356,7 +5356,8 @@ static int haswell_crtc_mode_set(struct drm_crtc
>>> *crtc,
>>>
>>> intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
>>>
>>> - ironlake_set_m_n(crtc, mode, adjusted_mode);
>>> + if (!(is_dp && !is_cpu_edp))
>>> + ironlake_set_m_n(crtc, mode, adjusted_mode);
>>
>>
>> The double-negation here hurts my brain. I think this would be clearer and
>> equivalent phrased positively:
>>
>> if (!is_dp || is_pch_edp)
>> ironlake_set_m_n(crtc, mode, adjusted_mode);
>
> pch_edp doesn't really exist (since nothing much is still on the pch,
> only the vga port is left),
I believe Adam wanted to say "if (!is_dp || is_cpu_edp)", there's no
pch_edp check :)
The check is in its current form because a few lines above there's a
"if (is_dp && !is_cpu_edp)", so this one just added a negation to the
previous test. I also agree that double-negation hurts brains, so no
problem in changing that.
> so not really clearer. I suspect we
> actually want a !is_dp check in there - since the eDP enabling is
> later in the series all edp checks don't really matter anyway.
> -Daniel
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
--
Paulo Zanoni
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH 08/83] drm/i915: fix Haswell DP M/N registers
2012-10-15 18:51 ` [PATCH 08/14] drm/i915: fix Haswell DP M/N registers Paulo Zanoni
2012-10-15 20:29 ` Adam Jackson
@ 2012-10-18 15:42 ` Paulo Zanoni
1 sibling, 0 replies; 34+ messages in thread
From: Paulo Zanoni @ 2012-10-18 15:42 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
We have to write the correct values inside intel_dp_set_m_n and then
prevent these values from being overwritten later.
V2: Unconfuse double negation.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 3 ++-
drivers/gpu/drm/i915/intel_dp.c | 7 ++++++-
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f48986b9..ba40aa7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5356,7 +5356,8 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
- ironlake_set_m_n(crtc, mode, adjusted_mode);
+ if (!is_dp || is_cpu_edp)
+ ironlake_set_m_n(crtc, mode, adjusted_mode);
if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
if (is_cpu_edp)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 52b5453..22702df 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -793,7 +793,12 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
mode->clock, adjusted_mode->clock, &m_n);
- if (HAS_PCH_SPLIT(dev)) {
+ if (IS_HASWELL(dev)) {
+ I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
+ I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
+ I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
+ I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
+ } else if (HAS_PCH_SPLIT(dev)) {
I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
--
1.7.11.4
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 09/14] drm/i915: fix DP AUX register definitions on Haswell
2012-10-15 18:51 [PATCH 00/14] Haswell DP enablement Paulo Zanoni
` (7 preceding siblings ...)
2012-10-15 18:51 ` [PATCH 08/14] drm/i915: fix Haswell DP M/N registers Paulo Zanoni
@ 2012-10-15 18:51 ` Paulo Zanoni
2012-10-18 13:57 ` Lespiau, Damien
2012-10-15 18:51 ` [PATCH 10/14] drm/i915: add DP support to intel_ddi_get_encoder_port Paulo Zanoni
` (4 subsequent siblings)
13 siblings, 1 reply; 34+ messages in thread
From: Paulo Zanoni @ 2012-10-15 18:51 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
The old rule that the AUX registers are just an offset (+4 and +10)
from output_reg is not true anymore, since output_reg in on the CPU
and some AUX regs are on the PCH.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
drivers/gpu/drm/i915/intel_dp.c | 23 +++++++++++++++++++++++
2 files changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 68ce163..84d9e69c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2548,6 +2548,14 @@
#define DPD_AUX_CH_DATA4 0x64320
#define DPD_AUX_CH_DATA5 0x64324
+#define PCH_DPB_AUX_CH_CTL 0xe4110
+#define PCH_DPC_AUX_CH_CTL 0xe4210
+#define PCH_DPD_AUX_CH_CTL 0xe4310
+
+#define PCH_DPB_AUX_CH_DATA 0xe4114
+#define PCH_DPC_AUX_CH_DATA 0xe4214
+#define PCH_DPD_AUX_CH_DATA 0xe4314
+
#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
#define DP_AUX_CH_CTL_DONE (1 << 30)
#define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 22702df..3a5fe2f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -356,6 +356,29 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
uint32_t aux_clock_divider;
int try, precharge;
+ if (IS_HASWELL(dev)) {
+ switch (intel_dp->port) {
+ case PORT_A:
+ ch_ctl = DPA_AUX_CH_CTL;
+ ch_data = DPA_AUX_CH_DATA1;
+ break;
+ case PORT_B:
+ ch_ctl = PCH_DPB_AUX_CH_CTL;
+ ch_data = PCH_DPB_AUX_CH_DATA;
+ break;
+ case PORT_C:
+ ch_ctl = PCH_DPC_AUX_CH_CTL;
+ ch_data = PCH_DPC_AUX_CH_DATA;
+ break;
+ case PORT_D:
+ ch_ctl = PCH_DPD_AUX_CH_CTL;
+ ch_data = PCH_DPD_AUX_CH_DATA;
+ break;
+ default:
+ BUG();
+ }
+ }
+
intel_dp_check_edp(intel_dp);
/* The clock divider is based off the hrawclk,
* and would like to run at 2MHz. So, take the
--
1.7.11.4
^ permalink raw reply related [flat|nested] 34+ messages in thread
* Re: [PATCH 09/14] drm/i915: fix DP AUX register definitions on Haswell
2012-10-15 18:51 ` [PATCH 09/14] drm/i915: fix DP AUX register definitions on Haswell Paulo Zanoni
@ 2012-10-18 13:57 ` Lespiau, Damien
0 siblings, 0 replies; 34+ messages in thread
From: Lespiau, Damien @ 2012-10-18 13:57 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx, Paulo Zanoni
On Mon, Oct 15, 2012 at 7:51 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> The old rule that the AUX registers are just an offset (+4 and +10)
> from output_reg is not true anymore, since output_reg in on the CPU
> and some AUX regs are on the PCH.
Right, dp.output_reg is now DDI_BUF_CTL(port), note that _DATA is
still _AUX_CH_CTL + 4, so could keep that logic and just have switch
for DP_AUX_CH_CTL.
> +#define PCH_DPB_AUX_CH_CTL 0xe4110
> +#define PCH_DPC_AUX_CH_CTL 0xe4210
> +#define PCH_DPD_AUX_CH_CTL 0xe4310
> +
> +#define PCH_DPB_AUX_CH_DATA 0xe4114
> +#define PCH_DPC_AUX_CH_DATA 0xe4214
> +#define PCH_DPD_AUX_CH_DATA 0xe4314
Those defines are already there AFAICS:
http://cgit.freedesktop.org/~danvet/drm-intel/tree/drivers/gpu/drm/i915/i915_reg.h#n4017
--
Damien
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH 10/14] drm/i915: add DP support to intel_ddi_get_encoder_port
2012-10-15 18:51 [PATCH 00/14] Haswell DP enablement Paulo Zanoni
` (8 preceding siblings ...)
2012-10-15 18:51 ` [PATCH 09/14] drm/i915: fix DP AUX register definitions on Haswell Paulo Zanoni
@ 2012-10-15 18:51 ` Paulo Zanoni
2012-10-18 14:06 ` Lespiau, Damien
2012-10-15 18:51 ` [PATCH 11/14] drm/i915: add DP support to intel_ddi_get_hw_state Paulo Zanoni
` (3 subsequent siblings)
13 siblings, 1 reply; 34+ messages in thread
From: Paulo Zanoni @ 2012-10-15 18:51 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index c6ddba9..817ebb2 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -60,14 +60,20 @@ static const u32 hsw_ddi_translations_fdi[] = {
static enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
{
+ struct drm_encoder *encoder = &intel_encoder->base;
int type = intel_encoder->type;
- if (type == INTEL_OUTPUT_HDMI) {
- struct intel_hdmi *intel_hdmi =
- enc_to_intel_hdmi(&intel_encoder->base);
+ if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ return intel_dp->port;
+
+ } else if (type == INTEL_OUTPUT_HDMI) {
+ struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
return intel_hdmi->ddi_port;
+
} else if (type == INTEL_OUTPUT_ANALOG) {
return PORT_E;
+
} else {
DRM_ERROR("Invalid DDI encoder type %d\n", type);
BUG();
--
1.7.11.4
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 11/14] drm/i915: add DP support to intel_ddi_get_hw_state
2012-10-15 18:51 [PATCH 00/14] Haswell DP enablement Paulo Zanoni
` (9 preceding siblings ...)
2012-10-15 18:51 ` [PATCH 10/14] drm/i915: add DP support to intel_ddi_get_encoder_port Paulo Zanoni
@ 2012-10-15 18:51 ` Paulo Zanoni
2012-10-18 14:14 ` Lespiau, Damien
2012-10-15 18:51 ` [PATCH 12/14] drm/i915: add DP support to intel_enable_ddi Paulo Zanoni
` (2 subsequent siblings)
13 siblings, 1 reply; 34+ messages in thread
From: Paulo Zanoni @ 2012-10-15 18:51 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 817ebb2..9324636 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1014,11 +1014,11 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
{
struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
+ enum port port = intel_ddi_get_encoder_port(encoder);
u32 tmp;
int i;
- tmp = I915_READ(DDI_BUF_CTL(intel_hdmi->ddi_port));
+ tmp = I915_READ(DDI_BUF_CTL(port));
if (!(tmp & DDI_BUF_CTL_ENABLE))
return false;
@@ -1027,13 +1027,13 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
tmp = I915_READ(DDI_FUNC_CTL(i));
if ((tmp & PIPE_DDI_PORT_MASK)
- == PIPE_DDI_SELECT_PORT(intel_hdmi->ddi_port)) {
+ == PIPE_DDI_SELECT_PORT(port)) {
*pipe = i;
return true;
}
}
- DRM_DEBUG_KMS("No pipe for ddi port %i found\n", intel_hdmi->ddi_port);
+ DRM_DEBUG_KMS("No pipe for ddi port %i found\n", port);
return true;
}
--
1.7.11.4
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 12/14] drm/i915: add DP support to intel_enable_ddi
2012-10-15 18:51 [PATCH 00/14] Haswell DP enablement Paulo Zanoni
` (10 preceding siblings ...)
2012-10-15 18:51 ` [PATCH 11/14] drm/i915: add DP support to intel_ddi_get_hw_state Paulo Zanoni
@ 2012-10-15 18:51 ` Paulo Zanoni
2012-10-18 14:20 ` Lespiau, Damien
2012-10-15 18:51 ` [PATCH 13/14] drm/i915: implement Haswell DP link train sequence Paulo Zanoni
2012-10-15 18:51 ` [PATCH 14/14] drm/i915: set the correct function pointers for Haswell DP Paulo Zanoni
13 siblings, 1 reply; 34+ messages in thread
From: Paulo Zanoni @ 2012-10-15 18:51 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
We should only write the DDI_BUF_CTL at this point for HDMI/DVI. For
DP we need to do this earlier, and the values written to the register
are also different.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 21 ++++++++++++---------
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 9324636..601ffc2 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1158,18 +1158,21 @@ void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
}
-void intel_enable_ddi(struct intel_encoder *encoder)
+void intel_enable_ddi(struct intel_encoder *intel_encoder)
{
- struct drm_device *dev = encoder->base.dev;
+ struct drm_encoder *encoder = &intel_encoder->base;
+ struct drm_device *dev = encoder->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
- int port = intel_hdmi->ddi_port;
+ enum port port = intel_ddi_get_encoder_port(intel_encoder);
+ int type = intel_encoder->type;
- /* Enable DDI_BUF_CTL. In HDMI/DVI mode, the port width,
- * and swing/emphasis values are ignored so nothing special needs
- * to be done besides enabling the port.
- */
- I915_WRITE(DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE);
+ if (type == INTEL_OUTPUT_HDMI) {
+ /* In HDMI/DVI mode, the port width, and swing/emphasis values
+ * are ignored so nothing special needs to be done besides
+ * enabling the port.
+ */
+ I915_WRITE(DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE);
+ }
}
void intel_disable_ddi(struct intel_encoder *encoder)
--
1.7.11.4
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH 13/14] drm/i915: implement Haswell DP link train sequence
2012-10-15 18:51 [PATCH 00/14] Haswell DP enablement Paulo Zanoni
` (11 preceding siblings ...)
2012-10-15 18:51 ` [PATCH 12/14] drm/i915: add DP support to intel_enable_ddi Paulo Zanoni
@ 2012-10-15 18:51 ` Paulo Zanoni
2012-10-18 17:34 ` Lespiau, Damien
2012-10-15 18:51 ` [PATCH 14/14] drm/i915: set the correct function pointers for Haswell DP Paulo Zanoni
13 siblings, 1 reply; 34+ messages in thread
From: Paulo Zanoni @ 2012-10-15 18:51 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Previous patch "drm/i915: add basic Haswell DP link train bits"
implemented the basic structure to set the voltage levels and training
patterns. This patch adds the higher-level bits that are part of the
mode set sequence and hot plug.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 53 ++++++++++++++++++++++++++++++++++++++--
drivers/gpu/drm/i915/intel_dp.c | 32 +++++++++++++++++++-----
drivers/gpu/drm/i915/intel_drv.h | 4 +++
3 files changed, 81 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 601ffc2..81cca48 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1108,14 +1108,23 @@ void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
{
- struct drm_crtc *crtc = intel_encoder->base.crtc;
- struct drm_i915_private *dev_priv = crtc->dev->dev_private;
+ struct drm_encoder *encoder = &intel_encoder->base;
+ struct drm_crtc *crtc = encoder->crtc;
+ struct drm_i915_private *dev_priv = encoder->dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
enum port port = intel_ddi_get_encoder_port(intel_encoder);
WARN_ON(intel_crtc->ddi_pll_sel == PORT_CLK_SEL_NONE);
I915_WRITE(PORT_CLK_SEL(port), intel_crtc->ddi_pll_sel);
+
+ if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+ intel_dp_start_link_train(intel_dp);
+ intel_dp_complete_link_train(intel_dp);
+ }
}
static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
@@ -1210,3 +1219,43 @@ void intel_ddi_pll_init(struct drm_device *dev)
if (val & LCPLL_PLL_DISABLE)
DRM_ERROR("LCPLL is disabled\n");
}
+
+void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
+{
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ struct drm_i915_private *dev_priv = encoder->dev->dev_private;
+ enum port port = intel_dp->port;
+ bool wait;
+ uint32_t val;
+
+ if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
+ val = I915_READ(DDI_BUF_CTL(port));
+ if (val & DDI_BUF_CTL_ENABLE) {
+ val &= ~DDI_BUF_CTL_ENABLE;
+ I915_WRITE(DDI_BUF_CTL(port), val);
+ wait = true;
+ }
+
+ val = I915_READ(DP_TP_CTL(port));
+ val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
+ val |= DP_TP_CTL_LINK_TRAIN_PAT1;
+ I915_WRITE(DP_TP_CTL(port), val);
+ POSTING_READ(DP_TP_CTL(port));
+
+ if (wait)
+ intel_wait_ddi_buf_idle(dev_priv, port);
+ }
+
+ val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST |
+ DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
+ if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
+ val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
+ I915_WRITE(DP_TP_CTL(port), val);
+ POSTING_READ(DP_TP_CTL(port));
+
+ intel_dp->DP |= DDI_BUF_CTL_ENABLE;
+ I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
+ POSTING_READ(DDI_BUF_CTL(port));
+
+ udelay(600);
+}
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 3a5fe2f..36687d9 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -102,8 +102,6 @@ bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
return is_pch_edp(intel_dp);
}
-static void intel_dp_start_link_train(struct intel_dp *intel_dp);
-static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
static void intel_dp_link_down(struct intel_dp *intel_dp);
void
@@ -1266,7 +1264,7 @@ static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
}
/* If the sink supports it, try to set the power state appropriately */
-static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
+void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
{
int ret, i;
@@ -1854,16 +1852,20 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
}
/* Enable corresponding port and start training pattern 1 */
-static void
+void
intel_dp_start_link_train(struct intel_dp *intel_dp)
{
- struct drm_device *dev = intel_dp->base.base.dev;
+ struct drm_encoder *encoder = &intel_dp->base.base;
+ struct drm_device *dev = encoder->dev;
int i;
uint8_t voltage;
bool clock_recovery = false;
int voltage_tries, loop_tries;
uint32_t DP = intel_dp->DP;
+ if (IS_HASWELL(dev))
+ intel_ddi_prepare_link_retrain(encoder);
+
/* Write the link configuration data */
intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
intel_dp->link_configuration,
@@ -1949,7 +1951,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
intel_dp->DP = DP;
}
-static void
+void
intel_dp_complete_link_train(struct intel_dp *intel_dp)
{
struct drm_device *dev = intel_dp->base.base.dev;
@@ -2035,6 +2037,24 @@ intel_dp_link_down(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = dev->dev_private;
uint32_t DP = intel_dp->DP;
+ /*
+ * DDI code has a strict mode set sequence and we should try to respect
+ * it, otherwise we might hang the machine in many different ways. So we
+ * really should be disabling the port only on a complete crtc_disable
+ * sequence. This function is just called under two conditions on DDI
+ * code:
+ * - Link train failed while doing crtc_enable, and on this case we
+ * really should respect the mode set sequence and wait for a
+ * crtc_disable.
+ * - Someone turned the monitor off and intel_dp_check_link_status
+ * called us. We don't need to disable the whole port on this case, so
+ * when someone turns the monitor on again,
+ * intel_ddi_prepare_link_retrain will take care of redoing the link
+ * train.
+ */
+ if (IS_HASWELL(dev))
+ return;
+
if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
return;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d89d428..95cbd67 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -423,6 +423,9 @@ void
intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode);
extern void intel_dp_init_link_config(struct intel_dp *intel_dp);
+extern void intel_dp_start_link_train(struct intel_dp *intel_dp);
+extern void intel_dp_complete_link_train(struct intel_dp *intel_dp);
+extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
extern bool intel_dpd_is_edp(struct drm_device *dev);
extern void intel_edp_link_config(struct intel_encoder *, int *, int *);
extern int intel_edp_target_clock(struct intel_encoder *,
@@ -599,5 +602,6 @@ extern void intel_ddi_pre_enable(struct intel_encoder *intel_encoder);
extern void intel_ddi_post_disable(struct intel_encoder *intel_encoder);
extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
+extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
#endif /* __INTEL_DRV_H__ */
--
1.7.11.4
^ permalink raw reply related [flat|nested] 34+ messages in thread
* Re: [PATCH 13/14] drm/i915: implement Haswell DP link train sequence
2012-10-15 18:51 ` [PATCH 13/14] drm/i915: implement Haswell DP link train sequence Paulo Zanoni
@ 2012-10-18 17:34 ` Lespiau, Damien
0 siblings, 0 replies; 34+ messages in thread
From: Lespiau, Damien @ 2012-10-18 17:34 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx, Paulo Zanoni
On Mon, Oct 15, 2012 at 7:51 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Previous patch "drm/i915: add basic Haswell DP link train bits"
> implemented the basic structure to set the voltage levels and training
> patterns. This patch adds the higher-level bits that are part of the
> mode set sequence and hot plug.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
--
Damien
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH 14/14] drm/i915: set the correct function pointers for Haswell DP
2012-10-15 18:51 [PATCH 00/14] Haswell DP enablement Paulo Zanoni
` (12 preceding siblings ...)
2012-10-15 18:51 ` [PATCH 13/14] drm/i915: implement Haswell DP link train sequence Paulo Zanoni
@ 2012-10-15 18:51 ` Paulo Zanoni
2012-10-18 17:36 ` Lespiau, Damien
13 siblings, 1 reply; 34+ messages in thread
From: Paulo Zanoni @ 2012-10-15 18:51 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
This is the final remaining piece of Haswell DP enablement. After this
patch, just calling intel_dp_init on any port will make DP work. We
still do not do this because we're currently initializing HDMI on all
the ports, so if we replace intel_hdmi_init with intel_dp_init, we
will break HDMI, and we can't call both because they share the same
registers.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 32 ++++++++++++++++++++++++++------
1 file changed, 26 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 36687d9..a58ca51 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2553,6 +2553,12 @@ static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
.disable = intel_encoder_noop,
};
+static const struct drm_encoder_helper_funcs intel_dp_helper_funcs_hsw = {
+ .mode_fixup = intel_dp_mode_fixup,
+ .mode_set = intel_ddi_mode_set,
+ .disable = intel_encoder_noop,
+};
+
static const struct drm_connector_funcs intel_dp_connector_funcs = {
.dpms = intel_connector_dpms,
.detect = intel_dp_detect,
@@ -2688,16 +2694,30 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
DRM_MODE_ENCODER_TMDS);
- drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
+
+ if (IS_HASWELL(dev))
+ drm_encoder_helper_add(&intel_encoder->base,
+ &intel_dp_helper_funcs_hsw);
+ else
+ drm_encoder_helper_add(&intel_encoder->base,
+ &intel_dp_helper_funcs);
intel_connector_attach_encoder(intel_connector, intel_encoder);
drm_sysfs_connector_add(connector);
- intel_encoder->enable = intel_enable_dp;
- intel_encoder->pre_enable = intel_pre_enable_dp;
- intel_encoder->disable = intel_disable_dp;
- intel_encoder->post_disable = intel_post_disable_dp;
- intel_encoder->get_hw_state = intel_dp_get_hw_state;
+ if (IS_HASWELL(dev)) {
+ intel_encoder->enable = intel_enable_ddi;
+ intel_encoder->pre_enable = intel_ddi_pre_enable;
+ intel_encoder->disable = intel_disable_ddi;
+ intel_encoder->post_disable = intel_ddi_post_disable;
+ intel_encoder->get_hw_state = intel_ddi_get_hw_state;
+ } else {
+ intel_encoder->enable = intel_enable_dp;
+ intel_encoder->pre_enable = intel_pre_enable_dp;
+ intel_encoder->disable = intel_disable_dp;
+ intel_encoder->post_disable = intel_post_disable_dp;
+ intel_encoder->get_hw_state = intel_dp_get_hw_state;
+ }
intel_connector->get_hw_state = intel_connector_get_hw_state;
/* Set up the DDC bus. */
--
1.7.11.4
^ permalink raw reply related [flat|nested] 34+ messages in thread
* Re: [PATCH 14/14] drm/i915: set the correct function pointers for Haswell DP
2012-10-15 18:51 ` [PATCH 14/14] drm/i915: set the correct function pointers for Haswell DP Paulo Zanoni
@ 2012-10-18 17:36 ` Lespiau, Damien
0 siblings, 0 replies; 34+ messages in thread
From: Lespiau, Damien @ 2012-10-18 17:36 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx, Paulo Zanoni
On Mon, Oct 15, 2012 at 7:51 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> This is the final remaining piece of Haswell DP enablement. After this
> patch, just calling intel_dp_init on any port will make DP work. We
> still do not do this because we're currently initializing HDMI on all
> the ports, so if we replace intel_hdmi_init with intel_dp_init, we
> will break HDMI, and we can't call both because they share the same
> registers.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
--
Damien
^ permalink raw reply [flat|nested] 34+ messages in thread