[PATCH 00/10] Random Haswell fixes

[PATCH 00/10] Random Haswell fixes

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Hi

This series contains small random fixes to the Haswell code. Improvements to the
VGA code, fixes for machines with ULT CPU or LPT-LP PCH, eDP panel fitter bug
fix for IVB+HSW, a workaround and a fix for the "unclaimed write" code.

There's really no specific order to apply these patches, they are all
independent from each other, except for the 2 panel fitter patches that have an
explicit order (and the IVB patch should to through -fixes IMHO).

Thanks,
Paulo

Paulo Zanoni (10):
  drm/i915: don't limit Haswell CRT encoder to pipe A
  drm/i915: fix FDI lane calculation
  drm/i915: use cpu/pch transcoder on intel_enable_pipe
  drm/i915: fix false positive "Unclaimed write" messages
  drm/i915: make DP work on LPT-LP machines
  drm/i915: don't intel_crt_init if DDI A has 4 lanes
  drm/i915: make the panel fitter work on pipes B and C on IVB
  drm/i915: make the panel fitter work on pipes B and C on Haswell
  drm/i915: fix intel_ddi_get_cdclk_freq for ULT machines
  drm/i915: implement WaMbcDriverBootEnable on Haswell

 drivers/gpu/drm/i915/i915_drv.c      |  9 +++++++
 drivers/gpu/drm/i915/i915_drv.h      |  3 +++
 drivers/gpu/drm/i915/i915_reg.h      |  4 +++
 drivers/gpu/drm/i915/intel_crt.c     |  5 +---
 drivers/gpu/drm/i915/intel_ddi.c     |  2 ++
 drivers/gpu/drm/i915/intel_display.c | 49 ++++++++++++++++++++----------------
 drivers/gpu/drm/i915/intel_pm.c      | 22 ++++++++++++++++
 7 files changed, 68 insertions(+), 26 deletions(-)

-- 
1.7.11.7

[PATCH 01/10] drm/i915: don't limit Haswell CRT encoder to pipe A

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

This is a full revert of 59c859d6f2e78344945e8a8406a194156176bc4e:
    drm/i915: account for only one PCH receiver on Haswell

Now that the PCH code is fixed to be able use the only PCH transcoder
independently of the pipe and CPU transcoder, we can revert this.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_crt.c     |  5 +----
 drivers/gpu/drm/i915/intel_display.c | 15 +++------------
 2 files changed, 4 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 1c97c27..124fd78 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -764,10 +764,7 @@ void intel_crt_init(struct drm_device *dev)
 
 	crt->base.type = INTEL_OUTPUT_ANALOG;
 	crt->base.cloneable = true;
-	if (IS_HASWELL(dev))
-		crt->base.crtc_mask = (1 << 0);
-	else
-		crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
+	crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
 
 	if (IS_GEN2(dev))
 		connector->interlace_allowed = 0;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 923d299..0102931 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1149,14 +1149,9 @@ static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 	u32 val;
 	bool cur_state;
 
-	if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
-			DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
-			return;
-	} else {
-		reg = FDI_RX_CTL(pipe);
-		val = I915_READ(reg);
-		cur_state = !!(val & FDI_RX_ENABLE);
-	}
+	reg = FDI_RX_CTL(pipe);
+	val = I915_READ(reg);
+	cur_state = !!(val & FDI_RX_ENABLE);
 	WARN(cur_state != state,
 	     "FDI RX state assertion failure (expected %s, current %s)\n",
 	     state_string(state), state_string(cur_state));
@@ -1189,10 +1184,6 @@ static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
 	int reg;
 	u32 val;
 
-	if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
-		DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
-		return;
-	}
 	reg = FDI_RX_CTL(pipe);
 	val = I915_READ(reg);
 	WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
-- 
1.7.11.7

[PATCH 02/10] drm/i915: fix FDI lane calculation

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

The previous code was making the bps value 5% higher than what the
spec says, which was enough to make certain VGA modes require 3 lanes
instead of 2, which breaks Haswell since it only has 2 FDI lanes. For
previous gens this was not a problem, since requiring more lanes than
the needed is ok, as long as you have all the lanes.

Notice that this might improve the case where we use pipes B and C on
Ivy Bridge since both pipes only have 4 lanes to share (see
ironlake_check_fdi_lanes).

We still need to code to refuse modes requiring more than 2 lanes on
Haswell.

Cc: Adam Jackson <ajax@redhat.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0102931..9940765 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5272,14 +5272,15 @@ static void ironlake_set_m_n(struct drm_crtc *crtc,
 
 	if (!lane) {
 		/*
-		 * Account for spread spectrum to avoid
-		 * oversubscribing the link. Max center spread
-		 * is 2.5%; use 5% for safety's sake.
+		 * The spec says:
+		 * Number of lanes >= INT(dot clock * bytes per pixel / ls_clk)
 		 */
-		u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
-		lane = bps / (link_bw * 8) + 1;
+		u32 bps = target_clock * intel_crtc->bpp;
+		lane = DIV_ROUND_UP(bps, (link_bw * 8));
 	}
 
+	DRM_DEBUG_KMS("Using %d FDI lanes on pipe %c\n", lane,
+		      pipe_name(intel_crtc->pipe));
 	intel_crtc->fdi_lanes = lane;
 
 	if (pixel_multiplier > 1)
-- 
1.7.11.7

[PATCH 03/10] drm/i915: use cpu/pch transcoder on intel_enable_pipe

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

This function runs on Haswell, so set the correct pch_transcoder and
cpu_transcoder variables. This fixes an assertion failure on Haswell
VGA.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9940765..e4d7079 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1812,9 +1812,15 @@ static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
 {
 	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 								      pipe);
+	enum transcoder pch_transcoder;
 	int reg;
 	u32 val;
 
+	if (IS_HASWELL(dev_priv->dev))
+		pch_transcoder = TRANSCODER_A;
+	else
+		pch_transcoder = pipe;
+
 	/*
 	 * A pipe without a PLL won't actually be able to drive bits from
 	 * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
@@ -1825,8 +1831,8 @@ static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
 	else {
 		if (pch_port) {
 			/* if driving the PCH, we need FDI enabled */
-			assert_fdi_rx_pll_enabled(dev_priv, pipe);
-			assert_fdi_tx_pll_enabled(dev_priv, pipe);
+			assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
+			assert_fdi_tx_pll_enabled(dev_priv, cpu_transcoder);
 		}
 		/* FIXME: assert CPU port conditions for SNB+ */
 	}
-- 
1.7.11.7

[PATCH 04/10] drm/i915: fix false positive "Unclaimed write" messages

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

We don't check if the "unclaimed register" bit is set before we call
writel, so if it was already set before, we might print a misleading
message about "unclaimed write" on the wrong register.

This patch makes us check the unclaimed bit before the writel, so we
can print a new "Unknown unclaimed register before writing to %x"
message.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 418d17c..88c44ad 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1251,6 +1251,10 @@ void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
 	} \
 	if (IS_GEN5(dev_priv->dev)) \
 		ilk_dummy_write(dev_priv); \
+	if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
+		DRM_ERROR("Unknown unclaimed register before writing to %x\n", reg); \
+		I915_WRITE_NOTRACE(GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \
+	} \
 	if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
 		write##y(val, dev_priv->regs + reg + 0x180000);		\
 	} else {							\
-- 
1.7.11.7

[PATCH 05/10] drm/i915: make DP work on LPT-LP machines

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

We need to enable a special bit, otherwise none of the DP functions
requiring the PCH will work.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c |  5 +++++
 drivers/gpu/drm/i915/i915_drv.h |  1 +
 drivers/gpu/drm/i915/i915_reg.h |  1 +
 drivers/gpu/drm/i915/intel_pm.c | 15 +++++++++++++++
 4 files changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 88c44ad..8728a94 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -416,27 +416,32 @@ void intel_detect_pch(struct drm_device *dev)
 			if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 				dev_priv->pch_type = PCH_IBX;
 				dev_priv->num_pch_pll = 2;
+				dev_priv->pch_is_lp = false;
 				DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 				WARN_ON(!IS_GEN5(dev));
 			} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 				dev_priv->pch_type = PCH_CPT;
 				dev_priv->num_pch_pll = 2;
+				dev_priv->pch_is_lp = false;
 				DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 				WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 			} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 				/* PantherPoint is CPT compatible */
 				dev_priv->pch_type = PCH_CPT;
 				dev_priv->num_pch_pll = 2;
+				dev_priv->pch_is_lp = false;
 				DRM_DEBUG_KMS("Found PatherPoint PCH\n");
 				WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 			} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 				dev_priv->pch_type = PCH_LPT;
 				dev_priv->num_pch_pll = 0;
+				dev_priv->pch_is_lp = false;
 				DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 				WARN_ON(!IS_HASWELL(dev));
 			} else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 				dev_priv->pch_type = PCH_LPT;
 				dev_priv->num_pch_pll = 0;
+				dev_priv->pch_is_lp = true;
 				DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 				WARN_ON(!IS_HASWELL(dev));
 			}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3229f04..976b470 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -737,6 +737,7 @@ typedef struct drm_i915_private {
 
 	/* PCH chipset type */
 	enum intel_pch pch_type;
+	bool pch_is_lp;
 
 	unsigned long quirks;
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9118bd1..2d83876 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3851,6 +3851,7 @@
 
 #define SOUTH_DSPCLK_GATE_D	0xc2020
 #define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
+#define  PCH_LP_PARTITION_LEVEL_DISABLE  (1<<12)
 
 /* CPU: FDI_TX */
 #define _FDI_TXA_CTL             0x60100
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0edb549..9dd4d22 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3549,6 +3549,20 @@ static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN7_FF_THREAD_MODE, reg);
 }
 
+static void lpt_init_clock_gating(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	/*
+	 * TODO: this bit should only be enabled when really needed, then
+	 * disabled when not needed anymore in order to save power.
+	 */
+	if (dev_priv->pch_is_lp)
+		I915_WRITE(SOUTH_DSPCLK_GATE_D,
+			   I915_READ(SOUTH_DSPCLK_GATE_D) |
+			   PCH_LP_PARTITION_LEVEL_DISABLE);
+}
+
 static void haswell_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3600,6 +3614,7 @@ static void haswell_init_clock_gating(struct drm_device *dev)
 			WM_DBG_DISALLOW_SPRITE |
 			WM_DBG_DISALLOW_MAXFIFO);
 
+	lpt_init_clock_gating(dev);
 }
 
 static void ivybridge_init_clock_gating(struct drm_device *dev)
-- 
1.7.11.7

[PATCH 06/10] drm/i915: don't intel_crt_init if DDI A has 4 lanes

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

DDI A and E have 4 lanes to share, so if DDI A is using 4 lanes,
there's nothing left for DDI E, which means there's no CRT port on the
machine.

The bit we're checking here is programmed at system boot and it cannot
be changed afterwards, so we cannot change the amount of lanes
reserved for each DDI port.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      | 1 +
 drivers/gpu/drm/i915/intel_display.c | 4 +++-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2d83876..5aba146 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4515,6 +4515,7 @@
 #define  DDI_BUF_EMP_800MV_3_5DB_HSW		(8<<24)   /* Sel8 */
 #define  DDI_BUF_EMP_MASK			(0xf<<24)
 #define  DDI_BUF_IS_IDLE			(1<<7)
+#define  DDI_A_4_LANES				(1<<4)
 #define  DDI_PORT_WIDTH_X1			(0<<1)
 #define  DDI_PORT_WIDTH_X2			(1<<1)
 #define  DDI_PORT_WIDTH_X4			(3<<1)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e4d7079..dd7aafc 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8258,7 +8258,9 @@ static void intel_setup_outputs(struct drm_device *dev)
 		I915_WRITE(PFIT_CONTROL, 0);
 	}
 
-	intel_crt_init(dev);
+	if (!(IS_HASWELL(dev) &&
+	      (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
+		intel_crt_init(dev);
 
 	if (IS_HASWELL(dev)) {
 		int found;
-- 
1.7.11.7

[PATCH 07/10] drm/i915: make the panel fitter work on pipes B and C on IVB

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

I actually found this problem on Haswell, but then discovered Ivy
Bridge also has it by reading the spec.

I don't have the hardware to test this.

Cc: stable@vger.kernel.org
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      | 2 ++
 drivers/gpu/drm/i915/intel_display.c | 6 +++++-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5aba146..97fbd9d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3339,6 +3339,8 @@
 #define _PFA_CTL_1               0x68080
 #define _PFB_CTL_1               0x68880
 #define  PF_ENABLE              (1<<31)
+#define  PF_PIPE_SEL_MASK_IVB	(3<<29)
+#define  PF_PIPE_SEL_IVB(pipe)	((pipe)<<29)
 #define  PF_FILTER_MASK		(3<<23)
 #define  PF_FILTER_PROGRAMMED	(0<<23)
 #define  PF_FILTER_MED_3x3	(1<<23)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index dd7aafc..909632e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3387,7 +3387,11 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
 		 * as some pre-programmed values are broken,
 		 * e.g. x201.
 		 */
-		I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
+		if (IS_IVYBRIDGE(dev))
+			I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
+						 PF_PIPE_SEL_IVB(pipe));
+		else
+			I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
 		I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
 		I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
 	}
-- 
1.7.11.7

[PATCH 08/10] drm/i915: make the panel fitter work on pipes B and C on Haswell

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

This goes on a separate patch since it won't apply on the stable
trees and there's nothing using panel fitter on HSW on the older
Kernels.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 909632e..4aa994a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3467,7 +3467,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
 		 * as some pre-programmed values are broken,
 		 * e.g. x201.
 		 */
-		I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
+		I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
+					 PF_PIPE_SEL_IVB(pipe));
 		I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
 		I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
 	}
-- 
1.7.11.7

[PATCH 09/10] drm/i915: fix intel_ddi_get_cdclk_freq for ULT machines

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

For now, this code is just used by the eDP AUX channel frequency.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h  | 2 ++
 drivers/gpu/drm/i915/intel_ddi.c | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 976b470..54a5c10 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1161,6 +1161,8 @@ struct drm_i915_file_private {
 #define IS_VALLEYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview)
 #define IS_HASWELL(dev)	(INTEL_INFO(dev)->is_haswell)
 #define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)
+#define IS_ULT(dev)		(IS_HASWELL(dev) && \
+				 ((dev)->pci_device & 0xFF00) == 0x0A00)
 
 /*
  * The genX designation typically refers to the render engine, so render
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index d706d53..852012b 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1309,6 +1309,8 @@ int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
 	else if ((I915_READ(LCPLL_CTL) & LCPLL_CLK_FREQ_MASK) ==
 		 LCPLL_CLK_FREQ_450)
 		return 450;
+	else if (IS_ULT(dev_priv->dev))
+		return 338;
 	else
 		return 540;
 }
-- 
1.7.11.7

[PATCH 10/10] drm/i915: implement WaMbcDriverBootEnable on Haswell

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Also document the WA name for the previous gens that implement it.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9dd4d22..849de13 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3519,6 +3519,7 @@ static void gen6_init_clock_gating(struct drm_device *dev)
 		   ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
 		   ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
 
+	/* WaMbcDriverBootEnable */
 	I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
 		   GEN6_MBCTL_ENABLE_BOOT_FETCH);
 
@@ -3605,6 +3606,10 @@ static void haswell_init_clock_gating(struct drm_device *dev)
 	I915_WRITE(CACHE_MODE_1,
 		   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
 
+	/* WaMbcDriverBootEnable */
+	I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
+		   GEN6_MBCTL_ENABLE_BOOT_FETCH);
+
 	/* XXX: This is a workaround for early silicon revisions and should be
 	 * removed later.
 	 */
@@ -3696,6 +3701,7 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
 		intel_flush_display_plane(dev_priv, pipe);
 	}
 
+	/* WaMbcDriverBootEnable */
 	I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
 		   GEN6_MBCTL_ENABLE_BOOT_FETCH);
 
@@ -3761,6 +3767,7 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
 		   I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
 		   GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
 
+	/* WaMbcDriverBootEnable */
 	I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
 		   GEN6_MBCTL_ENABLE_BOOT_FETCH);
 
-- 
1.7.11.7

Re: [PATCH 05/10] drm/i915: make DP work on LPT-LP machines

[Daniel Vetter]

On Tue, Nov 20, 2012 at 01:27:39PM -0200, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> We need to enable a special bit, otherwise none of the DP functions
> requiring the PCH will work.
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

I have a feeling pch ids will explode a bit more in the future. So what
about just storing the pch_id in dev-priv and checking for an exact match
for such specific workarounds? Avoids that we need to add another bit for
each and everything thing ...
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_drv.c |  5 +++++
>  drivers/gpu/drm/i915/i915_drv.h |  1 +
>  drivers/gpu/drm/i915/i915_reg.h |  1 +
>  drivers/gpu/drm/i915/intel_pm.c | 15 +++++++++++++++
>  4 files changed, 22 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 88c44ad..8728a94 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -416,27 +416,32 @@ void intel_detect_pch(struct drm_device *dev)
>  			if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
>  				dev_priv->pch_type = PCH_IBX;
>  				dev_priv->num_pch_pll = 2;
> +				dev_priv->pch_is_lp = false;
>  				DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
>  				WARN_ON(!IS_GEN5(dev));
>  			} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
>  				dev_priv->pch_type = PCH_CPT;
>  				dev_priv->num_pch_pll = 2;
> +				dev_priv->pch_is_lp = false;
>  				DRM_DEBUG_KMS("Found CougarPoint PCH\n");
>  				WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
>  			} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
>  				/* PantherPoint is CPT compatible */
>  				dev_priv->pch_type = PCH_CPT;
>  				dev_priv->num_pch_pll = 2;
> +				dev_priv->pch_is_lp = false;
>  				DRM_DEBUG_KMS("Found PatherPoint PCH\n");
>  				WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
>  			} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
>  				dev_priv->pch_type = PCH_LPT;
>  				dev_priv->num_pch_pll = 0;
> +				dev_priv->pch_is_lp = false;
>  				DRM_DEBUG_KMS("Found LynxPoint PCH\n");
>  				WARN_ON(!IS_HASWELL(dev));
>  			} else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
>  				dev_priv->pch_type = PCH_LPT;
>  				dev_priv->num_pch_pll = 0;
> +				dev_priv->pch_is_lp = true;
>  				DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
>  				WARN_ON(!IS_HASWELL(dev));
>  			}
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 3229f04..976b470 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -737,6 +737,7 @@ typedef struct drm_i915_private {
>  
>  	/* PCH chipset type */
>  	enum intel_pch pch_type;
> +	bool pch_is_lp;
>  
>  	unsigned long quirks;
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9118bd1..2d83876 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3851,6 +3851,7 @@
>  
>  #define SOUTH_DSPCLK_GATE_D	0xc2020
>  #define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
> +#define  PCH_LP_PARTITION_LEVEL_DISABLE  (1<<12)
>  
>  /* CPU: FDI_TX */
>  #define _FDI_TXA_CTL             0x60100
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 0edb549..9dd4d22 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3549,6 +3549,20 @@ static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
>  	I915_WRITE(GEN7_FF_THREAD_MODE, reg);
>  }
>  
> +static void lpt_init_clock_gating(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +
> +	/*
> +	 * TODO: this bit should only be enabled when really needed, then
> +	 * disabled when not needed anymore in order to save power.
> +	 */
> +	if (dev_priv->pch_is_lp)
> +		I915_WRITE(SOUTH_DSPCLK_GATE_D,
> +			   I915_READ(SOUTH_DSPCLK_GATE_D) |
> +			   PCH_LP_PARTITION_LEVEL_DISABLE);
> +}
> +
>  static void haswell_init_clock_gating(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -3600,6 +3614,7 @@ static void haswell_init_clock_gating(struct drm_device *dev)
>  			WM_DBG_DISALLOW_SPRITE |
>  			WM_DBG_DISALLOW_MAXFIFO);
>  
> +	lpt_init_clock_gating(dev);
>  }
>  
>  static void ivybridge_init_clock_gating(struct drm_device *dev)
> -- 
> 1.7.11.7
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

[PATCH 05/10] drm/i915: make DP work on LPT-LP machines

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

We need to enable a special bit, otherwise none of the DP functions
requiring the PCH will work.

Version 2: store the PCH ID inside dev_priv, as suggested by Daniel
Vetter.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 10 ++--------
 drivers/gpu/drm/i915/i915_drv.h |  8 ++++++++
 drivers/gpu/drm/i915/i915_reg.h |  1 +
 drivers/gpu/drm/i915/intel_pm.c | 15 +++++++++++++++
 4 files changed, 26 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 88c44ad..f157646 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -389,13 +389,6 @@ static const struct pci_device_id pciidlist[] = {		/* aka */
 MODULE_DEVICE_TABLE(pci, pciidlist);
 #endif
 
-#define INTEL_PCH_DEVICE_ID_MASK	0xff00
-#define INTEL_PCH_IBX_DEVICE_ID_TYPE	0x3b00
-#define INTEL_PCH_CPT_DEVICE_ID_TYPE	0x1c00
-#define INTEL_PCH_PPT_DEVICE_ID_TYPE	0x1e00
-#define INTEL_PCH_LPT_DEVICE_ID_TYPE	0x8c00
-#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE	0x9c00
-
 void intel_detect_pch(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -410,8 +403,9 @@ void intel_detect_pch(struct drm_device *dev)
 	pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
 	if (pch) {
 		if (pch->vendor == PCI_VENDOR_ID_INTEL) {
-			int id;
+			unsigned short id;
 			id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
+			dev_priv->pch_id = id;
 
 			if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 				dev_priv->pch_type = PCH_IBX;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3229f04..f1bb768 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -737,6 +737,7 @@ typedef struct drm_i915_private {
 
 	/* PCH chipset type */
 	enum intel_pch pch_type;
+	unsigned short pch_id;
 
 	unsigned long quirks;
 
@@ -1205,6 +1206,13 @@ struct drm_i915_file_private {
 
 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
 
+#define INTEL_PCH_DEVICE_ID_MASK		0xff00
+#define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
+#define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
+#define INTEL_PCH_PPT_DEVICE_ID_TYPE		0x1e00
+#define INTEL_PCH_LPT_DEVICE_ID_TYPE		0x8c00
+#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE		0x9c00
+
 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9118bd1..2d83876 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3851,6 +3851,7 @@
 
 #define SOUTH_DSPCLK_GATE_D	0xc2020
 #define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
+#define  PCH_LP_PARTITION_LEVEL_DISABLE  (1<<12)
 
 /* CPU: FDI_TX */
 #define _FDI_TXA_CTL             0x60100
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0edb549..647dfcc 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3549,6 +3549,20 @@ static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN7_FF_THREAD_MODE, reg);
 }
 
+static void lpt_init_clock_gating(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	/*
+	 * TODO: this bit should only be enabled when really needed, then
+	 * disabled when not needed anymore in order to save power.
+	 */
+	if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
+		I915_WRITE(SOUTH_DSPCLK_GATE_D,
+			   I915_READ(SOUTH_DSPCLK_GATE_D) |
+			   PCH_LP_PARTITION_LEVEL_DISABLE);
+}
+
 static void haswell_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3600,6 +3614,7 @@ static void haswell_init_clock_gating(struct drm_device *dev)
 			WM_DBG_DISALLOW_SPRITE |
 			WM_DBG_DISALLOW_MAXFIFO);
 
+	lpt_init_clock_gating(dev);
 }
 
 static void ivybridge_init_clock_gating(struct drm_device *dev)
-- 
1.7.11.7

Re: [PATCH 02/10] drm/i915: fix FDI lane calculation

[Damien Lespiau]

> -                * Account for spread spectrum to avoid
> -                * oversubscribing the link. Max center spread
> -                * is 2.5%; use 5% for safety's sake.
> +                * The spec says:
> +                * Number of lanes >= INT(dot clock * bytes per pixel / ls_clk)

Right, so the real question is: "Is that ok to not get the spread rate
(maximum of how much we derive from the requested frequency) into
account?"

I believe it is, on average the frequency is what we set-up. Maybe
Adam can shed more light on why he thought it was necessary?

As a side note, the spec does not mention that at all.

-- 
Damien

Re: [PATCH 01/10] drm/i915: don't limit Haswell CRT encoder to pipe A

[Damien Lespiau]

On Tue, Nov 20, 2012 at 3:27 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> This is a full revert of 59c859d6f2e78344945e8a8406a194156176bc4e:
>     drm/i915: account for only one PCH receiver on Haswell
>
> Now that the PCH code is fixed to be able use the only PCH transcoder
> independently of the pipe and CPU transcoder, we can revert this.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

Re: [PATCH 03/10] drm/i915: use cpu/pch transcoder on intel_enable_pipe

[Damien Lespiau]

On Tue, Nov 20, 2012 at 3:27 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> This function runs on Haswell, so set the correct pch_transcoder and
> cpu_transcoder variables. This fixes an assertion failure on Haswell
> VGA.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

Re: [PATCH 02/10] drm/i915: fix FDI lane calculation

[Paulo Zanoni]

Hi

2012/11/20 Damien Lespiau <damien.lespiau@intel.com>:
>> -                * Account for spread spectrum to avoid
>> -                * oversubscribing the link. Max center spread
>> -                * is 2.5%; use 5% for safety's sake.
>> +                * The spec says:
>> +                * Number of lanes >= INT(dot clock * bytes per pixel / ls_clk)
>
> Right, so the real question is: "Is that ok to not get the spread rate
> (maximum of how much we derive from the requested frequency) into
> account?"

Well, the spec does not say we need to do this. Also, I tested this
patch on SNB and some modes that were moved from 3 to 2 lanes still
work.

>
> I believe it is, on average the frequency is what we set-up. Maybe
> Adam can shed more light on why he thought it was necessary?
>
> As a side note, the spec does not mention that at all.
>
> --
> Damien



-- 
Paulo Zanoni

Re: [PATCH 04/10] drm/i915: fix false positive "Unclaimed write" messages

[Damien Lespiau]

> +       if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
> +               DRM_ERROR("Unknown unclaimed register before writing to %x\n", reg); \
> +               I915_WRITE_NOTRACE(GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \
> +       } \

Do we really have to DRM_ERROR here? this bit being set seems to be
beyond things we can fix (BIOS leaving that behind?)

-- 
Damien

Re: [PATCH 05/10] drm/i915: make DP work on LPT-LP machines

[Damien Lespiau]

On Tue, Nov 20, 2012 at 5:12 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> We need to enable a special bit, otherwise none of the DP functions
> requiring the PCH will work.
>
> Version 2: store the PCH ID inside dev_priv, as suggested by Daniel
> Vetter.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

This makes priv->pch_type and priv->pch_id somewhat redundant, but the
fact that type is always growing with newer PCHs is used in
intel_sdvo.c and seems a useful thing to be able to do, so:

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

Re: [PATCH 04/10] drm/i915: fix false positive "Unclaimed write" messages

[Paulo Zanoni]

Hi

2012/11/20 Damien Lespiau <damien.lespiau@intel.com>:
>> +       if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
>> +               DRM_ERROR("Unknown unclaimed register before writing to %x\n", reg); \
>> +               I915_WRITE_NOTRACE(GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \
>> +       } \
>
> Do we really have to DRM_ERROR here? this bit being set seems to be
> beyond things we can fix (BIOS leaving that behind?)

If we do I915_WRITE_NOTRACE or I915_READ_NOTRACE to a register that
does not exist I believe the unclaimed bit will be set.

>
> --
> Damien



-- 
Paulo Zanoni

Re: [PATCH 06/10] drm/i915: don't intel_crt_init if DDI A has 4 lanes

[Damien Lespiau]

On Tue, Nov 20, 2012 at 3:27 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> DDI A and E have 4 lanes to share, so if DDI A is using 4 lanes,
> there's nothing left for DDI E, which means there's no CRT port on the
> machine.
>
> The bit we're checking here is programmed at system boot and it cannot
> be changed afterwards, so we cannot change the amount of lanes
> reserved for each DDI port.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

Re: [PATCH 05/10] drm/i915: make DP work on LPT-LP machines

[Paulo Zanoni]

Hi

2012/11/20 Damien Lespiau <damien.lespiau@intel.com>:
> On Tue, Nov 20, 2012 at 5:12 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
>> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>>
>> We need to enable a special bit, otherwise none of the DP functions
>> requiring the PCH will work.
>>
>> Version 2: store the PCH ID inside dev_priv, as suggested by Daniel
>> Vetter.
>>
>> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> This makes priv->pch_type and priv->pch_id somewhat redundant, but the
> fact that type is always growing with newer PCHs is used in
> intel_sdvo.c and seems a useful thing to be able to do, so:

I believe the idea is that pch_type may include more than one pch_id.
Like for example, PCH_CPT involves not only the CougarPoint PCHs, but
also the PantherPoint PCH. Also, PCH_LPT currently involves LynxPoint
and LynxPoint-LP.

>
> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
>
> --
> Damien



-- 
Paulo Zanoni

Re: [PATCH 04/10] drm/i915: fix false positive "Unclaimed write" messages

[Damien Lespiau]

On Tue, Nov 20, 2012 at 7:10 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
> Hi
>
> 2012/11/20 Damien Lespiau <damien.lespiau@intel.com>:
>>> +       if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
>>> +               DRM_ERROR("Unknown unclaimed register before writing to %x\n", reg); \
>>> +               I915_WRITE_NOTRACE(GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \
>>> +       } \
>>
>> Do we really have to DRM_ERROR here? this bit being set seems to be
>> beyond things we can fix (BIOS leaving that behind?)
>
> If we do I915_WRITE_NOTRACE or I915_READ_NOTRACE to a register that
> does not exist I believe the unclaimed bit will be set.

Yup, that looks true, I guess that if we're seeing that BIOSes leave
that behind and generate a false positive we can write that bit when
cleaning up after the BIOS anyway.

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

Re: [PATCH 07/10] drm/i915: make the panel fitter work on pipes B and C on IVB

[Damien Lespiau]

On Tue, Nov 20, 2012 at 3:27 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> I actually found this problem on Haswell, but then discovered Ivy
> Bridge also has it by reading the spec.
>
> I don't have the hardware to test this.
>
> Cc: stable@vger.kernel.org
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Looks correct, but I don't have the hardware to test it either.

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

Re: [PATCH 04/10] drm/i915: fix false positive "Unclaimed write" messages

[Paulo Zanoni]

2012/11/20 Damien Lespiau <damien.lespiau@intel.com>:
> On Tue, Nov 20, 2012 at 7:10 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
>> Hi
>>
>> 2012/11/20 Damien Lespiau <damien.lespiau@intel.com>:
>>>> +       if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
>>>> +               DRM_ERROR("Unknown unclaimed register before writing to %x\n", reg); \
>>>> +               I915_WRITE_NOTRACE(GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \
>>>> +       } \
>>>
>>> Do we really have to DRM_ERROR here? this bit being set seems to be
>>> beyond things we can fix (BIOS leaving that behind?)
>>
>> If we do I915_WRITE_NOTRACE or I915_READ_NOTRACE to a register that
>> does not exist I believe the unclaimed bit will be set.
>
> Yup, that looks true, I guess that if we're seeing that BIOSes leave
> that behind and generate a false positive we can write that bit when
> cleaning up after the BIOS anyway.

As far as I have investigated, we are also seeing leftovers from the
BIOS that you're talking about. We need to do an initial clear in this
bit at the driver initialization time (irq initialization?).

I forgot to say, but the error message introduced by this patch will
also be print when we I915_READ a register that does not exist (which
is the case when we hang the gpu, for example).

>
> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
>
> --
> Damien



-- 
Paulo Zanoni

Re: [PATCH 08/10] drm/i915: make the panel fitter work on pipes B and C on Haswell

[Damien Lespiau]

On Tue, Nov 20, 2012 at 3:27 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> This goes on a separate patch since it won't apply on the stable
> trees and there's nothing using panel fitter on HSW on the older
> Kernels.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

Re: [PATCH 09/10] drm/i915: fix intel_ddi_get_cdclk_freq for ULT machines

[Damien Lespiau]

On Tue, Nov 20, 2012 at 3:27 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> For now, this code is just used by the eDP AUX channel frequency.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

Re: [PATCH 10/10] drm/i915: implement WaMbcDriverBootEnable on Haswell

[Daniel Vetter]

On Tue, Nov 20, 2012 at 01:27:44PM -0200, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> Also document the WA name for the previous gens that implement it.
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Slurped in this series, safe for the ssc fdi link oversubscription change,
I'm not yet sure what I should do with that.

For this one here, I'd _really_ like an i-g-t testcase that checks whether
these workarounds are still set correctly after driver load (in the module
reload test), after gpu resets (in the hangman) and after a suspend/resume
(that testcase doesn't exists yet).

Cheers, Daniel

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 9dd4d22..849de13 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3519,6 +3519,7 @@ static void gen6_init_clock_gating(struct drm_device *dev)
>  		   ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
>  		   ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
>  
> +	/* WaMbcDriverBootEnable */
>  	I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
>  		   GEN6_MBCTL_ENABLE_BOOT_FETCH);
>  
> @@ -3605,6 +3606,10 @@ static void haswell_init_clock_gating(struct drm_device *dev)
>  	I915_WRITE(CACHE_MODE_1,
>  		   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
>  
> +	/* WaMbcDriverBootEnable */
> +	I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
> +		   GEN6_MBCTL_ENABLE_BOOT_FETCH);
> +
>  	/* XXX: This is a workaround for early silicon revisions and should be
>  	 * removed later.
>  	 */
> @@ -3696,6 +3701,7 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
>  		intel_flush_display_plane(dev_priv, pipe);
>  	}
>  
> +	/* WaMbcDriverBootEnable */
>  	I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
>  		   GEN6_MBCTL_ENABLE_BOOT_FETCH);
>  
> @@ -3761,6 +3767,7 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>  		   I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
>  		   GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
>  
> +	/* WaMbcDriverBootEnable */
>  	I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
>  		   GEN6_MBCTL_ENABLE_BOOT_FETCH);
>  
> -- 
> 1.7.11.7
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch