From: Ben Widawsky <ben@bwidawsk.net>
To: intel-gfx@lists.freedesktop.org
Cc: Ben Widawsky <ben@bwidawsk.net>
Subject: [PATCH 5/5] drm/i915: Dynamically calculate dclv
Date: Fri, 28 Dec 2012 20:27:29 -0800 [thread overview]
Message-ID: <1356755249-19810-5-git-send-email-ben@bwidawsk.net> (raw)
In-Reply-To: <1356755249-19810-1-git-send-email-ben@bwidawsk.net>
Directory CacheLine Valid controls which PDEs are held in the directory
cache. Each bit represents 16 PDEs (16 PDEs at 4 bytes per entry is 1
cacheline, and therefore, almost makes sense).
Since we can now have an aliasing PPGTT which isn't 2GB, theoretically,
we should also modify the DCLV value to fit accordingly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 5 +++--
drivers/gpu/drm/i915/i915_reg.h | 1 -
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 2788ca5..c26aa3b 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -348,11 +348,12 @@ void i915_gem_init_ppgtt(struct drm_device *dev)
}
for_each_ring(ring, dev_priv, i) {
+ uint64_t dclv = ppgtt->mapped_size >> 26;
+ dclv = (1ULL << dclv) - 1;
if (INTEL_INFO(dev)->gen >= 7)
I915_WRITE(RING_MODE_GEN7(ring),
_MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
-
- I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
+ I915_WRITE(RING_PP_DIR_DCLV(ring), dclv);
I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
}
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5b3020f..4e8ecab 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -117,7 +117,6 @@
#define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228)
#define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518)
#define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220)
-#define PP_DIR_DCLV_2G 0xffffffff
#define GAM_ECOCHK 0x4090
#define ECOCHK_SNB_BIT (1<<10)
--
1.8.0.2
next prev parent reply other threads:[~2012-12-29 4:26 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-12-29 4:27 [PATCH 1/5] drm/i915: trivial: kill-agp collateral cleanups Ben Widawsky
2012-12-29 4:27 ` [PATCH 2/5] drm/i915: Reclaim GTT space for failed PPGTT Ben Widawsky
2012-12-29 4:27 ` [PATCH 3/5] drm/i915: Extract gen6 aliasing ppgtt code Ben Widawsky
2012-12-29 11:49 ` Chris Wilson
2012-12-29 19:45 ` Ben Widawsky
2012-12-29 23:44 ` Chris Wilson
2012-12-29 4:27 ` [PATCH 4/5] drm/i915: Aliased PPGTT size abstraction Ben Widawsky
2012-12-29 4:27 ` Ben Widawsky [this message]
2013-01-26 0:41 [PATCH 0/5] [REPOST] GTT cleanups, rebased Ben Widawsky
2013-01-26 0:41 ` [PATCH 5/5] drm/i915: Dynamically calculate dclv Ben Widawsky
2013-01-28 12:20 ` Jani Nikula
2013-01-28 20:36 ` Ben Widawsky
2013-01-28 21:08 ` Daniel Vetter
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