From: Daniel Vetter <daniel@ffwll.ch>
To: Ben Widawsky <ben@bwidawsk.net>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 5/5] drm/i915: Dynamically calculate dclv
Date: Mon, 28 Jan 2013 22:08:37 +0100 [thread overview]
Message-ID: <20130128210837.GB14766@phenom.ffwll.local> (raw)
In-Reply-To: <1359160867-780-6-git-send-email-ben@bwidawsk.net>
On Fri, Jan 25, 2013 at 04:41:07PM -0800, Ben Widawsky wrote:
> Directory CacheLine Valid controls which PDEs are held in the directory
> cache. Each bit represents 16 PDEs (16 PDEs at 4 bytes per entry is 1
> cacheline, and therefore, almost makes sense).
>
> Since we can now have an aliasing PPGTT which isn't 2GB, theoretically,
> we should also modify the DCLV value to fit accordingly.
>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 5 +++--
> drivers/gpu/drm/i915/i915_reg.h | 1 -
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index d9af815..168583b 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -344,11 +344,12 @@ void i915_gem_init_ppgtt(struct drm_device *dev)
> }
>
> for_each_ring(ring, dev_priv, i) {
> + uint64_t dclv = ppgtt->mapped_size >> 26;
ppgtt->num_pd_entries / 16? Would be much more self-documenting than the
almost magic >> 26 ...
-Daniel
> + dclv = (1ULL << dclv) - 1;
> if (INTEL_INFO(dev)->gen >= 7)
> I915_WRITE(RING_MODE_GEN7(ring),
> _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
> -
> - I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
> + I915_WRITE(RING_PP_DIR_DCLV(ring), dclv);
> I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
> }
> }
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 94a08b9..780a715 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -117,7 +117,6 @@
> #define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228)
> #define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518)
> #define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220)
> -#define PP_DIR_DCLV_2G 0xffffffff
>
> #define GAM_ECOCHK 0x4090
> #define ECOCHK_SNB_BIT (1<<10)
> --
> 1.8.1.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
next prev parent reply other threads:[~2013-01-28 21:06 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-01-26 0:41 [PATCH 0/5] [REPOST] GTT cleanups, rebased Ben Widawsky
2013-01-26 0:41 ` [PATCH 1/5] drm/i915: trivial: kill-agp collateral cleanups Ben Widawsky
2013-01-29 12:49 ` Daniel Vetter
2013-01-29 18:58 ` Ben Widawsky
2013-01-26 0:41 ` [PATCH 2/5] drm/i915: Reclaim GTT space for failed PPGTT Ben Widawsky
2013-01-29 12:51 ` Daniel Vetter
2013-01-26 0:41 ` [PATCH 3/5] drm/i915: Extract gen6 aliasing ppgtt code Ben Widawsky
2013-01-29 12:55 ` Daniel Vetter
2013-01-29 19:00 ` Ben Widawsky
2013-01-26 0:41 ` [PATCH 4/5] drm/i915: Aliased PPGTT size abstraction Ben Widawsky
2013-01-28 12:19 ` Jani Nikula
2013-01-28 18:26 ` Ben Widawsky
2013-01-28 18:31 ` Daniel Vetter
2013-01-28 20:35 ` [PATCH 4/5 v2] " Ben Widawsky
2013-01-29 12:58 ` Daniel Vetter
2013-01-26 0:41 ` [PATCH 5/5] drm/i915: Dynamically calculate dclv Ben Widawsky
2013-01-28 12:20 ` Jani Nikula
2013-01-28 20:36 ` Ben Widawsky
2013-01-28 21:08 ` Daniel Vetter [this message]
2013-01-28 12:24 ` [PATCH 0/5] [REPOST] GTT cleanups, rebased Jani Nikula
-- strict thread matches above, loose matches on Subject: below --
2012-12-29 4:27 [PATCH 1/5] drm/i915: trivial: kill-agp collateral cleanups Ben Widawsky
2012-12-29 4:27 ` [PATCH 5/5] drm/i915: Dynamically calculate dclv Ben Widawsky
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