* [PATCH 00/33] drm/915: Get rid of IS_DISPLAYREG()
@ 2013-01-24 13:29 ville.syrjala
2013-01-24 13:29 ` [PATCH 01/33] drm/i915: Convert intel_hdmi to enum port ville.syrjala
` (32 more replies)
0 siblings, 33 replies; 67+ messages in thread
From: ville.syrjala @ 2013-01-24 13:29 UTC (permalink / raw)
To: intel-gfx
Hi Daniel,
Here's the proper "kill IS_DISPLAYREG()" series, based on the feedback
to the RFC. Hopefully I managed to address most of the comments.
Changes since the RFC:
- split the monster patch into small chunks
- s/mmio_offset/display_mmio_offset
- use enum port in hdmi/dp code
- VLV only registers were adjusted to use VLV_DISPLAY_BASE directly
instead of display_mmio_offset.
- interrupt register changes moved to end of series (easy to drop if
you don't like it)
- VLV_ADPA left alone + fixed some code in intel_crt.c
- GMBUS regs dropped, they're handled via gpio_mmio_base
- VGA0/VGA1/VGA_PD dropped, and fixed the suspend/resume code not to
touch them
- _FPA0 & co., DPLL_TEST, RENCLK_GATE_D1/D2, DEUC dropped
- G4X_AUD_CNTL_ST & co. dropped (needs more work for VLV anyway)
- BLC registers dropped (needs more work for VLV anyway)
- VIDEO_DIP_CTL & co. dropped (VLV has per pipe regs for these,
probably needs more work)
- PP registers dropped (VLV has per pipe regs for these, probably
needs more work)
- PFA/PFB panel fitter regs dropped
^ permalink raw reply [flat|nested] 67+ messages in thread
* [PATCH 01/33] drm/i915: Convert intel_hdmi to enum port
2013-01-24 13:29 [PATCH 00/33] drm/915: Get rid of IS_DISPLAYREG() ville.syrjala
@ 2013-01-24 13:29 ` ville.syrjala
2013-01-24 17:49 ` Paulo Zanoni
2013-01-24 13:29 ` [PATCH 02/33] drm/i915: Convert intel_dp " ville.syrjala
` (31 subsequent siblings)
32 siblings, 1 reply; 67+ messages in thread
From: ville.syrjala @ 2013-01-24 13:29 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Use intel_dig_port->port rather than intel_hdmi->sdvox_erg.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_hdmi.c | 27 +++++++++++++++------------
1 file changed, 15 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index d53b731..5b4efd6 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -372,7 +372,8 @@ static void g4x_set_infoframes(struct drm_encoder *encoder,
struct drm_display_mode *adjusted_mode)
{
struct drm_i915_private *dev_priv = encoder->dev->dev_private;
- struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
+ struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
+ struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
u32 reg = VIDEO_DIP_CTL;
u32 val = I915_READ(reg);
u32 port;
@@ -399,11 +400,11 @@ static void g4x_set_infoframes(struct drm_encoder *encoder,
return;
}
- switch (intel_hdmi->sdvox_reg) {
- case SDVOB:
+ switch (intel_dig_port->port) {
+ case PORT_B:
port = VIDEO_DIP_PORT_B;
break;
- case SDVOC:
+ case PORT_C:
port = VIDEO_DIP_PORT_C;
break;
default:
@@ -436,7 +437,8 @@ static void ibx_set_infoframes(struct drm_encoder *encoder,
{
struct drm_i915_private *dev_priv = encoder->dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
- struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
+ struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
+ struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
u32 val = I915_READ(reg);
u32 port;
@@ -455,14 +457,14 @@ static void ibx_set_infoframes(struct drm_encoder *encoder,
return;
}
- switch (intel_hdmi->sdvox_reg) {
- case HDMIB:
+ switch (intel_dig_port->port) {
+ case PORT_B:
port = VIDEO_DIP_PORT_B;
break;
- case HDMIC:
+ case PORT_C:
port = VIDEO_DIP_PORT_C;
break;
- case HDMID:
+ case PORT_D:
port = VIDEO_DIP_PORT_D;
break;
default:
@@ -795,13 +797,14 @@ static bool g4x_hdmi_connected(struct intel_hdmi *intel_hdmi)
{
struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_digital_port *intel_dig_port = hdmi_to_dig_port(intel_hdmi);
uint32_t bit;
- switch (intel_hdmi->sdvox_reg) {
- case SDVOB:
+ switch (intel_dig_port->port) {
+ case PORT_B:
bit = HDMIB_HOTPLUG_LIVE_STATUS;
break;
- case SDVOC:
+ case PORT_C:
bit = HDMIC_HOTPLUG_LIVE_STATUS;
break;
default:
--
1.7.12.4
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 02/33] drm/i915: Convert intel_dp to enum port
2013-01-24 13:29 [PATCH 00/33] drm/915: Get rid of IS_DISPLAYREG() ville.syrjala
2013-01-24 13:29 ` [PATCH 01/33] drm/i915: Convert intel_hdmi to enum port ville.syrjala
@ 2013-01-24 13:29 ` ville.syrjala
2013-01-24 17:54 ` Paulo Zanoni
2013-01-24 13:29 ` [PATCH 03/33] drm/i915: Add display_display_mmio_offset to intel_device_info ville.syrjala
` (30 subsequent siblings)
32 siblings, 1 reply; 67+ messages in thread
From: ville.syrjala @ 2013-01-24 13:29 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Use intel_dig_port->port rather than intel_dp->output_reg.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f05364a..d274f8e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2293,16 +2293,17 @@ g4x_dp_detect(struct intel_dp *intel_dp)
{
struct drm_device *dev = intel_dp_to_dev(intel_dp);
struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
uint32_t bit;
- switch (intel_dp->output_reg) {
- case DP_B:
+ switch (intel_dig_port->port) {
+ case PORT_B:
bit = DPB_HOTPLUG_LIVE_STATUS;
break;
- case DP_C:
+ case PORT_C:
bit = DPC_HOTPLUG_LIVE_STATUS;
break;
- case DP_D:
+ case PORT_D:
bit = DPD_HOTPLUG_LIVE_STATUS;
break;
default:
--
1.7.12.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 03/33] drm/i915: Add display_display_mmio_offset to intel_device_info
2013-01-24 13:29 [PATCH 00/33] drm/915: Get rid of IS_DISPLAYREG() ville.syrjala
2013-01-24 13:29 ` [PATCH 01/33] drm/i915: Convert intel_hdmi to enum port ville.syrjala
2013-01-24 13:29 ` [PATCH 02/33] drm/i915: Convert intel_dp " ville.syrjala
@ 2013-01-24 13:29 ` ville.syrjala
2013-01-24 13:29 ` [PATCH 04/33] drm/i915: AUD_VID_DID needs an offset on VLV ville.syrjala
` (29 subsequent siblings)
32 siblings, 0 replies; 67+ messages in thread
From: ville.syrjala @ 2013-01-24 13:29 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add an optional offset to intel_device_info, which will added
to most display register offsets.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0a798ee..272af1d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -340,6 +340,7 @@ struct drm_i915_gt_funcs {
DEV_INFO_FLAG(has_llc)
struct intel_device_info {
+ u32 display_mmio_offset;
u8 gen;
u8 is_mobile:1;
u8 is_i85x:1;
--
1.7.12.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 04/33] drm/i915: AUD_VID_DID needs an offset on VLV
2013-01-24 13:29 [PATCH 00/33] drm/915: Get rid of IS_DISPLAYREG() ville.syrjala
` (2 preceding siblings ...)
2013-01-24 13:29 ` [PATCH 03/33] drm/i915: Add display_display_mmio_offset to intel_device_info ville.syrjala
@ 2013-01-24 13:29 ` ville.syrjala
2013-01-24 13:29 ` [PATCH 05/33] drm/i915: Per-pipe PP registers are for VLV only ville.syrjala
` (28 subsequent siblings)
32 siblings, 0 replies; 67+ messages in thread
From: ville.syrjala @ 2013-01-24 13:29 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index aea2d12..446de9a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4301,7 +4301,7 @@
#define GEN7_ROW_CHICKEN2_GT2 0xf4f4
#define DOP_CLOCK_GATING_DISABLE (1<<0)
-#define G4X_AUD_VID_DID 0x62020
+#define G4X_AUD_VID_DID (dev_priv->info->display_mmio_offset + 0x62020)
#define INTEL_AUDIO_DEVCL 0x808629FB
#define INTEL_AUDIO_DEVBLC 0x80862801
#define INTEL_AUDIO_DEVCTG 0x80862802
--
1.7.12.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 05/33] drm/i915: Per-pipe PP registers are for VLV only
2013-01-24 13:29 [PATCH 00/33] drm/915: Get rid of IS_DISPLAYREG() ville.syrjala
` (3 preceding siblings ...)
2013-01-24 13:29 ` [PATCH 04/33] drm/i915: AUD_VID_DID needs an offset on VLV ville.syrjala
@ 2013-01-24 13:29 ` ville.syrjala
2013-01-24 13:29 ` [PATCH 06/33] drm/i915: VLV_VIDEO_DIP_CTL is " ville.syrjala
` (27 subsequent siblings)
32 siblings, 0 replies; 67+ messages in thread
From: ville.syrjala @ 2013-01-24 13:29 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 446de9a..ac0837f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3999,17 +3999,17 @@
#define LVDS_DETECTED (1 << 1)
/* vlv has 2 sets of panel control regs. */
-#define PIPEA_PP_STATUS 0x61200
-#define PIPEA_PP_CONTROL 0x61204
-#define PIPEA_PP_ON_DELAYS 0x61208
-#define PIPEA_PP_OFF_DELAYS 0x6120c
-#define PIPEA_PP_DIVISOR 0x61210
-
-#define PIPEB_PP_STATUS 0x61300
-#define PIPEB_PP_CONTROL 0x61304
-#define PIPEB_PP_ON_DELAYS 0x61308
-#define PIPEB_PP_OFF_DELAYS 0x6130c
-#define PIPEB_PP_DIVISOR 0x61310
+#define PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200)
+#define PIPEA_PP_CONTROL (VLV_DISPLAY_BASE + 0x61204)
+#define PIPEA_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61208)
+#define PIPEA_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6120c)
+#define PIPEA_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61210)
+
+#define PIPEB_PP_STATUS (VLV_DISPLAY_BASE + 0x61300)
+#define PIPEB_PP_CONTROL (VLV_DISPLAY_BASE + 0x61304)
+#define PIPEB_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61308)
+#define PIPEB_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6130c)
+#define PIPEB_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61310)
#define PCH_PP_STATUS 0xc7200
#define PCH_PP_CONTROL 0xc7204
--
1.7.12.4
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 06/33] drm/i915: VLV_VIDEO_DIP_CTL is for VLV only
2013-01-24 13:29 [PATCH 00/33] drm/915: Get rid of IS_DISPLAYREG() ville.syrjala
` (4 preceding siblings ...)
2013-01-24 13:29 ` [PATCH 05/33] drm/i915: Per-pipe PP registers are for VLV only ville.syrjala
@ 2013-01-24 13:29 ` ville.syrjala
2013-01-24 13:29 ` [PATCH 07/33] drm/i915: PIPE M/N registers need an offset on VLV ville.syrjala
` (26 subsequent siblings)
32 siblings, 0 replies; 67+ messages in thread
From: ville.syrjala @ 2013-01-24 13:29 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ac0837f..1d65214 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3703,13 +3703,13 @@
#define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
#define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
-#define VLV_VIDEO_DIP_CTL_A 0x60200
-#define VLV_VIDEO_DIP_DATA_A 0x60208
-#define VLV_VIDEO_DIP_GDCP_PAYLOAD_A 0x60210
+#define VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200)
+#define VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208)
+#define VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210)
-#define VLV_VIDEO_DIP_CTL_B 0x61170
-#define VLV_VIDEO_DIP_DATA_B 0x61174
-#define VLV_VIDEO_DIP_GDCP_PAYLOAD_B 0x61178
+#define VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170)
+#define VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174)
+#define VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178)
#define VLV_TVIDEO_DIP_CTL(pipe) \
_PIPE(pipe, VLV_VIDEO_DIP_CTL_A, VLV_VIDEO_DIP_CTL_B)
--
1.7.12.4
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^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 07/33] drm/i915: PIPE M/N registers need an offset on VLV
2013-01-24 13:29 [PATCH 00/33] drm/915: Get rid of IS_DISPLAYREG() ville.syrjala
` (5 preceding siblings ...)
2013-01-24 13:29 ` [PATCH 06/33] drm/i915: VLV_VIDEO_DIP_CTL is " ville.syrjala
@ 2013-01-24 13:29 ` ville.syrjala
2013-01-24 13:29 ` [PATCH 08/33] drm/i915: SWF screatch " ville.syrjala
` (25 subsequent siblings)
32 siblings, 0 replies; 67+ messages in thread
From: ville.syrjala @ 2013-01-24 13:29 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 32 ++++++++++++++++----------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1d65214..80f9b6a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3272,41 +3272,41 @@
#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
-#define _PIPEA_DATA_M1 0x60030
+#define _PIPEA_DATA_M1 (dev_priv->info->display_mmio_offset + 0x60030)
#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
#define TU_SIZE_MASK 0x7e000000
#define PIPE_DATA_M1_OFFSET 0
-#define _PIPEA_DATA_N1 0x60034
+#define _PIPEA_DATA_N1 (dev_priv->info->display_mmio_offset + 0x60034)
#define PIPE_DATA_N1_OFFSET 0
-#define _PIPEA_DATA_M2 0x60038
+#define _PIPEA_DATA_M2 (dev_priv->info->display_mmio_offset + 0x60038)
#define PIPE_DATA_M2_OFFSET 0
-#define _PIPEA_DATA_N2 0x6003c
+#define _PIPEA_DATA_N2 (dev_priv->info->display_mmio_offset + 0x6003c)
#define PIPE_DATA_N2_OFFSET 0
-#define _PIPEA_LINK_M1 0x60040
+#define _PIPEA_LINK_M1 (dev_priv->info->display_mmio_offset + 0x60040)
#define PIPE_LINK_M1_OFFSET 0
-#define _PIPEA_LINK_N1 0x60044
+#define _PIPEA_LINK_N1 (dev_priv->info->display_mmio_offset + 0x60044)
#define PIPE_LINK_N1_OFFSET 0
-#define _PIPEA_LINK_M2 0x60048
+#define _PIPEA_LINK_M2 (dev_priv->info->display_mmio_offset + 0x60048)
#define PIPE_LINK_M2_OFFSET 0
-#define _PIPEA_LINK_N2 0x6004c
+#define _PIPEA_LINK_N2 (dev_priv->info->display_mmio_offset + 0x6004c)
#define PIPE_LINK_N2_OFFSET 0
/* PIPEB timing regs are same start from 0x61000 */
-#define _PIPEB_DATA_M1 0x61030
-#define _PIPEB_DATA_N1 0x61034
+#define _PIPEB_DATA_M1 (dev_priv->info->display_mmio_offset + 0x61030)
+#define _PIPEB_DATA_N1 (dev_priv->info->display_mmio_offset + 0x61034)
-#define _PIPEB_DATA_M2 0x61038
-#define _PIPEB_DATA_N2 0x6103c
+#define _PIPEB_DATA_M2 (dev_priv->info->display_mmio_offset + 0x61038)
+#define _PIPEB_DATA_N2 (dev_priv->info->display_mmio_offset + 0x6103c)
-#define _PIPEB_LINK_M1 0x61040
-#define _PIPEB_LINK_N1 0x61044
+#define _PIPEB_LINK_M1 (dev_priv->info->display_mmio_offset + 0x61040)
+#define _PIPEB_LINK_N1 (dev_priv->info->display_mmio_offset + 0x61044)
-#define _PIPEB_LINK_M2 0x61048
-#define _PIPEB_LINK_N2 0x6104c
+#define _PIPEB_LINK_M2 (dev_priv->info->display_mmio_offset + 0x61048)
+#define _PIPEB_LINK_N2 (dev_priv->info->display_mmio_offset + 0x6104c)
#define PIPE_DATA_M1(tran) _TRANSCODER(tran, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
#define PIPE_DATA_N1(tran) _TRANSCODER(tran, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
--
1.7.12.4
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^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 08/33] drm/i915: SWF screatch registers need an offset on VLV
2013-01-24 13:29 [PATCH 00/33] drm/915: Get rid of IS_DISPLAYREG() ville.syrjala
` (6 preceding siblings ...)
2013-01-24 13:29 ` [PATCH 07/33] drm/i915: PIPE M/N registers need an offset on VLV ville.syrjala
@ 2013-01-24 13:29 ` ville.syrjala
2013-01-24 21:37 ` Daniel Vetter
2013-01-24 13:29 ` [PATCH 09/33] drm/i915: VGACNTRL needs " ville.syrjala
` (24 subsequent siblings)
32 siblings, 1 reply; 67+ messages in thread
From: ville.syrjala @ 2013-01-24 13:29 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 26 +++++++++++++-------------
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 80f9b6a..87eed0c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3046,19 +3046,19 @@
(I915_WRITE((reg), (gfx_addr) | I915_LO_DISPBASE(I915_READ(reg))))
/* VBIOS flags */
-#define SWF00 0x71410
-#define SWF01 0x71414
-#define SWF02 0x71418
-#define SWF03 0x7141c
-#define SWF04 0x71420
-#define SWF05 0x71424
-#define SWF06 0x71428
-#define SWF10 0x70410
-#define SWF11 0x70414
-#define SWF14 0x71420
-#define SWF30 0x72414
-#define SWF31 0x72418
-#define SWF32 0x7241c
+#define SWF00 (dev_priv->info->display_mmio_offset + 0x71410)
+#define SWF01 (dev_priv->info->display_mmio_offset + 0x71414)
+#define SWF02 (dev_priv->info->display_mmio_offset + 0x71418)
+#define SWF03 (dev_priv->info->display_mmio_offset + 0x7141c)
+#define SWF04 (dev_priv->info->display_mmio_offset + 0x71420)
+#define SWF05 (dev_priv->info->display_mmio_offset + 0x71424)
+#define SWF06 (dev_priv->info->display_mmio_offset + 0x71428)
+#define SWF10 (dev_priv->info->display_mmio_offset + 0x70410)
+#define SWF11 (dev_priv->info->display_mmio_offset + 0x70414)
+#define SWF14 (dev_priv->info->display_mmio_offset + 0x71420)
+#define SWF30 (dev_priv->info->display_mmio_offset + 0x72414)
+#define SWF31 (dev_priv->info->display_mmio_offset + 0x72418)
+#define SWF32 (dev_priv->info->display_mmio_offset + 0x7241c)
/* Pipe B */
#define _PIPEBDSL 0x71000
--
1.7.12.4
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 09/33] drm/i915: VGACNTRL needs an offset on VLV
2013-01-24 13:29 [PATCH 00/33] drm/915: Get rid of IS_DISPLAYREG() ville.syrjala
` (7 preceding siblings ...)
2013-01-24 13:29 ` [PATCH 08/33] drm/i915: SWF screatch " ville.syrjala
@ 2013-01-24 13:29 ` ville.syrjala
2013-01-24 21:39 ` Daniel Vetter
2013-01-24 13:29 ` [PATCH 10/33] drm/i915: Primary plane registers need " ville.syrjala
` (23 subsequent siblings)
32 siblings, 1 reply; 67+ messages in thread
From: ville.syrjala @ 2013-01-24 13:29 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 87eed0c..8b581b5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3227,7 +3227,7 @@
#define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
/* VBIOS regs */
-#define VGACNTRL 0x71400
+#define VGACNTRL (dev_priv->info->display_mmio_offset + 0x71400)
# define VGA_DISP_DISABLE (1 << 31)
# define VGA_2X_MODE (1 << 30)
# define VGA_PIPE_B_SELECT (1 << 29)
--
1.7.12.4
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^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 10/33] drm/i915: Primary plane registers need an offset on VLV
2013-01-24 13:29 [PATCH 00/33] drm/915: Get rid of IS_DISPLAYREG() ville.syrjala
` (8 preceding siblings ...)
2013-01-24 13:29 ` [PATCH 09/33] drm/i915: VGACNTRL needs " ville.syrjala
@ 2013-01-24 13:29 ` ville.syrjala
2013-01-24 13:29 ` [PATCH 11/33] drm/i915: Pipe " ville.syrjala
` (22 subsequent siblings)
32 siblings, 0 replies; 67+ messages in thread
From: ville.syrjala @ 2013-01-24 13:29 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 36 ++++++++++++++++++------------------
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8b581b5..7ec9d58 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2985,7 +2985,7 @@
#define CURPOS_IVB(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS_IVB)
/* Display A control */
-#define _DSPACNTR 0x70180
+#define _DSPACNTR (dev_priv->info->display_mmio_offset + 0x70180)
#define DISPLAY_PLANE_ENABLE (1<<31)
#define DISPLAY_PLANE_DISABLE 0
#define DISPPLANE_GAMMA_ENABLE (1<<30)
@@ -3018,14 +3018,14 @@
#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
#define DISPPLANE_TILED (1<<10)
-#define _DSPAADDR 0x70184
-#define _DSPASTRIDE 0x70188
-#define _DSPAPOS 0x7018C /* reserved */
-#define _DSPASIZE 0x70190
-#define _DSPASURF 0x7019C /* 965+ only */
-#define _DSPATILEOFF 0x701A4 /* 965+ only */
-#define _DSPAOFFSET 0x701A4 /* HSW */
-#define _DSPASURFLIVE 0x701AC
+#define _DSPAADDR (dev_priv->info->display_mmio_offset + 0x70184)
+#define _DSPASTRIDE (dev_priv->info->display_mmio_offset + 0x70188)
+#define _DSPAPOS (dev_priv->info->display_mmio_offset + 0x7018C) /* reserved */
+#define _DSPASIZE (dev_priv->info->display_mmio_offset + 0x70190)
+#define _DSPASURF (dev_priv->info->display_mmio_offset + 0x7019C) /* 965+ only */
+#define _DSPATILEOFF (dev_priv->info->display_mmio_offset + 0x701A4) /* 965+ only */
+#define _DSPAOFFSET (dev_priv->info->display_mmio_offset + 0x701A4) /* HSW */
+#define _DSPASURFLIVE (dev_priv->info->display_mmio_offset + 0x701AC)
#define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR)
#define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR)
@@ -3071,19 +3071,19 @@
/* Display B control */
-#define _DSPBCNTR 0x71180
+#define _DSPBCNTR (dev_priv->info->display_mmio_offset + 0x71180)
#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
#define DISPPLANE_ALPHA_TRANS_DISABLE 0
#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
-#define _DSPBADDR 0x71184
-#define _DSPBSTRIDE 0x71188
-#define _DSPBPOS 0x7118C
-#define _DSPBSIZE 0x71190
-#define _DSPBSURF 0x7119C
-#define _DSPBTILEOFF 0x711A4
-#define _DSPBOFFSET 0x711A4
-#define _DSPBSURFLIVE 0x711AC
+#define _DSPBADDR (dev_priv->info->display_mmio_offset + 0x71184)
+#define _DSPBSTRIDE (dev_priv->info->display_mmio_offset + 0x71188)
+#define _DSPBPOS (dev_priv->info->display_mmio_offset + 0x7118C)
+#define _DSPBSIZE (dev_priv->info->display_mmio_offset + 0x71190)
+#define _DSPBSURF (dev_priv->info->display_mmio_offset + 0x7119C)
+#define _DSPBTILEOFF (dev_priv->info->display_mmio_offset + 0x711A4)
+#define _DSPBOFFSET (dev_priv->info->display_mmio_offset + 0x711A4)
+#define _DSPBSURFLIVE (dev_priv->info->display_mmio_offset + 0x711AC)
/* Sprite A control */
#define _DVSACNTR 0x72180
--
1.7.12.4
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^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 11/33] drm/i915: Pipe registers need an offset on VLV
2013-01-24 13:29 [PATCH 00/33] drm/915: Get rid of IS_DISPLAYREG() ville.syrjala
` (9 preceding siblings ...)
2013-01-24 13:29 ` [PATCH 10/33] drm/i915: Primary plane registers need " ville.syrjala
@ 2013-01-24 13:29 ` ville.syrjala
2013-01-24 13:29 ` [PATCH 12/33] drm/i915: Cursor " ville.syrjala
` (21 subsequent siblings)
32 siblings, 0 replies; 67+ messages in thread
From: ville.syrjala @ 2013-01-24 13:29 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7ec9d58..b859914 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2621,10 +2621,10 @@
/* Display & cursor control */
/* Pipe A */
-#define _PIPEADSL 0x70000
+#define _PIPEADSL (dev_priv->info->display_mmio_offset + 0x70000)
#define DSL_LINEMASK_GEN2 0x00000fff
#define DSL_LINEMASK_GEN3 0x00001fff
-#define _PIPEACONF 0x70008
+#define _PIPEACONF (dev_priv->info->display_mmio_offset + 0x70008)
#define PIPECONF_ENABLE (1<<31)
#define PIPECONF_DISABLE 0
#define PIPECONF_DOUBLE_WIDE (1<<30)
@@ -2665,7 +2665,7 @@
#define PIPECONF_DITHER_TYPE_ST1 (1<<2)
#define PIPECONF_DITHER_TYPE_ST2 (2<<2)
#define PIPECONF_DITHER_TYPE_TEMP (3<<2)
-#define _PIPEASTAT 0x70024
+#define _PIPEASTAT (dev_priv->info->display_mmio_offset + 0x70024)
#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
#define SPRITE1_FLIPDONE_INT_EN_VLV (1UL<<30)
#define PIPE_CRC_ERROR_ENABLE (1UL<<29)
@@ -2926,10 +2926,10 @@
* } while (high1 != high2);
* frame = (high1 << 8) | low1;
*/
-#define _PIPEAFRAMEHIGH 0x70040
+#define _PIPEAFRAMEHIGH (dev_priv->info->display_mmio_offset + 0x70040)
#define PIPE_FRAME_HIGH_MASK 0x0000ffff
#define PIPE_FRAME_HIGH_SHIFT 0
-#define _PIPEAFRAMEPIXEL 0x70044
+#define _PIPEAFRAMEPIXEL (dev_priv->info->display_mmio_offset + 0x70044)
#define PIPE_FRAME_LOW_MASK 0xff000000
#define PIPE_FRAME_LOW_SHIFT 24
#define PIPE_PIXEL_MASK 0x00ffffff
@@ -3061,11 +3061,11 @@
#define SWF32 (dev_priv->info->display_mmio_offset + 0x7241c)
/* Pipe B */
-#define _PIPEBDSL 0x71000
-#define _PIPEBCONF 0x71008
-#define _PIPEBSTAT 0x71024
-#define _PIPEBFRAMEHIGH 0x71040
-#define _PIPEBFRAMEPIXEL 0x71044
+#define _PIPEBDSL (dev_priv->info->display_mmio_offset + 0x71000)
+#define _PIPEBCONF (dev_priv->info->display_mmio_offset + 0x71008)
+#define _PIPEBSTAT (dev_priv->info->display_mmio_offset + 0x71024)
+#define _PIPEBFRAMEHIGH (dev_priv->info->display_mmio_offset + 0x71040)
+#define _PIPEBFRAMEPIXEL (dev_priv->info->display_mmio_offset + 0x71044)
#define _PIPEB_FRMCOUNT_GM45 0x71040
#define _PIPEB_FLIPCOUNT_GM45 0x71044
--
1.7.12.4
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 12/33] drm/i915: Cursor registers need an offset on VLV
2013-01-24 13:29 [PATCH 00/33] drm/915: Get rid of IS_DISPLAYREG() ville.syrjala
` (10 preceding siblings ...)
2013-01-24 13:29 ` [PATCH 11/33] drm/i915: Pipe " ville.syrjala
@ 2013-01-24 13:29 ` ville.syrjala
2013-01-24 13:29 ` [PATCH 13/33] drm/i915: VLV_DDL is VLV only and needs an offset ville.syrjala
` (20 subsequent siblings)
32 siblings, 0 replies; 67+ messages in thread
From: ville.syrjala @ 2013-01-24 13:29 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
CURSIZE is not present on VLV, so it was left out, as were the IVB
specific cursor B registers.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b859914..f31d770 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2940,7 +2940,7 @@
#define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45)
/* Cursor A & B regs */
-#define _CURACNTR 0x70080
+#define _CURACNTR (dev_priv->info->display_mmio_offset + 0x70080)
/* Old style CUR*CNTR flags (desktop 8xx) */
#define CURSOR_ENABLE 0x80000000
#define CURSOR_GAMMA_ENABLE 0x40000000
@@ -2961,16 +2961,16 @@
#define MCURSOR_PIPE_A 0x00
#define MCURSOR_PIPE_B (1 << 28)
#define MCURSOR_GAMMA_ENABLE (1 << 26)
-#define _CURABASE 0x70084
-#define _CURAPOS 0x70088
+#define _CURABASE (dev_priv->info->display_mmio_offset + 0x70084)
+#define _CURAPOS (dev_priv->info->display_mmio_offset + 0x70088)
#define CURSOR_POS_MASK 0x007FF
#define CURSOR_POS_SIGN 0x8000
#define CURSOR_X_SHIFT 0
#define CURSOR_Y_SHIFT 16
#define CURSIZE 0x700a0
-#define _CURBCNTR 0x700c0
-#define _CURBBASE 0x700c4
-#define _CURBPOS 0x700c8
+#define _CURBCNTR (dev_priv->info->display_mmio_offset + 0x700c0)
+#define _CURBBASE (dev_priv->info->display_mmio_offset + 0x700c4)
+#define _CURBPOS (dev_priv->info->display_mmio_offset + 0x700c8)
#define _CURBCNTR_IVB 0x71080
#define _CURBBASE_IVB 0x71084
--
1.7.12.4
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^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 13/33] drm/i915: VLV_DDL is VLV only and needs an offset
2013-01-24 13:29 [PATCH 00/33] drm/915: Get rid of IS_DISPLAYREG() ville.syrjala
` (11 preceding siblings ...)
2013-01-24 13:29 ` [PATCH 12/33] drm/i915: Cursor " ville.syrjala
@ 2013-01-24 13:29 ` ville.syrjala
2013-01-24 13:29 ` [PATCH 14/33] drm/i915: DSPFW registers need an offset on VLV ville.syrjala
` (19 subsequent siblings)
32 siblings, 0 replies; 67+ messages in thread
From: ville.syrjala @ 2013-01-24 13:29 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f31d770..98d65f8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2776,13 +2776,13 @@
/* drain latency register values*/
#define DRAIN_LATENCY_PRECISION_32 32
#define DRAIN_LATENCY_PRECISION_16 16
-#define VLV_DDL1 0x70050
+#define VLV_DDL1 (VLV_DISPLAY_BASE + 0x70050)
#define DDL_CURSORA_PRECISION_32 (1<<31)
#define DDL_CURSORA_PRECISION_16 (0<<31)
#define DDL_CURSORA_SHIFT 24
#define DDL_PLANEA_PRECISION_32 (1<<7)
#define DDL_PLANEA_PRECISION_16 (0<<7)
-#define VLV_DDL2 0x70054
+#define VLV_DDL2 (VLV_DISPLAY_BASE + 0x70054)
#define DDL_CURSORB_PRECISION_32 (1<<31)
#define DDL_CURSORB_PRECISION_16 (0<<31)
#define DDL_CURSORB_SHIFT 24
--
1.7.12.4
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^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 14/33] drm/i915: DSPFW registers need an offset on VLV
2013-01-24 13:29 [PATCH 00/33] drm/915: Get rid of IS_DISPLAYREG() ville.syrjala
` (12 preceding siblings ...)
2013-01-24 13:29 ` [PATCH 13/33] drm/i915: VLV_DDL is VLV only and needs an offset ville.syrjala
@ 2013-01-24 13:29 ` ville.syrjala
2013-01-24 13:29 ` [PATCH 15/33] drm/i915: DSPARB register needs " ville.syrjala
` (18 subsequent siblings)
32 siblings, 0 replies; 67+ messages in thread
From: ville.syrjala @ 2013-01-24 13:29 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 98d65f8..c3eaa69 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2752,7 +2752,7 @@
#define DSPARB_BEND_SHIFT 9 /* on 855 */
#define DSPARB_AEND_SHIFT 0
-#define DSPFW1 0x70034
+#define DSPFW1 (dev_priv->info->display_mmio_offset + 0x70034)
#define DSPFW_SR_SHIFT 23
#define DSPFW_SR_MASK (0x1ff<<23)
#define DSPFW_CURSORB_SHIFT 16
@@ -2760,11 +2760,11 @@
#define DSPFW_PLANEB_SHIFT 8
#define DSPFW_PLANEB_MASK (0x7f<<8)
#define DSPFW_PLANEA_MASK (0x7f)
-#define DSPFW2 0x70038
+#define DSPFW2 (dev_priv->info->display_mmio_offset + 0x70038)
#define DSPFW_CURSORA_MASK 0x00003f00
#define DSPFW_CURSORA_SHIFT 8
#define DSPFW_PLANEC_MASK (0x7f)
-#define DSPFW3 0x7003c
+#define DSPFW3 (dev_priv->info->display_mmio_offset + 0x7003c)
#define DSPFW_HPLL_SR_EN (1<<31)
#define DSPFW_CURSOR_SR_SHIFT 24
#define PINEVIEW_SELF_REFRESH_EN (1<<30)
--
1.7.12.4
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^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 15/33] drm/i915: DSPARB register needs an offset on VLV
2013-01-24 13:29 [PATCH 00/33] drm/915: Get rid of IS_DISPLAYREG() ville.syrjala
` (13 preceding siblings ...)
2013-01-24 13:29 ` [PATCH 14/33] drm/i915: DSPFW registers need an offset on VLV ville.syrjala
@ 2013-01-24 13:29 ` ville.syrjala
2013-01-24 22:01 ` Daniel Vetter
2013-01-24 13:29 ` [PATCH 16/33] drm/i915: DPFLIPSTAT and DPINVGTT registers are VLV only and need an offset ville.syrjala
` (17 subsequent siblings)
32 siblings, 1 reply; 67+ messages in thread
From: ville.syrjala @ 2013-01-24 13:29 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c3eaa69..3ac695d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2744,7 +2744,7 @@
#define PLANEA_INVALID_GTT_STATUS (1<<0)
#define DPINVGTT_STATUS_MASK 0xff
-#define DSPARB 0x70030
+#define DSPARB (dev_priv->info->display_mmio_offset + 0x70030)
#define DSPARB_CSTART_MASK (0x7f << 7)
#define DSPARB_CSTART_SHIFT 7
#define DSPARB_BSTART_MASK (0x7f)
--
1.7.12.4
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^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 16/33] drm/i915: DPFLIPSTAT and DPINVGTT registers are VLV only and need an offset
2013-01-24 13:29 [PATCH 00/33] drm/915: Get rid of IS_DISPLAYREG() ville.syrjala
` (14 preceding siblings ...)
2013-01-24 13:29 ` [PATCH 15/33] drm/i915: DSPARB register needs " ville.syrjala
@ 2013-01-24 13:29 ` ville.syrjala
2013-01-24 13:29 ` [PATCH 17/33] drm/i915: Pass VLV_DISPLAY_BASE + reg to intel_init_{sdvo, hdmi, dp} on VLV ville.syrjala
` (16 subsequent siblings)
32 siblings, 0 replies; 67+ messages in thread
From: ville.syrjala @ 2013-01-24 13:29 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3ac695d..f507550 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2710,7 +2710,7 @@
#define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
#define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
-#define VLV_DPFLIPSTAT 0x70028
+#define VLV_DPFLIPSTAT (VLV_DISPLAY_BASE + 0x70028)
#define PIPEB_LINE_COMPARE_INT_EN (1<<29)
#define PIPEB_HLINE_INT_EN (1<<28)
#define PIPEB_VBLANK_INT_EN (1<<27)
@@ -2724,7 +2724,7 @@
#define SPRITEA_FLIPDONE_INT_EN (1<<17)
#define PLANEA_FLIPDONE_INT_EN (1<<16)
-#define DPINVGTT 0x7002c /* VLV only */
+#define DPINVGTT (VLV_DISPLAY_BASE + 0x7002c) /* VLV only */
#define CURSORB_INVALID_GTT_INT_EN (1<<23)
#define CURSORA_INVALID_GTT_INT_EN (1<<22)
#define SPRITED_INVALID_GTT_INT_EN (1<<21)
--
1.7.12.4
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 17/33] drm/i915: Pass VLV_DISPLAY_BASE + reg to intel_init_{sdvo, hdmi, dp} on VLV
2013-01-24 13:29 [PATCH 00/33] drm/915: Get rid of IS_DISPLAYREG() ville.syrjala
` (15 preceding siblings ...)
2013-01-24 13:29 ` [PATCH 16/33] drm/i915: DPFLIPSTAT and DPINVGTT registers are VLV only and need an offset ville.syrjala
@ 2013-01-24 13:29 ` ville.syrjala
2013-01-24 22:05 ` Daniel Vetter
2013-01-24 13:29 ` [PATCH 18/33] drm/i915: Panel fitter registers need an offset " ville.syrjala
` (15 subsequent siblings)
32 siblings, 1 reply; 67+ messages in thread
From: ville.syrjala @ 2013-01-24 13:29 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
When passing the DP/HDMI/SDVO registers to the encoder init functions,
include the VLV specific offset in the value.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 26df9e3..60b5112 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8230,20 +8230,20 @@ static void intel_setup_outputs(struct drm_device *dev)
int found;
/* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
- if (I915_READ(DP_C) & DP_DETECTED)
- intel_dp_init(dev, DP_C, PORT_C);
+ if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
+ intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
- if (I915_READ(SDVOB) & PORT_DETECTED) {
+ if (I915_READ(VLV_DISPLAY_BASE + SDVOB) & PORT_DETECTED) {
/* SDVOB multiplex with HDMIB */
- found = intel_sdvo_init(dev, SDVOB, true);
+ found = intel_sdvo_init(dev, VLV_DISPLAY_BASE + SDVOB, true);
if (!found)
- intel_hdmi_init(dev, SDVOB, PORT_B);
- if (!found && (I915_READ(DP_B) & DP_DETECTED))
- intel_dp_init(dev, DP_B, PORT_B);
+ intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOB, PORT_B);
+ if (!found && (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED))
+ intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
}
- if (I915_READ(SDVOC) & PORT_DETECTED)
- intel_hdmi_init(dev, SDVOC, PORT_C);
+ if (I915_READ(VLV_DISPLAY_BASE + SDVOC) & PORT_DETECTED)
+ intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOC, PORT_C);
} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
bool found = false;
--
1.7.12.4
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 18/33] drm/i915: Panel fitter registers need an offset on VLV
2013-01-24 13:29 [PATCH 00/33] drm/915: Get rid of IS_DISPLAYREG() ville.syrjala
` (16 preceding siblings ...)
2013-01-24 13:29 ` [PATCH 17/33] drm/i915: Pass VLV_DISPLAY_BASE + reg to intel_init_{sdvo, hdmi, dp} on VLV ville.syrjala
@ 2013-01-24 13:29 ` ville.syrjala
2013-01-24 13:29 ` [PATCH 19/33] drm/i915: PORT_HOTPLUG " ville.syrjala
` (14 subsequent siblings)
32 siblings, 0 replies; 67+ messages in thread
From: ville.syrjala @ 2013-01-24 13:29 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f507550..8596995 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1861,7 +1861,7 @@
#define PP_DIVISOR 0x61210
/* Panel fitting */
-#define PFIT_CONTROL 0x61230
+#define PFIT_CONTROL (dev_priv->info->display_mmio_offset + 0x61230)
#define PFIT_ENABLE (1 << 31)
#define PFIT_PIPE_MASK (3 << 29)
#define PFIT_PIPE_SHIFT 29
@@ -1879,7 +1879,7 @@
#define PFIT_SCALING_PROGRAMMED (1 << 26)
#define PFIT_SCALING_PILLAR (2 << 26)
#define PFIT_SCALING_LETTER (3 << 26)
-#define PFIT_PGM_RATIOS 0x61234
+#define PFIT_PGM_RATIOS (dev_priv->info->display_mmio_offset + 0x61234)
/* Pre-965 */
#define PFIT_VERT_SCALE_SHIFT 20
#define PFIT_VERT_SCALE_MASK 0xfff00000
@@ -1891,7 +1891,7 @@
#define PFIT_HORIZ_SCALE_SHIFT_965 0
#define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
-#define PFIT_AUTO_RATIOS 0x61238
+#define PFIT_AUTO_RATIOS (dev_priv->info->display_mmio_offset + 0x61238)
/* Backlight control */
#define BLC_PWM_CTL2 0x61250 /* 965+ only */
--
1.7.12.4
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^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 19/33] drm/i915: PORT_HOTPLUG registers need an offset on VLV
2013-01-24 13:29 [PATCH 00/33] drm/915: Get rid of IS_DISPLAYREG() ville.syrjala
` (17 preceding siblings ...)
2013-01-24 13:29 ` [PATCH 18/33] drm/i915: Panel fitter registers need an offset " ville.syrjala
@ 2013-01-24 13:29 ` ville.syrjala
2013-01-24 13:29 ` [PATCH 20/33] drm/i915: VLV_ADPA must be used in VLV code ville.syrjala
` (13 subsequent siblings)
32 siblings, 0 replies; 67+ messages in thread
From: ville.syrjala @ 2013-01-24 13:29 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8596995..a8b4622 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1615,7 +1615,7 @@
/* Hotplug control (945+ only) */
-#define PORT_HOTPLUG_EN 0x61110
+#define PORT_HOTPLUG_EN (dev_priv->info->display_mmio_offset + 0x61110)
#define HDMIB_HOTPLUG_INT_EN (1 << 29)
#define DPB_HOTPLUG_INT_EN (1 << 29)
#define HDMIC_HOTPLUG_INT_EN (1 << 28)
@@ -1642,7 +1642,7 @@
#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
-#define PORT_HOTPLUG_STAT 0x61114
+#define PORT_HOTPLUG_STAT (dev_priv->info->display_mmio_offset + 0x61114)
/* HDMI/DP bits are gen4+ */
#define DPB_HOTPLUG_LIVE_STATUS (1 << 29)
#define DPC_HOTPLUG_LIVE_STATUS (1 << 28)
--
1.7.12.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 20/33] drm/i915: VLV_ADPA must be used in VLV code
2013-01-24 13:29 [PATCH 00/33] drm/915: Get rid of IS_DISPLAYREG() ville.syrjala
` (18 preceding siblings ...)
2013-01-24 13:29 ` [PATCH 19/33] drm/i915: PORT_HOTPLUG " ville.syrjala
@ 2013-01-24 13:29 ` ville.syrjala
2013-01-24 22:12 ` Daniel Vetter
2013-01-24 13:29 ` [PATCH 21/33] drm/i915: Pipe timing registers need an offset on VLV ville.syrjala
` (12 subsequent siblings)
32 siblings, 1 reply; 67+ messages in thread
From: ville.syrjala @ 2013-01-24 13:29 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
ADPA doesn't include the required offset, so don't use it in VLV
specific code. VLV_ADPA must be used instead.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_crt.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 71a5eba..9fe3d67 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -305,12 +305,12 @@ static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
bool ret;
u32 save_adpa;
- save_adpa = adpa = I915_READ(ADPA);
+ save_adpa = adpa = I915_READ(VLV_ADPA);
DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
- I915_WRITE(ADPA, adpa);
+ I915_WRITE(VLV_ADPA, adpa);
if (wait_for((I915_READ(ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
1000)) {
@@ -319,7 +319,7 @@ static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
}
/* Check the status to see if both blue and green are on now */
- adpa = I915_READ(ADPA);
+ adpa = I915_READ(VLV_ADPA);
if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
ret = true;
else
--
1.7.12.4
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^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 21/33] drm/i915: Pipe timing registers need an offset on VLV
2013-01-24 13:29 [PATCH 00/33] drm/915: Get rid of IS_DISPLAYREG() ville.syrjala
` (19 preceding siblings ...)
2013-01-24 13:29 ` [PATCH 20/33] drm/i915: VLV_ADPA must be used in VLV code ville.syrjala
@ 2013-01-24 13:29 ` ville.syrjala
2013-01-24 13:29 ` [PATCH 22/33] drm/i915: Pipe palette " ville.syrjala
` (11 subsequent siblings)
32 siblings, 0 replies; 67+ messages in thread
From: ville.syrjala @ 2013-01-24 13:29 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 36 ++++++++++++++++++------------------
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a8b4622..15ecded 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1535,26 +1535,26 @@
*/
/* Pipe A timing regs */
-#define _HTOTAL_A 0x60000
-#define _HBLANK_A 0x60004
-#define _HSYNC_A 0x60008
-#define _VTOTAL_A 0x6000c
-#define _VBLANK_A 0x60010
-#define _VSYNC_A 0x60014
-#define _PIPEASRC 0x6001c
-#define _BCLRPAT_A 0x60020
-#define _VSYNCSHIFT_A 0x60028
+#define _HTOTAL_A (dev_priv->info->display_mmio_offset + 0x60000)
+#define _HBLANK_A (dev_priv->info->display_mmio_offset + 0x60004)
+#define _HSYNC_A (dev_priv->info->display_mmio_offset + 0x60008)
+#define _VTOTAL_A (dev_priv->info->display_mmio_offset + 0x6000c)
+#define _VBLANK_A (dev_priv->info->display_mmio_offset + 0x60010)
+#define _VSYNC_A (dev_priv->info->display_mmio_offset + 0x60014)
+#define _PIPEASRC (dev_priv->info->display_mmio_offset + 0x6001c)
+#define _BCLRPAT_A (dev_priv->info->display_mmio_offset + 0x60020)
+#define _VSYNCSHIFT_A (dev_priv->info->display_mmio_offset + 0x60028)
/* Pipe B timing regs */
-#define _HTOTAL_B 0x61000
-#define _HBLANK_B 0x61004
-#define _HSYNC_B 0x61008
-#define _VTOTAL_B 0x6100c
-#define _VBLANK_B 0x61010
-#define _VSYNC_B 0x61014
-#define _PIPEBSRC 0x6101c
-#define _BCLRPAT_B 0x61020
-#define _VSYNCSHIFT_B 0x61028
+#define _HTOTAL_B (dev_priv->info->display_mmio_offset + 0x61000)
+#define _HBLANK_B (dev_priv->info->display_mmio_offset + 0x61004)
+#define _HSYNC_B (dev_priv->info->display_mmio_offset + 0x61008)
+#define _VTOTAL_B (dev_priv->info->display_mmio_offset + 0x6100c)
+#define _VBLANK_B (dev_priv->info->display_mmio_offset + 0x61010)
+#define _VSYNC_B (dev_priv->info->display_mmio_offset + 0x61014)
+#define _PIPEBSRC (dev_priv->info->display_mmio_offset + 0x6101c)
+#define _BCLRPAT_B (dev_priv->info->display_mmio_offset + 0x61020)
+#define _VSYNCSHIFT_B (dev_priv->info->display_mmio_offset + 0x61028)
#define HTOTAL(trans) _TRANSCODER(trans, _HTOTAL_A, _HTOTAL_B)
--
1.7.12.4
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 22/33] drm/i915: Pipe palette registers need an offset on VLV
2013-01-24 13:29 [PATCH 00/33] drm/915: Get rid of IS_DISPLAYREG() ville.syrjala
` (20 preceding siblings ...)
2013-01-24 13:29 ` [PATCH 21/33] drm/i915: Pipe timing registers need an offset on VLV ville.syrjala
@ 2013-01-24 13:29 ` ville.syrjala
2013-01-24 22:22 ` Daniel Vetter
2013-01-24 13:29 ` [PATCH 23/33] drm/i915: FB_BLC_SELF_VLV is VLV only and needs an offset ville.syrjala
` (10 subsequent siblings)
32 siblings, 1 reply; 67+ messages in thread
From: ville.syrjala @ 2013-01-24 13:29 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 15ecded..7c71622 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1169,8 +1169,8 @@
* Palette regs
*/
-#define _PALETTE_A 0x0a000
-#define _PALETTE_B 0x0a800
+#define _PALETTE_A (dev_priv->info->display_mmio_offset + 0xa000)
+#define _PALETTE_B (dev_priv->info->display_mmio_offset + 0xa800)
#define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B)
/* MCH MMIO space */
--
1.7.12.4
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^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 23/33] drm/i915: FB_BLC_SELF_VLV is VLV only and needs an offset
2013-01-24 13:29 [PATCH 00/33] drm/915: Get rid of IS_DISPLAYREG() ville.syrjala
` (21 preceding siblings ...)
2013-01-24 13:29 ` [PATCH 22/33] drm/i915: Pipe palette " ville.syrjala
@ 2013-01-24 13:29 ` ville.syrjala
2013-01-24 13:29 ` [PATCH 24/33] drm/i915: VLV doesn't seem to have VGA0/VGA1/VGA_PD registers ville.syrjala
` (9 subsequent siblings)
32 siblings, 0 replies; 67+ messages in thread
From: ville.syrjala @ 2013-01-24 13:29 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7c71622..1c1e7f8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1162,7 +1162,7 @@
#define RAMCLK_GATE_D 0x6210 /* CRL only */
#define DEUC 0x6214 /* CRL only */
-#define FW_BLC_SELF_VLV 0x6500
+#define FW_BLC_SELF_VLV (VLV_DISPLAY_BASE + 0x6500)
#define FW_CSPWRDWNEN (1<<15)
/*
--
1.7.12.4
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^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 24/33] drm/i915: VLV doesn't seem to have VGA0/VGA1/VGA_PD registers
2013-01-24 13:29 [PATCH 00/33] drm/915: Get rid of IS_DISPLAYREG() ville.syrjala
` (22 preceding siblings ...)
2013-01-24 13:29 ` [PATCH 23/33] drm/i915: FB_BLC_SELF_VLV is VLV only and needs an offset ville.syrjala
@ 2013-01-24 13:29 ` ville.syrjala
2013-01-24 22:26 ` Daniel Vetter
2013-01-24 13:29 ` [PATCH 25/33] drm/i915: PLL and clock gating registers need an offset on VLV ville.syrjala
` (8 subsequent siblings)
32 siblings, 1 reply; 67+ messages in thread
From: ville.syrjala @ 2013-01-24 13:29 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Don't touch VGA0/VGA1/VGA_PD in suspend/resume paths.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_suspend.c | 20 ++++++++++++--------
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 63d4d30..05d82dc 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -691,9 +691,11 @@ static void i915_save_display(struct drm_device *dev)
}
/* VGA state */
- dev_priv->regfile.saveVGA0 = I915_READ(VGA0);
- dev_priv->regfile.saveVGA1 = I915_READ(VGA1);
- dev_priv->regfile.saveVGA_PD = I915_READ(VGA_PD);
+ if (!IS_VALLEYVIEW(dev)) {
+ dev_priv->regfile.saveVGA0 = I915_READ(VGA0);
+ dev_priv->regfile.saveVGA1 = I915_READ(VGA1);
+ dev_priv->regfile.saveVGA_PD = I915_READ(VGA_PD);
+ }
if (HAS_PCH_SPLIT(dev))
dev_priv->regfile.saveVGACNTRL = I915_READ(CPU_VGACNTRL);
else
@@ -793,11 +795,13 @@ static void i915_restore_display(struct drm_device *dev)
else
I915_WRITE(VGACNTRL, dev_priv->regfile.saveVGACNTRL);
- I915_WRITE(VGA0, dev_priv->regfile.saveVGA0);
- I915_WRITE(VGA1, dev_priv->regfile.saveVGA1);
- I915_WRITE(VGA_PD, dev_priv->regfile.saveVGA_PD);
- POSTING_READ(VGA_PD);
- udelay(150);
+ if (!IS_VALLEYVIEW(dev)) {
+ I915_WRITE(VGA0, dev_priv->regfile.saveVGA0);
+ I915_WRITE(VGA1, dev_priv->regfile.saveVGA1);
+ I915_WRITE(VGA_PD, dev_priv->regfile.saveVGA_PD);
+ POSTING_READ(VGA_PD);
+ udelay(150);
+ }
i915_restore_vga(dev);
}
--
1.7.12.4
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^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 25/33] drm/i915: PLL and clock gating registers need an offset on VLV
2013-01-24 13:29 [PATCH 00/33] drm/915: Get rid of IS_DISPLAYREG() ville.syrjala
` (23 preceding siblings ...)
2013-01-24 13:29 ` [PATCH 24/33] drm/i915: VLV doesn't seem to have VGA0/VGA1/VGA_PD registers ville.syrjala
@ 2013-01-24 13:29 ` ville.syrjala
2013-01-24 22:41 ` Daniel Vetter
2013-01-24 13:29 ` [PATCH 26/33] drm/i915: Make VLV_GUNIT_CLOCK_GATE register value more readable ville.syrjala
` (7 subsequent siblings)
32 siblings, 1 reply; 67+ messages in thread
From: ville.syrjala @ 2013-01-24 13:29 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1c1e7f8..c3d4ddc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -922,8 +922,8 @@
#define VGA1_PD_P1_DIV_2 (1 << 13)
#define VGA1_PD_P1_SHIFT 8
#define VGA1_PD_P1_MASK (0x1f << 8)
-#define _DPLL_A 0x06014
-#define _DPLL_B 0x06018
+#define _DPLL_A (dev_priv->info->display_mmio_offset + 0x6014)
+#define _DPLL_B (dev_priv->info->display_mmio_offset + 0x6018)
#define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
#define DPLL_VCO_ENABLE (1 << 31)
#define DPLL_DVO_HIGH_SPEED (1 << 30)
@@ -982,7 +982,7 @@
#define SDVO_MULTIPLIER_MASK 0x000000ff
#define SDVO_MULTIPLIER_SHIFT_HIRES 4
#define SDVO_MULTIPLIER_SHIFT_VGA 0
-#define _DPLL_A_MD 0x0601c /* 965+ only */
+#define _DPLL_A_MD (dev_priv->info->display_mmio_offset + 0x601c) /* 965+ only */
/*
* UDI pixel divider, controlling how many pixels are stuffed into a packet.
*
@@ -1019,7 +1019,7 @@
*/
#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
-#define _DPLL_B_MD 0x06020 /* 965+ only */
+#define _DPLL_B_MD (dev_priv->info->display_mmio_offset + 0x6020) /* 965+ only */
#define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD)
#define _FPA0 0x06040
@@ -1047,12 +1047,12 @@
#define DPLLA_TEST_N_BYPASS (1 << 3)
#define DPLLA_TEST_M_BYPASS (1 << 2)
#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
-#define D_STATE 0x6104
+#define D_STATE (dev_priv->info->display_mmio_offset + 0x6104)
#define DSTATE_GFX_RESET_I830 (1<<6)
#define DSTATE_PLL_D3_OFF (1<<3)
#define DSTATE_GFX_CLOCK_GATING (1<<1)
#define DSTATE_DOT_CLOCK_GATING (1<<0)
-#define DSPCLK_GATE_D 0x6200
+#define DSPCLK_GATE_D (dev_priv->info->display_mmio_offset + 0x6200)
# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
@@ -1159,7 +1159,7 @@
#define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
#define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
#define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
-#define RAMCLK_GATE_D 0x6210 /* CRL only */
+#define RAMCLK_GATE_D (dev_priv->info->display_mmio_offset + 0x6210) /* CRL only */
#define DEUC 0x6214 /* CRL only */
#define FW_BLC_SELF_VLV (VLV_DISPLAY_BASE + 0x6500)
--
1.7.12.4
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^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 26/33] drm/i915: Make VLV_GUNIT_CLOCK_GATE register value more readable
2013-01-24 13:29 [PATCH 00/33] drm/915: Get rid of IS_DISPLAYREG() ville.syrjala
` (24 preceding siblings ...)
2013-01-24 13:29 ` [PATCH 25/33] drm/i915: PLL and clock gating registers need an offset on VLV ville.syrjala
@ 2013-01-24 13:29 ` ville.syrjala
2013-01-24 13:29 ` [PATCH 27/33] drm/i915: Spell out VLV_DISPLAY_BASE for interrupt registers ville.syrjala
` (6 subsequent siblings)
32 siblings, 0 replies; 67+ messages in thread
From: ville.syrjala @ 2013-01-24 13:29 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Instead of 0x18xxxx use (VLV_DISPLAY_BASE + xxxx).
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c3d4ddc..943eda3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -557,7 +557,7 @@
#define IIR 0x020a4
#define IMR 0x020a8
#define ISR 0x020ac
-#define VLV_GUNIT_CLOCK_GATE 0x182060
+#define VLV_GUNIT_CLOCK_GATE (VLV_DISPLAY_BASE + 0x2060)
#define GCFG_DIS (1<<8)
#define VLV_IIR_RW 0x182084
#define VLV_IER 0x1820a0
--
1.7.12.4
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 27/33] drm/i915: Spell out VLV_DISPLAY_BASE for interrupt registers
2013-01-24 13:29 [PATCH 00/33] drm/915: Get rid of IS_DISPLAYREG() ville.syrjala
` (25 preceding siblings ...)
2013-01-24 13:29 ` [PATCH 26/33] drm/i915: Make VLV_GUNIT_CLOCK_GATE register value more readable ville.syrjala
@ 2013-01-24 13:29 ` ville.syrjala
2013-01-24 13:29 ` [PATCH 28/33] drm/i915: DPIO registers are VLV only and need an offset ville.syrjala
` (5 subsequent siblings)
32 siblings, 0 replies; 67+ messages in thread
From: ville.syrjala @ 2013-01-24 13:29 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Instead of 0x18xxxx use (VLV_DISPLAY_BASE + xxxx).
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 943eda3..6a944b5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -559,11 +559,11 @@
#define ISR 0x020ac
#define VLV_GUNIT_CLOCK_GATE (VLV_DISPLAY_BASE + 0x2060)
#define GCFG_DIS (1<<8)
-#define VLV_IIR_RW 0x182084
-#define VLV_IER 0x1820a0
-#define VLV_IIR 0x1820a4
-#define VLV_IMR 0x1820a8
-#define VLV_ISR 0x1820ac
+#define VLV_IIR_RW (VLV_DISPLAY_BASE + 0x2084)
+#define VLV_IER (VLV_DISPLAY_BASE + 0x20a0)
+#define VLV_IIR (VLV_DISPLAY_BASE + 0x20a4)
+#define VLV_IMR (VLV_DISPLAY_BASE + 0x20a8)
+#define VLV_ISR (VLV_DISPLAY_BASE + 0x20ac)
#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
#define I915_DISPLAY_PORT_INTERRUPT (1<<17)
#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
--
1.7.12.4
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 28/33] drm/i915: DPIO registers are VLV only and need an offset
2013-01-24 13:29 [PATCH 00/33] drm/915: Get rid of IS_DISPLAYREG() ville.syrjala
` (26 preceding siblings ...)
2013-01-24 13:29 ` [PATCH 27/33] drm/i915: Spell out VLV_DISPLAY_BASE for interrupt registers ville.syrjala
@ 2013-01-24 13:29 ` ville.syrjala
2013-01-24 13:29 ` [PATCH 29/33] drm/i915: VGA registers need an offset on VLV ville.syrjala
` (4 subsequent siblings)
32 siblings, 0 replies; 67+ messages in thread
From: ville.syrjala @ 2013-01-24 13:29 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6a944b5..c149426 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -336,17 +336,19 @@
* 0x801c/3c: core clock bits
* 0x8048/68: low pass filter coefficients
* 0x8100: fast clock controls
+ *
+ * DPIO is VLV only.
*/
-#define DPIO_PKT 0x2100
+#define DPIO_PKT (VLV_DISPLAY_BASE + 0x2100)
#define DPIO_RID (0<<24)
#define DPIO_OP_WRITE (1<<16)
#define DPIO_OP_READ (0<<16)
#define DPIO_PORTID (0x12<<8)
#define DPIO_BYTE (0xf<<4)
#define DPIO_BUSY (1<<0) /* status only */
-#define DPIO_DATA 0x2104
-#define DPIO_REG 0x2108
-#define DPIO_CTL 0x2110
+#define DPIO_DATA (VLV_DISPLAY_BASE + 0x2104)
+#define DPIO_REG (VLV_DISPLAY_BASE + 0x2108)
+#define DPIO_CTL (VLV_DISPLAY_BASE + 0x2110)
#define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */
#define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */
#define DPIO_SFR_BYPASS (1<<1)
--
1.7.12.4
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 29/33] drm/i915: VGA registers need an offset on VLV
2013-01-24 13:29 [PATCH 00/33] drm/915: Get rid of IS_DISPLAYREG() ville.syrjala
` (27 preceding siblings ...)
2013-01-24 13:29 ` [PATCH 28/33] drm/i915: DPIO registers are VLV only and need an offset ville.syrjala
@ 2013-01-24 13:29 ` ville.syrjala
2013-01-24 22:44 ` Daniel Vetter
2013-01-24 13:29 ` [PATCH 30/33] drm/i915: GPIO/GMBUS " ville.syrjala
` (3 subsequent siblings)
32 siblings, 1 reply; 67+ messages in thread
From: ville.syrjala @ 2013-01-24 13:29 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 38 +++++++++++++++++++-------------------
1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c149426..75b46c8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -133,25 +133,25 @@
/* VGA stuff */
-#define VGA_ST01_MDA 0x3ba
-#define VGA_ST01_CGA 0x3da
+#define VGA_ST01_MDA (dev_priv->info->display_mmio_offset + 0x3ba)
+#define VGA_ST01_CGA (dev_priv->info->display_mmio_offset + 0x3da)
-#define VGA_MSR_WRITE 0x3c2
-#define VGA_MSR_READ 0x3cc
+#define VGA_MSR_WRITE (dev_priv->info->display_mmio_offset + 0x3c2)
+#define VGA_MSR_READ (dev_priv->info->display_mmio_offset + 0x3cc)
#define VGA_MSR_MEM_EN (1<<1)
#define VGA_MSR_CGA_MODE (1<<0)
-#define VGA_SR_INDEX 0x3c4
+#define VGA_SR_INDEX (dev_priv->info->display_mmio_offset + 0x3c4)
#define SR01 1
-#define VGA_SR_DATA 0x3c5
+#define VGA_SR_DATA (dev_priv->info->display_mmio_offset + 0x3c5)
-#define VGA_AR_INDEX 0x3c0
+#define VGA_AR_INDEX (dev_priv->info->display_mmio_offset + 0x3c0)
#define VGA_AR_VID_EN (1<<5)
-#define VGA_AR_DATA_WRITE 0x3c0
-#define VGA_AR_DATA_READ 0x3c1
+#define VGA_AR_DATA_WRITE (dev_priv->info->display_mmio_offset + 0x3c0)
+#define VGA_AR_DATA_READ (dev_priv->info->display_mmio_offset + 0x3c1)
-#define VGA_GR_INDEX 0x3ce
-#define VGA_GR_DATA 0x3cf
+#define VGA_GR_INDEX (dev_priv->info->display_mmio_offset + 0x3ce)
+#define VGA_GR_DATA (dev_priv->info->display_mmio_offset + 0x3cf)
/* GR05 */
#define VGA_GR_MEM_READ_MODE_SHIFT 3
#define VGA_GR_MEM_READ_MODE_PLANE 1
@@ -163,15 +163,15 @@
#define VGA_GR_MEM_B0000_B7FFF 2
#define VGA_GR_MEM_B0000_BFFFF 3
-#define VGA_DACMASK 0x3c6
-#define VGA_DACRX 0x3c7
-#define VGA_DACWX 0x3c8
-#define VGA_DACDATA 0x3c9
+#define VGA_DACMASK (dev_priv->info->display_mmio_offset + 0x3c6)
+#define VGA_DACRX (dev_priv->info->display_mmio_offset + 0x3c7)
+#define VGA_DACWX (dev_priv->info->display_mmio_offset + 0x3c8)
+#define VGA_DACDATA (dev_priv->info->display_mmio_offset + 0x3c9)
-#define VGA_CR_INDEX_MDA 0x3b4
-#define VGA_CR_DATA_MDA 0x3b5
-#define VGA_CR_INDEX_CGA 0x3d4
-#define VGA_CR_DATA_CGA 0x3d5
+#define VGA_CR_INDEX_MDA (dev_priv->info->display_mmio_offset + 0x3b4)
+#define VGA_CR_DATA_MDA (dev_priv->info->display_mmio_offset + 0x3b5)
+#define VGA_CR_INDEX_CGA (dev_priv->info->display_mmio_offset + 0x3d4)
+#define VGA_CR_DATA_CGA (dev_priv->info->display_mmio_offset + 0x3d5)
/*
* Memory interface instructions used by the kernel
--
1.7.12.4
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^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 30/33] drm/i915: GPIO/GMBUS registers need an offset on VLV
2013-01-24 13:29 [PATCH 00/33] drm/915: Get rid of IS_DISPLAYREG() ville.syrjala
` (28 preceding siblings ...)
2013-01-24 13:29 ` [PATCH 29/33] drm/i915: VGA registers need an offset on VLV ville.syrjala
@ 2013-01-24 13:29 ` ville.syrjala
2013-01-24 13:29 ` [PATCH 31/33] drm/i915: Set display_mmio_offset for VLV ville.syrjala
` (2 subsequent siblings)
32 siblings, 0 replies; 67+ messages in thread
From: ville.syrjala @ 2013-01-24 13:29 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
GPIO/GMBUS registers must be offset on VLV, so simply
adjust gpio_mmio_base to include the correct offset.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_i2c.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 7f09041..acf8aec 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -515,6 +515,8 @@ int intel_setup_gmbus(struct drm_device *dev)
if (HAS_PCH_SPLIT(dev))
dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;
+ else if (IS_VALLEYVIEW(dev))
+ dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
else
dev_priv->gpio_mmio_base = 0;
--
1.7.12.4
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^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 31/33] drm/i915: Set display_mmio_offset for VLV
2013-01-24 13:29 [PATCH 00/33] drm/915: Get rid of IS_DISPLAYREG() ville.syrjala
` (29 preceding siblings ...)
2013-01-24 13:29 ` [PATCH 30/33] drm/i915: GPIO/GMBUS " ville.syrjala
@ 2013-01-24 13:29 ` ville.syrjala
2013-01-24 22:59 ` Daniel Vetter
2013-01-24 13:29 ` [PATCH 32/33] drm/i915: Kill IS_DISPLAYREG() ville.syrjala
2013-01-24 13:29 ` [PATCH 33/33] drm/i915: Kill VLV specific interrupts registers ville.syrjala
32 siblings, 1 reply; 67+ messages in thread
From: ville.syrjala @ 2013-01-24 13:29 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
This will cause display registers to include the correct
offset on VLV.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 3ff8e73..521a253 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -276,6 +276,7 @@ static const struct intel_device_info intel_valleyview_m_info = {
.has_bsd_ring = 1,
.has_blt_ring = 1,
.is_valleyview = 1,
+ .display_mmio_offset = VLV_DISPLAY_BASE,
};
static const struct intel_device_info intel_valleyview_d_info = {
@@ -285,6 +286,7 @@ static const struct intel_device_info intel_valleyview_d_info = {
.has_bsd_ring = 1,
.has_blt_ring = 1,
.is_valleyview = 1,
+ .display_mmio_offset = VLV_DISPLAY_BASE,
};
static const struct intel_device_info intel_haswell_d_info = {
--
1.7.12.4
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^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 32/33] drm/i915: Kill IS_DISPLAYREG()
2013-01-24 13:29 [PATCH 00/33] drm/915: Get rid of IS_DISPLAYREG() ville.syrjala
` (30 preceding siblings ...)
2013-01-24 13:29 ` [PATCH 31/33] drm/i915: Set display_mmio_offset for VLV ville.syrjala
@ 2013-01-24 13:29 ` ville.syrjala
2013-01-24 13:29 ` [PATCH 33/33] drm/i915: Kill VLV specific interrupts registers ville.syrjala
32 siblings, 0 replies; 67+ messages in thread
From: ville.syrjala @ 2013-01-24 13:29 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
All display registers should now include the proper offset on VLV.
That means IS_DISPLAYREG() is now useless, and we can eliminate it.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 104 +---------------------------------------
1 file changed, 1 insertion(+), 103 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 521a253..1a5b04a 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1117,102 +1117,6 @@ MODULE_LICENSE("GPL and additional rights");
((HAS_FORCE_WAKE((dev_priv)->dev)) && \
((reg) < 0x40000) && \
((reg) != FORCEWAKE))
-
-static bool IS_DISPLAYREG(u32 reg)
-{
- /*
- * This should make it easier to transition modules over to the
- * new register block scheme, since we can do it incrementally.
- */
- if (reg >= VLV_DISPLAY_BASE)
- return false;
-
- if (reg >= RENDER_RING_BASE &&
- reg < RENDER_RING_BASE + 0xff)
- return false;
- if (reg >= GEN6_BSD_RING_BASE &&
- reg < GEN6_BSD_RING_BASE + 0xff)
- return false;
- if (reg >= BLT_RING_BASE &&
- reg < BLT_RING_BASE + 0xff)
- return false;
-
- if (reg == PGTBL_ER)
- return false;
-
- if (reg >= IPEIR_I965 &&
- reg < HWSTAM)
- return false;
-
- if (reg == MI_MODE)
- return false;
-
- if (reg == GFX_MODE_GEN7)
- return false;
-
- if (reg == RENDER_HWS_PGA_GEN7 ||
- reg == BSD_HWS_PGA_GEN7 ||
- reg == BLT_HWS_PGA_GEN7)
- return false;
-
- if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL ||
- reg == GEN6_BSD_RNCID)
- return false;
-
- if (reg == GEN6_BLITTER_ECOSKPD)
- return false;
-
- if (reg >= 0x4000c &&
- reg <= 0x4002c)
- return false;
-
- if (reg >= 0x4f000 &&
- reg <= 0x4f08f)
- return false;
-
- if (reg >= 0x4f100 &&
- reg <= 0x4f11f)
- return false;
-
- if (reg >= VLV_MASTER_IER &&
- reg <= GEN6_PMIER)
- return false;
-
- if (reg >= FENCE_REG_SANDYBRIDGE_0 &&
- reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8)))
- return false;
-
- if (reg >= VLV_IIR_RW &&
- reg <= VLV_ISR)
- return false;
-
- if (reg == FORCEWAKE_VLV ||
- reg == FORCEWAKE_ACK_VLV)
- return false;
-
- if (reg == GEN6_GDRST)
- return false;
-
- switch (reg) {
- case _3D_CHICKEN3:
- case IVB_CHICKEN3:
- case GEN7_COMMON_SLICE_CHICKEN1:
- case GEN7_L3CNTLREG1:
- case GEN7_L3_CHICKEN_MODE_REGISTER:
- case GEN7_ROW_CHICKEN2:
- case GEN7_L3SQCREG4:
- case GEN7_SQ_CHICKEN_MBCUNIT_CONFIG:
- case GEN7_HALF_SLICE_CHICKEN1:
- case GEN6_MBCTL:
- case GEN6_UCGCTL2:
- return false;
- default:
- break;
- }
-
- return true;
-}
-
static void
ilk_dummy_write(struct drm_i915_private *dev_priv)
{
@@ -1236,8 +1140,6 @@ u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
if (dev_priv->forcewake_count == 0) \
dev_priv->gt.force_wake_put(dev_priv); \
spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
- } else if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
- val = read##y(dev_priv->regs + reg + 0x180000); \
} else { \
val = read##y(dev_priv->regs + reg); \
} \
@@ -1264,11 +1166,7 @@ void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
DRM_ERROR("Unknown unclaimed register before writing to %x\n", reg); \
I915_WRITE_NOTRACE(GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \
} \
- if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
- write##y(val, dev_priv->regs + reg + 0x180000); \
- } else { \
- write##y(val, dev_priv->regs + reg); \
- } \
+ write##y(val, dev_priv->regs + reg); \
if (unlikely(__fifo_ret)) { \
gen6_gt_check_fifodbg(dev_priv); \
} \
--
1.7.12.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [PATCH 33/33] drm/i915: Kill VLV specific interrupts registers
2013-01-24 13:29 [PATCH 00/33] drm/915: Get rid of IS_DISPLAYREG() ville.syrjala
` (31 preceding siblings ...)
2013-01-24 13:29 ` [PATCH 32/33] drm/i915: Kill IS_DISPLAYREG() ville.syrjala
@ 2013-01-24 13:29 ` ville.syrjala
32 siblings, 0 replies; 67+ messages in thread
From: ville.syrjala @ 2013-01-24 13:29 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Apart from VLV_IIR_RW all the VLV interrupt registers are the
same as on pre-PCH platforms.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 6 ++---
drivers/gpu/drm/i915/i915_irq.c | 44 ++++++++++++++++++-------------------
drivers/gpu/drm/i915/i915_reg.h | 12 ++++------
3 files changed, 29 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 18971f5..76c5b2f 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -430,13 +430,13 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
if (IS_VALLEYVIEW(dev)) {
seq_printf(m, "Display IER:\t%08x\n",
- I915_READ(VLV_IER));
+ I915_READ(IER));
seq_printf(m, "Display IIR:\t%08x\n",
- I915_READ(VLV_IIR));
+ I915_READ(IIR));
seq_printf(m, "Display IIR_RW:\t%08x\n",
I915_READ(VLV_IIR_RW));
seq_printf(m, "Display IMR:\t%08x\n",
- I915_READ(VLV_IMR));
+ I915_READ(IMR));
for_each_pipe(pipe)
seq_printf(m, "Pipe %c stat:\t%08x\n",
pipe_name(pipe),
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9a9dda1..48c23af 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -552,7 +552,7 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
atomic_inc(&dev_priv->irq_received);
while (true) {
- iir = I915_READ(VLV_IIR);
+ iir = I915_READ(IIR);
gt_iir = I915_READ(GTIIR);
pm_iir = I915_READ(GEN6_PMIIR);
@@ -612,7 +612,7 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
I915_WRITE(GTIIR, gt_iir);
I915_WRITE(GEN6_PMIIR, pm_iir);
- I915_WRITE(VLV_IIR, iir);
+ I915_WRITE(IIR, iir);
}
out:
@@ -1317,7 +1317,7 @@ static void i915_capture_error_state(struct drm_device *dev)
if (HAS_PCH_SPLIT(dev))
error->ier = I915_READ(DEIER) | I915_READ(GTIER);
else if (IS_VALLEYVIEW(dev))
- error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
+ error->ier = I915_READ(GTIER) | I915_READ(IER);
else if (IS_GEN2(dev))
error->ier = I915_READ16(IER);
else
@@ -1659,12 +1659,12 @@ static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
return -EINVAL;
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
- imr = I915_READ(VLV_IMR);
+ imr = I915_READ(IMR);
if (pipe == 0)
imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
else
imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
- I915_WRITE(VLV_IMR, imr);
+ I915_WRITE(IMR, imr);
i915_enable_pipestat(dev_priv, pipe,
PIPE_START_VBLANK_INTERRUPT_ENABLE);
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
@@ -1721,12 +1721,12 @@ static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
i915_disable_pipestat(dev_priv, pipe,
PIPE_START_VBLANK_INTERRUPT_ENABLE);
- imr = I915_READ(VLV_IMR);
+ imr = I915_READ(IMR);
if (pipe == 0)
imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
else
imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
- I915_WRITE(VLV_IMR, imr);
+ I915_WRITE(IMR, imr);
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}
@@ -1892,7 +1892,7 @@ static void valleyview_irq_preinstall(struct drm_device *dev)
atomic_set(&dev_priv->irq_received, 0);
/* VLV magic */
- I915_WRITE(VLV_IMR, 0);
+ I915_WRITE(IMR, 0);
I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
@@ -1910,10 +1910,10 @@ static void valleyview_irq_preinstall(struct drm_device *dev)
I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
for_each_pipe(pipe)
I915_WRITE(PIPESTAT(pipe), 0xffff);
- I915_WRITE(VLV_IIR, 0xffffffff);
- I915_WRITE(VLV_IMR, 0xffffffff);
- I915_WRITE(VLV_IER, 0x0);
- POSTING_READ(VLV_IER);
+ I915_WRITE(IIR, 0xffffffff);
+ I915_WRITE(IMR, 0xffffffff);
+ I915_WRITE(IER, 0x0);
+ POSTING_READ(IER);
}
/*
@@ -2097,19 +2097,19 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
I915_WRITE(PORT_HOTPLUG_EN, 0);
POSTING_READ(PORT_HOTPLUG_EN);
- I915_WRITE(VLV_IMR, dev_priv->irq_mask);
- I915_WRITE(VLV_IER, enable_mask);
- I915_WRITE(VLV_IIR, 0xffffffff);
+ I915_WRITE(IMR, dev_priv->irq_mask);
+ I915_WRITE(IER, enable_mask);
+ I915_WRITE(IIR, 0xffffffff);
I915_WRITE(PIPESTAT(0), 0xffff);
I915_WRITE(PIPESTAT(1), 0xffff);
- POSTING_READ(VLV_IER);
+ POSTING_READ(IER);
i915_enable_pipestat(dev_priv, 0, pipestat_enable);
i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
i915_enable_pipestat(dev_priv, 1, pipestat_enable);
- I915_WRITE(VLV_IIR, 0xffffffff);
- I915_WRITE(VLV_IIR, 0xffffffff);
+ I915_WRITE(IIR, 0xffffffff);
+ I915_WRITE(IIR, 0xffffffff);
I915_WRITE(GTIIR, I915_READ(GTIIR));
I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
@@ -2170,10 +2170,10 @@ static void valleyview_irq_uninstall(struct drm_device *dev)
I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
for_each_pipe(pipe)
I915_WRITE(PIPESTAT(pipe), 0xffff);
- I915_WRITE(VLV_IIR, 0xffffffff);
- I915_WRITE(VLV_IMR, 0xffffffff);
- I915_WRITE(VLV_IER, 0x0);
- POSTING_READ(VLV_IER);
+ I915_WRITE(IIR, 0xffffffff);
+ I915_WRITE(IMR, 0xffffffff);
+ I915_WRITE(IER, 0x0);
+ POSTING_READ(IER);
}
static void ironlake_irq_uninstall(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 75b46c8..092066f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -555,17 +555,13 @@
#define VLV_DISPLAY_BASE 0x180000
#define SCPD0 0x0209c /* 915+ only */
-#define IER 0x020a0
-#define IIR 0x020a4
-#define IMR 0x020a8
-#define ISR 0x020ac
+#define IER (dev_priv->info->display_mmio_offset + 0x20a0)
+#define IIR (dev_priv->info->display_mmio_offset + 0x20a4)
+#define IMR (dev_priv->info->display_mmio_offset + 0x20a8)
+#define ISR (dev_priv->info->display_mmio_offset + 0x20ac)
#define VLV_GUNIT_CLOCK_GATE (VLV_DISPLAY_BASE + 0x2060)
#define GCFG_DIS (1<<8)
#define VLV_IIR_RW (VLV_DISPLAY_BASE + 0x2084)
-#define VLV_IER (VLV_DISPLAY_BASE + 0x20a0)
-#define VLV_IIR (VLV_DISPLAY_BASE + 0x20a4)
-#define VLV_IMR (VLV_DISPLAY_BASE + 0x20a8)
-#define VLV_ISR (VLV_DISPLAY_BASE + 0x20ac)
#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
#define I915_DISPLAY_PORT_INTERRUPT (1<<17)
#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
--
1.7.12.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 67+ messages in thread
* Re: [PATCH 01/33] drm/i915: Convert intel_hdmi to enum port
2013-01-24 13:29 ` [PATCH 01/33] drm/i915: Convert intel_hdmi to enum port ville.syrjala
@ 2013-01-24 17:49 ` Paulo Zanoni
0 siblings, 0 replies; 67+ messages in thread
From: Paulo Zanoni @ 2013-01-24 17:49 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
Hi
2013/1/24 <ville.syrjala@linux.intel.com>:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use intel_dig_port->port rather than intel_hdmi->sdvox_erg.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Possible optional suggestions:
- Create macros that receive port as argument (check DDI_BUF_CTL(port)
as example): IBX_VIDEO_DIP_PORT(port), G4X_VIDEO_DIP_PORT(port),
HDMI_HOTPLUG_LIVE_STATUS(port). Since the macros would only be used
once, I'm not really sure if this change is worth making, it's just a
suggestion.
- Rename some "port" variables to "dip_port"
The patch is still an improvement, so with or without the suggestions:
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/intel_hdmi.c | 27 +++++++++++++++------------
> 1 file changed, 15 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index d53b731..5b4efd6 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -372,7 +372,8 @@ static void g4x_set_infoframes(struct drm_encoder *encoder,
> struct drm_display_mode *adjusted_mode)
> {
> struct drm_i915_private *dev_priv = encoder->dev->dev_private;
> - struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
> + struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
> + struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
> u32 reg = VIDEO_DIP_CTL;
> u32 val = I915_READ(reg);
> u32 port;
> @@ -399,11 +400,11 @@ static void g4x_set_infoframes(struct drm_encoder *encoder,
> return;
> }
>
> - switch (intel_hdmi->sdvox_reg) {
> - case SDVOB:
> + switch (intel_dig_port->port) {
> + case PORT_B:
> port = VIDEO_DIP_PORT_B;
> break;
> - case SDVOC:
> + case PORT_C:
> port = VIDEO_DIP_PORT_C;
> break;
> default:
> @@ -436,7 +437,8 @@ static void ibx_set_infoframes(struct drm_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = encoder->dev->dev_private;
> struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
> - struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
> + struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
> + struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
> u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
> u32 val = I915_READ(reg);
> u32 port;
> @@ -455,14 +457,14 @@ static void ibx_set_infoframes(struct drm_encoder *encoder,
> return;
> }
>
> - switch (intel_hdmi->sdvox_reg) {
> - case HDMIB:
> + switch (intel_dig_port->port) {
> + case PORT_B:
> port = VIDEO_DIP_PORT_B;
> break;
> - case HDMIC:
> + case PORT_C:
> port = VIDEO_DIP_PORT_C;
> break;
> - case HDMID:
> + case PORT_D:
> port = VIDEO_DIP_PORT_D;
> break;
> default:
> @@ -795,13 +797,14 @@ static bool g4x_hdmi_connected(struct intel_hdmi *intel_hdmi)
> {
> struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
> struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_digital_port *intel_dig_port = hdmi_to_dig_port(intel_hdmi);
> uint32_t bit;
>
> - switch (intel_hdmi->sdvox_reg) {
> - case SDVOB:
> + switch (intel_dig_port->port) {
> + case PORT_B:
> bit = HDMIB_HOTPLUG_LIVE_STATUS;
> break;
> - case SDVOC:
> + case PORT_C:
> bit = HDMIC_HOTPLUG_LIVE_STATUS;
> break;
> default:
> --
> 1.7.12.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Paulo Zanoni
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH 02/33] drm/i915: Convert intel_dp to enum port
2013-01-24 13:29 ` [PATCH 02/33] drm/i915: Convert intel_dp " ville.syrjala
@ 2013-01-24 17:54 ` Paulo Zanoni
2013-01-25 12:28 ` Ville Syrjälä
0 siblings, 1 reply; 67+ messages in thread
From: Paulo Zanoni @ 2013-01-24 17:54 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
Hi
2013/1/24 <ville.syrjala@linux.intel.com>:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use intel_dig_port->port rather than intel_dp->output_reg.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 9 +++++----
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index f05364a..d274f8e 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2293,16 +2293,17 @@ g4x_dp_detect(struct intel_dp *intel_dp)
> {
> struct drm_device *dev = intel_dp_to_dev(intel_dp);
> struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
Minor optional detail:
With "struct drm_device *dev = intel_dig_port->base.base.dev" you
would save a call to intel_dp_to_dev (which calls dp_to_dig_port).
With or without that:
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> uint32_t bit;
>
> - switch (intel_dp->output_reg) {
> - case DP_B:
> + switch (intel_dig_port->port) {
> + case PORT_B:
> bit = DPB_HOTPLUG_LIVE_STATUS;
> break;
> - case DP_C:
> + case PORT_C:
> bit = DPC_HOTPLUG_LIVE_STATUS;
> break;
> - case DP_D:
> + case PORT_D:
> bit = DPD_HOTPLUG_LIVE_STATUS;
> break;
> default:
> --
> 1.7.12.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Paulo Zanoni
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH 08/33] drm/i915: SWF screatch registers need an offset on VLV
2013-01-24 13:29 ` [PATCH 08/33] drm/i915: SWF screatch " ville.syrjala
@ 2013-01-24 21:37 ` Daniel Vetter
2013-01-25 12:26 ` Ville Syrjälä
0 siblings, 1 reply; 67+ messages in thread
From: Daniel Vetter @ 2013-01-24 21:37 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Thu, Jan 24, 2013 at 03:29:33PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
It's true that we safe/restore these suckers across suspend/resume, but I
have no idea why or whether we need to. Since there's no way we'll ever
support ums on vlv I think we should just try to guard the safe/resume
code with DRIVER_MODESET checks and drop this chunk here.
Or too risky?
-Daniel
> ---
> drivers/gpu/drm/i915/i915_reg.h | 26 +++++++++++++-------------
> 1 file changed, 13 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 80f9b6a..87eed0c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3046,19 +3046,19 @@
> (I915_WRITE((reg), (gfx_addr) | I915_LO_DISPBASE(I915_READ(reg))))
>
> /* VBIOS flags */
> -#define SWF00 0x71410
> -#define SWF01 0x71414
> -#define SWF02 0x71418
> -#define SWF03 0x7141c
> -#define SWF04 0x71420
> -#define SWF05 0x71424
> -#define SWF06 0x71428
> -#define SWF10 0x70410
> -#define SWF11 0x70414
> -#define SWF14 0x71420
> -#define SWF30 0x72414
> -#define SWF31 0x72418
> -#define SWF32 0x7241c
> +#define SWF00 (dev_priv->info->display_mmio_offset + 0x71410)
> +#define SWF01 (dev_priv->info->display_mmio_offset + 0x71414)
> +#define SWF02 (dev_priv->info->display_mmio_offset + 0x71418)
> +#define SWF03 (dev_priv->info->display_mmio_offset + 0x7141c)
> +#define SWF04 (dev_priv->info->display_mmio_offset + 0x71420)
> +#define SWF05 (dev_priv->info->display_mmio_offset + 0x71424)
> +#define SWF06 (dev_priv->info->display_mmio_offset + 0x71428)
> +#define SWF10 (dev_priv->info->display_mmio_offset + 0x70410)
> +#define SWF11 (dev_priv->info->display_mmio_offset + 0x70414)
> +#define SWF14 (dev_priv->info->display_mmio_offset + 0x71420)
> +#define SWF30 (dev_priv->info->display_mmio_offset + 0x72414)
> +#define SWF31 (dev_priv->info->display_mmio_offset + 0x72418)
> +#define SWF32 (dev_priv->info->display_mmio_offset + 0x7241c)
>
> /* Pipe B */
> #define _PIPEBDSL 0x71000
> --
> 1.7.12.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH 09/33] drm/i915: VGACNTRL needs an offset on VLV
2013-01-24 13:29 ` [PATCH 09/33] drm/i915: VGACNTRL needs " ville.syrjala
@ 2013-01-24 21:39 ` Daniel Vetter
2013-01-25 12:21 ` Ville Syrjälä
0 siblings, 1 reply; 67+ messages in thread
From: Daniel Vetter @ 2013-01-24 21:39 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Thu, Jan 24, 2013 at 03:29:34PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
We already have a switch since VGACNTRL moved around on pch-split
platforms, too. To avoid confusion with different ways to select a given
reg I think a static inline and explicit VLV_VGACNTRL is better. Static
inline since with i915_redisable_vga and i915_disable_vga we already have
two callers.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH 15/33] drm/i915: DSPARB register needs an offset on VLV
2013-01-24 13:29 ` [PATCH 15/33] drm/i915: DSPARB register needs " ville.syrjala
@ 2013-01-24 22:01 ` Daniel Vetter
2013-01-25 12:05 ` Ville Syrjälä
0 siblings, 1 reply; 67+ messages in thread
From: Daniel Vetter @ 2013-01-24 22:01 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Thu, Jan 24, 2013 at 03:29:40PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
With Paulo's patch to no longer safe/resume DSPARB on gen4+ gone, there's
no user of this left for vlv. And I wouldn't be surprised at all if the
register has a completely different function now, so maybe if we ever need
it we need a VLV_DSPARB or something like that.
-Daniel
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c3eaa69..3ac695d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2744,7 +2744,7 @@
> #define PLANEA_INVALID_GTT_STATUS (1<<0)
> #define DPINVGTT_STATUS_MASK 0xff
>
> -#define DSPARB 0x70030
> +#define DSPARB (dev_priv->info->display_mmio_offset + 0x70030)
> #define DSPARB_CSTART_MASK (0x7f << 7)
> #define DSPARB_CSTART_SHIFT 7
> #define DSPARB_BSTART_MASK (0x7f)
> --
> 1.7.12.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH 17/33] drm/i915: Pass VLV_DISPLAY_BASE + reg to intel_init_{sdvo, hdmi, dp} on VLV
2013-01-24 13:29 ` [PATCH 17/33] drm/i915: Pass VLV_DISPLAY_BASE + reg to intel_init_{sdvo, hdmi, dp} on VLV ville.syrjala
@ 2013-01-24 22:05 ` Daniel Vetter
2013-01-25 12:03 ` Ville Syrjälä
0 siblings, 1 reply; 67+ messages in thread
From: Daniel Vetter @ 2013-01-24 22:05 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Thu, Jan 24, 2013 at 03:29:42PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> When passing the DP/HDMI/SDVO registers to the encoder init functions,
> include the VLV specific offset in the value.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 26df9e3..60b5112 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -8230,20 +8230,20 @@ static void intel_setup_outputs(struct drm_device *dev)
> int found;
>
> /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
> - if (I915_READ(DP_C) & DP_DETECTED)
> - intel_dp_init(dev, DP_C, PORT_C);
> + if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
> + intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
>
> - if (I915_READ(SDVOB) & PORT_DETECTED) {
> + if (I915_READ(VLV_DISPLAY_BASE + SDVOB) & PORT_DETECTED) {
> /* SDVOB multiplex with HDMIB */
> - found = intel_sdvo_init(dev, SDVOB, true);
> + found = intel_sdvo_init(dev, VLV_DISPLAY_BASE + SDVOB, true);
I think we should kill the intel_sdvo_init copy&pasta here beforehand. Or
notice that we have a big problem and need to fixup sdvo support ...
-Daniel
> if (!found)
> - intel_hdmi_init(dev, SDVOB, PORT_B);
> - if (!found && (I915_READ(DP_B) & DP_DETECTED))
> - intel_dp_init(dev, DP_B, PORT_B);
> + intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOB, PORT_B);
> + if (!found && (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED))
> + intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
> }
>
> - if (I915_READ(SDVOC) & PORT_DETECTED)
> - intel_hdmi_init(dev, SDVOC, PORT_C);
> + if (I915_READ(VLV_DISPLAY_BASE + SDVOC) & PORT_DETECTED)
> + intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOC, PORT_C);
>
> } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
> bool found = false;
> --
> 1.7.12.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH 20/33] drm/i915: VLV_ADPA must be used in VLV code
2013-01-24 13:29 ` [PATCH 20/33] drm/i915: VLV_ADPA must be used in VLV code ville.syrjala
@ 2013-01-24 22:12 ` Daniel Vetter
2013-01-25 11:59 ` Ville Syrjälä
0 siblings, 1 reply; 67+ messages in thread
From: Daniel Vetter @ 2013-01-24 22:12 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Thu, Jan 24, 2013 at 03:29:45PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> ADPA doesn't include the required offset, so don't use it in VLV
> specific code. VLV_ADPA must be used instead.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_crt.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index 71a5eba..9fe3d67 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -305,12 +305,12 @@ static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
> bool ret;
> u32 save_adpa;
>
> - save_adpa = adpa = I915_READ(ADPA);
> + save_adpa = adpa = I915_READ(VLV_ADPA);
> DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
>
> adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
>
> - I915_WRITE(ADPA, adpa);
> + I915_WRITE(VLV_ADPA, adpa);
>
> if (wait_for((I915_READ(ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
> 1000)) {
A few are missing here ... I wonder whether we shouldn't just use
crt->adpa_reg instead? intel_ironlake_crt_detect_hotplug right above
suffers from the same by using PCH_ADPA.
-Daniel
> @@ -319,7 +319,7 @@ static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
> }
>
> /* Check the status to see if both blue and green are on now */
> - adpa = I915_READ(ADPA);
> + adpa = I915_READ(VLV_ADPA);
> if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
> ret = true;
> else
> --
> 1.7.12.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH 22/33] drm/i915: Pipe palette registers need an offset on VLV
2013-01-24 13:29 ` [PATCH 22/33] drm/i915: Pipe palette " ville.syrjala
@ 2013-01-24 22:22 ` Daniel Vetter
2013-01-25 10:57 ` Ville Syrjälä
0 siblings, 1 reply; 67+ messages in thread
From: Daniel Vetter @ 2013-01-24 22:22 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Thu, Jan 24, 2013 at 03:29:47PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
I've noticed that the PALETTE moved around a bit for pch-split platforms
already, but otoh the palette support is quite enhanced there already, and
we don't bother with it. Which renders 10bpc a bit pointless. So I'll gulp
this one here.
-Daniel
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 15ecded..7c71622 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1169,8 +1169,8 @@
> * Palette regs
> */
>
> -#define _PALETTE_A 0x0a000
> -#define _PALETTE_B 0x0a800
> +#define _PALETTE_A (dev_priv->info->display_mmio_offset + 0xa000)
> +#define _PALETTE_B (dev_priv->info->display_mmio_offset + 0xa800)
> #define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B)
>
> /* MCH MMIO space */
> --
> 1.7.12.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH 24/33] drm/i915: VLV doesn't seem to have VGA0/VGA1/VGA_PD registers
2013-01-24 13:29 ` [PATCH 24/33] drm/i915: VLV doesn't seem to have VGA0/VGA1/VGA_PD registers ville.syrjala
@ 2013-01-24 22:26 ` Daniel Vetter
2013-01-25 10:51 ` Ville Syrjälä
0 siblings, 1 reply; 67+ messages in thread
From: Daniel Vetter @ 2013-01-24 22:26 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Thu, Jan 24, 2013 at 03:29:49PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Don't touch VGA0/VGA1/VGA_PD in suspend/resume paths.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
By sheer coincidence I'm working on a few patches to no longer
safe/restore the legacy vga regs for DRIVER_MODESET. Which means this here
isn't required any more. For the current wip:
http://cgit.freedesktop.org/~danvet/drm/log/?h=modeset_s-r
-Daniel
> ---
> drivers/gpu/drm/i915/i915_suspend.c | 20 ++++++++++++--------
> 1 file changed, 12 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
> index 63d4d30..05d82dc 100644
> --- a/drivers/gpu/drm/i915/i915_suspend.c
> +++ b/drivers/gpu/drm/i915/i915_suspend.c
> @@ -691,9 +691,11 @@ static void i915_save_display(struct drm_device *dev)
> }
>
> /* VGA state */
> - dev_priv->regfile.saveVGA0 = I915_READ(VGA0);
> - dev_priv->regfile.saveVGA1 = I915_READ(VGA1);
> - dev_priv->regfile.saveVGA_PD = I915_READ(VGA_PD);
> + if (!IS_VALLEYVIEW(dev)) {
> + dev_priv->regfile.saveVGA0 = I915_READ(VGA0);
> + dev_priv->regfile.saveVGA1 = I915_READ(VGA1);
> + dev_priv->regfile.saveVGA_PD = I915_READ(VGA_PD);
> + }
> if (HAS_PCH_SPLIT(dev))
> dev_priv->regfile.saveVGACNTRL = I915_READ(CPU_VGACNTRL);
> else
> @@ -793,11 +795,13 @@ static void i915_restore_display(struct drm_device *dev)
> else
> I915_WRITE(VGACNTRL, dev_priv->regfile.saveVGACNTRL);
>
> - I915_WRITE(VGA0, dev_priv->regfile.saveVGA0);
> - I915_WRITE(VGA1, dev_priv->regfile.saveVGA1);
> - I915_WRITE(VGA_PD, dev_priv->regfile.saveVGA_PD);
> - POSTING_READ(VGA_PD);
> - udelay(150);
> + if (!IS_VALLEYVIEW(dev)) {
> + I915_WRITE(VGA0, dev_priv->regfile.saveVGA0);
> + I915_WRITE(VGA1, dev_priv->regfile.saveVGA1);
> + I915_WRITE(VGA_PD, dev_priv->regfile.saveVGA_PD);
> + POSTING_READ(VGA_PD);
> + udelay(150);
> + }
>
> i915_restore_vga(dev);
> }
> --
> 1.7.12.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH 25/33] drm/i915: PLL and clock gating registers need an offset on VLV
2013-01-24 13:29 ` [PATCH 25/33] drm/i915: PLL and clock gating registers need an offset on VLV ville.syrjala
@ 2013-01-24 22:41 ` Daniel Vetter
2013-01-25 10:51 ` Ville Syrjälä
0 siblings, 1 reply; 67+ messages in thread
From: Daniel Vetter @ 2013-01-24 22:41 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Thu, Jan 24, 2013 at 03:29:50PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1c1e7f8..c3d4ddc 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -922,8 +922,8 @@
> #define VGA1_PD_P1_DIV_2 (1 << 13)
> #define VGA1_PD_P1_SHIFT 8
> #define VGA1_PD_P1_MASK (0x1f << 8)
> -#define _DPLL_A 0x06014
> -#define _DPLL_B 0x06018
> +#define _DPLL_A (dev_priv->info->display_mmio_offset + 0x6014)
> +#define _DPLL_B (dev_priv->info->display_mmio_offset + 0x6018)
> #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
> #define DPLL_VCO_ENABLE (1 << 31)
> #define DPLL_DVO_HIGH_SPEED (1 << 30)
> @@ -982,7 +982,7 @@
> #define SDVO_MULTIPLIER_MASK 0x000000ff
> #define SDVO_MULTIPLIER_SHIFT_HIRES 4
> #define SDVO_MULTIPLIER_SHIFT_VGA 0
> -#define _DPLL_A_MD 0x0601c /* 965+ only */
> +#define _DPLL_A_MD (dev_priv->info->display_mmio_offset + 0x601c) /* 965+ only */
> /*
> * UDI pixel divider, controlling how many pixels are stuffed into a packet.
> *
> @@ -1019,7 +1019,7 @@
> */
> #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
> #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
> -#define _DPLL_B_MD 0x06020 /* 965+ only */
> +#define _DPLL_B_MD (dev_priv->info->display_mmio_offset + 0x6020) /* 965+ only */
> #define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD)
>
> #define _FPA0 0x06040
> @@ -1047,12 +1047,12 @@
> #define DPLLA_TEST_N_BYPASS (1 << 3)
> #define DPLLA_TEST_M_BYPASS (1 << 2)
> #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
> -#define D_STATE 0x6104
> +#define D_STATE (dev_priv->info->display_mmio_offset + 0x6104)
I only see this one here used in gen2/3 code ...
> #define DSTATE_GFX_RESET_I830 (1<<6)
> #define DSTATE_PLL_D3_OFF (1<<3)
> #define DSTATE_GFX_CLOCK_GATING (1<<1)
> #define DSTATE_DOT_CLOCK_GATING (1<<0)
> -#define DSPCLK_GATE_D 0x6200
> +#define DSPCLK_GATE_D (dev_priv->info->display_mmio_offset + 0x6200)
This one here seems to be only used up to gen4 ...
> # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
> # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
> # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
> @@ -1159,7 +1159,7 @@
> #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
> #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
> #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
> -#define RAMCLK_GATE_D 0x6210 /* CRL only */
> +#define RAMCLK_GATE_D (dev_priv->info->display_mmio_offset + 0x6210) /* CRL only */
And same here. Do we need those in vlv code, or can we just drop them for
now?
-Daniel
> #define DEUC 0x6214 /* CRL only */
>
> #define FW_BLC_SELF_VLV (VLV_DISPLAY_BASE + 0x6500)
> --
> 1.7.12.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH 29/33] drm/i915: VGA registers need an offset on VLV
2013-01-24 13:29 ` [PATCH 29/33] drm/i915: VGA registers need an offset on VLV ville.syrjala
@ 2013-01-24 22:44 ` Daniel Vetter
2013-01-25 10:27 ` Ville Syrjälä
0 siblings, 1 reply; 67+ messages in thread
From: Daniel Vetter @ 2013-01-24 22:44 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Thu, Jan 24, 2013 at 03:29:54PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Admittedly I haven't checked them closely, but with my proposed patch in
he modeset_s-r branch, do we still need to adjust these? I kinda don't
want to keep the legacy vga plane registers around ...
-Daniel
> ---
> drivers/gpu/drm/i915/i915_reg.h | 38 +++++++++++++++++++-------------------
> 1 file changed, 19 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c149426..75b46c8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -133,25 +133,25 @@
>
> /* VGA stuff */
>
> -#define VGA_ST01_MDA 0x3ba
> -#define VGA_ST01_CGA 0x3da
> +#define VGA_ST01_MDA (dev_priv->info->display_mmio_offset + 0x3ba)
> +#define VGA_ST01_CGA (dev_priv->info->display_mmio_offset + 0x3da)
>
> -#define VGA_MSR_WRITE 0x3c2
> -#define VGA_MSR_READ 0x3cc
> +#define VGA_MSR_WRITE (dev_priv->info->display_mmio_offset + 0x3c2)
> +#define VGA_MSR_READ (dev_priv->info->display_mmio_offset + 0x3cc)
> #define VGA_MSR_MEM_EN (1<<1)
> #define VGA_MSR_CGA_MODE (1<<0)
>
> -#define VGA_SR_INDEX 0x3c4
> +#define VGA_SR_INDEX (dev_priv->info->display_mmio_offset + 0x3c4)
> #define SR01 1
> -#define VGA_SR_DATA 0x3c5
> +#define VGA_SR_DATA (dev_priv->info->display_mmio_offset + 0x3c5)
>
> -#define VGA_AR_INDEX 0x3c0
> +#define VGA_AR_INDEX (dev_priv->info->display_mmio_offset + 0x3c0)
> #define VGA_AR_VID_EN (1<<5)
> -#define VGA_AR_DATA_WRITE 0x3c0
> -#define VGA_AR_DATA_READ 0x3c1
> +#define VGA_AR_DATA_WRITE (dev_priv->info->display_mmio_offset + 0x3c0)
> +#define VGA_AR_DATA_READ (dev_priv->info->display_mmio_offset + 0x3c1)
>
> -#define VGA_GR_INDEX 0x3ce
> -#define VGA_GR_DATA 0x3cf
> +#define VGA_GR_INDEX (dev_priv->info->display_mmio_offset + 0x3ce)
> +#define VGA_GR_DATA (dev_priv->info->display_mmio_offset + 0x3cf)
> /* GR05 */
> #define VGA_GR_MEM_READ_MODE_SHIFT 3
> #define VGA_GR_MEM_READ_MODE_PLANE 1
> @@ -163,15 +163,15 @@
> #define VGA_GR_MEM_B0000_B7FFF 2
> #define VGA_GR_MEM_B0000_BFFFF 3
>
> -#define VGA_DACMASK 0x3c6
> -#define VGA_DACRX 0x3c7
> -#define VGA_DACWX 0x3c8
> -#define VGA_DACDATA 0x3c9
> +#define VGA_DACMASK (dev_priv->info->display_mmio_offset + 0x3c6)
> +#define VGA_DACRX (dev_priv->info->display_mmio_offset + 0x3c7)
> +#define VGA_DACWX (dev_priv->info->display_mmio_offset + 0x3c8)
> +#define VGA_DACDATA (dev_priv->info->display_mmio_offset + 0x3c9)
>
> -#define VGA_CR_INDEX_MDA 0x3b4
> -#define VGA_CR_DATA_MDA 0x3b5
> -#define VGA_CR_INDEX_CGA 0x3d4
> -#define VGA_CR_DATA_CGA 0x3d5
> +#define VGA_CR_INDEX_MDA (dev_priv->info->display_mmio_offset + 0x3b4)
> +#define VGA_CR_DATA_MDA (dev_priv->info->display_mmio_offset + 0x3b5)
> +#define VGA_CR_INDEX_CGA (dev_priv->info->display_mmio_offset + 0x3d4)
> +#define VGA_CR_DATA_CGA (dev_priv->info->display_mmio_offset + 0x3d5)
>
> /*
> * Memory interface instructions used by the kernel
> --
> 1.7.12.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH 31/33] drm/i915: Set display_mmio_offset for VLV
2013-01-24 13:29 ` [PATCH 31/33] drm/i915: Set display_mmio_offset for VLV ville.syrjala
@ 2013-01-24 22:59 ` Daniel Vetter
0 siblings, 0 replies; 67+ messages in thread
From: Daniel Vetter @ 2013-01-24 22:59 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Thu, Jan 24, 2013 at 03:29:56PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> This will cause display registers to include the correct
> offset on VLV.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Ok, applied most patches up to this one, dropped bikesheds and questions
on the other ones. I'll merge the final piece once everything's in place.
Thanks a lot for crawling through this sludge so that we can abolish
IS_DISPLAYREG!
Cheers, Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH 29/33] drm/i915: VGA registers need an offset on VLV
2013-01-24 22:44 ` Daniel Vetter
@ 2013-01-25 10:27 ` Ville Syrjälä
2013-01-25 16:18 ` Daniel Vetter
0 siblings, 1 reply; 67+ messages in thread
From: Ville Syrjälä @ 2013-01-25 10:27 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Thu, Jan 24, 2013 at 11:44:09PM +0100, Daniel Vetter wrote:
> On Thu, Jan 24, 2013 at 03:29:54PM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Admittedly I haven't checked them closely, but with my proposed patch in
> he modeset_s-r branch, do we still need to adjust these? I kinda don't
> want to keep the legacy vga plane registers around ...
I found two exceptions, well, one really.
i915_disable_vga() pokes at one sequencer register.
intel_crt_load_detect() polls the sense bit in ST00, but I don't think
we should ever go there w/ VLV due to is_hotplug=1.
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH 25/33] drm/i915: PLL and clock gating registers need an offset on VLV
2013-01-24 22:41 ` Daniel Vetter
@ 2013-01-25 10:51 ` Ville Syrjälä
2013-01-25 16:06 ` Daniel Vetter
0 siblings, 1 reply; 67+ messages in thread
From: Ville Syrjälä @ 2013-01-25 10:51 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Thu, Jan 24, 2013 at 11:41:53PM +0100, Daniel Vetter wrote:
> On Thu, Jan 24, 2013 at 03:29:50PM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 14 +++++++-------
> > 1 file changed, 7 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 1c1e7f8..c3d4ddc 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -922,8 +922,8 @@
> > #define VGA1_PD_P1_DIV_2 (1 << 13)
> > #define VGA1_PD_P1_SHIFT 8
> > #define VGA1_PD_P1_MASK (0x1f << 8)
> > -#define _DPLL_A 0x06014
> > -#define _DPLL_B 0x06018
> > +#define _DPLL_A (dev_priv->info->display_mmio_offset + 0x6014)
> > +#define _DPLL_B (dev_priv->info->display_mmio_offset + 0x6018)
> > #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
> > #define DPLL_VCO_ENABLE (1 << 31)
> > #define DPLL_DVO_HIGH_SPEED (1 << 30)
> > @@ -982,7 +982,7 @@
> > #define SDVO_MULTIPLIER_MASK 0x000000ff
> > #define SDVO_MULTIPLIER_SHIFT_HIRES 4
> > #define SDVO_MULTIPLIER_SHIFT_VGA 0
> > -#define _DPLL_A_MD 0x0601c /* 965+ only */
> > +#define _DPLL_A_MD (dev_priv->info->display_mmio_offset + 0x601c) /* 965+ only */
> > /*
> > * UDI pixel divider, controlling how many pixels are stuffed into a packet.
> > *
> > @@ -1019,7 +1019,7 @@
> > */
> > #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
> > #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
> > -#define _DPLL_B_MD 0x06020 /* 965+ only */
> > +#define _DPLL_B_MD (dev_priv->info->display_mmio_offset + 0x6020) /* 965+ only */
> > #define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD)
> >
> > #define _FPA0 0x06040
> > @@ -1047,12 +1047,12 @@
> > #define DPLLA_TEST_N_BYPASS (1 << 3)
> > #define DPLLA_TEST_M_BYPASS (1 << 2)
> > #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
> > -#define D_STATE 0x6104
> > +#define D_STATE (dev_priv->info->display_mmio_offset + 0x6104)
>
> I only see this one here used in gen2/3 code ...
>
> > #define DSTATE_GFX_RESET_I830 (1<<6)
> > #define DSTATE_PLL_D3_OFF (1<<3)
> > #define DSTATE_GFX_CLOCK_GATING (1<<1)
> > #define DSTATE_DOT_CLOCK_GATING (1<<0)
> > -#define DSPCLK_GATE_D 0x6200
> > +#define DSPCLK_GATE_D (dev_priv->info->display_mmio_offset + 0x6200)
>
> This one here seems to be only used up to gen4 ...
DSPCLK_GATE_D is used in intel_i2c_quirk_set(). OTOH gma500 has the
same code commented out, so it may be that we can skip it too. Anyone
have more details on this quirk?
gma500 also seems to use DSPCLK_GATE_D to disable clock gating for
some DP stuff on CDV. Considering the lineage we need to find out
if that's something that affects VLV as well.
> > # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
> > # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
> > # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
> > @@ -1159,7 +1159,7 @@
> > #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
> > #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
> > #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
> > -#define RAMCLK_GATE_D 0x6210 /* CRL only */
> > +#define RAMCLK_GATE_D (dev_priv->info->display_mmio_offset + 0x6210) /* CRL only */
>
> And same here. Do we need those in vlv code, or can we just drop them for
> now?
I think D_STATE and RAMCLK_GATE_D can be dropped. We can convert them
if and when we actaully have to touch them.
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH 24/33] drm/i915: VLV doesn't seem to have VGA0/VGA1/VGA_PD registers
2013-01-24 22:26 ` Daniel Vetter
@ 2013-01-25 10:51 ` Ville Syrjälä
0 siblings, 0 replies; 67+ messages in thread
From: Ville Syrjälä @ 2013-01-25 10:51 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Thu, Jan 24, 2013 at 11:26:10PM +0100, Daniel Vetter wrote:
> On Thu, Jan 24, 2013 at 03:29:49PM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Don't touch VGA0/VGA1/VGA_PD in suspend/resume paths.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> By sheer coincidence I'm working on a few patches to no longer
> safe/restore the legacy vga regs for DRIVER_MODESET. Which means this here
> isn't required any more. For the current wip:
>
> http://cgit.freedesktop.org/~danvet/drm/log/?h=modeset_s-r
OK
> > ---
> > drivers/gpu/drm/i915/i915_suspend.c | 20 ++++++++++++--------
> > 1 file changed, 12 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
> > index 63d4d30..05d82dc 100644
> > --- a/drivers/gpu/drm/i915/i915_suspend.c
> > +++ b/drivers/gpu/drm/i915/i915_suspend.c
> > @@ -691,9 +691,11 @@ static void i915_save_display(struct drm_device *dev)
> > }
> >
> > /* VGA state */
> > - dev_priv->regfile.saveVGA0 = I915_READ(VGA0);
> > - dev_priv->regfile.saveVGA1 = I915_READ(VGA1);
> > - dev_priv->regfile.saveVGA_PD = I915_READ(VGA_PD);
> > + if (!IS_VALLEYVIEW(dev)) {
> > + dev_priv->regfile.saveVGA0 = I915_READ(VGA0);
> > + dev_priv->regfile.saveVGA1 = I915_READ(VGA1);
> > + dev_priv->regfile.saveVGA_PD = I915_READ(VGA_PD);
> > + }
> > if (HAS_PCH_SPLIT(dev))
> > dev_priv->regfile.saveVGACNTRL = I915_READ(CPU_VGACNTRL);
> > else
> > @@ -793,11 +795,13 @@ static void i915_restore_display(struct drm_device *dev)
> > else
> > I915_WRITE(VGACNTRL, dev_priv->regfile.saveVGACNTRL);
> >
> > - I915_WRITE(VGA0, dev_priv->regfile.saveVGA0);
> > - I915_WRITE(VGA1, dev_priv->regfile.saveVGA1);
> > - I915_WRITE(VGA_PD, dev_priv->regfile.saveVGA_PD);
> > - POSTING_READ(VGA_PD);
> > - udelay(150);
> > + if (!IS_VALLEYVIEW(dev)) {
> > + I915_WRITE(VGA0, dev_priv->regfile.saveVGA0);
> > + I915_WRITE(VGA1, dev_priv->regfile.saveVGA1);
> > + I915_WRITE(VGA_PD, dev_priv->regfile.saveVGA_PD);
> > + POSTING_READ(VGA_PD);
> > + udelay(150);
> > + }
> >
> > i915_restore_vga(dev);
> > }
> > --
> > 1.7.12.4
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH 22/33] drm/i915: Pipe palette registers need an offset on VLV
2013-01-24 22:22 ` Daniel Vetter
@ 2013-01-25 10:57 ` Ville Syrjälä
0 siblings, 0 replies; 67+ messages in thread
From: Ville Syrjälä @ 2013-01-25 10:57 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Thu, Jan 24, 2013 at 11:22:15PM +0100, Daniel Vetter wrote:
> On Thu, Jan 24, 2013 at 03:29:47PM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> I've noticed that the PALETTE moved around a bit for pch-split platforms
> already, but otoh the palette support is quite enhanced there already, and
> we don't bother with it. Which renders 10bpc a bit pointless. So I'll gulp
> this one here.
Yeah we really need to revamp the palette/gamma code at some
point.
I think what we used to have on older hardware was 8bit LUT or
10bit interpolated ramp. And on more recent hardware we have
8bit LUT, 10bit LUT, or 12bit interpolated ramp. And currently
we only use the 8bit LUT.
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 15ecded..7c71622 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1169,8 +1169,8 @@
> > * Palette regs
> > */
> >
> > -#define _PALETTE_A 0x0a000
> > -#define _PALETTE_B 0x0a800
> > +#define _PALETTE_A (dev_priv->info->display_mmio_offset + 0xa000)
> > +#define _PALETTE_B (dev_priv->info->display_mmio_offset + 0xa800)
> > #define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B)
> >
> > /* MCH MMIO space */
> > --
> > 1.7.12.4
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH 20/33] drm/i915: VLV_ADPA must be used in VLV code
2013-01-24 22:12 ` Daniel Vetter
@ 2013-01-25 11:59 ` Ville Syrjälä
0 siblings, 0 replies; 67+ messages in thread
From: Ville Syrjälä @ 2013-01-25 11:59 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Thu, Jan 24, 2013 at 11:12:10PM +0100, Daniel Vetter wrote:
> On Thu, Jan 24, 2013 at 03:29:45PM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > ADPA doesn't include the required offset, so don't use it in VLV
> > specific code. VLV_ADPA must be used instead.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_crt.c | 6 +++---
> > 1 file changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> > index 71a5eba..9fe3d67 100644
> > --- a/drivers/gpu/drm/i915/intel_crt.c
> > +++ b/drivers/gpu/drm/i915/intel_crt.c
> > @@ -305,12 +305,12 @@ static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
> > bool ret;
> > u32 save_adpa;
> >
> > - save_adpa = adpa = I915_READ(ADPA);
> > + save_adpa = adpa = I915_READ(VLV_ADPA);
> > DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
> >
> > adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
> >
> > - I915_WRITE(ADPA, adpa);
> > + I915_WRITE(VLV_ADPA, adpa);
> >
> > if (wait_for((I915_READ(ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
> > 1000)) {
>
> A few are missing here ... I wonder whether we shouldn't just use
> crt->adpa_reg instead? intel_ironlake_crt_detect_hotplug right above
> suffers from the same by using PCH_ADPA.
Dang. I'll make a patch to use apda_reg always.
> -Daniel
>
> > @@ -319,7 +319,7 @@ static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
> > }
> >
> > /* Check the status to see if both blue and green are on now */
> > - adpa = I915_READ(ADPA);
> > + adpa = I915_READ(VLV_ADPA);
> > if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
> > ret = true;
> > else
> > --
> > 1.7.12.4
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH 17/33] drm/i915: Pass VLV_DISPLAY_BASE + reg to intel_init_{sdvo, hdmi, dp} on VLV
2013-01-24 22:05 ` Daniel Vetter
@ 2013-01-25 12:03 ` Ville Syrjälä
2013-01-25 16:02 ` Daniel Vetter
0 siblings, 1 reply; 67+ messages in thread
From: Ville Syrjälä @ 2013-01-25 12:03 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Thu, Jan 24, 2013 at 11:05:21PM +0100, Daniel Vetter wrote:
> On Thu, Jan 24, 2013 at 03:29:42PM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > When passing the DP/HDMI/SDVO registers to the encoder init functions,
> > include the VLV specific offset in the value.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 18 +++++++++---------
> > 1 file changed, 9 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 26df9e3..60b5112 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -8230,20 +8230,20 @@ static void intel_setup_outputs(struct drm_device *dev)
> > int found;
> >
> > /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
> > - if (I915_READ(DP_C) & DP_DETECTED)
> > - intel_dp_init(dev, DP_C, PORT_C);
> > + if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
> > + intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
> >
> > - if (I915_READ(SDVOB) & PORT_DETECTED) {
> > + if (I915_READ(VLV_DISPLAY_BASE + SDVOB) & PORT_DETECTED) {
> > /* SDVOB multiplex with HDMIB */
> > - found = intel_sdvo_init(dev, SDVOB, true);
> > + found = intel_sdvo_init(dev, VLV_DISPLAY_BASE + SDVOB, true);
>
> I think we should kill the intel_sdvo_init copy&pasta here beforehand. Or
> notice that we have a big problem and need to fixup sdvo support ...
I think Jesse something like that lined up. Should we wait for that, or
do you want me to make a quick fix?
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH 15/33] drm/i915: DSPARB register needs an offset on VLV
2013-01-24 22:01 ` Daniel Vetter
@ 2013-01-25 12:05 ` Ville Syrjälä
0 siblings, 0 replies; 67+ messages in thread
From: Ville Syrjälä @ 2013-01-25 12:05 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Thu, Jan 24, 2013 at 11:01:42PM +0100, Daniel Vetter wrote:
> On Thu, Jan 24, 2013 at 03:29:40PM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> With Paulo's patch to no longer safe/resume DSPARB on gen4+ gone, there's
> no user of this left for vlv. And I wouldn't be surprised at all if the
> register has a completely different function now, so maybe if we ever need
> it we need a VLV_DSPARB or something like that.
It has the same function, but the bits naturally get shuffled around a
lot. We can revisit it when/if it's really needed.
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH 09/33] drm/i915: VGACNTRL needs an offset on VLV
2013-01-24 21:39 ` Daniel Vetter
@ 2013-01-25 12:21 ` Ville Syrjälä
2013-01-25 16:00 ` Daniel Vetter
0 siblings, 1 reply; 67+ messages in thread
From: Ville Syrjälä @ 2013-01-25 12:21 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Thu, Jan 24, 2013 at 10:39:52PM +0100, Daniel Vetter wrote:
> On Thu, Jan 24, 2013 at 03:29:34PM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We already have a switch since VGACNTRL moved around on pch-split
> platforms, too. To avoid confusion with different ways to select a given
> reg I think a static inline and explicit VLV_VGACNTRL is better. Static
> inline since with i915_redisable_vga and i915_disable_vga we already have
> two callers.
All right. The save/restore paths also touch VGACNTRL. I'll convert
those too, even if we don't use them for much longer w/ kms.
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH 08/33] drm/i915: SWF screatch registers need an offset on VLV
2013-01-24 21:37 ` Daniel Vetter
@ 2013-01-25 12:26 ` Ville Syrjälä
2013-01-25 16:21 ` Daniel Vetter
0 siblings, 1 reply; 67+ messages in thread
From: Ville Syrjälä @ 2013-01-25 12:26 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Thu, Jan 24, 2013 at 10:37:28PM +0100, Daniel Vetter wrote:
> On Thu, Jan 24, 2013 at 03:29:33PM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> It's true that we safe/restore these suckers across suspend/resume, but I
> have no idea why or whether we need to. Since there's no way we'll ever
> support ums on vlv I think we should just try to guard the safe/resume
> code with DRIVER_MODESET checks and drop this chunk here.
>
> Or too risky?
No idea. I suppose some silly BIOS might assume that some of these regs
retain their contents.
> -Daniel
>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 26 +++++++++++++-------------
> > 1 file changed, 13 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 80f9b6a..87eed0c 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3046,19 +3046,19 @@
> > (I915_WRITE((reg), (gfx_addr) | I915_LO_DISPBASE(I915_READ(reg))))
> >
> > /* VBIOS flags */
> > -#define SWF00 0x71410
> > -#define SWF01 0x71414
> > -#define SWF02 0x71418
> > -#define SWF03 0x7141c
> > -#define SWF04 0x71420
> > -#define SWF05 0x71424
> > -#define SWF06 0x71428
> > -#define SWF10 0x70410
> > -#define SWF11 0x70414
> > -#define SWF14 0x71420
> > -#define SWF30 0x72414
> > -#define SWF31 0x72418
> > -#define SWF32 0x7241c
> > +#define SWF00 (dev_priv->info->display_mmio_offset + 0x71410)
> > +#define SWF01 (dev_priv->info->display_mmio_offset + 0x71414)
> > +#define SWF02 (dev_priv->info->display_mmio_offset + 0x71418)
> > +#define SWF03 (dev_priv->info->display_mmio_offset + 0x7141c)
> > +#define SWF04 (dev_priv->info->display_mmio_offset + 0x71420)
> > +#define SWF05 (dev_priv->info->display_mmio_offset + 0x71424)
> > +#define SWF06 (dev_priv->info->display_mmio_offset + 0x71428)
> > +#define SWF10 (dev_priv->info->display_mmio_offset + 0x70410)
> > +#define SWF11 (dev_priv->info->display_mmio_offset + 0x70414)
> > +#define SWF14 (dev_priv->info->display_mmio_offset + 0x71420)
> > +#define SWF30 (dev_priv->info->display_mmio_offset + 0x72414)
> > +#define SWF31 (dev_priv->info->display_mmio_offset + 0x72418)
> > +#define SWF32 (dev_priv->info->display_mmio_offset + 0x7241c)
> >
> > /* Pipe B */
> > #define _PIPEBDSL 0x71000
> > --
> > 1.7.12.4
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH 02/33] drm/i915: Convert intel_dp to enum port
2013-01-24 17:54 ` Paulo Zanoni
@ 2013-01-25 12:28 ` Ville Syrjälä
0 siblings, 0 replies; 67+ messages in thread
From: Ville Syrjälä @ 2013-01-25 12:28 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
On Thu, Jan 24, 2013 at 03:54:19PM -0200, Paulo Zanoni wrote:
> Hi
>
> 2013/1/24 <ville.syrjala@linux.intel.com>:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Use intel_dig_port->port rather than intel_dp->output_reg.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_dp.c | 9 +++++----
> > 1 file changed, 5 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index f05364a..d274f8e 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -2293,16 +2293,17 @@ g4x_dp_detect(struct intel_dp *intel_dp)
> > {
> > struct drm_device *dev = intel_dp_to_dev(intel_dp);
> > struct drm_i915_private *dev_priv = dev->dev_private;
> > + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>
>
> Minor optional detail:
> With "struct drm_device *dev = intel_dig_port->base.base.dev" you
> would save a call to intel_dp_to_dev (which calls dp_to_dig_port).
Dang :)
> With or without that:
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cheers. Daniel slurped it already, so w/o it is.
>
> > uint32_t bit;
> >
> > - switch (intel_dp->output_reg) {
> > - case DP_B:
> > + switch (intel_dig_port->port) {
> > + case PORT_B:
> > bit = DPB_HOTPLUG_LIVE_STATUS;
> > break;
> > - case DP_C:
> > + case PORT_C:
> > bit = DPC_HOTPLUG_LIVE_STATUS;
> > break;
> > - case DP_D:
> > + case PORT_D:
> > bit = DPD_HOTPLUG_LIVE_STATUS;
> > break;
> > default:
> > --
> > 1.7.12.4
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
>
> --
> Paulo Zanoni
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH 09/33] drm/i915: VGACNTRL needs an offset on VLV
2013-01-25 12:21 ` Ville Syrjälä
@ 2013-01-25 16:00 ` Daniel Vetter
2013-01-25 16:22 ` Ville Syrjälä
0 siblings, 1 reply; 67+ messages in thread
From: Daniel Vetter @ 2013-01-25 16:00 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Fri, Jan 25, 2013 at 02:21:16PM +0200, Ville Syrjälä wrote:
> On Thu, Jan 24, 2013 at 10:39:52PM +0100, Daniel Vetter wrote:
> > On Thu, Jan 24, 2013 at 03:29:34PM +0200, ville.syrjala@linux.intel.com wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > We already have a switch since VGACNTRL moved around on pch-split
> > platforms, too. To avoid confusion with different ways to select a given
> > reg I think a static inline and explicit VLV_VGACNTRL is better. Static
> > inline since with i915_redisable_vga and i915_disable_vga we already have
> > two callers.
>
> All right. The save/restore paths also touch VGACNTRL. I'll convert
> those too, even if we don't use them for much longer w/ kms.
Actually I think it'd be easier to merge the few patches I'm working on
first. I'm testing them right now, will submit soon.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH 17/33] drm/i915: Pass VLV_DISPLAY_BASE + reg to intel_init_{sdvo, hdmi, dp} on VLV
2013-01-25 12:03 ` Ville Syrjälä
@ 2013-01-25 16:02 ` Daniel Vetter
0 siblings, 0 replies; 67+ messages in thread
From: Daniel Vetter @ 2013-01-25 16:02 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Fri, Jan 25, 2013 at 02:03:40PM +0200, Ville Syrjälä wrote:
> On Thu, Jan 24, 2013 at 11:05:21PM +0100, Daniel Vetter wrote:
> > On Thu, Jan 24, 2013 at 03:29:42PM +0200, ville.syrjala@linux.intel.com wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > When passing the DP/HDMI/SDVO registers to the encoder init functions,
> > > include the VLV specific offset in the value.
> > >
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > > drivers/gpu/drm/i915/intel_display.c | 18 +++++++++---------
> > > 1 file changed, 9 insertions(+), 9 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > > index 26df9e3..60b5112 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -8230,20 +8230,20 @@ static void intel_setup_outputs(struct drm_device *dev)
> > > int found;
> > >
> > > /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
> > > - if (I915_READ(DP_C) & DP_DETECTED)
> > > - intel_dp_init(dev, DP_C, PORT_C);
> > > + if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
> > > + intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
> > >
> > > - if (I915_READ(SDVOB) & PORT_DETECTED) {
> > > + if (I915_READ(VLV_DISPLAY_BASE + SDVOB) & PORT_DETECTED) {
> > > /* SDVOB multiplex with HDMIB */
> > > - found = intel_sdvo_init(dev, SDVOB, true);
> > > + found = intel_sdvo_init(dev, VLV_DISPLAY_BASE + SDVOB, true);
> >
> > I think we should kill the intel_sdvo_init copy&pasta here beforehand. Or
> > notice that we have a big problem and need to fixup sdvo support ...
>
> I think Jesse something like that lined up. Should we wait for that, or
> do you want me to make a quick fix?
I'd vote for a quick fix first to remove sdvo, preferrably acked by Jesse,
then your conversion patch here on top. But if Jesse is awol, we can do it
the other way round, too.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH 25/33] drm/i915: PLL and clock gating registers need an offset on VLV
2013-01-25 10:51 ` Ville Syrjälä
@ 2013-01-25 16:06 ` Daniel Vetter
2013-01-25 16:20 ` Ville Syrjälä
0 siblings, 1 reply; 67+ messages in thread
From: Daniel Vetter @ 2013-01-25 16:06 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Fri, Jan 25, 2013 at 12:51:15PM +0200, Ville Syrjälä wrote:
> On Thu, Jan 24, 2013 at 11:41:53PM +0100, Daniel Vetter wrote:
> > On Thu, Jan 24, 2013 at 03:29:50PM +0200, ville.syrjala@linux.intel.com wrote:
> > > #define DSTATE_GFX_RESET_I830 (1<<6)
> > > #define DSTATE_PLL_D3_OFF (1<<3)
> > > #define DSTATE_GFX_CLOCK_GATING (1<<1)
> > > #define DSTATE_DOT_CLOCK_GATING (1<<0)
> > > -#define DSPCLK_GATE_D 0x6200
> > > +#define DSPCLK_GATE_D (dev_priv->info->display_mmio_offset + 0x6200)
> >
> > This one here seems to be only used up to gen4 ...
>
> DSPCLK_GATE_D is used in intel_i2c_quirk_set(). OTOH gma500 has the
> same code commented out, so it may be that we can skip it too. Anyone
> have more details on this quirk?
Afaict that quirk is for pnv only.
> gma500 also seems to use DSPCLK_GATE_D to disable clock gating for
> some DP stuff on CDV. Considering the lineage we need to find out
> if that's something that affects VLV as well.
I guess we could add it once we need it in a vlv clock gating functions.
Generally we tend to only add clock gating defines when we need them,
since there are soooooo many.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH 29/33] drm/i915: VGA registers need an offset on VLV
2013-01-25 10:27 ` Ville Syrjälä
@ 2013-01-25 16:18 ` Daniel Vetter
2013-01-25 16:24 ` Ville Syrjälä
0 siblings, 1 reply; 67+ messages in thread
From: Daniel Vetter @ 2013-01-25 16:18 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Fri, Jan 25, 2013 at 12:27:54PM +0200, Ville Syrjälä wrote:
> On Thu, Jan 24, 2013 at 11:44:09PM +0100, Daniel Vetter wrote:
> > On Thu, Jan 24, 2013 at 03:29:54PM +0200, ville.syrjala@linux.intel.com wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Admittedly I haven't checked them closely, but with my proposed patch in
> > he modeset_s-r branch, do we still need to adjust these? I kinda don't
> > want to keep the legacy vga plane registers around ...
>
> I found two exceptions, well, one really.
>
> i915_disable_vga() pokes at one sequencer register.
Ok, I think we should then only convert that register and add a comment
about it somewhere. I really hope we can get by without all this legacy
vga stuff here ...
> intel_crt_load_detect() polls the sense bit in ST00, but I don't think
> we should ever go there w/ VLV due to is_hotplug=1.
Yeah, load detect is used on gen2/3 for VGA, TV load detect has its own
magic.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH 25/33] drm/i915: PLL and clock gating registers need an offset on VLV
2013-01-25 16:06 ` Daniel Vetter
@ 2013-01-25 16:20 ` Ville Syrjälä
2013-01-25 16:24 ` Daniel Vetter
2013-01-25 16:28 ` Ville Syrjälä
0 siblings, 2 replies; 67+ messages in thread
From: Ville Syrjälä @ 2013-01-25 16:20 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Fri, Jan 25, 2013 at 05:06:51PM +0100, Daniel Vetter wrote:
> On Fri, Jan 25, 2013 at 12:51:15PM +0200, Ville Syrjälä wrote:
> > On Thu, Jan 24, 2013 at 11:41:53PM +0100, Daniel Vetter wrote:
> > > On Thu, Jan 24, 2013 at 03:29:50PM +0200, ville.syrjala@linux.intel.com wrote:
> > > > #define DSTATE_GFX_RESET_I830 (1<<6)
> > > > #define DSTATE_PLL_D3_OFF (1<<3)
> > > > #define DSTATE_GFX_CLOCK_GATING (1<<1)
> > > > #define DSTATE_DOT_CLOCK_GATING (1<<0)
> > > > -#define DSPCLK_GATE_D 0x6200
> > > > +#define DSPCLK_GATE_D (dev_priv->info->display_mmio_offset + 0x6200)
> > >
> > > This one here seems to be only used up to gen4 ...
> >
> > DSPCLK_GATE_D is used in intel_i2c_quirk_set(). OTOH gma500 has the
> > same code commented out, so it may be that we can skip it too. Anyone
> > have more details on this quirk?
>
> Afaict that quirk is for pnv only.
So, should we just kill it for other HW? At least it needs to be killed
for VLV if we don't merge this hunk.
> > gma500 also seems to use DSPCLK_GATE_D to disable clock gating for
> > some DP stuff on CDV. Considering the lineage we need to find out
> > if that's something that affects VLV as well.
>
> I guess we could add it once we need it in a vlv clock gating functions.
> Generally we tend to only add clock gating defines when we need them,
> since there are soooooo many.
Yeah. I need to write down my notes somewhere so we don't forget all
these questions that arose from this patch set.
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH 08/33] drm/i915: SWF screatch registers need an offset on VLV
2013-01-25 12:26 ` Ville Syrjälä
@ 2013-01-25 16:21 ` Daniel Vetter
2013-01-26 16:41 ` Daniel Vetter
0 siblings, 1 reply; 67+ messages in thread
From: Daniel Vetter @ 2013-01-25 16:21 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Fri, Jan 25, 2013 at 02:26:24PM +0200, Ville Syrjälä wrote:
> On Thu, Jan 24, 2013 at 10:37:28PM +0100, Daniel Vetter wrote:
> > On Thu, Jan 24, 2013 at 03:29:33PM +0200, ville.syrjala@linux.intel.com wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > It's true that we safe/restore these suckers across suspend/resume, but I
> > have no idea why or whether we need to. Since there's no way we'll ever
> > support ums on vlv I think we should just try to guard the safe/resume
> > code with DRIVER_MODESET checks and drop this chunk here.
> >
> > Or too risky?
>
> No idea. I suppose some silly BIOS might assume that some of these regs
> retain their contents.
Since opregion the driver/bios collaboration is rather well-defined, so I
think we could risk it by guarding the safe/restore code with a
(DRIVER_MODESET && opregion) check. Of course, if anyone knows anything to
the contrary we need to reconsider.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH 09/33] drm/i915: VGACNTRL needs an offset on VLV
2013-01-25 16:00 ` Daniel Vetter
@ 2013-01-25 16:22 ` Ville Syrjälä
0 siblings, 0 replies; 67+ messages in thread
From: Ville Syrjälä @ 2013-01-25 16:22 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Fri, Jan 25, 2013 at 05:00:42PM +0100, Daniel Vetter wrote:
> On Fri, Jan 25, 2013 at 02:21:16PM +0200, Ville Syrjälä wrote:
> > On Thu, Jan 24, 2013 at 10:39:52PM +0100, Daniel Vetter wrote:
> > > On Thu, Jan 24, 2013 at 03:29:34PM +0200, ville.syrjala@linux.intel.com wrote:
> > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > >
> > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > We already have a switch since VGACNTRL moved around on pch-split
> > > platforms, too. To avoid confusion with different ways to select a given
> > > reg I think a static inline and explicit VLV_VGACNTRL is better. Static
> > > inline since with i915_redisable_vga and i915_disable_vga we already have
> > > two callers.
> >
> > All right. The save/restore paths also touch VGACNTRL. I'll convert
> > those too, even if we don't use them for much longer w/ kms.
>
> Actually I think it'd be easier to merge the few patches I'm working on
> first. I'm testing them right now, will submit soon.
OK. I wrote the patch already but I can wait a bit and rebase before
sending it.
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH 25/33] drm/i915: PLL and clock gating registers need an offset on VLV
2013-01-25 16:20 ` Ville Syrjälä
@ 2013-01-25 16:24 ` Daniel Vetter
2013-01-25 16:28 ` Ville Syrjälä
1 sibling, 0 replies; 67+ messages in thread
From: Daniel Vetter @ 2013-01-25 16:24 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Fri, Jan 25, 2013 at 5:20 PM, Ville Syrjälä
<ville.syrjala@linux.intel.com> wrote:
>> > DSPCLK_GATE_D is used in intel_i2c_quirk_set(). OTOH gma500 has the
>> > same code commented out, so it may be that we can skip it too. Anyone
>> > have more details on this quirk?
>>
>> Afaict that quirk is for pnv only.
>
> So, should we just kill it for other HW? At least it needs to be killed
> for VLV if we don't merge this hunk.
There's a
/* When using bit bashing for I2C, this bit needs to be set to 1 */
if (!IS_PINEVIEW(dev_priv->dev))
return;
guard in the quirk function, hence why it's pnv-only. So nothing to
fix I think, or I'm blind again ;-)
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH 29/33] drm/i915: VGA registers need an offset on VLV
2013-01-25 16:18 ` Daniel Vetter
@ 2013-01-25 16:24 ` Ville Syrjälä
0 siblings, 0 replies; 67+ messages in thread
From: Ville Syrjälä @ 2013-01-25 16:24 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Fri, Jan 25, 2013 at 05:18:58PM +0100, Daniel Vetter wrote:
> On Fri, Jan 25, 2013 at 12:27:54PM +0200, Ville Syrjälä wrote:
> > On Thu, Jan 24, 2013 at 11:44:09PM +0100, Daniel Vetter wrote:
> > > On Thu, Jan 24, 2013 at 03:29:54PM +0200, ville.syrjala@linux.intel.com wrote:
> > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > >
> > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > Admittedly I haven't checked them closely, but with my proposed patch in
> > > he modeset_s-r branch, do we still need to adjust these? I kinda don't
> > > want to keep the legacy vga plane registers around ...
> >
> > I found two exceptions, well, one really.
> >
> > i915_disable_vga() pokes at one sequencer register.
>
> Ok, I think we should then only convert that register and add a comment
> about it somewhere. I really hope we can get by without all this legacy
> vga stuff here ...
Yeah I think the sequencer "screen off" bit is the only one the specs
says we need to touch. BTW I suppose we should really touch it in
i915_redisable_vga() too.
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH 25/33] drm/i915: PLL and clock gating registers need an offset on VLV
2013-01-25 16:20 ` Ville Syrjälä
2013-01-25 16:24 ` Daniel Vetter
@ 2013-01-25 16:28 ` Ville Syrjälä
1 sibling, 0 replies; 67+ messages in thread
From: Ville Syrjälä @ 2013-01-25 16:28 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Fri, Jan 25, 2013 at 06:20:53PM +0200, Ville Syrjälä wrote:
> On Fri, Jan 25, 2013 at 05:06:51PM +0100, Daniel Vetter wrote:
> > On Fri, Jan 25, 2013 at 12:51:15PM +0200, Ville Syrjälä wrote:
> > > On Thu, Jan 24, 2013 at 11:41:53PM +0100, Daniel Vetter wrote:
> > > > On Thu, Jan 24, 2013 at 03:29:50PM +0200, ville.syrjala@linux.intel.com wrote:
> > > > > #define DSTATE_GFX_RESET_I830 (1<<6)
> > > > > #define DSTATE_PLL_D3_OFF (1<<3)
> > > > > #define DSTATE_GFX_CLOCK_GATING (1<<1)
> > > > > #define DSTATE_DOT_CLOCK_GATING (1<<0)
> > > > > -#define DSPCLK_GATE_D 0x6200
> > > > > +#define DSPCLK_GATE_D (dev_priv->info->display_mmio_offset + 0x6200)
> > > >
> > > > This one here seems to be only used up to gen4 ...
> > >
> > > DSPCLK_GATE_D is used in intel_i2c_quirk_set(). OTOH gma500 has the
> > > same code commented out, so it may be that we can skip it too. Anyone
> > > have more details on this quirk?
> >
> > Afaict that quirk is for pnv only.
>
> So, should we just kill it for other HW? At least it needs to be killed
> for VLV if we don't merge this hunk.
Ah, it already is disabled for everything else. Great, less work for
me.
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [PATCH 08/33] drm/i915: SWF screatch registers need an offset on VLV
2013-01-25 16:21 ` Daniel Vetter
@ 2013-01-26 16:41 ` Daniel Vetter
0 siblings, 0 replies; 67+ messages in thread
From: Daniel Vetter @ 2013-01-26 16:41 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Fri, Jan 25, 2013 at 05:21:01PM +0100, Daniel Vetter wrote:
> On Fri, Jan 25, 2013 at 02:26:24PM +0200, Ville Syrjälä wrote:
> > On Thu, Jan 24, 2013 at 10:37:28PM +0100, Daniel Vetter wrote:
> > > On Thu, Jan 24, 2013 at 03:29:33PM +0200, ville.syrjala@linux.intel.com wrote:
> > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > >
> > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > It's true that we safe/restore these suckers across suspend/resume, but I
> > > have no idea why or whether we need to. Since there's no way we'll ever
> > > support ums on vlv I think we should just try to guard the safe/resume
> > > code with DRIVER_MODESET checks and drop this chunk here.
> > >
> > > Or too risky?
> >
> > No idea. I suppose some silly BIOS might assume that some of these regs
> > retain their contents.
>
> Since opregion the driver/bios collaboration is rather well-defined, so I
> think we could risk it by guarding the safe/restore code with a
> (DRIVER_MODESET && opregion) check. Of course, if anyone knows anything to
> the contrary we need to reconsider.
Ok, I've reconsidered: Since we currently still safe/restore these
registers, it's probably better to safe/restore the right ones. Patch
applied, thanks.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 67+ messages in thread
end of thread, other threads:[~2013-01-26 16:39 UTC | newest]
Thread overview: 67+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2013-01-24 13:29 [PATCH 00/33] drm/915: Get rid of IS_DISPLAYREG() ville.syrjala
2013-01-24 13:29 ` [PATCH 01/33] drm/i915: Convert intel_hdmi to enum port ville.syrjala
2013-01-24 17:49 ` Paulo Zanoni
2013-01-24 13:29 ` [PATCH 02/33] drm/i915: Convert intel_dp " ville.syrjala
2013-01-24 17:54 ` Paulo Zanoni
2013-01-25 12:28 ` Ville Syrjälä
2013-01-24 13:29 ` [PATCH 03/33] drm/i915: Add display_display_mmio_offset to intel_device_info ville.syrjala
2013-01-24 13:29 ` [PATCH 04/33] drm/i915: AUD_VID_DID needs an offset on VLV ville.syrjala
2013-01-24 13:29 ` [PATCH 05/33] drm/i915: Per-pipe PP registers are for VLV only ville.syrjala
2013-01-24 13:29 ` [PATCH 06/33] drm/i915: VLV_VIDEO_DIP_CTL is " ville.syrjala
2013-01-24 13:29 ` [PATCH 07/33] drm/i915: PIPE M/N registers need an offset on VLV ville.syrjala
2013-01-24 13:29 ` [PATCH 08/33] drm/i915: SWF screatch " ville.syrjala
2013-01-24 21:37 ` Daniel Vetter
2013-01-25 12:26 ` Ville Syrjälä
2013-01-25 16:21 ` Daniel Vetter
2013-01-26 16:41 ` Daniel Vetter
2013-01-24 13:29 ` [PATCH 09/33] drm/i915: VGACNTRL needs " ville.syrjala
2013-01-24 21:39 ` Daniel Vetter
2013-01-25 12:21 ` Ville Syrjälä
2013-01-25 16:00 ` Daniel Vetter
2013-01-25 16:22 ` Ville Syrjälä
2013-01-24 13:29 ` [PATCH 10/33] drm/i915: Primary plane registers need " ville.syrjala
2013-01-24 13:29 ` [PATCH 11/33] drm/i915: Pipe " ville.syrjala
2013-01-24 13:29 ` [PATCH 12/33] drm/i915: Cursor " ville.syrjala
2013-01-24 13:29 ` [PATCH 13/33] drm/i915: VLV_DDL is VLV only and needs an offset ville.syrjala
2013-01-24 13:29 ` [PATCH 14/33] drm/i915: DSPFW registers need an offset on VLV ville.syrjala
2013-01-24 13:29 ` [PATCH 15/33] drm/i915: DSPARB register needs " ville.syrjala
2013-01-24 22:01 ` Daniel Vetter
2013-01-25 12:05 ` Ville Syrjälä
2013-01-24 13:29 ` [PATCH 16/33] drm/i915: DPFLIPSTAT and DPINVGTT registers are VLV only and need an offset ville.syrjala
2013-01-24 13:29 ` [PATCH 17/33] drm/i915: Pass VLV_DISPLAY_BASE + reg to intel_init_{sdvo, hdmi, dp} on VLV ville.syrjala
2013-01-24 22:05 ` Daniel Vetter
2013-01-25 12:03 ` Ville Syrjälä
2013-01-25 16:02 ` Daniel Vetter
2013-01-24 13:29 ` [PATCH 18/33] drm/i915: Panel fitter registers need an offset " ville.syrjala
2013-01-24 13:29 ` [PATCH 19/33] drm/i915: PORT_HOTPLUG " ville.syrjala
2013-01-24 13:29 ` [PATCH 20/33] drm/i915: VLV_ADPA must be used in VLV code ville.syrjala
2013-01-24 22:12 ` Daniel Vetter
2013-01-25 11:59 ` Ville Syrjälä
2013-01-24 13:29 ` [PATCH 21/33] drm/i915: Pipe timing registers need an offset on VLV ville.syrjala
2013-01-24 13:29 ` [PATCH 22/33] drm/i915: Pipe palette " ville.syrjala
2013-01-24 22:22 ` Daniel Vetter
2013-01-25 10:57 ` Ville Syrjälä
2013-01-24 13:29 ` [PATCH 23/33] drm/i915: FB_BLC_SELF_VLV is VLV only and needs an offset ville.syrjala
2013-01-24 13:29 ` [PATCH 24/33] drm/i915: VLV doesn't seem to have VGA0/VGA1/VGA_PD registers ville.syrjala
2013-01-24 22:26 ` Daniel Vetter
2013-01-25 10:51 ` Ville Syrjälä
2013-01-24 13:29 ` [PATCH 25/33] drm/i915: PLL and clock gating registers need an offset on VLV ville.syrjala
2013-01-24 22:41 ` Daniel Vetter
2013-01-25 10:51 ` Ville Syrjälä
2013-01-25 16:06 ` Daniel Vetter
2013-01-25 16:20 ` Ville Syrjälä
2013-01-25 16:24 ` Daniel Vetter
2013-01-25 16:28 ` Ville Syrjälä
2013-01-24 13:29 ` [PATCH 26/33] drm/i915: Make VLV_GUNIT_CLOCK_GATE register value more readable ville.syrjala
2013-01-24 13:29 ` [PATCH 27/33] drm/i915: Spell out VLV_DISPLAY_BASE for interrupt registers ville.syrjala
2013-01-24 13:29 ` [PATCH 28/33] drm/i915: DPIO registers are VLV only and need an offset ville.syrjala
2013-01-24 13:29 ` [PATCH 29/33] drm/i915: VGA registers need an offset on VLV ville.syrjala
2013-01-24 22:44 ` Daniel Vetter
2013-01-25 10:27 ` Ville Syrjälä
2013-01-25 16:18 ` Daniel Vetter
2013-01-25 16:24 ` Ville Syrjälä
2013-01-24 13:29 ` [PATCH 30/33] drm/i915: GPIO/GMBUS " ville.syrjala
2013-01-24 13:29 ` [PATCH 31/33] drm/i915: Set display_mmio_offset for VLV ville.syrjala
2013-01-24 22:59 ` Daniel Vetter
2013-01-24 13:29 ` [PATCH 32/33] drm/i915: Kill IS_DISPLAYREG() ville.syrjala
2013-01-24 13:29 ` [PATCH 33/33] drm/i915: Kill VLV specific interrupts registers ville.syrjala
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