VLV updates

VLV updates

[Jesse Barnes]

Lots of updates and additions for VLV, all tested this time.  The
biggest changes are the DPIO programming bits.  Lots of the clock and
lane configuration stuff is off on the other side of DPIO, and these
patches are enough to get dual-head configs working with eDP and HDMI,
complete with hotplug and DPMS support.

Sprites are added as well, as is some initial RPS support.  Other than
that, it's just some small bug fixes and changes to better handle the hw
in different code paths.

Thanks,
Jesse

[PATCH 01/28] drm/i915: sprite support for ValleyView

[Jesse Barnes]

No constant alpha yet though, that needs a new ioctl and/or property to
get/set.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_dma.c      |    4 +
 drivers/gpu/drm/i915/i915_drv.h      |    1 +
 drivers/gpu/drm/i915/i915_reg.h      |   57 +++++++++
 drivers/gpu/drm/i915/intel_display.c |   13 ++-
 drivers/gpu/drm/i915/intel_drv.h     |    3 +-
 drivers/gpu/drm/i915/intel_sprite.c  |  213 +++++++++++++++++++++++++++++++++-
 6 files changed, 282 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index e16099b..2ba68b0 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1637,6 +1637,10 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 	else
 		dev_priv->num_pipe = 1;
 
+	dev_priv->num_plane = 1;
+	if (IS_VALLEYVIEW(dev))
+		dev_priv->num_plane = 2;
+
 	ret = drm_vblank_init(dev, dev_priv->num_pipe);
 	if (ret)
 		goto out_gem_unload;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e95337c..48426e1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -915,6 +915,7 @@ typedef struct drm_i915_private {
 
 	int num_pipe;
 	int num_pch_pll;
+	int num_plane;
 
 	unsigned long cfb_size;
 	unsigned int cfb_fb;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cd226c2..ce3e6f4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3237,6 +3237,63 @@
 #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
 #define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
 
+#define _SPACNTR		0x72180
+#define   SP_ENABLE			(1<<31)
+#define   SP_GEAMMA_ENABLE		(1<<30)
+#define   SP_PIXFORMAT_MASK		(0xf<<26)
+#define   SP_FORMAT_YUV422		(0<<26)
+#define   SP_FORMAT_BGR565		(5<<26)
+#define   SP_FORMAT_BGRX8888		(6<<26)
+#define   SP_FORMAT_BGRA8888		(7<<26)
+#define   SP_FORMAT_RGBX1010102		(8<<26)
+#define   SP_FORMAT_RGBA1010102		(9<<26)
+#define   SP_FORMAT_RGBX8888		(0xe<<26)
+#define   SP_FORMAT_RGBA8888		(0xf<<26)
+#define   SP_SOURCE_KEY			(1<<22)
+#define   SP_YUV_BYTE_ORDER_MASK	(3<<16)
+#define   SP_YUV_ORDER_YUYV		(0<<16)
+#define   SP_YUV_ORDER_UYVY		(1<<16)
+#define   SP_YUV_ORDER_YVYU		(2<<16)
+#define   SP_YUV_ORDER_VYUY		(3<<16)
+#define   SP_TILED			(1<<10)
+#define _SPALINOFF		0x72184
+#define _SPASTRIDE		0x72188
+#define _SPAPOS			0x7218c
+#define _SPASIZE		0x72190
+#define _SPAKEYMINVAL		0x72194
+#define _SPAKEYMSK		0x72198
+#define _SPASURF		0x7219c
+#define _SPAKEYMAXVAL		0x721a0
+#define _SPATILEOFF		0x721a4
+#define _SPACONSTALPHA		0x721a8
+#define _SPAGAMC		0x721f4
+
+#define _SPBCNTR		0x72280
+#define _SPBLINOFF		0x72284
+#define _SPBSTRIDE		0x72288
+#define _SPBPOS			0x7228c
+#define _SPBSIZE		0x72290
+#define _SPBKEYMINVAL		0x72294
+#define _SPBKEYMSK		0x72298
+#define _SPBSURF		0x7229c
+#define _SPBKEYMAXVAL		0x722a0
+#define _SPBTILEOFF		0x722a4
+#define _SPBCONSTALPHA		0x722a8
+#define _SPBGAMC		0x722f4
+
+#define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR)
+#define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF)
+#define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE, _SPBSTRIDE)
+#define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS)
+#define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE)
+#define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL, _SPBKEYMINVAL)
+#define SPKEYMSK(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMSK, _SPBKEYMSK)
+#define SPSURF(pipe, plane) _PIPE(pipe * 2 + plane, _SPASURF, _SPBSURF)
+#define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL, _SPBKEYMAXVAL)
+#define SPTILEOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPATILEOFF, _SPBTILEOFF)
+#define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA, _SPBCONSTALPHA)
+#define SPGAMC(pipe, plane) _PIPE(pipe * 2 + plane, _SPAGAMC, _SPBGAMC)
+
 /* VBIOS regs */
 #define VGACNTRL		0x71400
 # define VGA_DISP_DISABLE			(1 << 31)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9b0cd86..5baf850 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8511,6 +8511,8 @@ int intel_framebuffer_init(struct drm_device *dev,
 	case DRM_FORMAT_C8:
 	case DRM_FORMAT_RGB565:
 	case DRM_FORMAT_XRGB8888:
+	case DRM_FORMAT_RGBX8888:
+	case DRM_FORMAT_BGRX8888:
 	case DRM_FORMAT_ARGB8888:
 		break;
 	case DRM_FORMAT_XRGB1555:
@@ -8842,7 +8844,7 @@ void intel_modeset_init_hw(struct drm_device *dev)
 void intel_modeset_init(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	int i, ret;
+	int i, j, ret;
 
 	drm_mode_config_init(dev);
 
@@ -8877,9 +8879,12 @@ void intel_modeset_init(struct drm_device *dev)
 
 	for (i = 0; i < dev_priv->num_pipe; i++) {
 		intel_crtc_init(dev, i);
-		ret = intel_plane_init(dev, i);
-		if (ret)
-			DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
+		for (j = 0; j < dev_priv->num_plane; j++) {
+			ret = intel_plane_init(dev, i, j);
+			if (ret)
+				DRM_DEBUG_KMS("pipe %d plane %d init failed: %d\n",
+					      i, j, ret);
+		}
 	}
 
 	intel_cpu_pll_init(dev);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 010e998..494037d 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -242,6 +242,7 @@ struct intel_crtc {
 
 struct intel_plane {
 	struct drm_plane base;
+	int plane;
 	enum pipe pipe;
 	struct drm_i915_gem_object *obj;
 	bool can_scale;
@@ -488,7 +489,7 @@ extern void intel_edp_link_config(struct intel_encoder *, int *, int *);
 extern int intel_edp_target_clock(struct intel_encoder *,
 				  struct drm_display_mode *mode);
 extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
-extern int intel_plane_init(struct drm_device *dev, enum pipe pipe);
+extern int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
 extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
 				      enum plane plane);
 
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index d086e48..74864a1 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -37,6 +37,181 @@
 #include "i915_drv.h"
 
 static void
+vlv_update_plane(struct drm_plane *dplane, struct drm_framebuffer *fb,
+		 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
+		 unsigned int crtc_w, unsigned int crtc_h,
+		 uint32_t x, uint32_t y,
+		 uint32_t src_w, uint32_t src_h)
+{
+	struct drm_device *dev = dplane->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_plane *intel_plane = to_intel_plane(dplane);
+	int pipe = intel_plane->pipe;
+	int plane = intel_plane->plane;
+	u32 sprctl;
+	int pixel_size;
+
+	sprctl = I915_READ(SPCNTR(pipe, plane));
+
+	/* Mask out pixel format bits in case we change it */
+	sprctl &= ~SP_PIXFORMAT_MASK;
+	sprctl &= ~SP_YUV_BYTE_ORDER_MASK;
+	sprctl &= ~SP_TILED;
+
+	switch (fb->pixel_format) {
+	case DRM_FORMAT_YUYV:
+		sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
+		pixel_size = 2;
+		break;
+	case DRM_FORMAT_YVYU:
+		sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
+		pixel_size = 2;
+		break;
+	case DRM_FORMAT_UYVY:
+		sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
+		pixel_size = 2;
+		break;
+	case DRM_FORMAT_VYUY:
+		sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
+		pixel_size = 2;
+		break;
+	case DRM_FORMAT_BGR565:
+		sprctl |= SP_FORMAT_BGR565;
+		pixel_size = 2;
+		break;
+	case DRM_FORMAT_BGRX8888:
+		sprctl |= SP_FORMAT_BGRX8888;
+		pixel_size = 4;
+		break;
+	case DRM_FORMAT_BGRA8888:
+		sprctl |= SP_FORMAT_BGRA8888;
+		pixel_size = 4;
+		break;
+	case DRM_FORMAT_RGBX1010102:
+		sprctl |= SP_FORMAT_RGBX1010102;
+		pixel_size = 4;
+		break;
+	case DRM_FORMAT_RGBA1010102:
+		sprctl |= SP_FORMAT_RGBA1010102;
+		pixel_size = 4;
+		break;
+	case DRM_FORMAT_RGBX8888:
+		sprctl |= SP_FORMAT_RGBX8888;
+		pixel_size = 4;
+		break;
+	case DRM_FORMAT_RGBA8888:
+		sprctl |= SP_FORMAT_RGBA8888;
+		pixel_size = 4;
+		break;
+	default:
+		DRM_DEBUG_DRIVER("bad pixel format, assuming BGRX8888\n");
+		sprctl |= SP_FORMAT_BGRX8888;
+		pixel_size = 4;
+		break;
+	}
+
+	if (obj->tiling_mode != I915_TILING_NONE)
+		sprctl |= SP_TILED;
+
+	sprctl |= SP_ENABLE;
+
+	/* Sizes are 0 based */
+	src_w--;
+	src_h--;
+	crtc_w--;
+	crtc_h--;
+
+	intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size);
+
+	I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
+	I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
+	if (obj->tiling_mode != I915_TILING_NONE) {
+		I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
+	} else {
+		unsigned long offset;
+
+		offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
+		I915_WRITE(SPLINOFF(pipe, plane), offset);
+	}
+	I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
+	I915_WRITE(SPCNTR(pipe, plane), sprctl);
+	I915_MODIFY_DISPBASE(SPSURF(pipe, plane), obj->gtt_offset);
+	POSTING_READ(SPSURF(pipe, plane));
+}
+
+static void
+vlv_disable_plane(struct drm_plane *dplane)
+{
+	struct drm_device *dev = dplane->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_plane *intel_plane = to_intel_plane(dplane);
+	int pipe = intel_plane->pipe;
+	int plane = intel_plane->plane;
+
+	I915_WRITE(SPCNTR(pipe, plane), I915_READ(SPCNTR(pipe, plane)) &
+		   ~SP_ENABLE);
+	/* Activate double buffered register update */
+	I915_MODIFY_DISPBASE(SPSURF(pipe, plane), 0);
+	POSTING_READ(SPSURF(pipe, plane));
+
+	intel_wait_for_vblank(dev, pipe);
+
+	dev_priv->sprite_scaling_enabled = false;
+	intel_update_watermarks(dev);
+}
+
+static int
+vlv_update_colorkey(struct drm_plane *dplane,
+		    struct drm_intel_sprite_colorkey *key)
+{
+	struct drm_device *dev = dplane->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_plane *intel_plane = to_intel_plane(dplane);
+	int pipe = intel_plane->pipe;
+	int plane = intel_plane->plane;
+	u32 sprctl;
+
+	if (key->flags & I915_SET_COLORKEY_DESTINATION)
+		return -EINVAL;
+
+	I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
+	I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
+	I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask);
+
+	sprctl = I915_READ(SPCNTR(pipe, plane));
+	sprctl &= ~SP_SOURCE_KEY;
+	if (key->flags & I915_SET_COLORKEY_SOURCE)
+		sprctl |= SP_SOURCE_KEY;
+	I915_WRITE(SPCNTR(pipe, plane), sprctl);
+
+	POSTING_READ(SPKEYMSK(pipe, plane));
+
+	return 0;
+}
+
+static void
+vlv_get_colorkey(struct drm_plane *dplane,
+		 struct drm_intel_sprite_colorkey *key)
+{
+	struct drm_device *dev = dplane->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_plane *intel_plane = to_intel_plane(dplane);
+	int pipe = intel_plane->pipe;
+	int plane = intel_plane->plane;
+	u32 sprctl;
+
+	key->min_value = I915_READ(SPKEYMINVAL(pipe, plane));
+	key->max_value = I915_READ(SPKEYMAXVAL(pipe, plane));
+	key->channel_mask = I915_READ(SPKEYMSK(pipe, plane));
+
+	sprctl = I915_READ(SPCNTR(pipe, plane));
+	if (sprctl & SP_SOURCE_KEY)
+		key->flags = I915_SET_COLORKEY_SOURCE;
+	else
+		key->flags = I915_SET_COLORKEY_NONE;
+}
+
+static void
 ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
 		 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
 		 unsigned int crtc_w, unsigned int crtc_h,
@@ -670,8 +845,22 @@ static uint32_t snb_plane_formats[] = {
 	DRM_FORMAT_VYUY,
 };
 
+static uint32_t vlv_plane_formats[] = {
+	DRM_FORMAT_BGR565,
+	DRM_FORMAT_BGRA8888,
+	DRM_FORMAT_RGBA8888,
+	DRM_FORMAT_BGRX8888,
+	DRM_FORMAT_RGBX8888,
+	DRM_FORMAT_RGBX1010102,
+	DRM_FORMAT_RGBA1010102,
+	DRM_FORMAT_YUYV,
+	DRM_FORMAT_YVYU,
+	DRM_FORMAT_UYVY,
+	DRM_FORMAT_VYUY,
+};
+
 int
-intel_plane_init(struct drm_device *dev, enum pipe pipe)
+intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
 {
 	struct intel_plane *intel_plane;
 	unsigned long possible_crtcs;
@@ -718,21 +907,37 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe)
 
 		plane_formats = snb_plane_formats;
 		num_plane_formats = ARRAY_SIZE(snb_plane_formats);
+
+		if (IS_VALLEYVIEW(dev)) {
+			intel_plane->max_downscale = 1;
+			intel_plane->update_plane = vlv_update_plane;
+			intel_plane->disable_plane = vlv_disable_plane;
+			intel_plane->update_colorkey = vlv_update_colorkey;
+			intel_plane->get_colorkey = vlv_get_colorkey;
+
+			plane_formats = vlv_plane_formats;
+			num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
+		}
 		break;
 
 	default:
-		kfree(intel_plane);
-		return -ENODEV;
+		ret = -ENODEV;
+		goto err_free;
 	}
 
 	intel_plane->pipe = pipe;
+	intel_plane->plane = plane;
 	possible_crtcs = (1 << pipe);
 	ret = drm_plane_init(dev, &intel_plane->base, possible_crtcs,
 			     &intel_plane_funcs,
 			     plane_formats, num_plane_formats,
 			     false);
 	if (ret)
-		kfree(intel_plane);
+		goto err_free;
 
 	return ret;
+
+err_free:
+	kfree(intel_plane);
+	return ret;
 }
-- 
1.7.9.5

[PATCH 02/28] drm/i915: add sprite assertion function for VLV

[Jesse Barnes]

Need to make sure sprites are disabled before shutting off a pipe.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_display.c |   20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5baf850..794c23e5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1275,6 +1275,25 @@ static void assert_planes_disabled(struct drm_i915_private *dev_priv,
 	}
 }
 
+static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
+				    enum pipe pipe)
+{
+	int reg, i;
+	u32 val;
+
+	if (!IS_VALLEYVIEW(dev_priv->dev))
+		return;
+
+	/* Need to check both planes against the pipe */
+	for (i = 0; i < dev_priv->num_plane; i++) {
+		reg = SPCNTR(pipe, i);
+		val = I915_READ(reg);
+		WARN((val & SP_ENABLE),
+		     "sprite %d assertion failure, should be off on pipe %c but is still active\n",
+		     pipe * 2 + i, pipe_name(pipe));
+	}
+}
+
 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
 {
 	u32 val;
@@ -1859,6 +1878,7 @@ static void intel_disable_pipe(struct drm_i915_private *dev_priv,
 	 * or we might hang the display.
 	 */
 	assert_planes_disabled(dev_priv, pipe);
+	assert_sprites_disabled(dev_priv, pipe);
 
 	/* Don't disable pipe A or pipe A PLLs if needed */
 	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
-- 
1.7.9.5

[PATCH 03/28] drm/i915: add constant alpha support to sprite ioctl

[Jesse Barnes]

And implement it on ValleyView.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_reg.h     |    1 +
 drivers/gpu/drm/i915/intel_sprite.c |   11 ++++++++++-
 include/uapi/drm/i915_drm.h         |    1 +
 3 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ce3e6f4..fd55b20 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3266,6 +3266,7 @@
 #define _SPAKEYMAXVAL		0x721a0
 #define _SPATILEOFF		0x721a4
 #define _SPACONSTALPHA		0x721a8
+#define   SP_ALPHA_EN		(1<<31)
 #define _SPAGAMC		0x721f4
 
 #define _SPBCNTR		0x72280
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 74864a1..9563df8 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -171,7 +171,8 @@ vlv_update_colorkey(struct drm_plane *dplane,
 	int plane = intel_plane->plane;
 	u32 sprctl;
 
-	if (key->flags & I915_SET_COLORKEY_DESTINATION)
+	if (!(key->flags &
+	      (I915_SET_COLORKEY_SOURCE | I915_SET_COLORKEY_ALPHA)))
 		return -EINVAL;
 
 	I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
@@ -180,8 +181,16 @@ vlv_update_colorkey(struct drm_plane *dplane,
 
 	sprctl = I915_READ(SPCNTR(pipe, plane));
 	sprctl &= ~SP_SOURCE_KEY;
+
+	if (!(key->flags & I915_SET_COLORKEY_ALPHA))
+		I915_WRITE(SPCONSTALPHA(pipe, plane), 0);
+
 	if (key->flags & I915_SET_COLORKEY_SOURCE)
 		sprctl |= SP_SOURCE_KEY;
+	else if (key->flags & I915_SET_COLORKEY_ALPHA) {
+		I915_WRITE(SPCONSTALPHA(pipe, plane),
+			   SP_ALPHA_EN | key->channel_mask);
+	}
 	I915_WRITE(SPCNTR(pipe, plane), sprctl);
 
 	POSTING_READ(SPKEYMSK(pipe, plane));
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 07d5941..05e61bc 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -949,6 +949,7 @@ struct drm_intel_overlay_attrs {
 #define I915_SET_COLORKEY_NONE		(1<<0) /* disable color key matching */
 #define I915_SET_COLORKEY_DESTINATION	(1<<1)
 #define I915_SET_COLORKEY_SOURCE	(1<<2)
+#define I915_SET_COLORKEY_ALPHA		(1<<3)
 struct drm_intel_sprite_colorkey {
 	__u32 plane_id;
 	__u32 min_value;
-- 
1.7.9.5

[PATCH 04/28] drm/i915: update VLV PLL and DPIO code

[Jesse Barnes]

In Valleyview voltage swing, pre-emphasis and lane control registers can
be programmed only through the h/w side band fabric.  Update
vlv_update_pll, i9xx_crtc_enable, and intel_enable_pll with the
appropriate programming.

We need to make sure that the tx lane reset occurs in both the full mode
set and DPMS paths, so factor things out to allow that.

v2: use different DPIO_DIVISOR values for VGA and DisplayPort
v3: Fix update pll logic to use same DPIO_DIVISOR & DPIO_REFSFR values
	for all display interfaces
v4: collapse with various updates
v5: squash with crtc enable/pll enable bits

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |   54 ++++++-
 drivers/gpu/drm/i915/intel_display.c |  266 ++++++++++++++++++++++++++--------
 drivers/gpu/drm/i915/intel_dp.c      |    8 +-
 3 files changed, 261 insertions(+), 67 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fd55b20..b0124e3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -388,14 +388,61 @@
 #define _DPIO_CORE_CLK_B		0x803c
 #define DPIO_CORE_CLK(pipe) _PIPE(pipe, _DPIO_CORE_CLK_A, _DPIO_CORE_CLK_B)
 
+#define _DPIO_IREF_CTL_A		0x8040
+#define _DPIO_IREF_CTL_B		0x8060
+#define DPIO_IREF_CTL(pipe) _PIPE(pipe, _DPIO_IREF_CTL_A, _DPIO_IREF_CTL_B)
+
+#define _DPIO_IREF_A			0x8044
+#define _DPIO_IREF_B			0x8064
+#define DPIO_IREF(pipe) _PIPE(pipe, _DPIO_IREF_A, _DPIO_IREF_B)
+
+#define _DPIO_PLL_CML_A			0x804c
+#define _DPIO_PLL_CML_B			0x806c
+#define DPIO_PLL_CML(pipe) _PIPE(pipe, _DPIO_PLL_CML_A, _DPIO_PLL_CML_B)
+
 #define _DPIO_LFP_COEFF_A		0x8048
 #define _DPIO_LFP_COEFF_B		0x8068
 #define DPIO_LFP_COEFF(pipe) _PIPE(pipe, _DPIO_LFP_COEFF_A, _DPIO_LFP_COEFF_B)
 
+#define DPIO_CALIBRATION		0x80ac
+
 #define DPIO_FASTCLK_DISABLE		0x8100
 
-#define DPIO_DATA_CHANNEL1		0x8220
-#define DPIO_DATA_CHANNEL2		0x8420
+#define _DPIO_PCS_TX_0			0x8200
+#define _DPIO_PCS_TX_1			0x8400
+#define DPIO_PCS_TX(pipe) _PIPE(pipe, _DPIO_PCS_TX_0, _DPIO_PCS_TX_1)
+
+#define _DPIO_PCS_CLK_0			0x8204
+#define _DPIO_PCS_CLK_1			0x8404
+#define DPIO_PCS_CLK(pipe) _PIPE(pipe, _DPIO_PCS_CLK_0, _DPIO_PCS_CLK_1)
+
+#define _DPIO_PCS_STAGGER_0		0x8230
+#define _DPIO_PCS_STAGGER_1		0x8430
+#define DPIO_PCS_STAGGER(pipe) _PIPE(pipe, _DPIO_PCS_STAGGER_0, \
+				     _DPIO_PCS_STAGGER_1)
+
+#define _DPIO_TX_CTL_0			0x82ac
+#define _DPIO_TX_CTL_1			0x84ac
+#define DPIO_TX_CTL(pipe) _PIPE(pipe, _DPIO_TX_CTL_0, _DPIO_TX_CTL_1)
+
+#define _DPIO_TX_LANE_0			0x82b8
+#define _DPIO_TX_LANE_1			0x84b8
+#define DPIO_TX_LANE(pipe) _PIPE(pipe, _DPIO_TX_LANE_0, _DPIO_TX_LANE_1)
+
+#define _DPIO_DATA_CHANNEL1		0x8220
+#define _DPIO_DATA_CHANNEL2		0x8420
+#define DPIO_DATA_CHANNEL(pipe) _PIPE(pipe, _DPIO_DATA_CHANNEL1, _DPIO_DATA_CHANNEL2)
+
+#define _DPIO_DATA_LANE0		0x0220
+#define _DPIO_DATA_LANE1		0x0420
+#define _DPIO_DATA_LANE2		0x2620
+#define _DPIO_DATA_LANE3		0x2820
+#define DPIO_DATA_LANE_A(pipe) _PIPE(pipe, _DPIO_DATA_LANE0, _DPIO_DATA_LANE2)
+#define DPIO_DATA_LANE_B(pipe) _PIPE(pipe, _DPIO_DATA_LANE1, _DPIO_DATA_LANE3)
+#define DPIO_DATA_CHANNEL1              0x8220
+#define DPIO_DATA_CHANNEL2              0x8420
+
+#define DPIO_TX_BROADCAST		0xc044
 
 /*
  * Fence registers
@@ -956,7 +1003,10 @@
 #define   DPLL_FPA01_P1_POST_DIV_MASK	0x00ff0000 /* i915 */
 #define   DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW	0x00ff8000 /* Pineview */
 #define   DPLL_LOCK_VLV			(1<<15)
+#define   DPLL_INTEGRATED_CRI_CLK_VLV	(1<<14)
 #define   DPLL_INTEGRATED_CLOCK_VLV	(1<<13)
+#define   DPLL_PORTC_READY_MASK		(0xf << 4)
+#define   DPLL_PORTB_READY_MASK		(0xf)
 
 #define   DPLL_FPA01_P1_POST_DIV_MASK_I830	0x001f0000
 /*
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 794c23e5..cb4ecad 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3648,6 +3648,56 @@ static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
 	 */
 }
 
+static void vlv_pll_enable_reset(struct drm_crtc *crtc)
+{
+	struct drm_device *dev = crtc->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	int pipe = intel_crtc->pipe;
+
+	WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
+
+	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
+		u32 val;
+		val = intel_dpio_read(dev_priv, _DPIO_DATA_LANE0);
+		if (pipe)
+			val |= (1<<21);
+		val |= (1<<20);
+		intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, val);
+
+		intel_dpio_write(dev_priv, 0x8238, 0x00760018);
+		intel_dpio_write(dev_priv, 0x825c, 0x00400888);
+
+		intel_dpio_write(dev_priv, 0x8200, 0x10080);
+		intel_dpio_write(dev_priv, 0x8204, 0x00600060);
+
+		intel_dpio_write(dev_priv, 0x8294, 0x00000000);
+		intel_dpio_write(dev_priv, 0x8290, 0x2b245f5f);
+		intel_dpio_write(dev_priv, 0x8288, 0x5578b83a);
+		intel_dpio_write(dev_priv, 0x828c, 0x0c782040);
+		intel_dpio_write(dev_priv, 0x690, 0x2b247878);
+		intel_dpio_write(dev_priv, 0x822c, 0x00030000);
+		intel_dpio_write(dev_priv, 0x8224, 0x00002000);
+		intel_dpio_write(dev_priv, 0x8294, 0x80000000);
+
+	}
+	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
+	    intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
+		u32 val;
+		val = intel_dpio_read(dev_priv, _DPIO_DATA_LANE2);
+		if (pipe)
+			val |= (1<<21);
+		val |= (1<<20);
+		intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, val);
+
+		intel_dpio_write(dev_priv, 0x8438, 0x00760018);
+		intel_dpio_write(dev_priv, 0x845c, 0x00400888);
+
+		intel_dpio_write(dev_priv, 0x8400, 0x10080);
+		intel_dpio_write(dev_priv, 0x8404, 0x00600060);
+	}
+}
+
 static void i9xx_crtc_enable(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
@@ -3656,6 +3706,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
 	struct intel_encoder *encoder;
 	int pipe = intel_crtc->pipe;
 	int plane = intel_crtc->plane;
+	u32 port_mask;
 
 	WARN_ON(!crtc->enabled);
 
@@ -3667,10 +3718,26 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
 
 	intel_enable_pll(dev_priv, pipe);
 
+	mutex_lock(&dev_priv->dpio_lock);
+	vlv_pll_enable_reset(crtc);
+	mutex_unlock(&dev_priv->dpio_lock);
+
 	for_each_encoder_on_crtc(dev, crtc, encoder)
 		if (encoder->pre_enable)
 			encoder->pre_enable(encoder);
 
+	for_each_encoder_on_crtc(dev, crtc, encoder)
+		encoder->enable(encoder);
+
+	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
+	    intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
+		port_mask = DPLL_PORTB_READY_MASK;
+	else
+		port_mask = DPLL_PORTC_READY_MASK; /* eDP on port C */
+
+	if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 100))
+		DRM_ERROR("timed out waiting for port ready\n");
+
 	intel_enable_pipe(dev_priv, pipe, false);
 	intel_enable_plane(dev_priv, plane, pipe);
 
@@ -3680,9 +3747,6 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
 	/* Give the overlay scaler a chance to enable if it's on this pipe */
 	intel_crtc_dpms_overlay(intel_crtc, true);
 	intel_crtc_update_cursor(crtc, true);
-
-	for_each_encoder_on_crtc(dev, crtc, encoder)
-		encoder->enable(encoder);
 }
 
 static void i9xx_crtc_disable(struct drm_crtc *crtc)
@@ -3720,6 +3784,26 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
 	    ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe)
 		I915_WRITE(PFIT_CONTROL, 0);
 
+	for_each_encoder_on_crtc(dev, crtc, encoder)
+		if (encoder->post_disable)
+			encoder->post_disable(encoder);
+
+	/* Reset lane for VLV platform*/
+	if (IS_VALLEYVIEW(dev)) {
+		mutex_lock(&dev_priv->dpio_lock);
+		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
+			intel_dpio_write(dev_priv, 0x8200, 0x00000000);
+			intel_dpio_write(dev_priv, 0x8204, 0x00e00060);
+		} else {
+			intel_dpio_write(dev_priv, 0x8400, 0x00000000);
+			intel_dpio_write(dev_priv, 0x8404, 0x00e00060);
+		}
+
+		if (pipe)
+			vlv_init_dpio(dev);
+		mutex_unlock(&dev_priv->dpio_lock);
+	}
+
 	intel_disable_pll(dev_priv, pipe);
 
 	intel_crtc->active = false;
@@ -4272,6 +4356,10 @@ static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
 	int pipe = intel_crtc->pipe;
 	u32 fp, fp2 = 0;
 
+	/* Disable FP0 register programming for VLV X0 */
+	if (IS_VALLEYVIEW(dev))
+		return;
+
 	if (IS_PINEVIEW(dev)) {
 		fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
 		if (reduced_clock)
@@ -4296,6 +4384,31 @@ static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
 	}
 }
 
+static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
+{
+	u32 reg_val;
+
+	/*
+	 * PLLB opamp always calibrates to max value of 0x3f, force enable it
+	 * and set it to a reasonable value instead.
+	 */
+	reg_val = intel_dpio_read(dev_priv, 0x8064);
+	reg_val &= 0xffffff30;
+	intel_dpio_write(dev_priv, 0x8064, reg_val);
+
+	reg_val = intel_dpio_read(dev_priv, 0x80ac);
+	reg_val &= 0x8cffffff;
+	intel_dpio_write(dev_priv, 0x80ac, reg_val);
+
+	reg_val = intel_dpio_read(dev_priv, 0x8064);
+	reg_val &= 0xffffff00;
+	intel_dpio_write(dev_priv, 0x8064, reg_val);
+
+	reg_val = intel_dpio_read(dev_priv, 0x80ac);
+	reg_val &= 0xb0ffffff;
+	intel_dpio_write(dev_priv, 0x80ac, reg_val);
+}
+
 static void vlv_update_pll(struct drm_crtc *crtc,
 			   struct drm_display_mode *mode,
 			   struct drm_display_mode *adjusted_mode,
@@ -4306,23 +4419,14 @@ static void vlv_update_pll(struct drm_crtc *crtc,
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int pipe = intel_crtc->pipe;
-	u32 dpll, mdiv, pdiv;
+	u32 dpll, mdiv;
 	u32 bestn, bestm1, bestm2, bestp1, bestp2;
-	bool is_sdvo;
-	u32 temp;
+	bool is_hdmi;
+	u32 coreclk, reg_val;
 
 	mutex_lock(&dev_priv->dpio_lock);
 
-	is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
-		intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
-
-	dpll = DPLL_VGA_MODE_DIS;
-	dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
-	dpll |= DPLL_REFA_CLK_ENABLE_VLV;
-	dpll |= DPLL_INTEGRATED_CLOCK_VLV;
-
-	I915_WRITE(DPLL(pipe), dpll);
-	POSTING_READ(DPLL(pipe));
+	is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
 
 	bestn = clock->n;
 	bestm1 = clock->m1;
@@ -4330,71 +4434,99 @@ static void vlv_update_pll(struct drm_crtc *crtc,
 	bestp1 = clock->p1;
 	bestp2 = clock->p2;
 
-	/*
-	 * In Valleyview PLL and program lane counter registers are exposed
-	 * through DPIO interface
-	 */
+	/* See eDP HDMI DPIO driver vbios notes doc */
+
+	/* PLL B needs special handling */
+	if (pipe)
+		vlv_pllb_recal_opamp(dev_priv);
+
+	/* Set up Tx target for periodic Rcomp update */
+	intel_dpio_write(dev_priv, 0xc044, 0x0100000f);
+
+	/* Disable target IRef on PLL */
+	reg_val = intel_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
+	reg_val &= 0x00ffffff;
+	intel_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
+
+	intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
+
+	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
+	    intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
+		if (adjusted_mode->clock == 162000)
+			intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
+					 0x009f0003);
+		else
+			intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
+					 0x00d0000f);
+
+	} else
+		intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
+				 0x009f0003);
+
+	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
+	    intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
+		if (!pipe)
+			intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
+					 0x0df40000);
+		else
+			intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
+					 0x0df70000);
+	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
+		if (!pipe)
+			intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
+					 0x0df70000);
+		else
+			intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
+					 0x0df40000);
+	}
+
 	mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
 	mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
 	mdiv |= ((bestn << DPIO_N_SHIFT));
 	mdiv |= (1 << DPIO_POST_DIV_SHIFT);
 	mdiv |= (1 << DPIO_K_SHIFT);
+	intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
+
 	mdiv |= DPIO_ENABLE_CALIBRATION;
 	intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
 
-	intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
+	coreclk = intel_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
+	coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
+	intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
 
-	pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
-		(3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
-		(7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
-		(5 << DPIO_CLK_BIAS_CTL_SHIFT);
-	intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
+	intel_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
 
-	intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
+	/* Enable DPIO clock input */
+	dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
+		DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
+	if (pipe)
+		dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
 
 	dpll |= DPLL_VCO_ENABLE;
 	I915_WRITE(DPLL(pipe), dpll);
 	POSTING_READ(DPLL(pipe));
+	udelay(150);
+
 	if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
 		DRM_ERROR("DPLL %d failed to lock\n", pipe);
 
-	intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
+	if (is_hdmi) {
+		u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
 
-	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
-		intel_dp_set_m_n(crtc, mode, adjusted_mode);
-
-	I915_WRITE(DPLL(pipe), dpll);
-
-	/* Wait for the clocks to stabilize. */
-	POSTING_READ(DPLL(pipe));
-	udelay(150);
-
-	temp = 0;
-	if (is_sdvo) {
-		temp = intel_mode_get_pixel_multiplier(adjusted_mode);
 		if (temp > 1)
 			temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
 		else
 			temp = 0;
-	}
-	I915_WRITE(DPLL_MD(pipe), temp);
-	POSTING_READ(DPLL_MD(pipe));
 
-	/* Now program lane control registers */
-	if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
-			|| intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
-	{
-		temp = 0x1000C4;
-		if(pipe == 1)
-			temp |= (1 << 21);
-		intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
+		I915_WRITE(DPLL_MD(pipe), temp);
+		POSTING_READ(DPLL_MD(pipe));
 	}
-	if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
-	{
-		temp = 0x1000C4;
-		if(pipe == 1)
-			temp |= (1 << 21);
-		intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
+
+	vlv_pll_enable_reset(crtc);
+
+	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
+	    intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
+		intel_dp_set_m_n(crtc, mode, adjusted_mode);
 	}
 
 	mutex_unlock(&dev_priv->dpio_lock);
@@ -4710,11 +4842,12 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 		i8xx_update_pll(crtc, adjusted_mode, &clock,
 				has_reduced_clock ? &reduced_clock : NULL,
 				num_connectors);
-	else if (IS_VALLEYVIEW(dev))
+	else if (IS_VALLEYVIEW(dev)) {
+		refclk = i9xx_get_refclk(crtc, num_connectors);
 		vlv_update_pll(crtc, mode, adjusted_mode, &clock,
 				has_reduced_clock ? &reduced_clock : NULL,
 				num_connectors);
-	else
+	} else
 		i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
 				has_reduced_clock ? &reduced_clock : NULL,
 				num_connectors);
@@ -4805,6 +4938,17 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 
 	intel_update_watermarks(dev);
 
+	/* Wait for Phy status bits to go low */
+	for_each_encoder_on_crtc(dev, crtc, encoder) {
+		if (encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
+			if (wait_for(((I915_READ(DPLL(0)) & 0xF0) == 0), 2000))
+				DRM_ERROR("port c phyready timeout\n");
+		} else if (encoder->type == INTEL_OUTPUT_HDMI) {
+			if (wait_for(((I915_READ(DPLL(0)) & 0x0F) == 0), 2000))
+				DRM_ERROR("port b phyready timeout\n");
+		}
+	}
+
 	return ret;
 }
 
@@ -8410,7 +8554,6 @@ static void intel_setup_outputs(struct drm_device *dev)
 
 		if (I915_READ(VLV_DISPLAY_BASE + SDVOC) & PORT_DETECTED)
 			intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOC, PORT_C);
-
 	} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
 		bool found = false;
 
@@ -9261,9 +9404,6 @@ void intel_modeset_cleanup(struct drm_device *dev)
 
 	ironlake_teardown_rc6(dev);
 
-	if (IS_VALLEYVIEW(dev))
-		vlv_init_dpio(dev);
-
 	mutex_unlock(&dev->struct_mutex);
 
 	/* Disable the irq before mode object teardown, for the irq might
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 0e2750c..2903380 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1388,10 +1388,12 @@ static void intel_disable_dp(struct intel_encoder *encoder)
 static void intel_post_disable_dp(struct intel_encoder *encoder)
 {
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+	struct drm_device *dev = encoder->base.dev;
 
 	if (is_cpu_edp(intel_dp)) {
 		intel_dp_link_down(intel_dp);
-		ironlake_edp_pll_off(intel_dp);
+		if (!IS_VALLEYVIEW(dev))
+			ironlake_edp_pll_off(intel_dp);
 	}
 }
 
@@ -1417,8 +1419,9 @@ static void intel_enable_dp(struct intel_encoder *encoder)
 static void intel_pre_enable_dp(struct intel_encoder *encoder)
 {
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+	struct drm_device *dev = encoder->base.dev;
 
-	if (is_cpu_edp(intel_dp))
+	if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
 		ironlake_edp_pll_on(intel_dp);
 }
 
@@ -2760,6 +2763,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 	if (IS_VALLEYVIEW(dev) && port == PORT_C) {
 		type = DRM_MODE_CONNECTOR_eDP;
 		intel_encoder->type = INTEL_OUTPUT_EDP;
+		intel_dp->is_pch_edp = true;
 	} else if (port == PORT_A || is_pch_edp(intel_dp)) {
 		type = DRM_MODE_CONNECTOR_eDP;
 		intel_encoder->type = INTEL_OUTPUT_EDP;
-- 
1.7.9.5

[PATCH 05/28] drm/i915: panel power sequencing for VLV eDP

[Jesse Barnes]

PPS register offsets have changed in Valleyview.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |    9 ++
 drivers/gpu/drm/i915/intel_display.c |    1 -
 drivers/gpu/drm/i915/intel_dp.c      |  171 ++++++++++++++++++++++++----------
 3 files changed, 132 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b0124e3..766518b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4132,6 +4132,15 @@
 #define PIPEB_PP_OFF_DELAYS     (VLV_DISPLAY_BASE + 0x6130c)
 #define PIPEB_PP_DIVISOR        (VLV_DISPLAY_BASE + 0x61310)
 
+#define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS)
+#define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL)
+#define VLV_PIPE_PP_ON_DELAYS(pipe) \
+		_PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS)
+#define VLV_PIPE_PP_OFF_DELAYS(pipe) \
+		_PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS)
+#define VLV_PIPE_PP_DIVISOR(pipe) \
+		_PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR)
+
 #define PCH_PP_STATUS		0xc7200
 #define PCH_PP_CONTROL		0xc7204
 #define  PANEL_UNLOCK_REGS	(0xabcd << 16)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index cb4ecad..3b189fa 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8551,7 +8551,6 @@ static void intel_setup_outputs(struct drm_device *dev)
 			if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
 				intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
 		}
-
 		if (I915_READ(VLV_DISPLAY_BASE + SDVOC) & PORT_DETECTED)
 			intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOC, PORT_C);
 	} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 2903380..68d238d 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -294,16 +294,20 @@ static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
 {
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 pp_stat_reg;
 
-	return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
+	pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
+	return (I915_READ(pp_stat_reg) & PP_ON) != 0;
 }
 
 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
 {
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 pp_ctrl_reg;
 
-	return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
+	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+	return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
 }
 
 static void
@@ -311,14 +315,19 @@ intel_dp_check_edp(struct intel_dp *intel_dp)
 {
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 pp_stat_reg, pp_ctrl_reg;
 
 	if (!is_edp(intel_dp))
 		return;
+
+	pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
+	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+
 	if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
 		WARN(1, "eDP powered off while attempting aux channel communication.\n");
 		DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
-			      I915_READ(PCH_PP_STATUS),
-			      I915_READ(PCH_PP_CONTROL));
+				I915_READ(pp_stat_reg),
+				I915_READ(pp_ctrl_reg));
 	}
 }
 
@@ -986,16 +995,20 @@ static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
 {
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 pp_stat_reg, pp_ctrl_reg;
+
+	pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
+	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 
 	DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
-		      mask, value,
-		      I915_READ(PCH_PP_STATUS),
-		      I915_READ(PCH_PP_CONTROL));
+			mask, value,
+			I915_READ(pp_stat_reg),
+			I915_READ(pp_ctrl_reg));
 
-	if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
+	if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
 		DRM_ERROR("Panel status timeout: status %08x control %08x\n",
-			  I915_READ(PCH_PP_STATUS),
-			  I915_READ(PCH_PP_CONTROL));
+				I915_READ(pp_stat_reg),
+				I915_READ(pp_ctrl_reg));
 	}
 }
 
@@ -1022,9 +1035,15 @@ static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
  * is locked
  */
 
-static  u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
+static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
 {
-	u32	control = I915_READ(PCH_PP_CONTROL);
+	struct drm_device *dev = intel_dp_to_dev(intel_dp);
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 control;
+	u32 pp_ctrl_reg;
+
+	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+	control = I915_READ(pp_ctrl_reg);
 
 	control &= ~PANEL_UNLOCK_MASK;
 	control |= PANEL_UNLOCK_REGS;
@@ -1036,6 +1055,7 @@ void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 pp;
+	u32 pp_stat_reg, pp_ctrl_reg;
 
 	if (!is_edp(intel_dp))
 		return;
@@ -1054,13 +1074,16 @@ void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
 	if (!ironlake_edp_have_panel_power(intel_dp))
 		ironlake_wait_panel_power_cycle(intel_dp);
 
-	pp = ironlake_get_pp_control(dev_priv);
+	pp = ironlake_get_pp_control(intel_dp);
 	pp |= EDP_FORCE_VDD;
-	I915_WRITE(PCH_PP_CONTROL, pp);
-	POSTING_READ(PCH_PP_CONTROL);
-	DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
-		      I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
 
+	pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
+	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+
+	I915_WRITE(pp_ctrl_reg, pp);
+	POSTING_READ(pp_ctrl_reg);
+	DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
+			I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
 	/*
 	 * If the panel wasn't on, delay before accessing aux channel
 	 */
@@ -1075,19 +1098,23 @@ static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 pp;
+	u32 pp_stat_reg, pp_ctrl_reg;
 
 	WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
 
 	if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
-		pp = ironlake_get_pp_control(dev_priv);
+		pp = ironlake_get_pp_control(intel_dp);
 		pp &= ~EDP_FORCE_VDD;
-		I915_WRITE(PCH_PP_CONTROL, pp);
-		POSTING_READ(PCH_PP_CONTROL);
 
-		/* Make sure sequencer is idle before allowing subsequent activity */
-		DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
-			      I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
+		pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
+		pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+
+		I915_WRITE(pp_ctrl_reg, pp);
+		POSTING_READ(pp_ctrl_reg);
 
+		/* Make sure sequencer is idle before allowing subsequent activity */
+		DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
+		I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
 		msleep(intel_dp->panel_power_down_delay);
 	}
 }
@@ -1131,6 +1158,7 @@ void ironlake_edp_panel_on(struct intel_dp *intel_dp)
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 pp;
+	u32 pp_ctrl_reg;
 
 	if (!is_edp(intel_dp))
 		return;
@@ -1144,7 +1172,7 @@ void ironlake_edp_panel_on(struct intel_dp *intel_dp)
 
 	ironlake_wait_panel_power_cycle(intel_dp);
 
-	pp = ironlake_get_pp_control(dev_priv);
+	pp = ironlake_get_pp_control(intel_dp);
 	if (IS_GEN5(dev)) {
 		/* ILK workaround: disable reset around power sequence */
 		pp &= ~PANEL_POWER_RESET;
@@ -1156,8 +1184,10 @@ void ironlake_edp_panel_on(struct intel_dp *intel_dp)
 	if (!IS_GEN5(dev))
 		pp |= PANEL_POWER_RESET;
 
-	I915_WRITE(PCH_PP_CONTROL, pp);
-	POSTING_READ(PCH_PP_CONTROL);
+	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+
+	I915_WRITE(pp_ctrl_reg, pp);
+	POSTING_READ(pp_ctrl_reg);
 
 	ironlake_wait_panel_on(intel_dp);
 
@@ -1173,6 +1203,7 @@ void ironlake_edp_panel_off(struct intel_dp *intel_dp)
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 pp;
+	u32 pp_ctrl_reg;
 
 	if (!is_edp(intel_dp))
 		return;
@@ -1181,12 +1212,15 @@ void ironlake_edp_panel_off(struct intel_dp *intel_dp)
 
 	WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
 
-	pp = ironlake_get_pp_control(dev_priv);
+	pp = ironlake_get_pp_control(intel_dp);
 	/* We need to switch off panel power _and_ force vdd, for otherwise some
 	 * panels get very unhappy and cease to work. */
 	pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
-	I915_WRITE(PCH_PP_CONTROL, pp);
-	POSTING_READ(PCH_PP_CONTROL);
+
+	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+
+	I915_WRITE(pp_ctrl_reg, pp);
+	POSTING_READ(pp_ctrl_reg);
 
 	intel_dp->want_panel_vdd = false;
 
@@ -1200,6 +1234,7 @@ void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
 	u32 pp;
+	u32 pp_ctrl_reg;
 
 	if (!is_edp(intel_dp))
 		return;
@@ -1212,10 +1247,13 @@ void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
 	 * allowing it to appear.
 	 */
 	msleep(intel_dp->backlight_on_delay);
-	pp = ironlake_get_pp_control(dev_priv);
+	pp = ironlake_get_pp_control(intel_dp);
 	pp |= EDP_BLC_ENABLE;
-	I915_WRITE(PCH_PP_CONTROL, pp);
-	POSTING_READ(PCH_PP_CONTROL);
+
+	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+
+	I915_WRITE(pp_ctrl_reg, pp);
+	POSTING_READ(pp_ctrl_reg);
 
 	intel_panel_enable_backlight(dev, pipe);
 }
@@ -1225,6 +1263,7 @@ void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 pp;
+	u32 pp_ctrl_reg;
 
 	if (!is_edp(intel_dp))
 		return;
@@ -1232,10 +1271,13 @@ void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
 	intel_panel_disable_backlight(dev);
 
 	DRM_DEBUG_KMS("\n");
-	pp = ironlake_get_pp_control(dev_priv);
+	pp = ironlake_get_pp_control(intel_dp);
 	pp &= ~EDP_BLC_ENABLE;
-	I915_WRITE(PCH_PP_CONTROL, pp);
-	POSTING_READ(PCH_PP_CONTROL);
+
+	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+
+	I915_WRITE(pp_ctrl_reg, pp);
+	POSTING_READ(pp_ctrl_reg);
 	msleep(intel_dp->backlight_off_delay);
 }
 
@@ -2617,15 +2659,33 @@ intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct edp_power_seq cur, vbt, spec, final;
 	u32 pp_on, pp_off, pp_div, pp;
+	int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
+
+	if (HAS_PCH_SPLIT(dev)) {
+		pp_control_reg = PCH_PP_CONTROL;
+		pp_on_reg = PCH_PP_ON_DELAYS;
+		pp_off_reg = PCH_PP_OFF_DELAYS;
+		pp_div_reg = PCH_PP_DIVISOR;
+	} else if (IS_VALLEYVIEW(dev)) {
+		pp_control_reg = PIPEA_PP_CONTROL;
+		pp_on_reg = PIPEA_PP_ON_DELAYS;
+		pp_off_reg = PIPEA_PP_OFF_DELAYS;
+		pp_div_reg = PIPEA_PP_DIVISOR;
+	} else {
+		pp_control_reg = PP_CONTROL;
+		pp_on_reg = PP_ON_DELAYS;
+		pp_off_reg = PP_OFF_DELAYS;
+		pp_div_reg = PP_DIVISOR;
+	}
 
 	/* Workaround: Need to write PP_CONTROL with the unlock key as
 	 * the very first thing. */
-	pp = ironlake_get_pp_control(dev_priv);
-	I915_WRITE(PCH_PP_CONTROL, pp);
+	pp = ironlake_get_pp_control(intel_dp);
+	I915_WRITE(pp_control_reg, pp);
 
-	pp_on = I915_READ(PCH_PP_ON_DELAYS);
-	pp_off = I915_READ(PCH_PP_OFF_DELAYS);
-	pp_div = I915_READ(PCH_PP_DIVISOR);
+	pp_on = I915_READ(pp_on_reg);
+	pp_off = I915_READ(pp_off_reg);
+	pp_div = I915_READ(pp_div_reg);
 
 	/* Pull timing values out of registers */
 	cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
@@ -2701,6 +2761,22 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 pp_on, pp_off, pp_div;
+	int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
+	int pp_on_reg, pp_off_reg, pp_div_reg;
+
+	if (HAS_PCH_SPLIT(dev)) {
+		pp_on_reg = PCH_PP_ON_DELAYS;
+		pp_off_reg = PCH_PP_OFF_DELAYS;
+		pp_div_reg = PCH_PP_DIVISOR;
+	} else if (IS_VALLEYVIEW(dev)) {
+		pp_on_reg = PIPEA_PP_ON_DELAYS;
+		pp_off_reg = PIPEA_PP_OFF_DELAYS;
+		pp_div_reg = PIPEA_PP_DIVISOR;
+	} else {
+		pp_on_reg = PP_ON_DELAYS;
+		pp_off_reg = PP_OFF_DELAYS;
+		pp_div_reg = PP_DIVISOR;
+	}
 
 	/* And finally store the new values in the power sequencer. */
 	pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
@@ -2709,8 +2785,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 		 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
 	/* Compute the divisor for the pp clock, simply match the Bspec
 	 * formula. */
-	pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1)
-			<< PP_REFERENCE_DIVIDER_SHIFT;
+	pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
 	pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
 			<< PANEL_POWER_CYCLE_DELAY_SHIFT);
 
@@ -2723,14 +2798,14 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 			pp_on |= PANEL_POWER_PORT_DP_D;
 	}
 
-	I915_WRITE(PCH_PP_ON_DELAYS, pp_on);
-	I915_WRITE(PCH_PP_OFF_DELAYS, pp_off);
-	I915_WRITE(PCH_PP_DIVISOR, pp_div);
+	I915_WRITE(pp_on_reg, pp_on);
+	I915_WRITE(pp_off_reg, pp_off);
+	I915_WRITE(pp_div_reg, pp_div);
 
 	DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
-		      I915_READ(PCH_PP_ON_DELAYS),
-		      I915_READ(PCH_PP_OFF_DELAYS),
-		      I915_READ(PCH_PP_DIVISOR));
+		      I915_READ(pp_on_reg),
+		      I915_READ(pp_off_reg),
+		      I915_READ(pp_div_reg));
 }
 
 void
-- 
1.7.9.5

[PATCH 06/28] drm/i915: add more VLV IDs

[Jesse Barnes]

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_drv.c |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index b342749..dba68c3 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -387,6 +387,9 @@ static const struct pci_device_id pciidlist[] = {		/* aka */
 	INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
 	INTEL_VGA_DEVICE(0x0D36, &intel_haswell_m_info), /* CRW GT2 mobile */
 	INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
+	INTEL_VGA_DEVICE(0x0f31, &intel_valleyview_m_info),
+	INTEL_VGA_DEVICE(0x0f32, &intel_valleyview_m_info),
+	INTEL_VGA_DEVICE(0x0f33, &intel_valleyview_m_info),
 	INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
 	INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
 	{0, 0, 0}
-- 
1.7.9.5

[PATCH 07/28] drm/i915: implement WaForceL3Serialization on VLV and IVB

[Jesse Barnes]

References: https://bugs.freedesktop.org/show_bug.cgi?id=50250
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_reg.h |    3 +++
 drivers/gpu/drm/i915/intel_pm.c |    4 ++++
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 766518b..09b9072 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3583,6 +3583,9 @@
 #define GEN7_L3SQCREG4				0xb034
 #define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1<<27)
 
+#define GEN7_L3SQCREG4				0xb034
+#define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1<<27)
+
 /* WaCatErrorRejectionIssue */
 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030
 #define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 61fee7f..0f1adc8 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3830,6 +3830,10 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
 	I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
 		   ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
 
+	/* WaForceL3Serialization */
+	I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
+		   ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
+
 	/* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
 	 * gating disable must be set.  Failure to set it results in
 	 * flickering pixels due to Z write ordering failures after
-- 
1.7.9.5

[PATCH 08/28] drm/i915: implement WaGTEnableMiFlush on VLV

[Jesse Barnes]

We don't generally use MI_FLUSH these days, but this bit may affect
other flushing logic, so set it to be safe.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c |    6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 1d5d613..e82b994 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -524,10 +524,14 @@ static int init_render_ring(struct intel_ring_buffer *ring)
 		I915_WRITE(GFX_MODE,
 			   _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS));
 
-	if (IS_GEN7(dev))
+	if (IS_GEN7(dev)) {
 		I915_WRITE(GFX_MODE_GEN7,
 			   _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
 			   _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
+		if (IS_VALLEYVIEW(dev))
+			I915_WRITE(MI_MODE, I915_READ(MI_MODE) |
+				   _MASKED_BIT_ENABLE(MI_FLUSH_ENABLE));
+	}
 
 	if (INTEL_INFO(dev)->gen >= 5) {
 		ret = init_pipe_control(ring);
-- 
1.7.9.5

[PATCH 09/28] drm/i915: implement WaDisablePSDDualDispatchEnable on VLV

[Jesse Barnes]

Can prevent a hang when we get to tessellation.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_pm.c |    4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0f1adc8..d6d028a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3903,8 +3903,10 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
 		   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
 		   CHICKEN3_DGMG_DONE_FIX_DISABLE);
 
+	/* WaDisablePSDDualDispatchEnable */
 	I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
-		   _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
+		   _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
+				      GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
 
 	/* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
 	I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
-- 
1.7.9.5

[PATCH 10/28] drm/i915: VLV has force wake

[Jesse Barnes]

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_drv.c |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index dba68c3..af19dca 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -275,6 +275,7 @@ static const struct intel_device_info intel_valleyview_m_info = {
 	.has_blt_ring = 1,
 	.is_valleyview = 1,
 	.display_mmio_offset = VLV_DISPLAY_BASE,
+	.has_force_wake = 1,
 };
 
 static const struct intel_device_info intel_valleyview_d_info = {
@@ -285,6 +286,7 @@ static const struct intel_device_info intel_valleyview_d_info = {
 	.has_blt_ring = 1,
 	.is_valleyview = 1,
 	.display_mmio_offset = VLV_DISPLAY_BASE,
+	.has_force_wake = 1,
 };
 
 static const struct intel_device_info intel_haswell_d_info = {
-- 
1.7.9.5

[PATCH 11/28] drm/i915: add power context allocation and setup on VLV

[Jesse Barnes]

The Gunit has a separate reg for this, so allocate some stolen space for
the power context and initialize the reg.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_drv.h        |    2 ++
 drivers/gpu/drm/i915/i915_gem_stolen.c |   41 ++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h        |    1 +
 3 files changed, 44 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 48426e1..871d7c8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1024,6 +1024,8 @@ typedef struct drm_i915_private {
 
 	struct i915_gpu_error gpu_error;
 
+	struct drm_mm_node *vlv_pctx;
+
 	/* list of fbdev register on this device */
 	struct intel_fbdev *fbdev;
 
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
index 69d97cb..0d137de 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -171,11 +171,49 @@ void i915_gem_stolen_cleanup_compression(struct drm_device *dev)
 	dev_priv->cfb_size = 0;
 }
 
+static void i915_setup_pctx(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_mm_node *pctx;
+	unsigned long pctx_paddr;
+	int pctx_size = 24*1024;
+
+	pctx = drm_mm_search_free(&dev_priv->mm.stolen, pctx_size, 4096, 0);
+	if (pctx)
+		pctx = drm_mm_get_block(pctx, pctx_size, 4096);
+	if (!pctx)
+		goto err;
+
+	pctx_paddr = dev_priv->mm.stolen_base + pctx->start;
+	if (!pctx_paddr)
+		goto err_free_pctx;
+
+	dev_priv->vlv_pctx = pctx;
+	I915_WRITE(VLV_PCBR, pctx_paddr);
+
+	return;
+
+err_free_pctx:
+	drm_mm_put_block(pctx);
+err:
+	DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
+}
+
+static void i915_cleanup_pctx(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	I915_WRITE(VLV_PCBR, 0);
+	drm_mm_put_block(dev_priv->vlv_pctx);
+}
+
 void i915_gem_cleanup_stolen(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
 	i915_gem_stolen_cleanup_compression(dev);
+	if (IS_VALLEYVIEW(dev) && i915_powersave)
+		i915_cleanup_pctx(dev);
 	drm_mm_takedown(&dev_priv->mm.stolen);
 }
 
@@ -193,6 +231,9 @@ int i915_gem_init_stolen(struct drm_device *dev)
 	/* Basic memrange allocator for stolen space */
 	drm_mm_init(&dev_priv->mm.stolen, 0, dev_priv->gtt.stolen_size);
 
+	if (IS_VALLEYVIEW(dev) && i915_powersave)
+		i915_setup_pctx(dev);
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 09b9072..4c45e91 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -623,6 +623,7 @@
 #define VLV_IIR		(VLV_DISPLAY_BASE + 0x20a4)
 #define VLV_IMR		(VLV_DISPLAY_BASE + 0x20a8)
 #define VLV_ISR		(VLV_DISPLAY_BASE + 0x20ac)
+#define VLV_PCBR	(VLV_DISPLAY_BASE + 0x2120)
 #define   I915_PIPE_CONTROL_NOTIFY_INTERRUPT		(1<<18)
 #define   I915_DISPLAY_PORT_INTERRUPT			(1<<17)
 #define   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT	(1<<15)
-- 
1.7.9.5

[PATCH 12/28] drm/i915: add more clock gating for VLV, allow force wake at init

[Jesse Barnes]

From: Ben Widawsky <ben@bwidawsk.net>

Disable all Gunit clock gating and make set the "allow force wake" bit.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_gem.c |    4 ++++
 drivers/gpu/drm/i915/i915_reg.h |    1 +
 drivers/gpu/drm/i915/intel_pm.c |   10 +++++++++-
 3 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 8413ffc..dd67698 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4010,7 +4010,11 @@ int i915_gem_init(struct drm_device *dev)
 	int ret;
 
 	mutex_lock(&dev->struct_mutex);
+
+	/* VLVA0 (potential hack), BIOS isn't actually waking us */
+	I915_WRITE(VLV_GTLC_WAKE_CTRL, 1);
 	i915_gem_init_global_gtt(dev);
+
 	ret = i915_gem_init_hw(dev);
 	mutex_unlock(&dev->struct_mutex);
 	if (ret) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4c45e91..ecf5f30 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4276,6 +4276,7 @@
 #define  FORCEWAKE_ACK_VLV			0x1300b4
 #define  FORCEWAKE_ACK_HSW			0x130044
 #define  FORCEWAKE_ACK				0x130090
+#define  VLV_GTLC_WAKE_CTRL			0x130090
 #define  FORCEWAKE_MT				0xa188 /* multi-threaded */
 #define   FORCEWAKE_KERNEL			0x1
 #define   FORCEWAKE_USER			0x2
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d6d028a..7de8cec 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3991,7 +3991,15 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
 	 * Disable clock gating on th GCFG unit to prevent a delay
 	 * in the reporting of vblank events.
 	 */
-	I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
+	/* VLVA0 HACK */
+	I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
+	I915_WRITE(0x9400, 0xffffffff);
+	I915_WRITE(0x9404, 0xffffffff);
+	I915_WRITE(0x9408, 0xffffffff);
+	I915_WRITE(0x940c, 0xffffffff);
+	I915_WRITE(0x9410, 0xffffffff);
+	I915_WRITE(0x9414, 0xffffffff);
+	I915_WRITE(0x9418, 0xffffffff);
 }
 
 static void g4x_init_clock_gating(struct drm_device *dev)
-- 
1.7.9.5

[PATCH 13/28] drm/i915: fix VLV limits and m/n/p calculations

[Jesse Barnes]

For high res modes m n p calculation is fixed for VLV platform.

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Pallavi G <pallavi.g@intel.com>
Signed-off-by: Yogesh M <yogesh.mohan.marimuthu@intel.com>
Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |   31 +++++++++++++++++++++----------
 1 file changed, 21 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3b189fa..fd4a0d4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -380,21 +380,21 @@ static const intel_limit_t intel_limits_vlv_dac = {
 	.m1 = { .min = 2, .max = 3 },
 	.m2 = { .min = 11, .max = 156 },
 	.p = { .min = 10, .max = 30 },
-	.p1 = { .min = 2, .max = 3 },
+	.p1 = { .min = 1, .max = 3 },
 	.p2 = { .dot_limit = 270000,
 		.p2_slow = 2, .p2_fast = 20 },
 	.find_pll = intel_vlv_find_best_pll,
 };
 
 static const intel_limit_t intel_limits_vlv_hdmi = {
-	.dot = { .min = 20000, .max = 165000 },
-	.vco = { .min = 4000000, .max = 5994000},
-	.n = { .min = 1, .max = 7 },
+	.dot = { .min = 25000, .max = 180000 },
+	.vco = { .min = 4040000, .max = 5960000 },
+	.n = { .min = 1, .max = 5 },
 	.m = { .min = 60, .max = 300 }, /* guess */
 	.m1 = { .min = 2, .max = 3 },
-	.m2 = { .min = 11, .max = 156 },
+	.m2 = { .min = 15, .max = 149 },
 	.p = { .min = 10, .max = 30 },
-	.p1 = { .min = 2, .max = 3 },
+	.p1 = { .min = 1, .max = 3 },
 	.p2 = { .dot_limit = 270000,
 		.p2_slow = 2, .p2_fast = 20 },
 	.find_pll = intel_vlv_find_best_pll,
@@ -408,7 +408,7 @@ static const intel_limit_t intel_limits_vlv_dp = {
 	.m1 = { .min = 2, .max = 3 },
 	.m2 = { .min = 11, .max = 156 },
 	.p = { .min = 10, .max = 30 },
-	.p1 = { .min = 2, .max = 3 },
+	.p1 = { .min = 1, .max = 3 },
 	.p2 = { .dot_limit = 270000,
 		.p2_slow = 2, .p2_fast = 20 },
 	.find_pll = intel_vlv_find_best_pll,
@@ -809,10 +809,14 @@ intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 			int target, int refclk, intel_clock_t *match_clock,
 			intel_clock_t *best_clock)
 {
+#define LONG_OVERFLOW 0x7FFFFFFF
+#define DIFF_OVERFLOW (LONG_OVERFLOW/10000)
+
 	u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 	u32 m, n, fastclk;
 	u32 updrate, minupdate, fracbits, p;
-	unsigned long bestppm, ppm, absppm;
+	long bestppm, ppm, absppm, ppmdiff, absppmdiff;
+	unsigned long ulMult = 1;
 	int dotclk, flag;
 
 	flag = 0;
@@ -841,8 +845,15 @@ intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 					m = m1 * m2;
 					vco = updrate * m;
 					if (vco >= limit->vco.min && vco < limit->vco.max) {
-						ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
-						absppm = (ppm > 0) ? ppm : (-ppm);
+						ppmdiff = ((100*vco)/p) - (100*fastclk);
+						absppmdiff = (ppmdiff > 0) ? ppmdiff : (-ppmdiff);
+						ulMult = 1;
+						while (absppmdiff > DIFF_OVERFLOW) {
+							absppmdiff /= 10;
+							ulMult *= 10;
+						}
+						absppm = ((absppmdiff*10000)/fastclk)*ulMult;
+
 						if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 							bestppm = 0;
 							flag = 1;
-- 
1.7.9.5

[PATCH 14/28] drm/i915: disable watermarks on VLV, pondicherry takes care of this

[Jesse Barnes]

For current usage, not needed.

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c |    4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7de8cec..b8f5a17 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4211,7 +4211,9 @@ void intel_init_pm(struct drm_device *dev)
 		} else
 			dev_priv->display.update_wm = NULL;
 	} else if (IS_VALLEYVIEW(dev)) {
-		dev_priv->display.update_wm = valleyview_update_wm;
+//		dev_priv->display.update_wm = valleyview_update_wm;
+		dev_priv->display.update_wm = NULL;
+//		dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
 		dev_priv->display.init_clock_gating =
 			valleyview_init_clock_gating;
 	} else if (IS_PINEVIEW(dev)) {
-- 
1.7.9.5

[PATCH 15/28] drm/i915: use gen6 stolen check on VLV

[Jesse Barnes]

It uses the same bit definitions.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 926a1e2..2d7d3a9 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -752,7 +752,7 @@ static int gen6_gmch_probe(struct drm_device *dev,
 	pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
 	gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
 
-	if (IS_GEN7(dev))
+	if (IS_GEN7(dev) && !IS_VALLEYVIEW(dev))
 		*stolen = gen7_get_stolen_size(snb_gmch_ctl);
 	else
 		*stolen = gen6_get_stolen_size(snb_gmch_ctl);
-- 
1.7.9.5

[PATCH 16/28] drm/i915: add Punit read/write routines for VLV

[Jesse Barnes]

Slightly different than other platforms.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_drv.h |    2 ++
 drivers/gpu/drm/i915/i915_reg.h |   22 ++++++++++++
 drivers/gpu/drm/i915/intel_pm.c |   74 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 98 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 871d7c8..61e58cc 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1850,6 +1850,8 @@ int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
 
 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
+int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val);
+int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
 
 #define __i915_read(x, y) \
 	u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ecf5f30..27ff029 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4401,6 +4401,28 @@
 #define GEN6_PCODE_DATA				0x138128
 #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
 
+#define VLV_IOSF_DOORBELL_REQ			0x182100
+#define   IOSF_DEVFN_SHIFT			24
+#define   IOSF_OPCODE_SHIFT			16
+#define   IOSF_PORT_SHIFT			8
+#define   IOSF_BYTE_ENABLES_SHIFT		4
+#define   IOSF_BAR_SHIFT			1
+#define   IOSF_SB_BUSY				(1<<0)
+#define   IOSF_PORT_PUNIT			0x4
+#define VLV_IOSF_DATA				0x182104
+#define VLV_IOSF_ADDR				0x182108
+
+#define PUNIT_REG_GPU_LFM			0xd3
+#define PUNIT_REG_GPU_FREQ_REQ			0xd4
+#define PUNIT_REG_GPU_FREQ_STS			0xd8
+#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ		0xdc
+
+#define PUNIT_OPCODE_REG_READ			6
+#define PUNIT_OPCODE_REG_WRITE			7
+
+#define PUNIT_FUSE_BUS2				0xf6 /* bits 47:40 */
+#define PUNIT_FUSE_BUS1				0xf5 /* bits 55:48 */
+
 #define GEN6_GT_CORE_STATUS		0x138060
 #define   GEN6_CORE_CPD_STATE_MASK	(7<<4)
 #define   GEN6_RCn_MASK			7
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b8f5a17..1cedd7d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4524,3 +4524,77 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
 
 	return 0;
 }
+
+int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val)
+{
+	u32 cmd, devfn, opcode, port, be, bar;
+
+	bar = 0;
+	be = 0xf;
+	port = IOSF_PORT_PUNIT;
+	opcode = PUNIT_OPCODE_REG_READ;
+	devfn = 16;
+
+	cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
+		(port << IOSF_PORT_SHIFT) | (be | IOSF_BYTE_ENABLES_SHIFT) |
+		(bar << IOSF_BAR_SHIFT);
+
+	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+
+	if (I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) {
+		DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
+		return -EAGAIN;
+	}
+
+	I915_WRITE(VLV_IOSF_ADDR, addr);
+	I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd);
+
+	if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0,
+		     500)) {
+		DRM_ERROR("timeout waiting for pcode read (%d) to finish\n",
+			  addr);
+		return -ETIMEDOUT;
+	}
+
+	*val = I915_READ(VLV_IOSF_DATA);
+	I915_WRITE(VLV_IOSF_DATA, 0);
+
+	return 0;
+}
+
+int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
+{
+	u32 cmd, devfn, opcode, port, be, bar;
+
+	bar = 0;
+	be = 0xf;
+	port = IOSF_PORT_PUNIT;
+	opcode = PUNIT_OPCODE_REG_WRITE;
+	devfn = 16;
+
+	cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
+		(port << IOSF_PORT_SHIFT) | (be | IOSF_BYTE_ENABLES_SHIFT) |
+		(bar << IOSF_BAR_SHIFT);
+
+	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+
+	if (I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) {
+		DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
+		return -EAGAIN;
+	}
+
+	I915_WRITE(VLV_IOSF_ADDR, addr);
+	I915_WRITE(VLV_IOSF_DATA, val);
+	I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd);
+
+	if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0,
+		     500)) {
+		DRM_ERROR("timeout waiting for pcode write (%d) to finish\n",
+			  addr);
+		return -ETIMEDOUT;
+	}
+
+	I915_WRITE(VLV_IOSF_DATA, 0);
+
+	return 0;
+}
-- 
1.7.9.5

[PATCH 17/28] drm/i915: add media well to VLV force wake routines

[Jesse Barnes]

We could split this out into a separate routine at some point as an
optimization.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_reg.h |    2 ++
 drivers/gpu/drm/i915/intel_pm.c |   11 ++++++++---
 2 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 27ff029..bc5c8d8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4274,6 +4274,8 @@
 #define  FORCEWAKE				0xA18C
 #define  FORCEWAKE_VLV				0x1300b0
 #define  FORCEWAKE_ACK_VLV			0x1300b4
+#define  FORCEWAKE_MEDIA_VLV			0x1300b8
+#define  FORCEWAKE_ACK_MEDIA_VLV		0x1300bc
 #define  FORCEWAKE_ACK_HSW			0x130044
 #define  FORCEWAKE_ACK				0x130090
 #define  VLV_GTLC_WAKE_CTRL			0x130090
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1cedd7d..cc4be1a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4427,10 +4427,15 @@ static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
 		DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
 
 	I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
+	I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
 
 	if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1),
 			    FORCEWAKE_ACK_TIMEOUT_MS))
-		DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
+		DRM_ERROR("Timed out waiting for GT to ack forcewake request.\n");
+
+	if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_MEDIA_VLV) & 1),
+			    FORCEWAKE_ACK_TIMEOUT_MS))
+		DRM_ERROR("Timed out waiting for media to ack forcewake request.\n");
 
 	__gen6_gt_wait_for_thread_c0(dev_priv);
 }
@@ -4438,8 +4443,8 @@ static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
 static void vlv_force_wake_put(struct drm_i915_private *dev_priv)
 {
 	I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
-	/* something from same cacheline, but !FORCEWAKE_VLV */
-	POSTING_READ(FORCEWAKE_ACK_VLV);
+	I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
+	/* The below doubles as a POSTING_READ */
 	gen6_gt_check_fifodbg(dev_priv);
 }
 
-- 
1.7.9.5

[PATCH 18/28] drm/i915: turbo & RC6 support for VLV

[Jesse Barnes]

From: Ben Widawsky <ben@bwidawsk.net>

Uses slightly different interfaces than other platforms.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_pm.c |  148 +++++++++++++++++++++++++++++++++++++--
 1 file changed, 144 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index cc4be1a..fdddc8b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2477,6 +2477,47 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
 	trace_intel_gpu_freq_change(val * 50);
 }
 
+void valleyview_set_rps(struct drm_device *dev, u8 val)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	unsigned long timeout = jiffies + msecs_to_jiffies(100);
+	u32 limits = gen6_rps_limits(dev_priv, &val);
+	u32 pval;
+
+	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+	WARN_ON(val > dev_priv->rps.max_delay);
+	WARN_ON(val < dev_priv->rps.min_delay);
+
+	if (val == dev_priv->rps.cur_delay)
+		return;
+
+	valleyview_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
+
+	do {
+		valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &pval);
+		if (time_after(jiffies, timeout)) {
+			DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
+			break;
+		}
+		udelay(10);
+	} while (pval & 1);
+
+	valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &pval);
+	if ((pval >> 8) != val)
+		DRM_DEBUG_DRIVER("punit overrode freq: %d requested, but got %d\n",
+			  val, pval >> 8);
+
+	/* Make sure we continue to get interrupts
+	 * until we hit the minimum or maximum frequencies.
+	 */
+	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
+
+	dev_priv->rps.cur_delay = val;
+
+	trace_intel_gpu_freq_change(val * 50);
+}
+
+
 static void gen6_disable_rps(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -2714,6 +2755,100 @@ static void gen6_update_ring_freq(struct drm_device *dev)
 	}
 }
 
+static void valleyview_enable_rps(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_ring_buffer *ring;
+	u32 gtfifodbg, val;
+	int i;
+
+	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+
+	if ((gtfifodbg = I915_READ(GTFIFODBG))) {
+		DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
+		I915_WRITE(GTFIFODBG, gtfifodbg);
+	}
+
+	gen6_gt_force_wake_get(dev_priv);
+
+	I915_WRITE(GEN6_RC_SLEEP, 0);
+
+	I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
+	I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
+	I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 0x19);
+
+	for_each_ring(ring, dev_priv, i)
+		I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
+
+	I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
+	I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
+
+	I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
+	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
+	I915_WRITE(GEN6_RP_UP_EI, 66000);
+	I915_WRITE(GEN6_RP_DOWN_EI, 350000);
+
+	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
+
+	I915_WRITE(GEN6_RP_CONTROL,
+		   GEN6_RP_MEDIA_TURBO |
+		   GEN6_RP_MEDIA_HW_NORMAL_MODE |
+		   GEN6_RP_MEDIA_IS_GFX |
+		   GEN6_RP_ENABLE |
+		   GEN6_RP_UP_BUSY_AVG |
+		   GEN6_RP_DOWN_IDLE_CONT);
+
+	/* allows RC6 residency counter to work */
+	I915_WRITE(0x138104, 0xffff00ff);
+	I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE);
+
+	valleyview_punit_read(dev_priv, PUNIT_FUSE_BUS1, &val);
+	DRM_DEBUG_DRIVER("max GPU freq: %d\n", val);
+	dev_priv->rps.max_delay = val;
+
+	valleyview_punit_read(dev_priv, PUNIT_REG_GPU_LFM, &val);
+	DRM_DEBUG_DRIVER("min GPU freq: %d\n", val);
+	dev_priv->rps.min_delay = val;
+
+	valleyview_punit_read(dev_priv, PUNIT_FUSE_BUS2, &val);
+	DRM_DEBUG_DRIVER("max GPLL freq: %d\n", val);
+
+	valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &val);
+	DRM_DEBUG_DRIVER("DDR speed: ");
+	if (((val >> 6) & 3) == 0) {
+		dev_priv->mem_freq = 800;
+		printk("800 MHz\n");
+	} else if (((val >> 6) & 3) == 1) {
+		printk("1066 MHz\n");
+		dev_priv->mem_freq = 1066;
+	} else if (((val >> 6) & 3) == 2) {
+		printk("1333 MHz\n");
+		dev_priv->mem_freq = 1333;
+	} else if (((val >> 6) & 3) == 3)
+		printk("invalid\n");
+	DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 8 ? "yes" : "no");
+	DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
+
+	DRM_DEBUG_DRIVER("current GPU freq: %x\n", (val >> 8) & 0xff);
+	dev_priv->rps.cur_delay = (val >> 8) & 0xff;
+
+	val = 0xd500;
+	DRM_DEBUG_DRIVER("setting GPU freq to %d\n", (val >> 8) & 0xff);
+
+	valleyview_set_rps(dev_priv->dev, (val >> 8) & 0xff);
+
+	/* requires MSI enabled */
+	I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
+	spin_lock_irq(&dev_priv->rps.lock);
+	WARN_ON(dev_priv->rps.pm_iir != 0);
+	I915_WRITE(GEN6_PMIMR, 0);
+	spin_unlock_irq(&dev_priv->rps.lock);
+	/* enable all PM interrupts */
+	I915_WRITE(GEN6_PMINTRMSK, 0);
+
+	gen6_gt_force_wake_put(dev_priv);
+}
+
 void ironlake_teardown_rc6(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3440,7 +3575,7 @@ void intel_disable_gt_powersave(struct drm_device *dev)
 	if (IS_IRONLAKE_M(dev)) {
 		ironlake_disable_drps(dev);
 		ironlake_disable_rc6(dev);
-	} else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) {
+	} else if (INTEL_INFO(dev)->gen >= 6) {
 		cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
 		mutex_lock(&dev_priv->rps.hw_lock);
 		gen6_disable_rps(dev);
@@ -3456,8 +3591,13 @@ static void intel_gen6_powersave_work(struct work_struct *work)
 	struct drm_device *dev = dev_priv->dev;
 
 	mutex_lock(&dev_priv->rps.hw_lock);
-	gen6_enable_rps(dev);
-	gen6_update_ring_freq(dev);
+
+	if (IS_VALLEYVIEW(dev)) {
+		valleyview_enable_rps(dev);
+	} else {
+		gen6_enable_rps(dev);
+		gen6_update_ring_freq(dev);
+	}
 	mutex_unlock(&dev_priv->rps.hw_lock);
 }
 
@@ -3469,7 +3609,7 @@ void intel_enable_gt_powersave(struct drm_device *dev)
 		ironlake_enable_drps(dev);
 		ironlake_enable_rc6(dev);
 		intel_init_emon(dev);
-	} else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
+	} else if (IS_GEN6(dev) || IS_GEN7(dev)) {
 		/*
 		 * PCU communication is slow and this doesn't need to be
 		 * done at any specific time, so do this out of our fast path
-- 
1.7.9.5

[PATCH 19/28] drm/i915: remove VLV MSI IRQ hack

[Jesse Barnes]

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_irq.c |    8 --------
 1 file changed, 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 29037e0..fafef4a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2053,7 +2053,6 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
 	u32 enable_mask;
 	u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
 	u32 render_irqs;
-	u16 msid;
 
 	enable_mask = I915_DISPLAY_PORT_INTERRUPT;
 	enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
@@ -2072,13 +2071,6 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
 	dev_priv->pipestat[0] = 0;
 	dev_priv->pipestat[1] = 0;
 
-	/* Hack for broken MSIs on VLV */
-	pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
-	pci_read_config_word(dev->pdev, 0x98, &msid);
-	msid &= 0xff; /* mask out delivery bits */
-	msid |= (1<<14);
-	pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
-
 	I915_WRITE(PORT_HOTPLUG_EN, 0);
 	POSTING_READ(PORT_HOTPLUG_EN);
 
-- 
1.7.9.5

[PATCH 20/28] drm/i915: don't enumerate VGA on VLV

[Jesse Barnes]

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_display.c |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index fd4a0d4..60397e8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8503,7 +8503,8 @@ static void intel_setup_outputs(struct drm_device *dev)
 		I915_WRITE(PFIT_CONTROL, 0);
 	}
 
-	if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
+	if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)) &&
+	    !IS_VALLEYVIEW(dev))
 		intel_crt_init(dev);
 
 	if (HAS_DDI(dev)) {
-- 
1.7.9.5

[PATCH 21/28] drm/i915: DSPFW and BLC regs are in the display offset range

[Jesse Barnes]

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_reg.h |    8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bc5c8d8..775f11d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1953,7 +1953,7 @@
 #define PFIT_AUTO_RATIOS (dev_priv->info->display_mmio_offset + 0x61238)
 
 /* Backlight control */
-#define BLC_PWM_CTL2		0x61250 /* 965+ only */
+#define BLC_PWM_CTL2	(dev_priv->info->display_mmio_offset + 0x61250) /* 965+ only */
 #define   BLM_PWM_ENABLE		(1 << 31)
 #define   BLM_COMBINATION_MODE		(1 << 30) /* gen4 only */
 #define   BLM_PIPE_SELECT		(1 << 29)
@@ -1972,7 +1972,7 @@
 #define   BLM_PHASE_IN_COUNT_MASK	(0xff << 8)
 #define   BLM_PHASE_IN_INCR_SHIFT	(0)
 #define   BLM_PHASE_IN_INCR_MASK	(0xff << 0)
-#define BLC_PWM_CTL		0x61254
+#define BLC_PWM_CTL	(dev_priv->info->display_mmio_offset + 0x61254)
 /*
  * This is the most significant 15 bits of the number of backlight cycles in a
  * complete cycle of the modulated backlight control.
@@ -1994,7 +1994,7 @@
 #define   BACKLIGHT_DUTY_CYCLE_MASK_PNV		(0xfffe)
 #define   BLM_POLARITY_PNV			(1 << 0) /* pnv only */
 
-#define BLC_HIST_CTL		0x61260
+#define BLC_HIST_CTL	(dev_priv->info->display_mmio_offset + 0x61260)
 
 /* New registers for PCH-split platforms. Safe where new bits show up, the
  * register layout machtes with gen4 BLC_PWM_CTL[12]. */
@@ -2831,6 +2831,8 @@
 #define   DSPFW_HPLL_CURSOR_SHIFT	16
 #define   DSPFW_HPLL_CURSOR_MASK	(0x3f<<16)
 #define   DSPFW_HPLL_SR_MASK		(0x1ff)
+#define DSPFW4			(dev_priv->info->display_mmio_offset + 0x70070)
+#define DSPFW7			(dev_priv->info->display_mmio_offset + 0x7007c)
 
 /* drain latency register values*/
 #define DRAIN_LATENCY_PRECISION_32	32
-- 
1.7.9.5

[PATCH 22/28] drm/i915: don't use plane pipe select on VLV

[Jesse Barnes]

Planes are fixed to pipes in VLV.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_display.c |   12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 60397e8..2559435 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1265,7 +1265,7 @@ static void assert_planes_disabled(struct drm_i915_private *dev_priv,
 	int cur_pipe;
 
 	/* Planes are fixed to pipes on ILK+ */
-	if (HAS_PCH_SPLIT(dev_priv->dev)) {
+	if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
 		reg = DSPCNTR(pipe);
 		val = I915_READ(reg);
 		WARN((val & DISPLAY_PLANE_ENABLE),
@@ -4869,10 +4869,12 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 	/* Set up the display plane register */
 	dspcntr = DISPPLANE_GAMMA_ENABLE;
 
-	if (pipe == 0)
-		dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
-	else
-		dspcntr |= DISPPLANE_SEL_PIPE_B;
+	if (!IS_VALLEYVIEW(dev)) {
+		if (pipe == 0)
+			dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
+		else
+			dspcntr |= DISPPLANE_SEL_PIPE_B;
+	}
 
 	if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
 		/* Enable pixel doubling when the dot clock is > 90% of the (display)
-- 
1.7.9.5

[PATCH 23/28] drm/i915: use VLV DIP routines on VLV

[Jesse Barnes]

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_hdmi.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index fcb36c6..9982b7f 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1038,7 +1038,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
 		BUG();
 	}
 
-	if (!HAS_PCH_SPLIT(dev)) {
+	if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) {
 		intel_hdmi->write_infoframe = g4x_write_infoframe;
 		intel_hdmi->set_infoframes = g4x_set_infoframes;
 	} else if (IS_VALLEYVIEW(dev)) {
-- 
1.7.9.5

[PATCH 24/28] drm/i915: export intel_dpio_write for use in intel_dp.c

[Jesse Barnes]

We need it for some DP training related bits.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_display.c |    3 +--
 drivers/gpu/drm/i915/intel_drv.h     |    2 ++
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2559435..022349b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -434,8 +434,7 @@ u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 	return I915_READ(DPIO_DATA);
 }
 
-static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
-			     u32 val)
+void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
 {
 	WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 494037d..03fdfbd 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -661,6 +661,8 @@ extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
 				     struct drm_file *file_priv);
 
 extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg);
+extern void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
+			     u32 val);
 
 /* Power-related functions, located in intel_pm.c */
 extern void intel_init_pm(struct drm_device *dev);
-- 
1.7.9.5

[PATCH 25/28] drm/i915/dp: program VSwing and Preemphasis control settings on VLV

[Jesse Barnes]

From: Pallavi G <pallavi.g@intel.com>

Program few Tx buffer Swing control settings through DPIO.

Signed-off-by: Pallavi G <pallavi.g@intel.com>
Signed-off-by: Yogesh M <yogesh.mohan.marimuthu@intel.com>
Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c |  114 ++++++++++++++++++++++++++++++++++++++-
 1 file changed, 112 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 68d238d..03340fd 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1527,7 +1527,9 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
 {
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
 
-	if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
+	if (IS_VALLEYVIEW(dev))
+		return DP_TRAIN_VOLTAGE_SWING_1200;
+	else if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
 		return DP_TRAIN_VOLTAGE_SWING_800;
 	else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
 		return DP_TRAIN_VOLTAGE_SWING_1200;
@@ -1552,7 +1554,19 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
 		default:
 			return DP_TRAIN_PRE_EMPHASIS_0;
 		}
-	} else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
+	} else if (IS_VALLEYVIEW(dev)) {
+		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
+		case DP_TRAIN_VOLTAGE_SWING_400:
+			return DP_TRAIN_PRE_EMPHASIS_9_5;
+		case DP_TRAIN_VOLTAGE_SWING_600:
+			return DP_TRAIN_PRE_EMPHASIS_6;
+		case DP_TRAIN_VOLTAGE_SWING_800:
+			return DP_TRAIN_PRE_EMPHASIS_3_5;
+		case DP_TRAIN_VOLTAGE_SWING_1200:
+		default:
+			return DP_TRAIN_PRE_EMPHASIS_0;
+		}
+	} else if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
 		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
 		case DP_TRAIN_VOLTAGE_SWING_400:
 			return DP_TRAIN_PRE_EMPHASIS_6;
@@ -1577,15 +1591,111 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
 	}
 }
 
+static void vlv_set_vswing_pre_emphasis(struct intel_dp *intel_dp, uint8_t v,
+					uint8_t p)
+{
+	struct drm_device *dev = intel_dp_to_dev(intel_dp);
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	unsigned long Demph_reg_value, Preemph_reg_value,
+		Uniqtranscale_reg_value;
+	switch (p) {
+	case DP_TRAIN_PRE_EMPHASIS_0:
+		Preemph_reg_value = 0x0004000;
+		switch (v) {
+		case DP_TRAIN_VOLTAGE_SWING_400:
+			Demph_reg_value = 0x2B405555;
+			Uniqtranscale_reg_value = 0x552AB83A;
+			break;
+		case DP_TRAIN_VOLTAGE_SWING_600:
+			Demph_reg_value = 0x2B404040;
+			Uniqtranscale_reg_value = 0x5548B83A;
+			break;
+		case DP_TRAIN_VOLTAGE_SWING_800:
+			Demph_reg_value = 0x2B245555;
+			Uniqtranscale_reg_value = 0x5560B83A;
+			break;
+		case DP_TRAIN_VOLTAGE_SWING_1200:
+			Demph_reg_value = 0x2B405555;
+			Uniqtranscale_reg_value = 0x5598DA3A;
+			break;
+		default:
+			return;
+		}
+		break;
+	case DP_TRAIN_PRE_EMPHASIS_3_5:
+		Preemph_reg_value = 0x0002000;
+		switch (v) {
+		case DP_TRAIN_VOLTAGE_SWING_400:
+			Demph_reg_value = 0x2B404040;
+			Uniqtranscale_reg_value = 0x5552B83A;
+			break;
+		case DP_TRAIN_VOLTAGE_SWING_600:
+			Demph_reg_value = 0x2B404848;
+			Uniqtranscale_reg_value = 0x5580B83A;
+			break;
+		case DP_TRAIN_VOLTAGE_SWING_800:
+			Demph_reg_value = 0x2B404040;
+			Uniqtranscale_reg_value = 0x55ADDA3A;
+			break;
+		default:
+			return;
+		}
+		break;
+	case DP_TRAIN_PRE_EMPHASIS_6:
+		Preemph_reg_value = 0x0000000;
+		switch (v) {
+		case DP_TRAIN_VOLTAGE_SWING_400:
+			Demph_reg_value = 0x2B305555;
+			Uniqtranscale_reg_value = 0x5570B83A;
+			break;
+		case DP_TRAIN_VOLTAGE_SWING_600:
+			Demph_reg_value = 0x2B2B4040;
+			Uniqtranscale_reg_value = 0x55ADDA3A;
+			break;
+		default:
+			return;
+		}
+		break;
+	case DP_TRAIN_PRE_EMPHASIS_9_5:
+		Preemph_reg_value = 0x0006000;
+		switch (v) {
+		case DP_TRAIN_VOLTAGE_SWING_400:
+			Demph_reg_value = 0x1B405555;
+			Uniqtranscale_reg_value = 0x55ADDA3A;
+			break;
+		default:
+			return;
+		}
+		break;
+	default:
+		return;
+	}
+
+	/* eDP is only on port C */
+	mutex_lock(&dev_priv->dpio_lock);
+	intel_dpio_write(dev_priv, 0x8494, 0x00000000);
+	intel_dpio_write(dev_priv, 0x8490, Demph_reg_value);
+	intel_dpio_write(dev_priv, 0x8488, Uniqtranscale_reg_value);
+	intel_dpio_write(dev_priv, 0x848c, 0x0C782040);
+	intel_dpio_write(dev_priv, 0x842c, 0x00030000);
+	intel_dpio_write(dev_priv, 0x8424, Preemph_reg_value);
+	intel_dpio_write(dev_priv, 0x8494, 0x80000000);
+	mutex_unlock(&dev_priv->dpio_lock);
+}
+
 static void
 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
 {
+	struct drm_device *dev = intel_dp_to_dev(intel_dp);
 	uint8_t v = 0;
 	uint8_t p = 0;
 	int lane;
 	uint8_t voltage_max;
 	uint8_t preemph_max;
 
+	if (IS_VALLEYVIEW(dev))
+		vlv_set_vswing_pre_emphasis(intel_dp, v, p);
+
 	for (lane = 0; lane < intel_dp->lane_count; lane++) {
 		uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
 		uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
-- 
1.7.9.5

[PATCH 26/28] drm/i915: VLV doesn't have HDMI on port C

[Jesse Barnes]

Port C is for eDP.  Port B is shared between HDMI and DP.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_display.c |    2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 022349b..1a4a19e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8564,8 +8564,6 @@ static void intel_setup_outputs(struct drm_device *dev)
 			if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
 				intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
 		}
-		if (I915_READ(VLV_DISPLAY_BASE + SDVOC) & PORT_DETECTED)
-			intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOC, PORT_C);
 	} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
 		bool found = false;
 
-- 
1.7.9.5

[PATCH 27/28] drm/i915/dp: don't use ILK paths on VLV

[Jesse Barnes]

Fix up a couple of places where we messed with PCH bits on VLV.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_dp.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 03340fd..05e1000 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -976,7 +976,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 	}
 
-	if (is_cpu_edp(intel_dp))
+	if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
 		ironlake_set_pll_edp(crtc, adjusted_mode->clock);
 }
 
@@ -1373,7 +1373,7 @@ static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
 	if (!(tmp & DP_PORT_EN))
 		return false;
 
-	if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
+	if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
 		*pipe = PORT_TO_PIPE_CPT(tmp);
 	} else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
 		*pipe = PORT_TO_PIPE(tmp);
-- 
1.7.9.5

[PATCH 28/28] drm/i915/dp: add pre-PCH eDP checking to DP detect for VLV

[Jesse Barnes]

Allows us to detect eDP panels that may not have the hotplug pin wired up.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_dp.c |   10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 05e1000..c127cb7 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2413,6 +2413,16 @@ g4x_dp_detect(struct intel_dp *intel_dp)
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 	uint32_t bit;
 
+	/* Can't disconnect eDP, but you can close the lid... */
+	if (is_edp(intel_dp)) {
+		enum drm_connector_status status;
+
+		status = intel_panel_detect(dev);
+		if (status == connector_status_unknown)
+			status = connector_status_connected;
+		return status;
+	}
+
 	switch (intel_dig_port->port) {
 	case PORT_B:
 		bit = PORTB_HOTPLUG_LIVE_STATUS;
-- 
1.7.9.5

Re: [PATCH 07/28] drm/i915: implement WaForceL3Serialization on VLV and IVB

[Ville Syrjälä]

On Fri, Mar 01, 2013 at 01:14:10PM -0800, Jesse Barnes wrote:
> References: https://bugs.freedesktop.org/show_bug.cgi?id=50250
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |    3 +++
>  drivers/gpu/drm/i915/intel_pm.c |    4 ++++
>  2 files changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 766518b..09b9072 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3583,6 +3583,9 @@
>  #define GEN7_L3SQCREG4				0xb034
>  #define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1<<27)
>  
> +#define GEN7_L3SQCREG4				0xb034
> +#define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1<<27)
> +
>  /* WaCatErrorRejectionIssue */
>  #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030
>  #define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 61fee7f..0f1adc8 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3830,6 +3830,10 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
>  	I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
>  		   ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
>  
> +	/* WaForceL3Serialization */
> +	I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
> +		   ~L3SQ_URB_READ_CAM_MATCH_DISABLE);

I suspect doing it twice won't serialize things any further ;)

Actually it seems we're already clearing the bit twice. So this
is the third one you're adding.

> +
>  	/* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
>  	 * gating disable must be set.  Failure to set it results in
>  	 * flickering pixels due to Z write ordering failures after
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 05/28] drm/i915: panel power sequencing for VLV eDP

[Ville Syrjälä]

On Fri, Mar 01, 2013 at 01:14:08PM -0800, Jesse Barnes wrote:
> PPS register offsets have changed in Valleyview.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      |    9 ++
>  drivers/gpu/drm/i915/intel_display.c |    1 -
>  drivers/gpu/drm/i915/intel_dp.c      |  171 ++++++++++++++++++++++++----------
>  3 files changed, 132 insertions(+), 49 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b0124e3..766518b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4132,6 +4132,15 @@
>  #define PIPEB_PP_OFF_DELAYS     (VLV_DISPLAY_BASE + 0x6130c)
>  #define PIPEB_PP_DIVISOR        (VLV_DISPLAY_BASE + 0x61310)
>  
> +#define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS)
> +#define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL)
> +#define VLV_PIPE_PP_ON_DELAYS(pipe) \
> +		_PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS)
> +#define VLV_PIPE_PP_OFF_DELAYS(pipe) \
> +		_PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS)
> +#define VLV_PIPE_PP_DIVISOR(pipe) \
> +		_PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR)
> +
>  #define PCH_PP_STATUS		0xc7200
>  #define PCH_PP_CONTROL		0xc7204
>  #define  PANEL_UNLOCK_REGS	(0xabcd << 16)
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index cb4ecad..3b189fa 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -8551,7 +8551,6 @@ static void intel_setup_outputs(struct drm_device *dev)
>  			if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
>  				intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
>  		}
> -
>  		if (I915_READ(VLV_DISPLAY_BASE + SDVOC) & PORT_DETECTED)
>  			intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOC, PORT_C);
>  	} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 2903380..68d238d 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -294,16 +294,20 @@ static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
>  {
>  	struct drm_device *dev = intel_dp_to_dev(intel_dp);
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> +	u32 pp_stat_reg;
>  
> -	return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
> +	pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;

You added the macros that take pipe as a parameter. But why is the
actual code hardcoded for pipe A?

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 08/28] drm/i915: implement WaGTEnableMiFlush on VLV

[Ville Syrjälä]

On Fri, Mar 01, 2013 at 01:14:11PM -0800, Jesse Barnes wrote:
> We don't generally use MI_FLUSH these days, but this bit may affect
> other flushing logic, so set it to be safe.

My earlier question stands. Why are we doing this only for VLV, when
the WA applies to everything since SNB?

> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c |    6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 1d5d613..e82b994 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -524,10 +524,14 @@ static int init_render_ring(struct intel_ring_buffer *ring)
>  		I915_WRITE(GFX_MODE,
>  			   _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS));
>  
> -	if (IS_GEN7(dev))
> +	if (IS_GEN7(dev)) {
>  		I915_WRITE(GFX_MODE_GEN7,
>  			   _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
>  			   _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
> +		if (IS_VALLEYVIEW(dev))
> +			I915_WRITE(MI_MODE, I915_READ(MI_MODE) |
> +				   _MASKED_BIT_ENABLE(MI_FLUSH_ENABLE));
> +	}
>  
>  	if (INTEL_INFO(dev)->gen >= 5) {
>  		ret = init_pipe_control(ring);
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 05/28] drm/i915: panel power sequencing for VLV eDP

[Jesse Barnes]

On Fri, 1 Mar 2013 23:43:36 +0200
Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:

> On Fri, Mar 01, 2013 at 01:14:08PM -0800, Jesse Barnes wrote:
> > PPS register offsets have changed in Valleyview.
> > 
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
> > Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> > Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h      |    9 ++
> >  drivers/gpu/drm/i915/intel_display.c |    1 -
> >  drivers/gpu/drm/i915/intel_dp.c      |  171 ++++++++++++++++++++++++----------
> >  3 files changed, 132 insertions(+), 49 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index b0124e3..766518b 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -4132,6 +4132,15 @@
> >  #define PIPEB_PP_OFF_DELAYS     (VLV_DISPLAY_BASE + 0x6130c)
> >  #define PIPEB_PP_DIVISOR        (VLV_DISPLAY_BASE + 0x61310)
> >  
> > +#define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS)
> > +#define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL)
> > +#define VLV_PIPE_PP_ON_DELAYS(pipe) \
> > +		_PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS)
> > +#define VLV_PIPE_PP_OFF_DELAYS(pipe) \
> > +		_PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS)
> > +#define VLV_PIPE_PP_DIVISOR(pipe) \
> > +		_PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR)
> > +
> >  #define PCH_PP_STATUS		0xc7200
> >  #define PCH_PP_CONTROL		0xc7204
> >  #define  PANEL_UNLOCK_REGS	(0xabcd << 16)
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index cb4ecad..3b189fa 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -8551,7 +8551,6 @@ static void intel_setup_outputs(struct drm_device *dev)
> >  			if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
> >  				intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
> >  		}
> > -
> >  		if (I915_READ(VLV_DISPLAY_BASE + SDVOC) & PORT_DETECTED)
> >  			intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOC, PORT_C);
> >  	} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index 2903380..68d238d 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -294,16 +294,20 @@ static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
> >  {
> >  	struct drm_device *dev = intel_dp_to_dev(intel_dp);
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > +	u32 pp_stat_reg;
> >  
> > -	return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
> > +	pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
> 
> You added the macros that take pipe as a parameter. But why is the
> actual code hardcoded for pipe A?

Just because current systems are hard wired to pipe A at this point.
When we get more diverse configs, we'll have to figure out a way to map
the PPS control regs to the right panel (it may not be pipe, but actual
hard wiring).

-- 
Jesse Barnes, Intel Open Source Technology Center
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Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 07/28] drm/i915: implement WaForceL3Serialization on VLV and IVB

[Jesse Barnes]

On Fri, 1 Mar 2013 23:43:25 +0200
Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:

> On Fri, Mar 01, 2013 at 01:14:10PM -0800, Jesse Barnes wrote:
> > References: https://bugs.freedesktop.org/show_bug.cgi?id=50250
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h |    3 +++
> >  drivers/gpu/drm/i915/intel_pm.c |    4 ++++
> >  2 files changed, 7 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 766518b..09b9072 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3583,6 +3583,9 @@
> >  #define GEN7_L3SQCREG4				0xb034
> >  #define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1<<27)
> >  
> > +#define GEN7_L3SQCREG4				0xb034
> > +#define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1<<27)
> > +
> >  /* WaCatErrorRejectionIssue */
> >  #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030
> >  #define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 61fee7f..0f1adc8 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3830,6 +3830,10 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
> >  	I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
> >  		   ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
> >  
> > +	/* WaForceL3Serialization */
> > +	I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
> > +		   ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
> 
> I suspect doing it twice won't serialize things any further ;)
> 
> Actually it seems we're already clearing the bit twice. So this
> is the third one you're adding.
> 

Oh good I can drop this one then.

-- 
Jesse Barnes, Intel Open Source Technology Center
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Re: [PATCH 08/28] drm/i915: implement WaGTEnableMiFlush on VLV

[Jesse Barnes]

On Fri, 1 Mar 2013 23:47:01 +0200
Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:

> On Fri, Mar 01, 2013 at 01:14:11PM -0800, Jesse Barnes wrote:
> > We don't generally use MI_FLUSH these days, but this bit may affect
> > other flushing logic, so set it to be safe.
> 
> My earlier question stands. Why are we doing this only for VLV, when
> the WA applies to everything since SNB?

Sorry I should have looked harder for the earlier comments.  Let's just
drop this one.

-- 
Jesse Barnes, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
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Re: VLV updates

[Jesse Barnes]

On Fri,  1 Mar 2013 13:14:03 -0800
Jesse Barnes <jbarnes@virtuousgeek.org> wrote:

> Lots of updates and additions for VLV, all tested this time.  The
> biggest changes are the DPIO programming bits.  Lots of the clock and
> lane configuration stuff is off on the other side of DPIO, and these
> patches are enough to get dual-head configs working with eDP and HDMI,
> complete with hotplug and DPMS support.
> 
> Sprites are added as well, as is some initial RPS support.  Other than
> that, it's just some small bug fixes and changes to better handle the hw
> in different code paths.

I need to respin this with correct Author info, and drop the patches
Ville mentioned, so please don't take any from this set yet.

Thanks,
-- 
Jesse Barnes, Intel Open Source Technology Center

Re: [PATCH 16/28] drm/i915: add Punit read/write routines for VLV

[Jani Nikula]

On Fri, 01 Mar 2013, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> Slightly different than other platforms.
>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/i915_drv.h |    2 ++
>  drivers/gpu/drm/i915/i915_reg.h |   22 ++++++++++++
>  drivers/gpu/drm/i915/intel_pm.c |   74 +++++++++++++++++++++++++++++++++++++++
>  3 files changed, 98 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 871d7c8..61e58cc 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1850,6 +1850,8 @@ int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
>  
>  int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
>  int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
> +int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val);
> +int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
>  
>  #define __i915_read(x, y) \
>  	u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ecf5f30..27ff029 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4401,6 +4401,28 @@
>  #define GEN6_PCODE_DATA				0x138128
>  #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
>  
> +#define VLV_IOSF_DOORBELL_REQ			0x182100
> +#define   IOSF_DEVFN_SHIFT			24
> +#define   IOSF_OPCODE_SHIFT			16
> +#define   IOSF_PORT_SHIFT			8
> +#define   IOSF_BYTE_ENABLES_SHIFT		4
> +#define   IOSF_BAR_SHIFT			1
> +#define   IOSF_SB_BUSY				(1<<0)
> +#define   IOSF_PORT_PUNIT			0x4
> +#define VLV_IOSF_DATA				0x182104
> +#define VLV_IOSF_ADDR				0x182108
> +
> +#define PUNIT_REG_GPU_LFM			0xd3
> +#define PUNIT_REG_GPU_FREQ_REQ			0xd4
> +#define PUNIT_REG_GPU_FREQ_STS			0xd8
> +#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ		0xdc
> +
> +#define PUNIT_OPCODE_REG_READ			6
> +#define PUNIT_OPCODE_REG_WRITE			7
> +
> +#define PUNIT_FUSE_BUS2				0xf6 /* bits 47:40 */
> +#define PUNIT_FUSE_BUS1				0xf5 /* bits 55:48 */
> +
>  #define GEN6_GT_CORE_STATUS		0x138060
>  #define   GEN6_CORE_CPD_STATE_MASK	(7<<4)
>  #define   GEN6_RCn_MASK			7
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index b8f5a17..1cedd7d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4524,3 +4524,77 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
>  
>  	return 0;
>  }
> +
> +int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val)
> +{
> +	u32 cmd, devfn, opcode, port, be, bar;
> +
> +	bar = 0;
> +	be = 0xf;
> +	port = IOSF_PORT_PUNIT;
> +	opcode = PUNIT_OPCODE_REG_READ;
> +	devfn = 16;
> +
> +	cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
> +		(port << IOSF_PORT_SHIFT) | (be | IOSF_BYTE_ENABLES_SHIFT) |

Should be << not | for IOSF_BYTE_ENABLES_SHIFT. Ditto in the write
function below.

How about picking up a fixed and reworked version of this patch from the
series I sent you? ;)

BR,
Jani.


> +		(bar << IOSF_BAR_SHIFT);
> +
> +	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
> +
> +	if (I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) {
> +		DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
> +		return -EAGAIN;
> +	}
> +
> +	I915_WRITE(VLV_IOSF_ADDR, addr);
> +	I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd);
> +
> +	if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0,
> +		     500)) {
> +		DRM_ERROR("timeout waiting for pcode read (%d) to finish\n",
> +			  addr);
> +		return -ETIMEDOUT;
> +	}
> +
> +	*val = I915_READ(VLV_IOSF_DATA);
> +	I915_WRITE(VLV_IOSF_DATA, 0);
> +
> +	return 0;
> +}
> +
> +int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
> +{
> +	u32 cmd, devfn, opcode, port, be, bar;
> +
> +	bar = 0;
> +	be = 0xf;
> +	port = IOSF_PORT_PUNIT;
> +	opcode = PUNIT_OPCODE_REG_WRITE;
> +	devfn = 16;
> +
> +	cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
> +		(port << IOSF_PORT_SHIFT) | (be | IOSF_BYTE_ENABLES_SHIFT) |
> +		(bar << IOSF_BAR_SHIFT);
> +
> +	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
> +
> +	if (I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) {
> +		DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
> +		return -EAGAIN;
> +	}
> +
> +	I915_WRITE(VLV_IOSF_ADDR, addr);
> +	I915_WRITE(VLV_IOSF_DATA, val);
> +	I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd);
> +
> +	if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0,
> +		     500)) {
> +		DRM_ERROR("timeout waiting for pcode write (%d) to finish\n",
> +			  addr);
> +		return -ETIMEDOUT;
> +	}
> +
> +	I915_WRITE(VLV_IOSF_DATA, 0);
> +
> +	return 0;
> +}
> -- 
> 1.7.9.5
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 16/28] drm/i915: add Punit read/write routines for VLV

[Jesse Barnes]

On Mon, 04 Mar 2013 10:43:03 +0200
Jani Nikula <jani.nikula@linux.intel.com> wrote:

> > +int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val)
> > +{
> > +	u32 cmd, devfn, opcode, port, be, bar;
> > +
> > +	bar = 0;
> > +	be = 0xf;
> > +	port = IOSF_PORT_PUNIT;
> > +	opcode = PUNIT_OPCODE_REG_READ;
> > +	devfn = 16;
> > +
> > +	cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
> > +		(port << IOSF_PORT_SHIFT) | (be | IOSF_BYTE_ENABLES_SHIFT) |  
> 
> Should be << not | for IOSF_BYTE_ENABLES_SHIFT. Ditto in the write
> function below.
> 
> How about picking up a fixed and reworked version of this patch from the
> series I sent you? ;)

Yeah I suck.  I'll respin with your bits.

Thanks,
-- 
Jesse Barnes, Intel Open Source Technology Center

Re: [PATCH 01/28] drm/i915: sprite support for ValleyView

[Ville Syrjälä]

On Fri, Mar 01, 2013 at 01:14:04PM -0800, Jesse Barnes wrote:
> No constant alpha yet though, that needs a new ioctl and/or property to
> get/set.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/i915_dma.c      |    4 +
>  drivers/gpu/drm/i915/i915_drv.h      |    1 +
>  drivers/gpu/drm/i915/i915_reg.h      |   57 +++++++++
>  drivers/gpu/drm/i915/intel_display.c |   13 ++-
>  drivers/gpu/drm/i915/intel_drv.h     |    3 +-
>  drivers/gpu/drm/i915/intel_sprite.c  |  213 +++++++++++++++++++++++++++++++++-
>  6 files changed, 282 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index e16099b..2ba68b0 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -1637,6 +1637,10 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
>  	else
>  		dev_priv->num_pipe = 1;
>  
> +	dev_priv->num_plane = 1;
> +	if (IS_VALLEYVIEW(dev))
> +		dev_priv->num_plane = 2;
> +
>  	ret = drm_vblank_init(dev, dev_priv->num_pipe);
>  	if (ret)
>  		goto out_gem_unload;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index e95337c..48426e1 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -915,6 +915,7 @@ typedef struct drm_i915_private {
>  
>  	int num_pipe;
>  	int num_pch_pll;
> +	int num_plane;
>  
>  	unsigned long cfb_size;
>  	unsigned int cfb_fb;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index cd226c2..ce3e6f4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3237,6 +3237,63 @@
>  #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
>  #define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
>  
> +#define _SPACNTR		0x72180
> +#define   SP_ENABLE			(1<<31)
> +#define   SP_GEAMMA_ENABLE		(1<<30)
> +#define   SP_PIXFORMAT_MASK		(0xf<<26)
> +#define   SP_FORMAT_YUV422		(0<<26)
> +#define   SP_FORMAT_BGR565		(5<<26)
> +#define   SP_FORMAT_BGRX8888		(6<<26)
> +#define   SP_FORMAT_BGRA8888		(7<<26)
> +#define   SP_FORMAT_RGBX1010102		(8<<26)
> +#define   SP_FORMAT_RGBA1010102		(9<<26)
> +#define   SP_FORMAT_RGBX8888		(0xe<<26)
> +#define   SP_FORMAT_RGBA8888		(0xf<<26)
> +#define   SP_SOURCE_KEY			(1<<22)
> +#define   SP_YUV_BYTE_ORDER_MASK	(3<<16)
> +#define   SP_YUV_ORDER_YUYV		(0<<16)
> +#define   SP_YUV_ORDER_UYVY		(1<<16)
> +#define   SP_YUV_ORDER_YVYU		(2<<16)
> +#define   SP_YUV_ORDER_VYUY		(3<<16)
> +#define   SP_TILED			(1<<10)
> +#define _SPALINOFF		0x72184
> +#define _SPASTRIDE		0x72188
> +#define _SPAPOS			0x7218c
> +#define _SPASIZE		0x72190
> +#define _SPAKEYMINVAL		0x72194
> +#define _SPAKEYMSK		0x72198
> +#define _SPASURF		0x7219c
> +#define _SPAKEYMAXVAL		0x721a0
> +#define _SPATILEOFF		0x721a4
> +#define _SPACONSTALPHA		0x721a8
> +#define _SPAGAMC		0x721f4
> +
> +#define _SPBCNTR		0x72280
> +#define _SPBLINOFF		0x72284
> +#define _SPBSTRIDE		0x72288
> +#define _SPBPOS			0x7228c
> +#define _SPBSIZE		0x72290
> +#define _SPBKEYMINVAL		0x72294
> +#define _SPBKEYMSK		0x72298
> +#define _SPBSURF		0x7229c
> +#define _SPBKEYMAXVAL		0x722a0
> +#define _SPBTILEOFF		0x722a4
> +#define _SPBCONSTALPHA		0x722a8
> +#define _SPBGAMC		0x722f4
> +
> +#define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR)
> +#define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF)
> +#define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE, _SPBSTRIDE)
> +#define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS)
> +#define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE)
> +#define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL, _SPBKEYMINVAL)
> +#define SPKEYMSK(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMSK, _SPBKEYMSK)
> +#define SPSURF(pipe, plane) _PIPE(pipe * 2 + plane, _SPASURF, _SPBSURF)
> +#define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL, _SPBKEYMAXVAL)
> +#define SPTILEOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPATILEOFF, _SPBTILEOFF)
> +#define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA, _SPBCONSTALPHA)
> +#define SPGAMC(pipe, plane) _PIPE(pipe * 2 + plane, _SPAGAMC, _SPBGAMC)
> +
>  /* VBIOS regs */
>  #define VGACNTRL		0x71400
>  # define VGA_DISP_DISABLE			(1 << 31)
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 9b0cd86..5baf850 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -8511,6 +8511,8 @@ int intel_framebuffer_init(struct drm_device *dev,
>  	case DRM_FORMAT_C8:
>  	case DRM_FORMAT_RGB565:
>  	case DRM_FORMAT_XRGB8888:
> +	case DRM_FORMAT_RGBX8888:
> +	case DRM_FORMAT_BGRX8888:
>  	case DRM_FORMAT_ARGB8888:
>  		break;
>  	case DRM_FORMAT_XRGB1555:
> @@ -8842,7 +8844,7 @@ void intel_modeset_init_hw(struct drm_device *dev)
>  void intel_modeset_init(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	int i, ret;
> +	int i, j, ret;
>  
>  	drm_mode_config_init(dev);
>  
> @@ -8877,9 +8879,12 @@ void intel_modeset_init(struct drm_device *dev)
>  
>  	for (i = 0; i < dev_priv->num_pipe; i++) {
>  		intel_crtc_init(dev, i);
> -		ret = intel_plane_init(dev, i);
> -		if (ret)
> -			DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
> +		for (j = 0; j < dev_priv->num_plane; j++) {
> +			ret = intel_plane_init(dev, i, j);
> +			if (ret)
> +				DRM_DEBUG_KMS("pipe %d plane %d init failed: %d\n",
> +					      i, j, ret);
> +		}
>  	}
>  
>  	intel_cpu_pll_init(dev);
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 010e998..494037d 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -242,6 +242,7 @@ struct intel_crtc {
>  
>  struct intel_plane {
>  	struct drm_plane base;
> +	int plane;
>  	enum pipe pipe;
>  	struct drm_i915_gem_object *obj;
>  	bool can_scale;
> @@ -488,7 +489,7 @@ extern void intel_edp_link_config(struct intel_encoder *, int *, int *);
>  extern int intel_edp_target_clock(struct intel_encoder *,
>  				  struct drm_display_mode *mode);
>  extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
> -extern int intel_plane_init(struct drm_device *dev, enum pipe pipe);
> +extern int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
>  extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
>  				      enum plane plane);
>  
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index d086e48..74864a1 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -37,6 +37,181 @@
>  #include "i915_drv.h"
>  
>  static void
> +vlv_update_plane(struct drm_plane *dplane, struct drm_framebuffer *fb,
> +		 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
> +		 unsigned int crtc_w, unsigned int crtc_h,
> +		 uint32_t x, uint32_t y,
> +		 uint32_t src_w, uint32_t src_h)
> +{
> +	struct drm_device *dev = dplane->dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_plane *intel_plane = to_intel_plane(dplane);
> +	int pipe = intel_plane->pipe;
> +	int plane = intel_plane->plane;
> +	u32 sprctl;
> +	int pixel_size;

Use drm_format_plane_cpp() for pixel_size

> +
> +	sprctl = I915_READ(SPCNTR(pipe, plane));
> +
> +	/* Mask out pixel format bits in case we change it */
> +	sprctl &= ~SP_PIXFORMAT_MASK;
> +	sprctl &= ~SP_YUV_BYTE_ORDER_MASK;
> +	sprctl &= ~SP_TILED;
> +
> +	switch (fb->pixel_format) {
> +	case DRM_FORMAT_YUYV:
> +		sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
> +		pixel_size = 2;
> +		break;
> +	case DRM_FORMAT_YVYU:
> +		sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
> +		pixel_size = 2;
> +		break;
> +	case DRM_FORMAT_UYVY:
> +		sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
> +		pixel_size = 2;
> +		break;
> +	case DRM_FORMAT_VYUY:
> +		sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
> +		pixel_size = 2;
> +		break;
> +	case DRM_FORMAT_BGR565:
> +		sprctl |= SP_FORMAT_BGR565;
> +		pixel_size = 2;
> +		break;
> +	case DRM_FORMAT_BGRX8888:
> +		sprctl |= SP_FORMAT_BGRX8888;
> +		pixel_size = 4;
> +		break;
> +	case DRM_FORMAT_BGRA8888:
> +		sprctl |= SP_FORMAT_BGRA8888;
> +		pixel_size = 4;
> +		break;
> +	case DRM_FORMAT_RGBX1010102:
> +		sprctl |= SP_FORMAT_RGBX1010102;
> +		pixel_size = 4;
> +		break;
> +	case DRM_FORMAT_RGBA1010102:
> +		sprctl |= SP_FORMAT_RGBA1010102;
> +		pixel_size = 4;
> +		break;
> +	case DRM_FORMAT_RGBX8888:
> +		sprctl |= SP_FORMAT_RGBX8888;
> +		pixel_size = 4;
> +		break;
> +	case DRM_FORMAT_RGBA8888:
> +		sprctl |= SP_FORMAT_RGBA8888;
> +		pixel_size = 4;
> +		break;
> +	default:
> +		DRM_DEBUG_DRIVER("bad pixel format, assuming BGRX8888\n");
> +		sprctl |= SP_FORMAT_BGRX8888;
> +		pixel_size = 4;
> +		break;

BUG();

> +	}
> +
> +	if (obj->tiling_mode != I915_TILING_NONE)
> +		sprctl |= SP_TILED;
> +
> +	sprctl |= SP_ENABLE;
> +
> +	/* Sizes are 0 based */
> +	src_w--;
> +	src_h--;
> +	crtc_w--;
> +	crtc_h--;
> +
> +	intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size);
> +
> +	I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
> +	I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
> +	if (obj->tiling_mode != I915_TILING_NONE) {
> +		I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
> +	} else {
> +		unsigned long offset;
> +
> +		offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
> +		I915_WRITE(SPLINOFF(pipe, plane), offset);
> +	}

intel_gen4_compute_page_offset() should be used.

> +	I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
> +	I915_WRITE(SPCNTR(pipe, plane), sprctl);
> +	I915_MODIFY_DISPBASE(SPSURF(pipe, plane), obj->gtt_offset);
> +	POSTING_READ(SPSURF(pipe, plane));
> +}
> +
> +static void
> +vlv_disable_plane(struct drm_plane *dplane)
> +{
> +	struct drm_device *dev = dplane->dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_plane *intel_plane = to_intel_plane(dplane);
> +	int pipe = intel_plane->pipe;
> +	int plane = intel_plane->plane;
> +
> +	I915_WRITE(SPCNTR(pipe, plane), I915_READ(SPCNTR(pipe, plane)) &
> +		   ~SP_ENABLE);
> +	/* Activate double buffered register update */
> +	I915_MODIFY_DISPBASE(SPSURF(pipe, plane), 0);
> +	POSTING_READ(SPSURF(pipe, plane));
> +
> +	intel_wait_for_vblank(dev, pipe);

We don't do this for ilk/ivb. I guess we should. Although w/ my sprite
clipping patches, it needs to be placed into intel_disable_plane() to
avoid double waits when fully clipped. Also having it in
intel_disable_plane() would be a bit more symmetric with the other
intel_wait_for_vblank() call in intel_update_plane().

> +
> +	dev_priv->sprite_scaling_enabled = false;
> +	intel_update_watermarks(dev);

ivb only stuff. Not needed on vlv.

> +}
> +
> +static int
> +vlv_update_colorkey(struct drm_plane *dplane,
> +		    struct drm_intel_sprite_colorkey *key)
> +{
> +	struct drm_device *dev = dplane->dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_plane *intel_plane = to_intel_plane(dplane);
> +	int pipe = intel_plane->pipe;
> +	int plane = intel_plane->plane;
> +	u32 sprctl;
> +
> +	if (key->flags & I915_SET_COLORKEY_DESTINATION)
> +		return -EINVAL;
> +
> +	I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
> +	I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
> +	I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask);
> +
> +	sprctl = I915_READ(SPCNTR(pipe, plane));
> +	sprctl &= ~SP_SOURCE_KEY;
> +	if (key->flags & I915_SET_COLORKEY_SOURCE)
> +		sprctl |= SP_SOURCE_KEY;
> +	I915_WRITE(SPCNTR(pipe, plane), sprctl);
> +
> +	POSTING_READ(SPKEYMSK(pipe, plane));
> +
> +	return 0;
> +}
> +
> +static void
> +vlv_get_colorkey(struct drm_plane *dplane,
> +		 struct drm_intel_sprite_colorkey *key)
> +{
> +	struct drm_device *dev = dplane->dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_plane *intel_plane = to_intel_plane(dplane);
> +	int pipe = intel_plane->pipe;
> +	int plane = intel_plane->plane;
> +	u32 sprctl;
> +
> +	key->min_value = I915_READ(SPKEYMINVAL(pipe, plane));
> +	key->max_value = I915_READ(SPKEYMAXVAL(pipe, plane));
> +	key->channel_mask = I915_READ(SPKEYMSK(pipe, plane));
> +
> +	sprctl = I915_READ(SPCNTR(pipe, plane));
> +	if (sprctl & SP_SOURCE_KEY)
> +		key->flags = I915_SET_COLORKEY_SOURCE;
> +	else
> +		key->flags = I915_SET_COLORKEY_NONE;
> +}
> +
> +static void
>  ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
>  		 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
>  		 unsigned int crtc_w, unsigned int crtc_h,
> @@ -670,8 +845,22 @@ static uint32_t snb_plane_formats[] = {
>  	DRM_FORMAT_VYUY,
>  };
>  
> +static uint32_t vlv_plane_formats[] = {
> +	DRM_FORMAT_BGR565,
> +	DRM_FORMAT_BGRA8888,
> +	DRM_FORMAT_RGBA8888,
> +	DRM_FORMAT_BGRX8888,
> +	DRM_FORMAT_RGBX8888,
> +	DRM_FORMAT_RGBX1010102,
> +	DRM_FORMAT_RGBA1010102,

RGB vs. BGR most likely mixed up. Maybe we should change our defines to
follow the drm_fourcc.h order to avoid confusion...

> +	DRM_FORMAT_YUYV,
> +	DRM_FORMAT_YVYU,
> +	DRM_FORMAT_UYVY,
> +	DRM_FORMAT_VYUY,
> +};
> +
>  int
> -intel_plane_init(struct drm_device *dev, enum pipe pipe)
> +intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
>  {
>  	struct intel_plane *intel_plane;
>  	unsigned long possible_crtcs;
> @@ -718,21 +907,37 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe)
>  
>  		plane_formats = snb_plane_formats;
>  		num_plane_formats = ARRAY_SIZE(snb_plane_formats);
> +
> +		if (IS_VALLEYVIEW(dev)) {
> +			intel_plane->max_downscale = 1;
> +			intel_plane->update_plane = vlv_update_plane;
> +			intel_plane->disable_plane = vlv_disable_plane;
> +			intel_plane->update_colorkey = vlv_update_colorkey;
> +			intel_plane->get_colorkey = vlv_get_colorkey;
> +
> +			plane_formats = vlv_plane_formats;
> +			num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
> +		}

A bit odd to first init everything with ivb values and then overwrite
with vlv values.

>  		break;
>  
>  	default:
> -		kfree(intel_plane);
> -		return -ENODEV;
> +		ret = -ENODEV;
> +		goto err_free;

Reworking the error paths seems to be an unrelated change. Maybe split it
to another patch if there's some merit in it.

>  	}
>  
>  	intel_plane->pipe = pipe;
> +	intel_plane->plane = plane;
>  	possible_crtcs = (1 << pipe);
>  	ret = drm_plane_init(dev, &intel_plane->base, possible_crtcs,
>  			     &intel_plane_funcs,
>  			     plane_formats, num_plane_formats,
>  			     false);
>  	if (ret)
> -		kfree(intel_plane);
> +		goto err_free;
>  
>  	return ret;
> +
> +err_free:
> +	kfree(intel_plane);
> +	return ret;
>  }
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 02/28] drm/i915: add sprite assertion function for VLV

[Ville Syrjälä]

On Fri, Mar 01, 2013 at 01:14:05PM -0800, Jesse Barnes wrote:
> Need to make sure sprites are disabled before shutting off a pipe.

But we don't actually turn them off anywhere, do we?

> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/intel_display.c |   20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 5baf850..794c23e5 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1275,6 +1275,25 @@ static void assert_planes_disabled(struct drm_i915_private *dev_priv,
>  	}
>  }
>  
> +static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
> +				    enum pipe pipe)
> +{
> +	int reg, i;
> +	u32 val;
> +
> +	if (!IS_VALLEYVIEW(dev_priv->dev))
> +		return;
> +
> +	/* Need to check both planes against the pipe */
> +	for (i = 0; i < dev_priv->num_plane; i++) {
> +		reg = SPCNTR(pipe, i);
> +		val = I915_READ(reg);
> +		WARN((val & SP_ENABLE),
> +		     "sprite %d assertion failure, should be off on pipe %c but is still active\n",
> +		     pipe * 2 + i, pipe_name(pipe));
> +	}
> +}
> +
>  static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
>  {
>  	u32 val;
> @@ -1859,6 +1878,7 @@ static void intel_disable_pipe(struct drm_i915_private *dev_priv,
>  	 * or we might hang the display.
>  	 */
>  	assert_planes_disabled(dev_priv, pipe);
> +	assert_sprites_disabled(dev_priv, pipe);
>  
>  	/* Don't disable pipe A or pipe A PLLs if needed */
>  	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 13/28] drm/i915: fix VLV limits and m/n/p calculations

[Ville Syrjälä]

On Fri, Mar 01, 2013 at 01:14:16PM -0800, Jesse Barnes wrote:
> For high res modes m n p calculation is fixed for VLV platform.
> 
> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> Signed-off-by: Pallavi G <pallavi.g@intel.com>
> Signed-off-by: Yogesh M <yogesh.mohan.marimuthu@intel.com>
> Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c |   31 +++++++++++++++++++++----------
>  1 file changed, 21 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 3b189fa..fd4a0d4 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -380,21 +380,21 @@ static const intel_limit_t intel_limits_vlv_dac = {
>  	.m1 = { .min = 2, .max = 3 },
>  	.m2 = { .min = 11, .max = 156 },
>  	.p = { .min = 10, .max = 30 },
> -	.p1 = { .min = 2, .max = 3 },
> +	.p1 = { .min = 1, .max = 3 },
>  	.p2 = { .dot_limit = 270000,
>  		.p2_slow = 2, .p2_fast = 20 },
>  	.find_pll = intel_vlv_find_best_pll,
>  };
>  
>  static const intel_limit_t intel_limits_vlv_hdmi = {
> -	.dot = { .min = 20000, .max = 165000 },
> -	.vco = { .min = 4000000, .max = 5994000},
> -	.n = { .min = 1, .max = 7 },
> +	.dot = { .min = 25000, .max = 180000 },
> +	.vco = { .min = 4040000, .max = 5960000 },
> +	.n = { .min = 1, .max = 5 },
>  	.m = { .min = 60, .max = 300 }, /* guess */
>  	.m1 = { .min = 2, .max = 3 },
> -	.m2 = { .min = 11, .max = 156 },
> +	.m2 = { .min = 15, .max = 149 },
>  	.p = { .min = 10, .max = 30 },
> -	.p1 = { .min = 2, .max = 3 },
> +	.p1 = { .min = 1, .max = 3 },
>  	.p2 = { .dot_limit = 270000,
>  		.p2_slow = 2, .p2_fast = 20 },
>  	.find_pll = intel_vlv_find_best_pll,
> @@ -408,7 +408,7 @@ static const intel_limit_t intel_limits_vlv_dp = {
>  	.m1 = { .min = 2, .max = 3 },
>  	.m2 = { .min = 11, .max = 156 },
>  	.p = { .min = 10, .max = 30 },
> -	.p1 = { .min = 2, .max = 3 },
> +	.p1 = { .min = 1, .max = 3 },
>  	.p2 = { .dot_limit = 270000,
>  		.p2_slow = 2, .p2_fast = 20 },
>  	.find_pll = intel_vlv_find_best_pll,
> @@ -809,10 +809,14 @@ intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
>  			int target, int refclk, intel_clock_t *match_clock,
>  			intel_clock_t *best_clock)
>  {
> +#define LONG_OVERFLOW 0x7FFFFFFF
> +#define DIFF_OVERFLOW (LONG_OVERFLOW/10000)
> +
>  	u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
>  	u32 m, n, fastclk;
>  	u32 updrate, minupdate, fracbits, p;
> -	unsigned long bestppm, ppm, absppm;
> +	long bestppm, ppm, absppm, ppmdiff, absppmdiff;
> +	unsigned long ulMult = 1;
>  	int dotclk, flag;
>  
>  	flag = 0;
> @@ -841,8 +845,15 @@ intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
>  					m = m1 * m2;
>  					vco = updrate * m;
>  					if (vco >= limit->vco.min && vco < limit->vco.max) {
> -						ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
> -						absppm = (ppm > 0) ? ppm : (-ppm);
> +						ppmdiff = ((100*vco)/p) - (100*fastclk);
> +						absppmdiff = (ppmdiff > 0) ? ppmdiff : (-ppmdiff);
> +						ulMult = 1;
> +						while (absppmdiff > DIFF_OVERFLOW) {
> +							absppmdiff /= 10;
> +							ulMult *= 10;
> +						}
> +						absppm = ((absppmdiff*10000)/fastclk)*ulMult;
> +

This seems to expect long to be >32 bits. If it needs 64bit math it
should use proper sized types, and of course the division needs to
use something like div_s64().

Also it should use abs()/abs64() instead of the open-coded versions.
That would also allow getting rid of some of these temporary variables.

>  						if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
>  							bestppm = 0;
>  							flag = 1;
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 10/28] drm/i915: VLV has force wake

[Daniel Vetter]

On Fri, Mar 01, 2013 at 01:14:13PM -0800, Jesse Barnes wrote:
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

Commit message is a bit sparse given that the only thing this does is
enable the forcewake duct-tape for more coherent seqno waiting. I've
pimped the commit message a bit.

Applied, thanks.
-Daniel
> ---
>  drivers/gpu/drm/i915/i915_drv.c |    2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index dba68c3..af19dca 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -275,6 +275,7 @@ static const struct intel_device_info intel_valleyview_m_info = {
>  	.has_blt_ring = 1,
>  	.is_valleyview = 1,
>  	.display_mmio_offset = VLV_DISPLAY_BASE,
> +	.has_force_wake = 1,
>  };
>  
>  static const struct intel_device_info intel_valleyview_d_info = {
> @@ -285,6 +286,7 @@ static const struct intel_device_info intel_valleyview_d_info = {
>  	.has_blt_ring = 1,
>  	.is_valleyview = 1,
>  	.display_mmio_offset = VLV_DISPLAY_BASE,
> +	.has_force_wake = 1,
>  };
>  
>  static const struct intel_device_info intel_haswell_d_info = {
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 12/28] drm/i915: add more clock gating for VLV, allow force wake at init

[Daniel Vetter]

On Fri, Mar 01, 2013 at 01:14:15PM -0800, Jesse Barnes wrote:
> From: Ben Widawsky <ben@bwidawsk.net>
> 
> Disable all Gunit clock gating and make set the "allow force wake" bit.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

Can we make the in-code comments here a bit louder to explain that this is
pre-production w/a stuff which should be killed eventually?
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_gem.c |    4 ++++
>  drivers/gpu/drm/i915/i915_reg.h |    1 +
>  drivers/gpu/drm/i915/intel_pm.c |   10 +++++++++-
>  3 files changed, 14 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 8413ffc..dd67698 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4010,7 +4010,11 @@ int i915_gem_init(struct drm_device *dev)
>  	int ret;
>  
>  	mutex_lock(&dev->struct_mutex);
> +
> +	/* VLVA0 (potential hack), BIOS isn't actually waking us */
> +	I915_WRITE(VLV_GTLC_WAKE_CTRL, 1);
>  	i915_gem_init_global_gtt(dev);
> +
>  	ret = i915_gem_init_hw(dev);
>  	mutex_unlock(&dev->struct_mutex);
>  	if (ret) {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4c45e91..ecf5f30 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4276,6 +4276,7 @@
>  #define  FORCEWAKE_ACK_VLV			0x1300b4
>  #define  FORCEWAKE_ACK_HSW			0x130044
>  #define  FORCEWAKE_ACK				0x130090
> +#define  VLV_GTLC_WAKE_CTRL			0x130090
>  #define  FORCEWAKE_MT				0xa188 /* multi-threaded */
>  #define   FORCEWAKE_KERNEL			0x1
>  #define   FORCEWAKE_USER			0x2
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d6d028a..7de8cec 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3991,7 +3991,15 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>  	 * Disable clock gating on th GCFG unit to prevent a delay
>  	 * in the reporting of vblank events.
>  	 */
> -	I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
> +	/* VLVA0 HACK */
> +	I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
> +	I915_WRITE(0x9400, 0xffffffff);
> +	I915_WRITE(0x9404, 0xffffffff);
> +	I915_WRITE(0x9408, 0xffffffff);
> +	I915_WRITE(0x940c, 0xffffffff);
> +	I915_WRITE(0x9410, 0xffffffff);
> +	I915_WRITE(0x9414, 0xffffffff);
> +	I915_WRITE(0x9418, 0xffffffff);
>  }
>  
>  static void g4x_init_clock_gating(struct drm_device *dev)
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 14/28] drm/i915: disable watermarks on VLV, pondicherry takes care of this

[Daniel Vetter]

On Fri, Mar 01, 2013 at 01:14:17PM -0800, Jesse Barnes wrote:
> For current usage, not needed.
> 
> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c |    4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 7de8cec..b8f5a17 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4211,7 +4211,9 @@ void intel_init_pm(struct drm_device *dev)
>  		} else
>  			dev_priv->display.update_wm = NULL;
>  	} else if (IS_VALLEYVIEW(dev)) {
> -		dev_priv->display.update_wm = valleyview_update_wm;
> +//		dev_priv->display.update_wm = valleyview_update_wm;
> +		dev_priv->display.update_wm = NULL;
> +//		dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;

Either kill this all (it's kzalloced so no need for NULL assignments) or
add a giant comment explaining what's going on. Adding commented-out code
without comment is strange ...
-Daniel

>  		dev_priv->display.init_clock_gating =
>  			valleyview_init_clock_gating;
>  	} else if (IS_PINEVIEW(dev)) {
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 20/28] drm/i915: don't enumerate VGA on VLV

[Daniel Vetter]

On Fri, Mar 01, 2013 at 01:14:23PM -0800, Jesse Barnes wrote:
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/intel_display.c |    3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index fd4a0d4..60397e8 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -8503,7 +8503,8 @@ static void intel_setup_outputs(struct drm_device *dev)
>  		I915_WRITE(PFIT_CONTROL, 0);
>  	}
>  
> -	if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
> +	if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)) &&
> +	    !IS_VALLEYVIEW(dev))

If HAS_DDI is true on baytrail, that's a bug in the HAS_DDI macro. And I'd
like that to be a feature-flag in the intel_infor struct anyway, iirc
Damien is volunteered.
-Daniel
>  		intel_crt_init(dev);
>  
>  	if (HAS_DDI(dev)) {
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 20/28] drm/i915: don't enumerate VGA on VLV

[Ville Syrjälä]

On Fri, Mar 01, 2013 at 01:14:23PM -0800, Jesse Barnes wrote:
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/intel_display.c |    3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index fd4a0d4..60397e8 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -8503,7 +8503,8 @@ static void intel_setup_outputs(struct drm_device *dev)
>  		I915_WRITE(PFIT_CONTROL, 0);
>  	}
>  
> -	if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
> +	if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)) &&
> +	    !IS_VALLEYVIEW(dev))
>  		intel_crt_init(dev);

I was under the impression that VLV still has this. Was I mistaken?

>  	if (HAS_DDI(dev)) {
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 23/28] drm/i915: use VLV DIP routines on VLV

[Daniel Vetter]

On Fri, Mar 01, 2013 at 01:14:26PM -0800, Jesse Barnes wrote:
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/intel_hdmi.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index fcb36c6..9982b7f 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1038,7 +1038,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
>  		BUG();
>  	}
>  
> -	if (!HAS_PCH_SPLIT(dev)) {
> +	if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) {

We have an IS_VLV block right below ... move it up? Or just rework the if
ladder here to not use negation, that's imo easier to parse, too.
-Daniel

>  		intel_hdmi->write_infoframe = g4x_write_infoframe;
>  		intel_hdmi->set_infoframes = g4x_set_infoframes;
>  	} else if (IS_VALLEYVIEW(dev)) {
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 24/28] drm/i915: export intel_dpio_write for use in intel_dp.c

[Daniel Vetter]

On Fri, Mar 01, 2013 at 01:14:27PM -0800, Jesse Barnes wrote:
> We need it for some DP training related bits.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

Maintainer-bikeshed: Imo having such unstatic-only patches doesn't really
add value, I prefer it squashed with the new use-site (with a small
comment in the commit message maybe). True bikeshed, so will merge anyway.
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_display.c |    3 +--
>  drivers/gpu/drm/i915/intel_drv.h     |    2 ++
>  2 files changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 2559435..022349b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -434,8 +434,7 @@ u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
>  	return I915_READ(DPIO_DATA);
>  }
>  
> -static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
> -			     u32 val)
> +void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
>  {
>  	WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
>  
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 494037d..03fdfbd 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -661,6 +661,8 @@ extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
>  				     struct drm_file *file_priv);
>  
>  extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg);
> +extern void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
> +			     u32 val);
>  
>  /* Power-related functions, located in intel_pm.c */
>  extern void intel_init_pm(struct drm_device *dev);
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 27/28] drm/i915/dp: don't use ILK paths on VLV

[Daniel Vetter]

On Fri, Mar 01, 2013 at 01:14:30PM -0800, Jesse Barnes wrote:
> Fix up a couple of places where we messed with PCH bits on VLV.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

We might want ot untangle the cpu vs. pch dp port question from the dp vs.
edp question eventually. Anyway, I've merged this patch here to dinq.
-Daniel
> ---
>  drivers/gpu/drm/i915/intel_dp.c |    4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 03340fd..05e1000 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -976,7 +976,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
>  		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
>  	}
>  
> -	if (is_cpu_edp(intel_dp))
> +	if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
>  		ironlake_set_pll_edp(crtc, adjusted_mode->clock);
>  }
>  
> @@ -1373,7 +1373,7 @@ static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
>  	if (!(tmp & DP_PORT_EN))
>  		return false;
>  
> -	if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
> +	if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
>  		*pipe = PORT_TO_PIPE_CPT(tmp);
>  	} else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
>  		*pipe = PORT_TO_PIPE(tmp);
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 28/28] drm/i915/dp: add pre-PCH eDP checking to DP detect for VLV

[Daniel Vetter]

On Fri, Mar 01, 2013 at 01:14:31PM -0800, Jesse Barnes wrote:
> Allows us to detect eDP panels that may not have the hotplug pin wired up.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

Historically the lid status is horribly broken which is why it's disabled
by default. What changed to now enable it unconditionally? Is this a
requirement on vlv?
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_dp.c |   10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 05e1000..c127cb7 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2413,6 +2413,16 @@ g4x_dp_detect(struct intel_dp *intel_dp)
>  	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>  	uint32_t bit;
>  
> +	/* Can't disconnect eDP, but you can close the lid... */
> +	if (is_edp(intel_dp)) {
> +		enum drm_connector_status status;
> +
> +		status = intel_panel_detect(dev);
> +		if (status == connector_status_unknown)
> +			status = connector_status_connected;
> +		return status;
> +	}
> +
>  	switch (intel_dig_port->port) {
>  	case PORT_B:
>  		bit = PORTB_HOTPLUG_LIVE_STATUS;
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 14/28] drm/i915: disable watermarks on VLV, pondicherry takes care of this

[Ville Syrjälä]

On Wed, Mar 06, 2013 at 07:56:33PM +0100, Daniel Vetter wrote:
> On Fri, Mar 01, 2013 at 01:14:17PM -0800, Jesse Barnes wrote:
> > For current usage, not needed.
> > 
> > Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c |    4 +++-
> >  1 file changed, 3 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 7de8cec..b8f5a17 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -4211,7 +4211,9 @@ void intel_init_pm(struct drm_device *dev)
> >  		} else
> >  			dev_priv->display.update_wm = NULL;
> >  	} else if (IS_VALLEYVIEW(dev)) {
> > -		dev_priv->display.update_wm = valleyview_update_wm;
> > +//		dev_priv->display.update_wm = valleyview_update_wm;
> > +		dev_priv->display.update_wm = NULL;
> > +//		dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
> 
> Either kill this all (it's kzalloced so no need for NULL assignments) or
> add a giant comment explaining what's going on. Adding commented-out code
> without comment is strange ...

The whole premise that pondicherry magically handles things is a bit
weird too. I suppose all it really means is that the default WMs were
high enough to avoid underruns for the guys who tested this.

Actually wasn't there a comment on an earlier version of this patch
that there was a div by zero or something, and that's the real reason
for this patch?

> -Daniel
> 
> >  		dev_priv->display.init_clock_gating =
> >  			valleyview_init_clock_gating;
> >  	} else if (IS_PINEVIEW(dev)) {
> > -- 
> > 1.7.9.5
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 20/28] drm/i915: don't enumerate VGA on VLV

[Jesse Barnes]

On Wed, 6 Mar 2013 21:00:11 +0200
Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:

> On Fri, Mar 01, 2013 at 01:14:23PM -0800, Jesse Barnes wrote:
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c |    3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index fd4a0d4..60397e8 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -8503,7 +8503,8 @@ static void intel_setup_outputs(struct drm_device *dev)
> >  		I915_WRITE(PFIT_CONTROL, 0);
> >  	}
> >  
> > -	if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
> > +	if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)) &&
> > +	    !IS_VALLEYVIEW(dev))
> >  		intel_crt_init(dev);
> 
> I was under the impression that VLV still has this. Was I mistaken?

Not exposed anymore I think.  And yeah this can be dropped since the
DDI check should dtrt.

-- 
Jesse Barnes, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 23/28] drm/i915: use VLV DIP routines on VLV

[Jesse Barnes]

On Wed, 6 Mar 2013 20:00:37 +0100
Daniel Vetter <daniel@ffwll.ch> wrote:

> On Fri, Mar 01, 2013 at 01:14:26PM -0800, Jesse Barnes wrote:
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > ---
> >  drivers/gpu/drm/i915/intel_hdmi.c |    2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> > index fcb36c6..9982b7f 100644
> > --- a/drivers/gpu/drm/i915/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> > @@ -1038,7 +1038,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
> >  		BUG();
> >  	}
> >  
> > -	if (!HAS_PCH_SPLIT(dev)) {
> > +	if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) {
> 
> We have an IS_VLV block right below ... move it up? Or just rework the if
> ladder here to not use negation, that's imo easier to parse, too.
> -Daniel
> 
> >  		intel_hdmi->write_infoframe = g4x_write_infoframe;
> >  		intel_hdmi->set_infoframes = g4x_set_infoframes;
> >  	} else if (IS_VALLEYVIEW(dev)) {
> > -- 

Yeah that would be better.

-- 
Jesse Barnes, Intel Open Source Technology Center

Re: [PATCH 24/28] drm/i915: export intel_dpio_write for use in intel_dp.c

[Jesse Barnes]

On Wed, 6 Mar 2013 20:02:43 +0100
Daniel Vetter <daniel@ffwll.ch> wrote:

> On Fri, Mar 01, 2013 at 01:14:27PM -0800, Jesse Barnes wrote:
> > We need it for some DP training related bits.
> > 
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> 
> Maintainer-bikeshed: Imo having such unstatic-only patches doesn't really
> add value, I prefer it squashed with the new use-site (with a small
> comment in the commit message maybe). True bikeshed, so will merge anyway.

Yeah feel free to squash into the DP vswing/preemphasis patch, that's
what needs it.  Having it split out helped me with merge & rebase along
the way but it's definitely not necessary...

-- 
Jesse Barnes, Intel Open Source Technology Center

Re: [PATCH 20/28] drm/i915: don't enumerate VGA on VLV

[Ville Syrjälä]

On Wed, Mar 06, 2013 at 11:09:08AM -0800, Jesse Barnes wrote:
> On Wed, 6 Mar 2013 21:00:11 +0200
> Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> 
> > On Fri, Mar 01, 2013 at 01:14:23PM -0800, Jesse Barnes wrote:
> > > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > > ---
> > >  drivers/gpu/drm/i915/intel_display.c |    3 ++-
> > >  1 file changed, 2 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > > index fd4a0d4..60397e8 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -8503,7 +8503,8 @@ static void intel_setup_outputs(struct drm_device *dev)
> > >  		I915_WRITE(PFIT_CONTROL, 0);
> > >  	}
> > >  
> > > -	if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
> > > +	if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)) &&
> > > +	    !IS_VALLEYVIEW(dev))
> > >  		intel_crt_init(dev);
> > 
> > I was under the impression that VLV still has this. Was I mistaken?
> 
> Not exposed anymore I think.  And yeah this can be dropped since the
> DDI check should dtrt.

It's testing for !HAS_DDI() which should equal true for VLV.

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 14/28] drm/i915: disable watermarks on VLV, pondicherry takes care of this

[Daniel Vetter]

On Wed, Mar 06, 2013 at 09:09:06PM +0200, Ville Syrjälä wrote:
> On Wed, Mar 06, 2013 at 07:56:33PM +0100, Daniel Vetter wrote:
> > On Fri, Mar 01, 2013 at 01:14:17PM -0800, Jesse Barnes wrote:
> > > For current usage, not needed.
> > > 
> > > Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_pm.c |    4 +++-
> > >  1 file changed, 3 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > index 7de8cec..b8f5a17 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -4211,7 +4211,9 @@ void intel_init_pm(struct drm_device *dev)
> > >  		} else
> > >  			dev_priv->display.update_wm = NULL;
> > >  	} else if (IS_VALLEYVIEW(dev)) {
> > > -		dev_priv->display.update_wm = valleyview_update_wm;
> > > +//		dev_priv->display.update_wm = valleyview_update_wm;
> > > +		dev_priv->display.update_wm = NULL;
> > > +//		dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
> > 
> > Either kill this all (it's kzalloced so no need for NULL assignments) or
> > add a giant comment explaining what's going on. Adding commented-out code
> > without comment is strange ...
> 
> The whole premise that pondicherry magically handles things is a bit
> weird too. I suppose all it really means is that the default WMs were
> high enough to avoid underruns for the guys who tested this.
> 
> Actually wasn't there a comment on an earlier version of this patch
> that there was a div by zero or something, and that's the real reason
> for this patch?

Fyi the patch which fixed div-by-zero on other platforms is:

commit 3490ea5de6ac4af309c3df8a26a5cca61306334c
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Mon Jan 7 10:11:40 2013 +0000

    drm/i915: Treat crtc->mode.clock == 0 as disabled

Cheers, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 14/28] drm/i915: disable watermarks on VLV, pondicherry takes care of this

[Ville Syrjälä]

On Wed, Mar 06, 2013 at 08:14:54PM +0100, Daniel Vetter wrote:
> On Wed, Mar 06, 2013 at 09:09:06PM +0200, Ville Syrjälä wrote:
> > On Wed, Mar 06, 2013 at 07:56:33PM +0100, Daniel Vetter wrote:
> > > On Fri, Mar 01, 2013 at 01:14:17PM -0800, Jesse Barnes wrote:
> > > > For current usage, not needed.
> > > > 
> > > > Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/intel_pm.c |    4 +++-
> > > >  1 file changed, 3 insertions(+), 1 deletion(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > index 7de8cec..b8f5a17 100644
> > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > @@ -4211,7 +4211,9 @@ void intel_init_pm(struct drm_device *dev)
> > > >  		} else
> > > >  			dev_priv->display.update_wm = NULL;
> > > >  	} else if (IS_VALLEYVIEW(dev)) {
> > > > -		dev_priv->display.update_wm = valleyview_update_wm;
> > > > +//		dev_priv->display.update_wm = valleyview_update_wm;
> > > > +		dev_priv->display.update_wm = NULL;
> > > > +//		dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
> > > 
> > > Either kill this all (it's kzalloced so no need for NULL assignments) or
> > > add a giant comment explaining what's going on. Adding commented-out code
> > > without comment is strange ...
> > 
> > The whole premise that pondicherry magically handles things is a bit
> > weird too. I suppose all it really means is that the default WMs were
> > high enough to avoid underruns for the guys who tested this.
> > 
> > Actually wasn't there a comment on an earlier version of this patch
> > that there was a div by zero or something, and that's the real reason
> > for this patch?
> 
> Fyi the patch which fixed div-by-zero on other platforms is:
> 
> commit 3490ea5de6ac4af309c3df8a26a5cca61306334c
> Author: Chris Wilson <chris@chris-wilson.co.uk>
> Date:   Mon Jan 7 10:11:40 2013 +0000
> 
>     drm/i915: Treat crtc->mode.clock == 0 as disabled

Now I actually remember that Jani did try reverting this patch in his
tree, and didn't get any div by zeros. So we were a bit confused about
the patch at the time. If he had that fix in his tree, then that would
explain it. Maybe this patch can be dropped then?

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 14/28] drm/i915: disable watermarks on VLV, pondicherry takes care of this

[Daniel Vetter]

On Wed, Mar 06, 2013 at 09:19:27PM +0200, Ville Syrjälä wrote:
> On Wed, Mar 06, 2013 at 08:14:54PM +0100, Daniel Vetter wrote:
> > On Wed, Mar 06, 2013 at 09:09:06PM +0200, Ville Syrjälä wrote:
> > > On Wed, Mar 06, 2013 at 07:56:33PM +0100, Daniel Vetter wrote:
> > > > On Fri, Mar 01, 2013 at 01:14:17PM -0800, Jesse Barnes wrote:
> > > > > For current usage, not needed.
> > > > > 
> > > > > Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> > > > > ---
> > > > >  drivers/gpu/drm/i915/intel_pm.c |    4 +++-
> > > > >  1 file changed, 3 insertions(+), 1 deletion(-)
> > > > > 
> > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > > index 7de8cec..b8f5a17 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > > @@ -4211,7 +4211,9 @@ void intel_init_pm(struct drm_device *dev)
> > > > >  		} else
> > > > >  			dev_priv->display.update_wm = NULL;
> > > > >  	} else if (IS_VALLEYVIEW(dev)) {
> > > > > -		dev_priv->display.update_wm = valleyview_update_wm;
> > > > > +//		dev_priv->display.update_wm = valleyview_update_wm;
> > > > > +		dev_priv->display.update_wm = NULL;
> > > > > +//		dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
> > > > 
> > > > Either kill this all (it's kzalloced so no need for NULL assignments) or
> > > > add a giant comment explaining what's going on. Adding commented-out code
> > > > without comment is strange ...
> > > 
> > > The whole premise that pondicherry magically handles things is a bit
> > > weird too. I suppose all it really means is that the default WMs were
> > > high enough to avoid underruns for the guys who tested this.
> > > 
> > > Actually wasn't there a comment on an earlier version of this patch
> > > that there was a div by zero or something, and that's the real reason
> > > for this patch?
> > 
> > Fyi the patch which fixed div-by-zero on other platforms is:
> > 
> > commit 3490ea5de6ac4af309c3df8a26a5cca61306334c
> > Author: Chris Wilson <chris@chris-wilson.co.uk>
> > Date:   Mon Jan 7 10:11:40 2013 +0000
> > 
> >     drm/i915: Treat crtc->mode.clock == 0 as disabled
> 
> Now I actually remember that Jani did try reverting this patch in his
> tree, and didn't get any div by zeros. So we were a bit confused about
> the patch at the time. If he had that fix in his tree, then that would
> explain it. Maybe this patch can be dropped then?

This is a fallout from the reworked modeset code. Since we now read out
the bios hw state, if the new state leaves pipe B running, but enables
pipe A (happens only when the bios enables pipe B) we try to recompute
watermarks for pipe B, but that mode is 0. Hence boom.

This patch can be killed once the hw state readout is properly extended to
cover the required information (i.e. we need to move all the wm code to
only look at pipe_config and ensure that all the values in there are
correct).

Once booted, you can't hit this any more.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 28/28] drm/i915/dp: add pre-PCH eDP checking to DP detect for VLV

[Jesse Barnes]

On Wed, 6 Mar 2013 20:05:59 +0100
Daniel Vetter <daniel@ffwll.ch> wrote:

> On Fri, Mar 01, 2013 at 01:14:31PM -0800, Jesse Barnes wrote:
> > Allows us to detect eDP panels that may not have the hotplug pin wired up.
> > 
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> 
> Historically the lid status is horribly broken which is why it's disabled
> by default. What changed to now enable it unconditionally? Is this a
> requirement on vlv?
> -Daniel
> 
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c |   10 ++++++++++
> >  1 file changed, 10 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index 05e1000..c127cb7 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -2413,6 +2413,16 @@ g4x_dp_detect(struct intel_dp *intel_dp)
> >  	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> >  	uint32_t bit;
> >  
> > +	/* Can't disconnect eDP, but you can close the lid... */
> > +	if (is_edp(intel_dp)) {
> > +		enum drm_connector_status status;
> > +
> > +		status = intel_panel_detect(dev);
> > +		if (status == connector_status_unknown)
> > +			status = connector_status_connected;
> > +		return status;
> > +	}
> > +

Well this doesn't touch the panel_detect() stuff at all, where we have
the hacks to avoid using _LID...

-- 
Jesse Barnes, Intel Open Source Technology Center

Re: [PATCH 28/28] drm/i915/dp: add pre-PCH eDP checking to DP detect for VLV

[Daniel Vetter]

On Wed, Mar 6, 2013 at 9:55 PM, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> On Wed, 6 Mar 2013 20:05:59 +0100
> Daniel Vetter <daniel@ffwll.ch> wrote:
>
>> On Fri, Mar 01, 2013 at 01:14:31PM -0800, Jesse Barnes wrote:
>> > Allows us to detect eDP panels that may not have the hotplug pin wired up.
>> >
>> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
>>
>> Historically the lid status is horribly broken which is why it's disabled
>> by default. What changed to now enable it unconditionally? Is this a
>> requirement on vlv?
>> -Daniel
>>
>> > ---
>> >  drivers/gpu/drm/i915/intel_dp.c |   10 ++++++++++
>> >  1 file changed, 10 insertions(+)
>> >
>> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> > index 05e1000..c127cb7 100644
>> > --- a/drivers/gpu/drm/i915/intel_dp.c
>> > +++ b/drivers/gpu/drm/i915/intel_dp.c
>> > @@ -2413,6 +2413,16 @@ g4x_dp_detect(struct intel_dp *intel_dp)
>> >     struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>> >     uint32_t bit;
>> >
>> > +   /* Can't disconnect eDP, but you can close the lid... */
>> > +   if (is_edp(intel_dp)) {
>> > +           enum drm_connector_status status;
>> > +
>> > +           status = intel_panel_detect(dev);
>> > +           if (status == connector_status_unknown)
>> > +                   status = connector_status_connected;
>> > +           return status;
>> > +   }
>> > +
>
> Well this doesn't touch the panel_detect() stuff at all, where we have
> the hacks to avoid using _LID...

Oh right, patch looks good to me now ;-) Merget to dinq, thanks.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 14/28] drm/i915: disable watermarks on VLV, pondicherry takes care of this

[Jesse Barnes]

On Wed, 6 Mar 2013 20:32:22 +0100
Daniel Vetter <daniel@ffwll.ch> wrote:

> On Wed, Mar 06, 2013 at 09:19:27PM +0200, Ville Syrjälä wrote:
> > On Wed, Mar 06, 2013 at 08:14:54PM +0100, Daniel Vetter wrote:
> > > On Wed, Mar 06, 2013 at 09:09:06PM +0200, Ville Syrjälä wrote:
> > > > On Wed, Mar 06, 2013 at 07:56:33PM +0100, Daniel Vetter wrote:
> > > > > On Fri, Mar 01, 2013 at 01:14:17PM -0800, Jesse Barnes wrote:
> > > > > > For current usage, not needed.
> > > > > > 
> > > > > > Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> > > > > > ---
> > > > > >  drivers/gpu/drm/i915/intel_pm.c |    4 +++-
> > > > > >  1 file changed, 3 insertions(+), 1 deletion(-)
> > > > > > 
> > > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > index 7de8cec..b8f5a17 100644
> > > > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > @@ -4211,7 +4211,9 @@ void intel_init_pm(struct drm_device *dev)
> > > > > >  		} else
> > > > > >  			dev_priv->display.update_wm = NULL;
> > > > > >  	} else if (IS_VALLEYVIEW(dev)) {
> > > > > > -		dev_priv->display.update_wm = valleyview_update_wm;
> > > > > > +//		dev_priv->display.update_wm = valleyview_update_wm;
> > > > > > +		dev_priv->display.update_wm = NULL;
> > > > > > +//		dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
> > > > > 
> > > > > Either kill this all (it's kzalloced so no need for NULL assignments) or
> > > > > add a giant comment explaining what's going on. Adding commented-out code
> > > > > without comment is strange ...
> > > > 
> > > > The whole premise that pondicherry magically handles things is a bit
> > > > weird too. I suppose all it really means is that the default WMs were
> > > > high enough to avoid underruns for the guys who tested this.
> > > > 
> > > > Actually wasn't there a comment on an earlier version of this patch
> > > > that there was a div by zero or something, and that's the real reason
> > > > for this patch?
> > > 
> > > Fyi the patch which fixed div-by-zero on other platforms is:
> > > 
> > > commit 3490ea5de6ac4af309c3df8a26a5cca61306334c
> > > Author: Chris Wilson <chris@chris-wilson.co.uk>
> > > Date:   Mon Jan 7 10:11:40 2013 +0000
> > > 
> > >     drm/i915: Treat crtc->mode.clock == 0 as disabled
> > 
> > Now I actually remember that Jani did try reverting this patch in his
> > tree, and didn't get any div by zeros. So we were a bit confused about
> > the patch at the time. If he had that fix in his tree, then that would
> > explain it. Maybe this patch can be dropped then?
> 
> This is a fallout from the reworked modeset code. Since we now read out
> the bios hw state, if the new state leaves pipe B running, but enables
> pipe A (happens only when the bios enables pipe B) we try to recompute
> watermarks for pipe B, but that mode is 0. Hence boom.
> 
> This patch can be killed once the hw state readout is properly extended to
> cover the required information (i.e. we need to move all the wm code to
> only look at pipe_config and ensure that all the values in there are
> correct).
> 
> Once booted, you can't hit this any more.

I don't think this patch is necessary anymore... just tested and things
work fine w/o so I'll drop.

-- 
Jesse Barnes, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 02/28] drm/i915: add sprite assertion function for VLV

[Jesse Barnes]

On Mon, 4 Mar 2013 20:29:49 +0200
Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:

> On Fri, Mar 01, 2013 at 01:14:05PM -0800, Jesse Barnes wrote:
> > Need to make sure sprites are disabled before shutting off a pipe.
> 
> But we don't actually turn them off anywhere, do we?

We do at unload time right?  But this will catch if we leave them on at
mode set or dpms time, so we'll need to fix that up for sure.

-- 
Jesse Barnes, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx