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* [PATCH 1/3] drm/i915: Add ECOBITS_SNB_BIT
@ 2013-04-04 12:13 ville.syrjala
  2013-04-04 12:13 ` [PATCH 2/3] drm/i915: Set GAC_ECO_BITS register on Gen7+ ville.syrjala
                   ` (2 more replies)
  0 siblings, 3 replies; 5+ messages in thread
From: ville.syrjala @ 2013-04-04 12:13 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

GAC_ECO_BITS has a bit similar to GAM_ECOCHK's ECOCHK_SNB_BIT. Add
the define, and enable it on SNB.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 3 ++-
 drivers/gpu/drm/i915/i915_reg.h     | 1 +
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 24a23b3..593137b 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -312,7 +312,8 @@ void i915_gem_init_ppgtt(struct drm_device *dev)
 		uint32_t ecochk, gab_ctl, ecobits;
 
 		ecobits = I915_READ(GAC_ECO_BITS);
-		I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
+		I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
+					 ECOBITS_PPGTT_CACHE64B);
 
 		gab_ctl = I915_READ(GAB_CTL);
 		I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 058686c..4b8fd4d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -127,6 +127,7 @@
 #define   ECOCHK_PPGTT_CACHE4B		(0x0<<3)
 
 #define GAC_ECO_BITS			0x14090
+#define   ECOBITS_SNB_BIT		(1<<13)
 #define   ECOBITS_PPGTT_CACHE64B	(3<<8)
 #define   ECOBITS_PPGTT_CACHE4B		(0<<8)
 
-- 
1.8.1.5

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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 5+ messages in thread
* [PATCH 2/3] drm/i915: Set GAC_ECO_BITS register on Gen7+
  2013-04-04 12:13 [PATCH 1/3] drm/i915: Add ECOBITS_SNB_BIT ville.syrjala
@ 2013-04-04 12:13 ` ville.syrjala
  2013-04-04 12:13 ` [PATCH 3/3] drm/i915: Configure GAM_ECOCHK appropriatly for Gen7 ville.syrjala
  2013-04-09 16:23 ` [PATCH 1/3] drm/i915: Add ECOBITS_SNB_BIT Imre Deak
  2 siblings, 0 replies; 5+ messages in thread
From: ville.syrjala @ 2013-04-04 12:13 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

According to BSpec GAC_ECO_BITS register exists on Gen7 platforms as
well. Configure it accordingly.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 593137b..a851362 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -323,6 +323,11 @@ void i915_gem_init_ppgtt(struct drm_device *dev)
 				       ECOCHK_PPGTT_CACHE64B);
 		I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 	} else if (INTEL_INFO(dev)->gen >= 7) {
+		uint32_t ecobits;
+
+		ecobits = I915_READ(GAC_ECO_BITS);
+		I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
+
 		I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B);
 		/* GFX_MODE is per-ring on gen7+ */
 	}
-- 
1.8.1.5

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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 5+ messages in thread
* [PATCH 3/3] drm/i915: Configure GAM_ECOCHK appropriatly for Gen7
  2013-04-04 12:13 [PATCH 1/3] drm/i915: Add ECOBITS_SNB_BIT ville.syrjala
  2013-04-04 12:13 ` [PATCH 2/3] drm/i915: Set GAC_ECO_BITS register on Gen7+ ville.syrjala
@ 2013-04-04 12:13 ` ville.syrjala
  2013-04-09 16:23 ` [PATCH 1/3] drm/i915: Add ECOBITS_SNB_BIT Imre Deak
  2 siblings, 0 replies; 5+ messages in thread
From: ville.syrjala @ 2013-04-04 12:13 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

IVB and HSW use different encodings for the PPGTT cacheability bits in
the GAM_ECOCHK register.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 11 +++++++++--
 drivers/gpu/drm/i915/i915_reg.h     |  5 +++++
 2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index a851362..4d86fe4 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -323,12 +323,19 @@ void i915_gem_init_ppgtt(struct drm_device *dev)
 				       ECOCHK_PPGTT_CACHE64B);
 		I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 	} else if (INTEL_INFO(dev)->gen >= 7) {
-		uint32_t ecobits;
+		uint32_t ecochk, ecobits;
 
 		ecobits = I915_READ(GAC_ECO_BITS);
 		I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
 
-		I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B);
+		ecochk = I915_READ(GAM_ECOCHK);
+		if (IS_HASWELL(dev)) {
+			ecochk |= ECOCHK_PPGTT_WB_HSW;
+		} else {
+			ecochk |= ECOCHK_PPGTT_LLC_IVB;
+			ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
+		}
+		I915_WRITE(GAM_ECOCHK, ecochk);
 		/* GFX_MODE is per-ring on gen7+ */
 	}
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4b8fd4d..44051fa 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -125,6 +125,11 @@
 #define   HSW_ECOCHK_ARB_PRIO_SOL	(1<<6)
 #define   ECOCHK_PPGTT_CACHE64B		(0x3<<3)
 #define   ECOCHK_PPGTT_CACHE4B		(0x0<<3)
+#define   ECOCHK_PPGTT_GFDT_IVB		(0x1<<4)
+#define   ECOCHK_PPGTT_LLC_IVB		(0x1<<3)
+#define   ECOCHK_PPGTT_UC_HSW		(0x1<<3)
+#define   ECOCHK_PPGTT_WT_HSW		(0x2<<3)
+#define   ECOCHK_PPGTT_WB_HSW		(0x3<<3)
 
 #define GAC_ECO_BITS			0x14090
 #define   ECOBITS_SNB_BIT		(1<<13)
-- 
1.8.1.5

_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 5+ messages in thread
* Re: [PATCH 1/3] drm/i915: Add ECOBITS_SNB_BIT
  2013-04-04 12:13 [PATCH 1/3] drm/i915: Add ECOBITS_SNB_BIT ville.syrjala
  2013-04-04 12:13 ` [PATCH 2/3] drm/i915: Set GAC_ECO_BITS register on Gen7+ ville.syrjala
  2013-04-04 12:13 ` [PATCH 3/3] drm/i915: Configure GAM_ECOCHK appropriatly for Gen7 ville.syrjala
@ 2013-04-09 16:23 ` Imre Deak
  2013-04-09 17:01   ` Daniel Vetter
  2 siblings, 1 reply; 5+ messages in thread
From: Imre Deak @ 2013-04-09 16:23 UTC (permalink / raw)
  To: ville.syrjala; +Cc: intel-gfx

On Thu, 2013-04-04 at 15:13 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> GAC_ECO_BITS has a bit similar to GAM_ECOCHK's ECOCHK_SNB_BIT. Add
> the define, and enable it on SNB.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

On the series:
Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 3 ++-
>  drivers/gpu/drm/i915/i915_reg.h     | 1 +
>  2 files changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 24a23b3..593137b 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -312,7 +312,8 @@ void i915_gem_init_ppgtt(struct drm_device *dev)
>  		uint32_t ecochk, gab_ctl, ecobits;
>  
>  		ecobits = I915_READ(GAC_ECO_BITS);
> -		I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
> +		I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
> +					 ECOBITS_PPGTT_CACHE64B);
>  
>  		gab_ctl = I915_READ(GAB_CTL);
>  		I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 058686c..4b8fd4d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -127,6 +127,7 @@
>  #define   ECOCHK_PPGTT_CACHE4B		(0x0<<3)
>  
>  #define GAC_ECO_BITS			0x14090
> +#define   ECOBITS_SNB_BIT		(1<<13)
>  #define   ECOBITS_PPGTT_CACHE64B	(3<<8)
>  #define   ECOBITS_PPGTT_CACHE4B		(0<<8)
>  


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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 5+ messages in thread
* Re: [PATCH 1/3] drm/i915: Add ECOBITS_SNB_BIT
  2013-04-09 16:23 ` [PATCH 1/3] drm/i915: Add ECOBITS_SNB_BIT Imre Deak
@ 2013-04-09 17:01   ` Daniel Vetter
  0 siblings, 0 replies; 5+ messages in thread
From: Daniel Vetter @ 2013-04-09 17:01 UTC (permalink / raw)
  To: Imre Deak; +Cc: intel-gfx

On Tue, Apr 09, 2013 at 07:23:18PM +0300, Imre Deak wrote:
> On Thu, 2013-04-04 at 15:13 +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > GAC_ECO_BITS has a bit similar to GAM_ECOCHK's ECOCHK_SNB_BIT. Add
> > the define, and enable it on SNB.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> On the series:
> Reviewed-by: Imre Deak <imre.deak@intel.com>

Queued for -next, thanks for the patches.
-Daniel
> 
> > ---
> >  drivers/gpu/drm/i915/i915_gem_gtt.c | 3 ++-
> >  drivers/gpu/drm/i915/i915_reg.h     | 1 +
> >  2 files changed, 3 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > index 24a23b3..593137b 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > @@ -312,7 +312,8 @@ void i915_gem_init_ppgtt(struct drm_device *dev)
> >  		uint32_t ecochk, gab_ctl, ecobits;
> >  
> >  		ecobits = I915_READ(GAC_ECO_BITS);
> > -		I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
> > +		I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
> > +					 ECOBITS_PPGTT_CACHE64B);
> >  
> >  		gab_ctl = I915_READ(GAB_CTL);
> >  		I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 058686c..4b8fd4d 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -127,6 +127,7 @@
> >  #define   ECOCHK_PPGTT_CACHE4B		(0x0<<3)
> >  
> >  #define GAC_ECO_BITS			0x14090
> > +#define   ECOBITS_SNB_BIT		(1<<13)
> >  #define   ECOBITS_PPGTT_CACHE64B	(3<<8)
> >  #define   ECOBITS_PPGTT_CACHE4B		(0<<8)
> >  
> 
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

^ permalink raw reply	[flat|nested] 5+ messages in thread
end of thread, other threads:[~2013-04-09 16:58 UTC | newest]

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2013-04-04 12:13 [PATCH 1/3] drm/i915: Add ECOBITS_SNB_BIT ville.syrjala
2013-04-04 12:13 ` [PATCH 2/3] drm/i915: Set GAC_ECO_BITS register on Gen7+ ville.syrjala
2013-04-04 12:13 ` [PATCH 3/3] drm/i915: Configure GAM_ECOCHK appropriatly for Gen7 ville.syrjala
2013-04-09 16:23 ` [PATCH 1/3] drm/i915: Add ECOBITS_SNB_BIT Imre Deak
2013-04-09 17:01   ` Daniel Vetter

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