* [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601 @ 2020-01-22 23:40 Anusha Srivatsa 2020-01-23 4:36 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for " Patchwork 2020-01-23 17:50 ` [Intel-gfx] [PATCH] " Matt Roper 0 siblings, 2 replies; 4+ messages in thread From: Anusha Srivatsa @ 2020-01-22 23:40 UTC (permalink / raw) To: intel-gfx Disable Early Read and Src Swap by setting the bit 14 and 15 in the chicken register. BSpec: 46045,52890 HSDES: 1606931601 Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++ drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 5a7db279f702..53b448b61a5f 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -593,6 +593,11 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val, IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 : FF_MODE2_TDS_TIMER_MASK); + + /* Wa_1606931601:tgl */ + WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, + GEN11_EARLY_READ_SRC0_DISABLE_MASK); + } static void diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b93c4c18f05c..69a1c2227b91 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -9146,6 +9146,7 @@ enum { #define DOP_CLOCK_GATING_DISABLE (1 << 0) #define PUSH_CONSTANT_DEREF_DISABLE (1 << 8) #define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1) +#define GEN11_EARLY_READ_SRC0_DISABLE_MASK REG_GENMASK(15, 14) #define HSW_ROW_CHICKEN3 _MMIO(0xe49c) #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) -- 2.23.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 4+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/tgl: Implement Wa_1606931601 2020-01-22 23:40 [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601 Anusha Srivatsa @ 2020-01-23 4:36 ` Patchwork 2020-01-23 17:50 ` [Intel-gfx] [PATCH] " Matt Roper 1 sibling, 0 replies; 4+ messages in thread From: Patchwork @ 2020-01-23 4:36 UTC (permalink / raw) To: Anusha Srivatsa; +Cc: intel-gfx == Series Details == Series: drm/i915/tgl: Implement Wa_1606931601 URL : https://patchwork.freedesktop.org/series/72433/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7799 -> Patchwork_16223 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_16223 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_16223, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16223/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_16223: ### IGT changes ### #### Possible regressions #### * igt@gem_exec_parallel@contexts: - fi-byt-j1900: NOTRUN -> [FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16223/fi-byt-j1900/igt@gem_exec_parallel@contexts.html * igt@i915_selftest@live_workarounds: - fi-tgl-y: [PASS][2] -> [DMESG-FAIL][3] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-tgl-y/igt@i915_selftest@live_workarounds.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16223/fi-tgl-y/igt@i915_selftest@live_workarounds.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt@i915_selftest@live_workarounds: - {fi-tgl-u}: [PASS][4] -> [DMESG-FAIL][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-tgl-u/igt@i915_selftest@live_workarounds.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16223/fi-tgl-u/igt@i915_selftest@live_workarounds.html Known issues ------------ Here are the changes found in Patchwork_16223 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@i915_module_load@reload-with-fault-injection: - fi-skl-6700k2: [PASS][6] -> [INCOMPLETE][7] ([i915#671]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-skl-6700k2/igt@i915_module_load@reload-with-fault-injection.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16223/fi-skl-6700k2/igt@i915_module_load@reload-with-fault-injection.html * igt@i915_selftest@live_blt: - fi-hsw-4770: [PASS][8] -> [DMESG-FAIL][9] ([i915#553] / [i915#725]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-hsw-4770/igt@i915_selftest@live_blt.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16223/fi-hsw-4770/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_mman: - fi-bxt-dsi: [PASS][10] -> [DMESG-WARN][11] ([i915#889]) +23 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-bxt-dsi/igt@i915_selftest@live_mman.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16223/fi-bxt-dsi/igt@i915_selftest@live_mman.html * igt@i915_selftest@live_reset: - fi-bxt-dsi: [PASS][12] -> [DMESG-FAIL][13] ([i915#889]) +7 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-bxt-dsi/igt@i915_selftest@live_reset.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16223/fi-bxt-dsi/igt@i915_selftest@live_reset.html #### Possible fixes #### * igt@gem_close_race@basic-threads: - fi-byt-j1900: [INCOMPLETE][14] ([i915#45]) -> [PASS][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-byt-j1900/igt@gem_close_race@basic-threads.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16223/fi-byt-j1900/igt@gem_close_race@basic-threads.html * igt@i915_module_load@reload-with-fault-injection: - fi-cfl-guc: [INCOMPLETE][16] ([i915#505] / [i915#671]) -> [PASS][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-cfl-guc/igt@i915_module_load@reload-with-fault-injection.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16223/fi-cfl-guc/igt@i915_module_load@reload-with-fault-injection.html #### Warnings #### * igt@i915_selftest@live_blt: - fi-hsw-4770r: [DMESG-FAIL][18] ([i915#553] / [i915#725]) -> [DMESG-FAIL][19] ([i915#563]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-hsw-4770r/igt@i915_selftest@live_blt.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16223/fi-hsw-4770r/igt@i915_selftest@live_blt.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45 [i915#505]: https://gitlab.freedesktop.org/drm/intel/issues/505 [i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553 [i915#563]: https://gitlab.freedesktop.org/drm/intel/issues/563 [i915#671]: https://gitlab.freedesktop.org/drm/intel/issues/671 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 [i915#889]: https://gitlab.freedesktop.org/drm/intel/issues/889 Participating hosts (50 -> 45) ------------------------------ Additional (2): fi-glk-dsi fi-ilk-650 Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * CI: CI-20190529 -> None * Linux: CI_DRM_7799 -> Patchwork_16223 CI-20190529: 20190529 CI_DRM_7799: 0f8a46a25a7781ef6ede604c9cb50f82cfb5e960 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5377: 1e6cb3e75925cf623df04f78430ae9299632ec3f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16223: 57155b45b5763f4b0ecf37c4bca111565219a2fd @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 57155b45b576 drm/i915/tgl: Implement Wa_1606931601 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16223/index.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601 2020-01-22 23:40 [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601 Anusha Srivatsa 2020-01-23 4:36 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for " Patchwork @ 2020-01-23 17:50 ` Matt Roper 2020-01-24 19:36 ` Srivatsa, Anusha 1 sibling, 1 reply; 4+ messages in thread From: Matt Roper @ 2020-01-23 17:50 UTC (permalink / raw) To: Anusha Srivatsa; +Cc: intel-gfx On Wed, Jan 22, 2020 at 03:40:27PM -0800, Anusha Srivatsa wrote: > Disable Early Read and Src Swap by setting the bit 14 > and 15 in the chicken register. > > BSpec: 46045,52890 > HSDES: 1606931601 Hmm. The bspec WA description (which is very poorly written) only mentions setting bit 14, but comments in the HSD indicate that both 14 and 15 should be set. Do we have offline confirmation/clarification about which we should trust? If we do need to program both bits, it might still be a good idea to use two separate #define's for those rather than a single bitmask to make it more clear what we're doing and also to give us the option of just setting one or the other in case that winds up being necessary as a workaround for a different platform or future stepping. Matt > > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++ > drivers/gpu/drm/i915/i915_reg.h | 1 + > 2 files changed, 6 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 5a7db279f702..53b448b61a5f 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -593,6 +593,11 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, > wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val, > IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 : > FF_MODE2_TDS_TIMER_MASK); > + > + /* Wa_1606931601:tgl */ > + WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, > + GEN11_EARLY_READ_SRC0_DISABLE_MASK); > + > } > > static void > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index b93c4c18f05c..69a1c2227b91 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -9146,6 +9146,7 @@ enum { > #define DOP_CLOCK_GATING_DISABLE (1 << 0) > #define PUSH_CONSTANT_DEREF_DISABLE (1 << 8) > #define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1) > +#define GEN11_EARLY_READ_SRC0_DISABLE_MASK REG_GENMASK(15, 14) > > #define HSW_ROW_CHICKEN3 _MMIO(0xe49c) > #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) > -- > 2.23.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601 2020-01-23 17:50 ` [Intel-gfx] [PATCH] " Matt Roper @ 2020-01-24 19:36 ` Srivatsa, Anusha 0 siblings, 0 replies; 4+ messages in thread From: Srivatsa, Anusha @ 2020-01-24 19:36 UTC (permalink / raw) To: Roper, Matthew D; +Cc: intel-gfx > -----Original Message----- > From: Roper, Matthew D <matthew.d.roper@intel.com> > Sent: Thursday, January 23, 2020 9:50 AM > To: Srivatsa, Anusha <anusha.srivatsa@intel.com> > Cc: intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601 > > On Wed, Jan 22, 2020 at 03:40:27PM -0800, Anusha Srivatsa wrote: > > Disable Early Read and Src Swap by setting the bit 14 and 15 in the > > chicken register. > > > > BSpec: 46045,52890 > > HSDES: 1606931601 > > Hmm. The bspec WA description (which is very poorly written) only > mentions setting bit 14, but comments in the HSD indicate that both 14 and > 15 should be set. Do we have offline confirmation/clarification about which > we should trust? > > If we do need to program both bits, it might still be a good idea to use two > separate #define's for those rather than a single bitmask to make it more > clear what we're doing and also to give us the option of just setting one or > the other in case that winds up being necessary as a workaround for a > different platform or future stepping. > Going ahead with what the BSpec expects us to do - setting just bit 14. Sending v2 version shortly. Anusha > Matt > > > > > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> > > --- > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++ > > drivers/gpu/drm/i915/i915_reg.h | 1 + > > 2 files changed, 6 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c > > b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > index 5a7db279f702..53b448b61a5f 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > @@ -593,6 +593,11 @@ static void tgl_ctx_workarounds_init(struct > intel_engine_cs *engine, > > wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val, > > IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 : > > FF_MODE2_TDS_TIMER_MASK); > > + > > + /* Wa_1606931601:tgl */ > > + WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, > > + GEN11_EARLY_READ_SRC0_DISABLE_MASK); > > + > > } > > > > static void > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > b/drivers/gpu/drm/i915/i915_reg.h index b93c4c18f05c..69a1c2227b91 > > 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -9146,6 +9146,7 @@ enum { > > #define DOP_CLOCK_GATING_DISABLE (1 << 0) > > #define PUSH_CONSTANT_DEREF_DISABLE (1 << 8) > > #define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1) > > +#define GEN11_EARLY_READ_SRC0_DISABLE_MASK > REG_GENMASK(15, 14) > > > > #define HSW_ROW_CHICKEN3 _MMIO(0xe49c) > > #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) > > -- > > 2.23.0 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Matt Roper > Graphics Software Engineer > VTT-OSGC Platform Enablement > Intel Corporation > (916) 356-2795 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2020-01-24 19:36 UTC | newest] Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-01-22 23:40 [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601 Anusha Srivatsa 2020-01-23 4:36 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for " Patchwork 2020-01-23 17:50 ` [Intel-gfx] [PATCH] " Matt Roper 2020-01-24 19:36 ` Srivatsa, Anusha
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