[Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601

[Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601

[Anusha Srivatsa]

Disable Inter and intra Read Suppression (bit 15) and
Early Read and Src Swap (bit 14) by setting the chicken
register.

BSpec: 46045,52890

v2: Follow the Bspec implementation for the WA.
v3: Have 2 separate defines for bit 14 and 15.
- Rename register definitions with TGL_ prefix

Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
 drivers/gpu/drm/i915/i915_reg.h             | 2 ++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 5a7db279f702..1f84cd595f88 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -593,6 +593,12 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
 	wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
 	       IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 :
 			    FF_MODE2_TDS_TIMER_MASK);
+
+	/* Wa_1606931601:tgl */
+	WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
+			  GEN12_EARLY_READ_SRC0_DISABLE |
+			  GEN12_INTER_INTRA_READ_SUPPRESSION_DISABLE);
+
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4c72b8ac0f2e..70ead809c706 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9149,6 +9149,8 @@ enum {
 #define   DOP_CLOCK_GATING_DISABLE	(1 << 0)
 #define   PUSH_CONSTANT_DEREF_DISABLE	(1 << 8)
 #define   GEN11_TDL_CLOCK_GATING_FIX_DISABLE	(1 << 1)
+#define   GEN12_EARLY_READ_SRC0_DISABLE		(1 << 14)
+#define   GEN12_INTER_INTRA_READ_SUPPRESSION_DISABLE	(1 << 15)
 
 #define HSW_ROW_CHICKEN3		_MMIO(0xe49c)
 #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE    (1 << 6)
-- 
2.25.0

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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/tgl: Implement Wa_1606931601 (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/tgl: Implement Wa_1606931601 (rev3)
URL   : https://patchwork.freedesktop.org/series/72433/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_7839 -> Patchwork_16323
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_16323 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_16323, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16323/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_16323:

### IGT changes ###

#### Possible regressions ####

  * igt@runner@aborted:
    - fi-bsw-kefka:       NOTRUN -> [FAIL][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16323/fi-bsw-kefka/igt@runner@aborted.html

  
#### Warnings ####

  * igt@gem_exec_suspend@basic-s3:
    - fi-cml-s:           [FAIL][2] ([fdo#103375]) -> [TIMEOUT][3]
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7839/fi-cml-s/igt@gem_exec_suspend@basic-s3.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16323/fi-cml-s/igt@gem_exec_suspend@basic-s3.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live_workarounds:
    - {fi-tgl-u}:         [PASS][4] -> [DMESG-FAIL][5]
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7839/fi-tgl-u/igt@i915_selftest@live_workarounds.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16323/fi-tgl-u/igt@i915_selftest@live_workarounds.html

  
Known issues
------------

  Here are the changes found in Patchwork_16323 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_close_race@basic-threads:
    - fi-byt-j1900:       [PASS][6] -> [TIMEOUT][7] ([fdo#112271] / [i915#816])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7839/fi-byt-j1900/igt@gem_close_race@basic-threads.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16323/fi-byt-j1900/igt@gem_close_race@basic-threads.html
    - fi-byt-n2820:       [PASS][8] -> [TIMEOUT][9] ([fdo#112271] / [i915#816])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7839/fi-byt-n2820/igt@gem_close_race@basic-threads.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16323/fi-byt-n2820/igt@gem_close_race@basic-threads.html

  * igt@i915_pm_rpm@module-reload:
    - fi-skl-6770hq:      [PASS][10] -> [FAIL][11] ([i915#178])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7839/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16323/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live_blt:
    - fi-hsw-4770r:       [PASS][12] -> [DMESG-FAIL][13] ([i915#553] / [i915#725])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7839/fi-hsw-4770r/igt@i915_selftest@live_blt.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16323/fi-hsw-4770r/igt@i915_selftest@live_blt.html
    - fi-ivb-3770:        [PASS][14] -> [DMESG-FAIL][15] ([i915#725])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7839/fi-ivb-3770/igt@i915_selftest@live_blt.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16323/fi-ivb-3770/igt@i915_selftest@live_blt.html
    - fi-hsw-4770:        [PASS][16] -> [DMESG-FAIL][17] ([i915#553] / [i915#725])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7839/fi-hsw-4770/igt@i915_selftest@live_blt.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16323/fi-hsw-4770/igt@i915_selftest@live_blt.html

  * igt@kms_chamelium@dp-crc-fast:
    - fi-kbl-7500u:       [PASS][18] -> [FAIL][19] ([fdo#109635] / [i915#217])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7839/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16323/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s0:
    - fi-cml-s:           [FAIL][20] ([fdo#103375]) -> [PASS][21]
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7839/fi-cml-s/igt@gem_exec_suspend@basic-s0.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16323/fi-cml-s/igt@gem_exec_suspend@basic-s0.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][22] ([fdo#111407]) -> [PASS][23]
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7839/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16323/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109635]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
  [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
  [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271
  [i915#178]: https://gitlab.freedesktop.org/drm/intel/issues/178
  [i915#217]: https://gitlab.freedesktop.org/drm/intel/issues/217
  [i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553
  [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725
  [i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816


Participating hosts (47 -> 46)
------------------------------

  Additional (3): fi-hsw-peppy fi-bsw-kefka fi-kbl-r 
  Missing    (4): fi-byt-squawks fi-bsw-cyan fi-bdw-samus fi-hsw-4200u 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7839 -> Patchwork_16323

  CI-20190529: 20190529
  CI_DRM_7839: 41a9319a45aaf77e220c8101d6ce76ec66036ffc @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5406: 786c79af483a9f6e4688811f74116030c734ca1f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_16323: 94aff763b02c81cedafdcf7b706f5817e19d5816 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

94aff763b02c drm/i915/tgl: Implement Wa_1606931601

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16323/index.html
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Re: [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601

[Matt Roper]

On Wed, Jan 29, 2020 at 02:42:06PM -0800, Anusha Srivatsa wrote:
> Disable Inter and intra Read Suppression (bit 15) and
> Early Read and Src Swap (bit 14) by setting the chicken
> register.
> 
> BSpec: 46045,52890
> 
> v2: Follow the Bspec implementation for the WA.
> v3: Have 2 separate defines for bit 14 and 15.
> - Rename register definitions with TGL_ prefix

The hardware guys changed their mind again and we're back to only
needing bit 14 now.  They updated the bspec and the underlying database
yet again.  :-/

> 
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
>  drivers/gpu/drm/i915/i915_reg.h             | 2 ++
>  2 files changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 5a7db279f702..1f84cd595f88 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -593,6 +593,12 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
>  	wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
>  	       IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 :
>  			    FF_MODE2_TDS_TIMER_MASK);
> +
> +	/* Wa_1606931601:tgl */
> +	WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
> +			  GEN12_EARLY_READ_SRC0_DISABLE |
> +			  GEN12_INTER_INTRA_READ_SUPPRESSION_DISABLE);

I think Daniele already mentioned this on the other discussion, but
ROW_CHICKEN2 isn't part of the context image on gen12 (see bspec page
46255).  This is a change from ICL where it *was* part of the context
(see bspec page 18907), so even though we handled this register in the
ctx_workarounds_init for ICL, that's not the appropriate place to put it
for TGL.

Since this isn't a context workaround, we need to determine whether it's
a general GT workaround (which would be initialized in
tgl_gt_workarounds_init) or an engine workaround (which would be
initialized in {rcs,xcs}_engine_wa_init.  In this case the register
we're modifying is 0xe49c; according to bspec page 52078 this falls in
one of the forcewake ranges listed under the render engine column
(0E000-0E8FF).  So I believe in this case that means we want to update
rcs_engine_wa_init() with this workaround --- that ensures that the
workaround will be re-applied any time the engine is reset (even if it's
not a full-GPU reset).



Matt

> +
>  }
>  
>  static void
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4c72b8ac0f2e..70ead809c706 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9149,6 +9149,8 @@ enum {
>  #define   DOP_CLOCK_GATING_DISABLE	(1 << 0)
>  #define   PUSH_CONSTANT_DEREF_DISABLE	(1 << 8)
>  #define   GEN11_TDL_CLOCK_GATING_FIX_DISABLE	(1 << 1)
> +#define   GEN12_EARLY_READ_SRC0_DISABLE		(1 << 14)
> +#define   GEN12_INTER_INTRA_READ_SUPPRESSION_DISABLE	(1 << 15)
>  
>  #define HSW_ROW_CHICKEN3		_MMIO(0xe49c)
>  #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE    (1 << 6)
> -- 
> 2.25.0
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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Re: [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601

[Srivatsa, Anusha]

> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@intel.com>
> Sent: Thursday, January 30, 2020 12:43 PM
> To: Srivatsa, Anusha <anusha.srivatsa@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Ceraolo Spurio, Daniele
> <daniele.ceraolospurio@intel.com>
> Subject: Re: [PATCH] drm/i915/tgl: Implement Wa_1606931601
> 
> On Wed, Jan 29, 2020 at 02:42:06PM -0800, Anusha Srivatsa wrote:
> > Disable Inter and intra Read Suppression (bit 15) and Early Read and
> > Src Swap (bit 14) by setting the chicken register.
> >
> > BSpec: 46045,52890
> >
> > v2: Follow the Bspec implementation for the WA.
> > v3: Have 2 separate defines for bit 14 and 15.
> > - Rename register definitions with TGL_ prefix
> 
> The hardware guys changed their mind again and we're back to only needing
> bit 14 now.  They updated the bspec and the underlying database yet again.
> :-/
 ☹

> >
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > ---
> >  drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
> >  drivers/gpu/drm/i915/i915_reg.h             | 2 ++
> >  2 files changed, 8 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 5a7db279f702..1f84cd595f88 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -593,6 +593,12 @@ static void tgl_ctx_workarounds_init(struct
> intel_engine_cs *engine,
> >  	wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
> >  	       IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 :
> >  			    FF_MODE2_TDS_TIMER_MASK);
> > +
> > +	/* Wa_1606931601:tgl */
> > +	WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
> > +			  GEN12_EARLY_READ_SRC0_DISABLE |
> > +
> GEN12_INTER_INTRA_READ_SUPPRESSION_DISABLE);
> 
> I think Daniele already mentioned this on the other discussion, but
> ROW_CHICKEN2 isn't part of the context image on gen12 (see bspec page
> 46255).  This is a change from ICL where it *was* part of the context (see
> bspec page 18907), so even though we handled this register in the
> ctx_workarounds_init for ICL, that's not the appropriate place to put it for
> TGL.
Agreed. 

> Since this isn't a context workaround, we need to determine whether it's a
> general GT workaround (which would be initialized in
> tgl_gt_workarounds_init) or an engine workaround (which would be
> initialized in {rcs,xcs}_engine_wa_init.  In this case the register we're
> modifying is 0xe49c; according to bspec page 52078 this falls in one of the
> forcewake ranges listed under the render engine column (0E000-0E8FF). 

The register we are setting is 0xe4f4. This comes under Render engine. Adding this change to rcs_engine_wa_init().

> So I
> believe in this case that means we want to update
> rcs_engine_wa_init() with this workaround --- that ensures that the
> workaround will be re-applied any time the engine is reset (even if it's not a
> full-GPU reset).
Yes. Adding this to rcs_engine_wa_init().


Anusha 
> 
> Matt
> 
> > +
> >  }
> >
> >  static void
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 4c72b8ac0f2e..70ead809c706
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -9149,6 +9149,8 @@ enum {
> >  #define   DOP_CLOCK_GATING_DISABLE	(1 << 0)
> >  #define   PUSH_CONSTANT_DEREF_DISABLE	(1 << 8)
> >  #define   GEN11_TDL_CLOCK_GATING_FIX_DISABLE	(1 << 1)
> > +#define   GEN12_EARLY_READ_SRC0_DISABLE		(1 << 14)
> > +#define   GEN12_INTER_INTRA_READ_SUPPRESSION_DISABLE	(1 <<
> 15)
> >
> >  #define HSW_ROW_CHICKEN3		_MMIO(0xe49c)
> >  #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE    (1 << 6)
> > --
> > 2.25.0
> >
> 
> --
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
> (916) 356-2795
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