[Intel-gfx] [PATCH 1/4] drm/i915/display: Wake the power well during resume

[Intel-gfx] [PATCH 1/4] drm/i915/display: Wake the power well during resume

[Chris Wilson]

Acquire the power well before writing the setup during resume so that
our mmio are not dropped. E.g. on Braswell we see,

<4> [135.959703] i915 0000:00:02.0: Unclaimed write to register 0x1e0100
<4> [135.959936] WARNING: CPU: 1 PID: 3085 at drivers/gpu/drm/i915/intel_uncore.c:1166 __unclaimed_reg_debug+0x69/0x80 [i915]
<4> [135.959944] Modules linked in: vgem snd_hda_codec_hdmi snd_hda_codec_realtek snd_hda_codec_generic i915 coretemp btusb crct10dif_pclmul btrtl crc32_pclmul btbcm btintel snd_hda_intel ghash_clmulni_intel snd_intel_dspcfg bluetooth snd_hda_codec snd_hwdep ecdh_generic ecc snd_hda_core r8169 realtek snd_pcm lpc_ich prime_numbers pinctrl_cherryview
<4> [135.960011] CPU: 1 PID: 3085 Comm: kworker/u4:5 Tainted: G     U            5.5.0-CI-CI_DRM_7849+ #1
<4> [135.960019] Hardware name:  /NUC5CPYB, BIOS PYBSWCEL.86A.0058.2016.1102.1842 11/02/2016
<4> [135.960033] Workqueue: events_unbound async_run_entry_fn
<4> [135.960189] RIP: 0010:__unclaimed_reg_debug+0x69/0x80 [i915]
<4> [135.960199] Code: 48 8b 78 18 48 8b 5f 50 48 85 db 74 2d e8 0f d1 43 e1 45 89 e8 48 89 e9 48 89 da 48 89 c6 48 c7 c7 58 4c 44 a0 e8 37 bd e3 e0 <0f> 0b 83 2d 7e cd 2b 00 01 5b 5d 41 5c 41 5d c3 48 8b 1f eb ce 66
<4> [135.960207] RSP: 0018:ffffc9000047bd08 EFLAGS: 00010082
<4> [135.960217] RAX: 0000000000000000 RBX: ffff88817a0edb60 RCX: 0000000000000003
<4> [135.960225] RDX: 0000000080000003 RSI: 0000000000000000 RDI: 00000000ffffffff
<4> [135.960232] RBP: ffffffffa0485e86 R08: 0000000000000000 R09: 0000000000000001
<4> [135.960240] R10: 00000000d3945727 R11: 000000009a92dbc6 R12: 0000000000000000
<4> [135.960248] R13: 00000000001e0100 R14: 0000000000000286 R15: ffffffff8234a213
<4> [135.960257] FS:  0000000000000000(0000) GS:ffff88817bd00000(0000) knlGS:0000000000000000
<4> [135.960264] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
<4> [135.960272] CR2: 00007f2f0dab2778 CR3: 000000016f78c000 CR4: 00000000001006e0
<4> [135.960279] Call Trace:
<4> [135.960448]  fwtable_write32+0x114/0x1d0 [i915]
<4> [135.960633]  intel_power_domains_init_hw+0x4ff/0x650 [i915]
<4> [135.960821]  intel_power_domains_resume+0x3d/0x70 [i915]
<4> [135.960974]  i915_drm_resume_early+0x97/0xd0 [i915]

Closes: https://gitlab.freedesktop.org/drm/intel/issues/1089
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Imre Deak <imre.deak@intel.com>
---
 .../gpu/drm/i915/display/intel_display_power.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 64943179c05e..99463356be03 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5255,6 +5255,15 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
 	/* Must happen before power domain init on VLV/CHV */
 	intel_update_rawclk(i915);
 
+	/*
+	 * Keep all power wells enabled for any dependent HW access during
+	 * initialization and to make sure we keep BIOS enabled display HW
+	 * resources powered until display HW readout is complete. We drop
+	 * this reference in intel_power_domains_enable().
+	 */
+	power_domains->wakeref =
+		intel_display_power_get(i915, POWER_DOMAIN_INIT);
+
 	if (INTEL_GEN(i915) >= 11) {
 		icl_display_core_init(i915, resume);
 	} else if (IS_CANNONLAKE(i915)) {
@@ -5281,15 +5290,6 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
 		intel_pch_reset_handshake(i915, !HAS_PCH_NOP(i915));
 	}
 
-	/*
-	 * Keep all power wells enabled for any dependent HW access during
-	 * initialization and to make sure we keep BIOS enabled display HW
-	 * resources powered until display HW readout is complete. We drop
-	 * this reference in intel_power_domains_enable().
-	 */
-	power_domains->wakeref =
-		intel_display_power_get(i915, POWER_DOMAIN_INIT);
-
 	/* Disable power support if the user asked so. */
 	if (!i915_modparams.disable_power_well)
 		intel_display_power_get(i915, POWER_DOMAIN_INIT);
-- 
2.25.0

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[Intel-gfx] [PATCH 2/4] drm/i915: Initialise basic fence before acquiring seqno

[Chris Wilson]

Inside the intel_timeline_get_seqno(), we currently track the retirement
of the old cachelines by listening to the new request. This requires
that the new request is ready to be used and so requires a minimum bit
of initialisation prior to getting the new seqno.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
---
 drivers/gpu/drm/i915/i915_request.c | 21 ++++++++++++++-------
 1 file changed, 14 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
index 78a5f5d3c070..f56b046a32de 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -595,6 +595,8 @@ static void __i915_request_ctor(void *arg)
 	i915_sw_fence_init(&rq->submit, submit_notify);
 	i915_sw_fence_init(&rq->semaphore, semaphore_notify);
 
+	dma_fence_init(&rq->fence, &i915_fence_ops, &rq->lock, 0, 0);
+
 	rq->file_priv = NULL;
 	rq->capture_list = NULL;
 
@@ -653,25 +655,30 @@ __i915_request_create(struct intel_context *ce, gfp_t gfp)
 		}
 	}
 
-	ret = intel_timeline_get_seqno(tl, rq, &seqno);
-	if (ret)
-		goto err_free;
-
 	rq->i915 = ce->engine->i915;
 	rq->context = ce;
 	rq->engine = ce->engine;
 	rq->ring = ce->ring;
 	rq->execution_mask = ce->engine->mask;
 
+	kref_init(&rq->fence.refcount);
+	rq->fence.flags = 0;
+	rq->fence.error = 0;
+	INIT_LIST_HEAD(&rq->fence.cb_list);
+
+	ret = intel_timeline_get_seqno(tl, rq, &seqno);
+	if (ret)
+		goto err_free;
+
+	rq->fence.context = tl->fence_context;
+	rq->fence.seqno = seqno;
+
 	RCU_INIT_POINTER(rq->timeline, tl);
 	RCU_INIT_POINTER(rq->hwsp_cacheline, tl->hwsp_cacheline);
 	rq->hwsp_seqno = tl->hwsp_seqno;
 
 	rq->rcustate = get_state_synchronize_rcu(); /* acts as smp_mb() */
 
-	dma_fence_init(&rq->fence, &i915_fence_ops, &rq->lock,
-		       tl->fence_context, seqno);
-
 	/* We bump the ref for the fence chain */
 	i915_sw_fence_reinit(&i915_request_get(rq)->submit);
 	i915_sw_fence_reinit(&i915_request_get(rq)->semaphore);
-- 
2.25.0

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[Intel-gfx] [PATCH 3/4] drm/i915/gt: Warn about the hidden i915_vma_pin in timeline_get_seqno

[Chris Wilson]

On seqno rollover, we need to allocate ourselves a new cacheline. This
might incur grabbing a new page and pinning it into the GGTT, with some
rather unfortunate lockdep implications.

To avoid a mutex, and more specifically pinning in the GGTT from inside
the kernel context being used to flush the GGTT in emergencies, we will
likely need to lift the next-cacheline allocation to a pre-reservation.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_timeline.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c b/drivers/gpu/drm/i915/gt/intel_timeline.c
index 465f87b65901..54e1e55f3c81 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.c
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
@@ -406,6 +406,8 @@ __intel_timeline_get_seqno(struct intel_timeline *tl,
 	void *vaddr;
 	int err;
 
+	might_lock(&tl->gt->ggtt->vm.mutex);
+
 	/*
 	 * If there is an outstanding GPU reference to this cacheline,
 	 * such as it being sampled by a HW semaphore on another timeline,
-- 
2.25.0

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[Intel-gfx] [PATCH 4/4] drm/i915/selftests: Add a simple rollover for the kernel context

[Chris Wilson]

Exercise the seqno wrap paths on the kernel context to provide a small
amount of sanity checking and ensure that they are visible to lockdep.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/selftest_timeline.c | 171 ++++++++++++++++++++
 1 file changed, 171 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c b/drivers/gpu/drm/i915/gt/selftest_timeline.c
index e2d78cc22fb4..ddbe029cbde8 100644
--- a/drivers/gpu/drm/i915/gt/selftest_timeline.c
+++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c
@@ -6,6 +6,8 @@
 
 #include <linux/prime_numbers.h>
 
+#include "intel_context.h"
+#include "intel_engine_heartbeat.h"
 #include "intel_engine_pm.h"
 #include "intel_gt.h"
 #include "intel_gt_requests.h"
@@ -750,6 +752,173 @@ static int live_hwsp_wrap(void *arg)
 	return err;
 }
 
+static void engine_heartbeat_disable(struct intel_engine_cs *engine,
+				     unsigned long *saved)
+{
+	*saved = engine->props.heartbeat_interval_ms;
+	engine->props.heartbeat_interval_ms = 0;
+
+	intel_engine_pm_get(engine);
+	intel_engine_park_heartbeat(engine);
+}
+
+static void engine_heartbeat_enable(struct intel_engine_cs *engine,
+				    unsigned long saved)
+{
+	intel_engine_pm_put(engine);
+
+	engine->props.heartbeat_interval_ms = saved;
+}
+
+static int live_hwsp_rollover_kernel(void *arg)
+{
+	struct intel_gt *gt = arg;
+	struct intel_engine_cs *engine;
+	enum intel_engine_id id;
+	int err = 0;
+
+	/*
+	 * Run the host for long enough, and even the kernel context will
+	 * see a seqno rollover.
+	 */
+
+	for_each_engine(engine, gt, id) {
+		struct intel_context *ce = engine->kernel_context;
+		struct intel_timeline *tl = ce->timeline;
+		struct i915_request *rq[3] = {};
+		unsigned long heartbeat;
+		int i;
+
+		engine_heartbeat_disable(engine, &heartbeat);
+		if (intel_gt_wait_for_idle(gt, HZ / 2)) {
+			err = -EIO;
+			goto out;
+		}
+
+		GEM_BUG_ON(i915_active_fence_isset(&tl->last_request));
+		tl->seqno = 0;
+		timeline_rollback(tl);
+		timeline_rollback(tl);
+		WRITE_ONCE(*(u32 *)tl->hwsp_seqno, tl->seqno);
+
+		for (i = 0; i < ARRAY_SIZE(rq); i++) {
+			rq[i] = i915_request_create(ce);
+			if (IS_ERR(rq[i])) {
+				err = PTR_ERR(rq[i]);
+				goto out;
+			}
+
+			pr_debug("%s: create fence.seqnp:%d\n",
+				 engine->name, lower_32_bits(rq[i]->fence.seqno));
+			i915_request_get(rq[i]);
+			i915_request_add(rq[i]);
+		}
+
+		/* We expected a wrap! */
+		GEM_BUG_ON(rq[2]->fence.seqno > rq[0]->fence.seqno);
+
+		if (i915_request_wait(rq[2], 0, HZ / 5) < 0) {
+			pr_err("Wait for timeline wrap timed out!\n");
+			err = -EIO;
+			goto out;
+		}
+
+		for (i = 0; i < ARRAY_SIZE(rq); i++) {
+			if (!i915_request_completed(rq[i])) {
+				pr_err("Pre-wrap request not completed!\n");
+				err = -EINVAL;
+				goto out;
+			}
+		}
+
+out:
+		for (i = 0; i < ARRAY_SIZE(rq); i++)
+			i915_request_put(rq[i]);
+		engine_heartbeat_enable(engine, heartbeat);
+		if (err)
+			break;
+	}
+
+	if (igt_flush_test(gt->i915))
+		err = -EIO;
+
+	return err;
+}
+
+static int live_hwsp_rollover_user(void *arg)
+{
+	struct intel_gt *gt = arg;
+	struct intel_engine_cs *engine;
+	enum intel_engine_id id;
+	int err = 0;
+
+	/*
+	 * Run the host for long enough, and even the kernel context will
+	 * see a seqno rollover.
+	 */
+
+	for_each_engine(engine, gt, id) {
+		struct i915_request *rq[3] = {};
+		struct intel_context *ce;
+		int i;
+
+		ce = intel_context_create(engine);
+		if (IS_ERR(ce))
+			return PTR_ERR(ce);
+
+		err = intel_context_alloc_state(ce);
+		if (err)
+			goto out;
+
+		timeline_rollback(ce->timeline);
+		timeline_rollback(ce->timeline);
+		WRITE_ONCE(*(u32 *)ce->timeline->hwsp_seqno,
+			   ce->timeline->seqno);
+
+		for (i = 0; i < ARRAY_SIZE(rq); i++) {
+			rq[i] = intel_context_create_request(ce);
+			if (IS_ERR(rq[i])) {
+				err = PTR_ERR(rq[i]);
+				goto out;
+			}
+
+			pr_debug("%s: create fence.seqnp:%d\n",
+				 engine->name, lower_32_bits(rq[i]->fence.seqno));
+			i915_request_get(rq[i]);
+			i915_request_add(rq[i]);
+		}
+
+		/* We expected a wrap! */
+		GEM_BUG_ON(rq[2]->fence.seqno > rq[0]->fence.seqno);
+
+		if (i915_request_wait(rq[2], 0, HZ / 5) < 0) {
+			pr_err("Wait for timeline wrap timed out!\n");
+			err = -EIO;
+			goto out;
+		}
+
+		for (i = 0; i < ARRAY_SIZE(rq); i++) {
+			if (!i915_request_completed(rq[i])) {
+				pr_err("Pre-wrap request not completed!\n");
+				err = -EINVAL;
+				goto out;
+			}
+		}
+
+out:
+		for (i = 0; i < ARRAY_SIZE(rq); i++)
+			i915_request_put(rq[i]);
+		intel_context_put(ce);
+		if (err)
+			break;
+	}
+
+	if (igt_flush_test(gt->i915))
+		err = -EIO;
+
+	return err;
+}
+
 static int live_hwsp_recycle(void *arg)
 {
 	struct intel_gt *gt = arg;
@@ -827,6 +996,8 @@ int intel_timeline_live_selftests(struct drm_i915_private *i915)
 		SUBTEST(live_hwsp_engine),
 		SUBTEST(live_hwsp_alternate),
 		SUBTEST(live_hwsp_wrap),
+		SUBTEST(live_hwsp_rollover_kernel),
+		SUBTEST(live_hwsp_rollover_user),
 	};
 
 	if (intel_gt_is_wedged(&i915->gt))
-- 
2.25.0

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915/display: Wake the power well during resume

[Patchwork]

== Series Details ==

Series: series starting with [1/4] drm/i915/display: Wake the power well during resume
URL   : https://patchwork.freedesktop.org/series/72849/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
ced9ffb2a020 drm/i915/display: Wake the power well during resume
-:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#10: 
<4> [135.959936] WARNING: CPU: 1 PID: 3085 at drivers/gpu/drm/i915/intel_uncore.c:1166 __unclaimed_reg_debug+0x69/0x80 [i915]

total: 0 errors, 1 warnings, 0 checks, 30 lines checked
c6ba1e64e9ab drm/i915: Initialise basic fence before acquiring seqno
8af8c775d115 drm/i915/gt: Warn about the hidden i915_vma_pin in timeline_get_seqno
edce88fb05d2 drm/i915/selftests: Add a simple rollover for the kernel context

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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/4] drm/i915/display: Wake the power well during resume

[Patchwork]

== Series Details ==

Series: series starting with [1/4] drm/i915/display: Wake the power well during resume
URL   : https://patchwork.freedesktop.org/series/72849/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_7853 -> Patchwork_16366
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_16366 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_16366, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_16366:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_module_load@reload:
    - fi-bsw-nick:        NOTRUN -> [TIMEOUT][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/fi-bsw-nick/igt@i915_module_load@reload.html

  * igt@i915_selftest@live_gt_timelines:
    - fi-snb-2520m:       [PASS][2] -> [TIMEOUT][3]
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-snb-2520m/igt@i915_selftest@live_gt_timelines.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/fi-snb-2520m/igt@i915_selftest@live_gt_timelines.html
    - fi-hsw-4770:        [PASS][4] -> [TIMEOUT][5]
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-hsw-4770/igt@i915_selftest@live_gt_timelines.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/fi-hsw-4770/igt@i915_selftest@live_gt_timelines.html
    - fi-blb-e6850:       [PASS][6] -> [TIMEOUT][7]
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-blb-e6850/igt@i915_selftest@live_gt_timelines.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/fi-blb-e6850/igt@i915_selftest@live_gt_timelines.html
    - fi-gdg-551:         NOTRUN -> [TIMEOUT][8]
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/fi-gdg-551/igt@i915_selftest@live_gt_timelines.html
    - fi-bwr-2160:        [PASS][9] -> [TIMEOUT][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-bwr-2160/igt@i915_selftest@live_gt_timelines.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/fi-bwr-2160/igt@i915_selftest@live_gt_timelines.html
    - fi-snb-2600:        NOTRUN -> [TIMEOUT][11]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/fi-snb-2600/igt@i915_selftest@live_gt_timelines.html
    - fi-hsw-4770r:       [PASS][12] -> [TIMEOUT][13]
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-hsw-4770r/igt@i915_selftest@live_gt_timelines.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/fi-hsw-4770r/igt@i915_selftest@live_gt_timelines.html
    - fi-elk-e7500:       [PASS][14] -> [TIMEOUT][15]
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-elk-e7500/igt@i915_selftest@live_gt_timelines.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/fi-elk-e7500/igt@i915_selftest@live_gt_timelines.html
    - fi-ivb-3770:        [PASS][16] -> [TIMEOUT][17]
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-ivb-3770/igt@i915_selftest@live_gt_timelines.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/fi-ivb-3770/igt@i915_selftest@live_gt_timelines.html

  * igt@runner@aborted:
    - fi-hsw-4770r:       NOTRUN -> [FAIL][18]
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/fi-hsw-4770r/igt@runner@aborted.html
    - fi-gdg-551:         NOTRUN -> [FAIL][19]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/fi-gdg-551/igt@runner@aborted.html
    - fi-snb-2520m:       NOTRUN -> [FAIL][20]
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/fi-snb-2520m/igt@runner@aborted.html
    - fi-hsw-4770:        NOTRUN -> [FAIL][21]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/fi-hsw-4770/igt@runner@aborted.html
    - fi-whl-u:           NOTRUN -> [FAIL][22]
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/fi-whl-u/igt@runner@aborted.html
    - fi-ivb-3770:        NOTRUN -> [FAIL][23]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/fi-ivb-3770/igt@runner@aborted.html
    - fi-bxt-dsi:         NOTRUN -> [FAIL][24]
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/fi-bxt-dsi/igt@runner@aborted.html
    - fi-elk-e7500:       NOTRUN -> [FAIL][25]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/fi-elk-e7500/igt@runner@aborted.html
    - fi-blb-e6850:       NOTRUN -> [FAIL][26]
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/fi-blb-e6850/igt@runner@aborted.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@runner@aborted:
    - {fi-ehl-1}:         NOTRUN -> [FAIL][27]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/fi-ehl-1/igt@runner@aborted.html

  
Known issues
------------

  Here are the changes found in Patchwork_16366 that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s0:
    - fi-bsw-nick:        [TIMEOUT][28] ([i915#1089]) -> [PASS][29]
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-bsw-nick/igt@gem_exec_suspend@basic-s0.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/fi-bsw-nick/igt@gem_exec_suspend@basic-s0.html

  
#### Warnings ####

  * igt@gem_close_race@basic-threads:
    - fi-byt-n2820:       [TIMEOUT][30] ([fdo#112271] / [i915#1084] / [i915#816]) -> [TIMEOUT][31] ([fdo#112271] / [i915#816])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-byt-n2820/igt@gem_close_race@basic-threads.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/fi-byt-n2820/igt@gem_close_race@basic-threads.html

  * igt@runner@aborted:
    - fi-bsw-nick:        [FAIL][32] ([fdo#110446]) -> [FAIL][33] ([fdo#110446] / [k.org#204565])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-bsw-nick/igt@runner@aborted.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/fi-bsw-nick/igt@runner@aborted.html
    - fi-kbl-soraka:      [FAIL][34] ([fdo#109383] / [fdo#111012]) -> [FAIL][35] ([i915#192] / [i915#193] / [i915#194])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-kbl-soraka/igt@runner@aborted.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/fi-kbl-soraka/igt@runner@aborted.html
    - fi-cml-s:           [FAIL][36] ([fdo#111012] / [fdo#111764] / [i915#577]) -> [FAIL][37] ([i915#577])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-cml-s/igt@runner@aborted.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/fi-cml-s/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109383]: https://bugs.freedesktop.org/show_bug.cgi?id=109383
  [fdo#110446]: https://bugs.freedesktop.org/show_bug.cgi?id=110446
  [fdo#111012]: https://bugs.freedesktop.org/show_bug.cgi?id=111012
  [fdo#111764]: https://bugs.freedesktop.org/show_bug.cgi?id=111764
  [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271
  [i915#1084]: https://gitlab.freedesktop.org/drm/intel/issues/1084
  [i915#1089]: https://gitlab.freedesktop.org/drm/intel/issues/1089
  [i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192
  [i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193
  [i915#194]: https://gitlab.freedesktop.org/drm/intel/issues/194
  [i915#577]: https://gitlab.freedesktop.org/drm/intel/issues/577
  [i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816
  [k.org#204565]: https://bugzilla.kernel.org/show_bug.cgi?id=204565


Participating hosts (47 -> 40)
------------------------------

  Additional (6): fi-gdg-551 fi-cfl-8109u fi-skl-6600u fi-kbl-7560u fi-skl-6700k2 fi-snb-2600 
  Missing    (13): fi-ilk-m540 fi-bdw-5557u fi-bsw-n3050 fi-hsw-4200u fi-hsw-peppy fi-byt-squawks fi-icl-u2 fi-bsw-cyan fi-ilk-650 fi-pnv-d510 fi-bsw-kefka fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7853 -> Patchwork_16366

  CI-20190529: 20190529
  CI_DRM_7853: 1df04205c16923e525efe9c26d6e98612d38c9b3 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5409: 93aefe6baa3fabf8c0cabe83e185f7b8f8d8753d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_16366: edce88fb05d2c4acd24a6a43b4c86e762ef874c8 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

edce88fb05d2 drm/i915/selftests: Add a simple rollover for the kernel context
8af8c775d115 drm/i915/gt: Warn about the hidden i915_vma_pin in timeline_get_seqno
c6ba1e64e9ab drm/i915: Initialise basic fence before acquiring seqno
ced9ffb2a020 drm/i915/display: Wake the power well during resume

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16366/index.html
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