[Intel-gfx] [PATCH v16 0/7] Refactor Gen11+ SAGV support

[Intel-gfx] [PATCH v16 0/7] Refactor Gen11+ SAGV support

[Stanislav Lisovskiy]

For Gen11+ platforms BSpec suggests disabling specific
QGV points separately, depending on bandwidth limitations
and current display configuration. Thus it required adding
a new PCode request for disabling QGV points and some
refactoring of already existing SAGV code.
Also had to refactor intel_can_enable_sagv function,
as current seems to be outdated and using skl specific
workarounds, also not following BSpec for Gen11+.

Stanislav Lisovskiy (7):
  drm/i915: Start passing latency as parameter
  drm/i915: Introduce skl_plane_wm_level accessor.
  drm/i915: Init obj state in intel_atomic_get_old/new_global_obj_state
  drm/i915: Refactor intel_can_enable_sagv
  drm/i915: Added required new PCode commands
  drm/i915: Restrict qgv points which don't have enough bandwidth.
  drm/i915: Enable SAGV support for Gen12

 drivers/gpu/drm/i915/display/intel_bw.c       | 199 ++++--
 drivers/gpu/drm/i915/display/intel_bw.h       |  24 +
 drivers/gpu/drm/i915/display/intel_display.c  | 131 +++-
 .../drm/i915/display/intel_display_types.h    |   8 +
 .../gpu/drm/i915/display/intel_global_state.h |   1 +
 drivers/gpu/drm/i915/i915_drv.h               |   3 +
 drivers/gpu/drm/i915/i915_reg.h               |   4 +
 drivers/gpu/drm/i915/intel_pm.c               | 564 +++++++++++++++---
 drivers/gpu/drm/i915/intel_pm.h               |   4 +-
 drivers/gpu/drm/i915/intel_sideband.c         |   2 +
 10 files changed, 801 insertions(+), 139 deletions(-)

-- 
2.24.1.485.gad05a3d8e5

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[Intel-gfx] [PATCH v16 1/7] drm/i915: Start passing latency as parameter

[Stanislav Lisovskiy]

We need to start passing memory latency as a
parameter when calculating plane wm levels,
as latency can get changed in different
circumstances(for example with or without SAGV).
So we need to be more flexible on that matter.

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ffac0b862ca5..d6933e382657 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4002,6 +4002,7 @@ static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
 				 int color_plane);
 static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
 				 int level,
+				 u32 latency,
 				 const struct skl_wm_params *wp,
 				 const struct skl_wm_level *result_prev,
 				 struct skl_wm_level *result /* out */);
@@ -4024,7 +4025,9 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
 	drm_WARN_ON(&dev_priv->drm, ret);
 
 	for (level = 0; level <= max_level; level++) {
-		skl_compute_plane_wm(crtc_state, level, &wp, &wm, &wm);
+		u32 latency = dev_priv->wm.skl_latency[level];
+
+		skl_compute_plane_wm(crtc_state, level, latency, &wp, &wm, &wm);
 		if (wm.min_ddb_alloc == U16_MAX)
 			break;
 
@@ -4978,12 +4981,12 @@ static bool skl_wm_has_lines(struct drm_i915_private *dev_priv, int level)
 
 static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
 				 int level,
+				 u32 latency,
 				 const struct skl_wm_params *wp,
 				 const struct skl_wm_level *result_prev,
 				 struct skl_wm_level *result /* out */)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
-	u32 latency = dev_priv->wm.skl_latency[level];
 	uint_fixed_16_16_t method1, method2;
 	uint_fixed_16_16_t selected_result;
 	u32 res_blocks, res_lines, min_ddb_alloc = 0;
@@ -5112,9 +5115,10 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
 
 	for (level = 0; level <= max_level; level++) {
 		struct skl_wm_level *result = &levels[level];
+		u32 latency = dev_priv->wm.skl_latency[level];
 
-		skl_compute_plane_wm(crtc_state, level, wm_params,
-				     result_prev, result);
+		skl_compute_plane_wm(crtc_state, level, latency,
+				     wm_params, result_prev, result);
 
 		result_prev = result;
 	}
-- 
2.24.1.485.gad05a3d8e5

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[Intel-gfx] [PATCH v16 2/7] drm/i915: Introduce skl_plane_wm_level accessor.

[Stanislav Lisovskiy]

For future Gen12 SAGV implementation we need to
seemlessly alter wm levels calculated, depending
on whether we are allowed to enable SAGV or not.

So this accessor will give additional flexibility
to do that.

Currently this accessor is still simply working
as "pass-through" function. This will be changed
in next coming patches from this series.

v2: - plane_id -> plane->id(Ville Syrjälä)
    - Moved wm_level var to have more local scope
      (Ville Syrjälä)
    - Renamed yuv to color_plane(Ville Syrjälä) in
      skl_plane_wm_level

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 120 +++++++++++++++++++++-----------
 1 file changed, 81 insertions(+), 39 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d6933e382657..e1d167429489 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4548,6 +4548,18 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
 	return total_data_rate;
 }
 
+static const struct skl_wm_level *
+skl_plane_wm_level(struct intel_plane *plane,
+		   const struct intel_crtc_state *crtc_state,
+		   int level,
+		   int color_plane)
+{
+	const struct skl_plane_wm *wm =
+		&crtc_state->wm.skl.optimal.planes[plane->id];
+
+	return color_plane ? &wm->uv_wm[level] : &wm->wm[level];
+}
+
 static int
 skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
 {
@@ -4560,7 +4572,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
 	u16 total[I915_MAX_PLANES] = {};
 	u16 uv_total[I915_MAX_PLANES] = {};
 	u64 total_data_rate;
-	enum plane_id plane_id;
+	struct intel_plane *plane;
 	int num_active;
 	u64 plane_data_rate[I915_MAX_PLANES] = {};
 	u64 uv_plane_data_rate[I915_MAX_PLANES] = {};
@@ -4612,22 +4624,28 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
 	 */
 	for (level = ilk_wm_max_level(dev_priv); level >= 0; level--) {
 		blocks = 0;
-		for_each_plane_id_on_crtc(intel_crtc, plane_id) {
-			const struct skl_plane_wm *wm =
-				&crtc_state->wm.skl.optimal.planes[plane_id];
 
-			if (plane_id == PLANE_CURSOR) {
-				if (wm->wm[level].min_ddb_alloc > total[PLANE_CURSOR]) {
+		for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
+			const struct skl_wm_level *wm_level;
+			const struct skl_wm_level *wm_uv_level;
+
+			wm_level = skl_plane_wm_level(plane, crtc_state,
+						      level, false);
+			wm_uv_level = skl_plane_wm_level(plane, crtc_state,
+							 level, true);
+
+			if (plane->id == PLANE_CURSOR) {
+				if (wm_level->min_ddb_alloc > total[PLANE_CURSOR]) {
 					drm_WARN_ON(&dev_priv->drm,
-						    wm->wm[level].min_ddb_alloc != U16_MAX);
+						    wm_level->min_ddb_alloc != U16_MAX);
 					blocks = U32_MAX;
 					break;
 				}
 				continue;
 			}
 
-			blocks += wm->wm[level].min_ddb_alloc;
-			blocks += wm->uv_wm[level].min_ddb_alloc;
+			blocks += wm_level->min_ddb_alloc;
+			blocks += wm_uv_level->min_ddb_alloc;
 		}
 
 		if (blocks <= alloc_size) {
@@ -4649,13 +4667,18 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
 	 * watermark level, plus an extra share of the leftover blocks
 	 * proportional to its relative data rate.
 	 */
-	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
-		const struct skl_plane_wm *wm =
-			&crtc_state->wm.skl.optimal.planes[plane_id];
+	for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
+		const struct skl_wm_level *wm_level;
+		const struct skl_wm_level *wm_uv_level;
 		u64 rate;
 		u16 extra;
 
-		if (plane_id == PLANE_CURSOR)
+		wm_level = skl_plane_wm_level(plane, crtc_state,
+					      level, false);
+		wm_uv_level = skl_plane_wm_level(plane, crtc_state,
+						 level, true);
+
+		if (plane->id == PLANE_CURSOR)
 			continue;
 
 		/*
@@ -4665,22 +4688,22 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
 		if (total_data_rate == 0)
 			break;
 
-		rate = plane_data_rate[plane_id];
+		rate = plane_data_rate[plane->id];
 		extra = min_t(u16, alloc_size,
 			      DIV64_U64_ROUND_UP(alloc_size * rate,
 						 total_data_rate));
-		total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
+		total[plane->id] = wm_level->min_ddb_alloc + extra;
 		alloc_size -= extra;
 		total_data_rate -= rate;
 
 		if (total_data_rate == 0)
 			break;
 
-		rate = uv_plane_data_rate[plane_id];
+		rate = uv_plane_data_rate[plane->id];
 		extra = min_t(u16, alloc_size,
 			      DIV64_U64_ROUND_UP(alloc_size * rate,
 						 total_data_rate));
-		uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
+		uv_total[plane->id] = wm_uv_level->min_ddb_alloc + extra;
 		alloc_size -= extra;
 		total_data_rate -= rate;
 	}
@@ -4688,29 +4711,29 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
 
 	/* Set the actual DDB start/end points for each plane */
 	start = alloc->start;
-	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
+	for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
 		struct skl_ddb_entry *plane_alloc =
-			&crtc_state->wm.skl.plane_ddb_y[plane_id];
+			&crtc_state->wm.skl.plane_ddb_y[plane->id];
 		struct skl_ddb_entry *uv_plane_alloc =
-			&crtc_state->wm.skl.plane_ddb_uv[plane_id];
+			&crtc_state->wm.skl.plane_ddb_uv[plane->id];
 
-		if (plane_id == PLANE_CURSOR)
+		if (plane->id == PLANE_CURSOR)
 			continue;
 
 		/* Gen11+ uses a separate plane for UV watermarks */
 		drm_WARN_ON(&dev_priv->drm,
-			    INTEL_GEN(dev_priv) >= 11 && uv_total[plane_id]);
+			    INTEL_GEN(dev_priv) >= 11 && uv_total[plane->id]);
 
 		/* Leave disabled planes at (0,0) */
-		if (total[plane_id]) {
+		if (total[plane->id]) {
 			plane_alloc->start = start;
-			start += total[plane_id];
+			start += total[plane->id];
 			plane_alloc->end = start;
 		}
 
-		if (uv_total[plane_id]) {
+		if (uv_total[plane->id]) {
 			uv_plane_alloc->start = start;
-			start += uv_total[plane_id];
+			start += uv_total[plane->id];
 			uv_plane_alloc->end = start;
 		}
 	}
@@ -4722,9 +4745,16 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
 	 * that aren't actually possible.
 	 */
 	for (level++; level <= ilk_wm_max_level(dev_priv); level++) {
-		for_each_plane_id_on_crtc(intel_crtc, plane_id) {
+		for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
+			const struct skl_wm_level *wm_level;
+			const struct skl_wm_level *wm_uv_level;
 			struct skl_plane_wm *wm =
-				&crtc_state->wm.skl.optimal.planes[plane_id];
+				&crtc_state->wm.skl.optimal.planes[plane->id];
+
+			wm_level = skl_plane_wm_level(plane, crtc_state,
+						      level, false);
+			wm_uv_level = skl_plane_wm_level(plane, crtc_state,
+							 level, true);
 
 			/*
 			 * We only disable the watermarks for each plane if
@@ -4738,9 +4768,10 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
 			 *  planes must be enabled before the level will be used."
 			 * So this is actually safe to do.
 			 */
-			if (wm->wm[level].min_ddb_alloc > total[plane_id] ||
-			    wm->uv_wm[level].min_ddb_alloc > uv_total[plane_id])
-				memset(&wm->wm[level], 0, sizeof(wm->wm[level]));
+			if (wm_level->min_ddb_alloc > total[plane->id] ||
+			    wm_uv_level->min_ddb_alloc > uv_total[plane->id])
+				memset(&wm->wm[level], 0,
+				       sizeof(struct skl_wm_level));
 
 			/*
 			 * Wa_1408961008:icl, ehl
@@ -4748,9 +4779,14 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
 			 */
 			if (IS_GEN(dev_priv, 11) &&
 			    level == 1 && wm->wm[0].plane_en) {
-				wm->wm[level].plane_res_b = wm->wm[0].plane_res_b;
-				wm->wm[level].plane_res_l = wm->wm[0].plane_res_l;
-				wm->wm[level].ignore_lines = wm->wm[0].ignore_lines;
+				wm_level = skl_plane_wm_level(plane, crtc_state,
+							      0, false);
+				wm->wm[level].plane_res_b =
+					wm_level->plane_res_b;
+				wm->wm[level].plane_res_l =
+					wm_level->plane_res_l;
+				wm->wm[level].ignore_lines =
+					wm_level->ignore_lines;
 			}
 		}
 	}
@@ -4759,11 +4795,11 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
 	 * Go back and disable the transition watermark if it turns out we
 	 * don't have enough DDB blocks for it.
 	 */
-	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
+	for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
 		struct skl_plane_wm *wm =
-			&crtc_state->wm.skl.optimal.planes[plane_id];
+			&crtc_state->wm.skl.optimal.planes[plane->id];
 
-		if (wm->trans_wm.plane_res_b >= total[plane_id])
+		if (wm->trans_wm.plane_res_b >= total[plane->id])
 			memset(&wm->trans_wm, 0, sizeof(wm->trans_wm));
 	}
 
@@ -5354,10 +5390,13 @@ void skl_write_plane_wm(struct intel_plane *plane,
 		&crtc_state->wm.skl.plane_ddb_y[plane_id];
 	const struct skl_ddb_entry *ddb_uv =
 		&crtc_state->wm.skl.plane_ddb_uv[plane_id];
+	const struct skl_wm_level *wm_level;
 
 	for (level = 0; level <= max_level; level++) {
+		wm_level = skl_plane_wm_level(plane, crtc_state, level, false);
+
 		skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
-				   &wm->wm[level]);
+				   wm_level);
 	}
 	skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
 			   &wm->trans_wm);
@@ -5388,10 +5427,13 @@ void skl_write_cursor_wm(struct intel_plane *plane,
 		&crtc_state->wm.skl.optimal.planes[plane_id];
 	const struct skl_ddb_entry *ddb =
 		&crtc_state->wm.skl.plane_ddb_y[plane_id];
+	const struct skl_wm_level *wm_level;
 
 	for (level = 0; level <= max_level; level++) {
+		wm_level = skl_plane_wm_level(plane, crtc_state, level, false);
+
 		skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
-				   &wm->wm[level]);
+				   wm_level);
 	}
 	skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
 
-- 
2.24.1.485.gad05a3d8e5

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[Intel-gfx] [PATCH v16 3/7] drm/i915: Init obj state in intel_atomic_get_old/new_global_obj_state

[Stanislav Lisovskiy]

We might be willing to call intel_atomic_get_old_global_obj_state
and intel_atomic_get_new_global_obj_state right away, however
those are not initializing global obj state as
intel_atomic_get_global_obj_state does.
Extracted initializing part to separate function and now using this
also in intel_atomic_get_old_global_obj_state and intel_atomic_get_new_global_obj_state

v2: - Fixed typo in function call

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 28 ++++++++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_bw.h |  9 ++++++++
 2 files changed, 36 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 58b264bc318d..ff57277e8880 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -374,7 +374,33 @@ static unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
 	return data_rate;
 }
 
-static struct intel_bw_state *
+struct intel_bw_state *
+intel_atomic_get_old_bw_state(struct intel_atomic_state *state)
+{
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+	struct intel_global_state *bw_state;
+
+	bw_state = intel_atomic_get_old_global_obj_state(state, &dev_priv->bw_obj);
+	if (IS_ERR(bw_state))
+		return ERR_CAST(bw_state);
+
+	return to_intel_bw_state(bw_state);
+}
+
+struct intel_bw_state *
+intel_atomic_get_new_bw_state(struct intel_atomic_state *state)
+{
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+	struct intel_global_state *bw_state;
+	bw_state = intel_atomic_get_new_global_obj_state(state, &dev_priv->bw_obj);
+
+	if (IS_ERR(bw_state))
+		return ERR_CAST(bw_state);
+
+	return to_intel_bw_state(bw_state);
+}
+
+struct intel_bw_state *
 intel_atomic_get_bw_state(struct intel_atomic_state *state)
 {
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index a8aa7624c5aa..ac004d6f4276 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -24,6 +24,15 @@ struct intel_bw_state {
 
 #define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base)
 
+struct intel_bw_state *
+intel_atomic_get_old_bw_state(struct intel_atomic_state *state);
+
+struct intel_bw_state *
+intel_atomic_get_new_bw_state(struct intel_atomic_state *state);
+
+struct intel_bw_state *
+intel_atomic_get_bw_state(struct intel_atomic_state *state);
+
 void intel_bw_init_hw(struct drm_i915_private *dev_priv);
 int intel_bw_init(struct drm_i915_private *dev_priv);
 int intel_bw_atomic_check(struct intel_atomic_state *state);
-- 
2.24.1.485.gad05a3d8e5

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[Intel-gfx] [PATCH v16 4/7] drm/i915: Refactor intel_can_enable_sagv

[Stanislav Lisovskiy]

Currently intel_can_enable_sagv function contains
a mix of workarounds for different platforms
some of them are not valid for gens >= 11 already,
so lets split it into separate functions.

v2:
    - Rework watermark calculation algorithm to
      attempt to calculate Level 0 watermark
      with added sagv block time latency and
      check if it fits in DBuf in order to
      determine if SAGV can be enabled already
      at this stage, just as BSpec 49325 states.
      if that fails rollback to usual Level 0
      latency and disable SAGV.
    - Remove unneeded tabs(James Ausmus)

v3: Rebased the patch

v4: - Added back interlaced check for Gen12 and
      added separate function for TGL SAGV check
      (thanks to James Ausmus for spotting)
    - Removed unneeded gen check
    - Extracted Gen12 SAGV decision making code
      to a separate function from skl_compute_wm

v5: - Added SAGV global state to dev_priv, because
      we need to track all pipes, not only those
      in atomic state. Each pipe has now correspondent
      bit mask reflecting, whether it can tolerate
      SAGV or not(thanks to Ville Syrjala for suggestions).
    - Now using active flag instead of enable in crc
      usage check.

v6: - Fixed rebase conflicts

v7: - kms_cursor_legacy seems to get broken because of multiple memcpy
      calls when copying level 0 water marks for enabled SAGV, to
      fix this now simply using that field right away, without copying,
      for that introduced a new wm_level accessor which decides which
      wm_level to return based on SAGV state.

v8: - Protect crtc_sagv_mask same way as we do for other global state
      changes: i.e check if changes are needed, then grab all crtc locks
      to serialize the changes(Ville Syrjälä)
    - Add crtc_sagv_mask caching in order to avoid needless recalculations
      (Matthew Roper)
    - Put back Gen12 SAGV switch in order to get it enabled in separate
      patch(Matthew Roper)
    - Rename *_set_sagv_mask to *_compute_sagv_mask(Matthew Roper)
    - Check if there are no active pipes in intel_can_enable_sagv
      instead of platform specific functions(Matthew Roper), same
      for intel_has_sagv check.

v9  - Switched to u8 for crtc_sagv_mask(Ville Syrjälä)
    - crtc_sagv_mask now is pipe_sagv_mask(Ville Syrjälä)
    - Extracted sagv checking logic from skl/icl/tgl_compute_sagv_mask
    - Extracted skl_plane_wm_level function and passing latency to
      separate patches(Ville Syrjälä)
    - Removed part of unneeded copy-paste from tgl_check_pipe_fits_sagv_wm
      (Ville Syrjälä)
    - Now using simple assignment for sagv_wm0 as it contains only
      pod types and no pointers(Ville Syrjälä)
    - Fixed intel_can_enable_sagv not to do double duty, now it only
      check SAGV bits by ANDing those between local and global state.
      The SAGV masks are now computed after watermarks are available,
      in order to be able to figure out if ddb ranges are fitting nicely.
      (Ville Syrjälä)
    - Now having uv_sagv_wm0 and sagv_wm0, otherwise we have wrong logic
      when using skl_plane_wm_level accessor, as we had previously for Gen11+
      color plane and regular wm levels, so probably both has to be recalculated
      with additional SAGV block time for Level 0.

v10: - Starting to use new global state for storing pipe_sagv_mask

v11: - Fixed rebase conflict with recent drm-tip
     - Check if we really need to recalculate SAGV mask, otherwise
       bail out without making any changes.

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Ville Syrjälä <ville.syrjala@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.h       |   6 +
 drivers/gpu/drm/i915/display/intel_display.c  |  22 +-
 .../drm/i915/display/intel_display_types.h    |   8 +
 .../gpu/drm/i915/display/intel_global_state.h |   1 +
 drivers/gpu/drm/i915/intel_pm.c               | 428 ++++++++++++++++--
 drivers/gpu/drm/i915/intel_pm.h               |   4 +-
 6 files changed, 427 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index ac004d6f4276..6c33d3af50a9 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -18,6 +18,12 @@ struct intel_crtc_state;
 struct intel_bw_state {
 	struct intel_global_state base;
 
+	/*
+	 * Contains a bit mask, whether correspondent
+	 * pipe allows SAGV or not.
+	 */
+	u8 pipe_sagv_mask;
+
 	unsigned int data_rate[I915_MAX_PIPES];
 	u8 num_active_planes[I915_MAX_PIPES];
 };
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 24542281a73e..ef2e9155090f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14105,7 +14105,10 @@ static void verify_wm_state(struct intel_crtc *crtc,
 		/* Watermarks */
 		for (level = 0; level <= max_level; level++) {
 			if (skl_wm_level_equals(&hw_plane_wm->wm[level],
-						&sw_plane_wm->wm[level]))
+						&sw_plane_wm->wm[level]) ||
+			   (skl_wm_level_equals(&hw_plane_wm->wm[level],
+						&sw_plane_wm->sagv_wm0) &&
+			   (level == 0)))
 				continue;
 
 			drm_err(&dev_priv->drm,
@@ -14160,7 +14163,10 @@ static void verify_wm_state(struct intel_crtc *crtc,
 		/* Watermarks */
 		for (level = 0; level <= max_level; level++) {
 			if (skl_wm_level_equals(&hw_plane_wm->wm[level],
-						&sw_plane_wm->wm[level]))
+						&sw_plane_wm->wm[level]) ||
+			   (skl_wm_level_equals(&hw_plane_wm->wm[level],
+						&sw_plane_wm->sagv_wm0) &&
+			   (level == 0)))
 				continue;
 
 			drm_err(&dev_priv->drm,
@@ -15712,8 +15718,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 		 * SKL workaround: bspec recommends we disable the SAGV when we
 		 * have more then one pipe enabled
 		 */
-		if (!intel_can_enable_sagv(state))
-			intel_disable_sagv(dev_priv);
+		if (INTEL_GEN(dev_priv) < 11)
+			if (!intel_can_enable_sagv(dev_priv))
+				intel_disable_sagv(dev_priv);
 
 		intel_modeset_verify_disabled(dev_priv, state);
 	}
@@ -15813,8 +15820,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	if (state->modeset)
 		intel_verify_planes(state);
 
-	if (state->modeset && intel_can_enable_sagv(state))
-		intel_enable_sagv(dev_priv);
+	if (INTEL_GEN(dev_priv) < 11) {
+		if (state->modeset && intel_can_enable_sagv(dev_priv))
+			intel_enable_sagv(dev_priv);
+	}
 
 	drm_atomic_helper_commit_hw_done(&state->base);
 
@@ -15966,7 +15975,6 @@ static int intel_atomic_commit(struct drm_device *dev,
 
 	if (state->global_state_changed) {
 		assert_global_state_locked(dev_priv);
-
 		dev_priv->active_pipes = state->active_pipes;
 	}
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 283c622f8ba1..b5f7986dd1dc 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -478,6 +478,12 @@ struct intel_atomic_state {
 	 */
 	u8 active_pipe_changes;
 
+	/*
+	 * Used to determine if we already had calculated
+	 * SAGV mask for this state once.
+	 */
+	bool sagv_calculated;
+
 	u8 active_pipes;
 
 	struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
@@ -651,6 +657,8 @@ struct skl_plane_wm {
 	struct skl_wm_level wm[8];
 	struct skl_wm_level uv_wm[8];
 	struct skl_wm_level trans_wm;
+	struct skl_wm_level sagv_wm0;
+	struct skl_wm_level uv_sagv_wm0;
 	bool is_planar;
 };
 
diff --git a/drivers/gpu/drm/i915/display/intel_global_state.h b/drivers/gpu/drm/i915/display/intel_global_state.h
index e6163a469029..481bf5ea90a3 100644
--- a/drivers/gpu/drm/i915/display/intel_global_state.h
+++ b/drivers/gpu/drm/i915/display/intel_global_state.h
@@ -84,4 +84,5 @@ void intel_atomic_clear_global_state(struct intel_atomic_state *state);
 int intel_atomic_lock_global_state(struct intel_global_state *obj_state);
 int intel_atomic_serialize_global_state(struct intel_global_state *obj_state);
 
+
 #endif
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e1d167429489..e8f10a413808 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -42,6 +42,7 @@
 #include "i915_drv.h"
 #include "i915_irq.h"
 #include "i915_trace.h"
+#include "display/intel_bw.h"
 #include "intel_pm.h"
 #include "intel_sideband.h"
 #include "../../../platform/x86/intel_ips.h"
@@ -3620,7 +3621,7 @@ static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
 	return IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv);
 }
 
-static bool
+bool
 intel_has_sagv(struct drm_i915_private *dev_priv)
 {
 	/* HACK! */
@@ -3743,39 +3744,24 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
 	return 0;
 }
 
-bool intel_can_enable_sagv(struct intel_atomic_state *state)
+static bool skl_can_enable_sagv_on_pipe(struct intel_atomic_state *state,
+					enum pipe pipe)
 {
 	struct drm_device *dev = state->base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct intel_crtc *crtc;
 	struct intel_plane *plane;
 	struct intel_crtc_state *crtc_state;
-	enum pipe pipe;
 	int level, latency;
 
-	if (!intel_has_sagv(dev_priv))
-		return false;
-
-	/*
-	 * If there are no active CRTCs, no additional checks need be performed
-	 */
-	if (hweight8(state->active_pipes) == 0)
-		return true;
-
-	/*
-	 * SKL+ workaround: bspec recommends we disable SAGV when we have
-	 * more then one pipe enabled
-	 */
-	if (hweight8(state->active_pipes) > 1)
-		return false;
-
-	/* Since we're now guaranteed to only have one active CRTC... */
-	pipe = ffs(state->active_pipes) - 1;
 	crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
 	crtc_state = to_intel_crtc_state(crtc->base.state);
 
-	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
+	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
+		DRM_DEBUG_KMS("No SAGV for interlaced mode on pipe %c\n",
+			      pipe_name(pipe));
 		return false;
+	}
 
 	for_each_intel_plane_on_crtc(dev, crtc, plane) {
 		struct skl_plane_wm *wm =
@@ -3802,7 +3788,159 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
 		 * incur memory latencies higher than sagv_block_time_us we
 		 * can't enable SAGV.
 		 */
-		if (latency < dev_priv->sagv_block_time_us)
+		if (latency < dev_priv->sagv_block_time_us) {
+			DRM_DEBUG_KMS("Latency %d < sagv block time %d, no SAGV for pipe %c\n",
+				      latency, dev_priv->sagv_block_time_us, pipe_name(pipe));
+			return false;
+		}
+	}
+
+	return true;
+}
+
+static void skl_compute_sagv_mask(struct intel_atomic_state *state)
+{
+	struct intel_crtc *crtc;
+	enum pipe pipe;
+	struct intel_bw_state *new_bw_state = intel_atomic_get_bw_state(state);
+
+	if (IS_ERR(new_bw_state)) {
+		WARN(1, "Could not get bw_state\n");
+		return;
+	}
+
+
+	if (state->active_pipes != 1) {
+		new_bw_state->pipe_sagv_mask = 0;
+		DRM_DEBUG_KMS("No SAGV for multiple pipes on Gen 9\n");
+		return;
+	}
+
+	/* Since we're now guaranteed to only have one active CRTC... */
+	pipe = ffs(state->active_pipes) - 1;
+
+	if (skl_can_enable_sagv_on_pipe(state, pipe))
+		new_bw_state->pipe_sagv_mask |= BIT(crtc->pipe);
+	else
+		new_bw_state->pipe_sagv_mask &= ~BIT(crtc->pipe);
+}
+
+static void tgl_compute_sagv_mask(struct intel_atomic_state *state);
+
+static void icl_compute_sagv_mask(struct intel_atomic_state *state)
+{
+	struct intel_crtc *crtc;
+	struct intel_crtc_state *new_crtc_state;
+	int i;
+	struct intel_bw_state *new_bw_state = intel_atomic_get_bw_state(state);
+
+	if (IS_ERR(new_bw_state)) {
+		WARN(1, "Could not get bw_state\n");
+		return;
+	}
+
+	for_each_new_intel_crtc_in_state(state, crtc,
+					 new_crtc_state, i) {
+		if (skl_can_enable_sagv_on_pipe(state, crtc->pipe))
+			new_bw_state->pipe_sagv_mask |= BIT(crtc->pipe);
+		else
+			new_bw_state->pipe_sagv_mask &= ~BIT(crtc->pipe);
+	}
+}
+
+void intel_compute_sagv_mask(struct intel_atomic_state *state, int total_affected_planes)
+{
+	int ret;
+	struct drm_device *dev = state->base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct intel_bw_state *new_bw_state = intel_atomic_get_bw_state(state);
+	struct intel_bw_state *old_bw_state = intel_atomic_get_old_bw_state(state);
+
+	if (IS_ERR(new_bw_state) || IS_ERR(old_bw_state)) {
+		WARN(1, "Could not get bw_state\n");
+		return;
+	}
+
+	/*
+	 * If active_pipes had changed, means we have added/removed crtc,
+	 * if total_affected_planes had changed - means we have changed wm/ddb.
+	 * Both require SAGV recalculation - otherwise just return and SAGV mask
+	 * will stay the same.
+	 * Also we will have crtc locks grabbed only in mentioned above cases.
+	 */
+	if ((state->active_pipes == dev_priv->active_pipes) &&
+	    (total_affected_planes == 0))
+		return;
+
+	/*
+	 * Now once we got wm levels calculated,
+	 * check if we can have SAGV.
+	 */
+	if (INTEL_GEN(dev_priv) >= 12)
+		tgl_compute_sagv_mask(state);
+	else if (INTEL_GEN(dev_priv) == 11)
+		icl_compute_sagv_mask(state);
+	else
+		skl_compute_sagv_mask(state);
+
+	state->sagv_calculated = true;
+
+	/*
+	 * For SAGV we need to account all the pipes,
+	 * not only the ones which are in state currently.
+	 * Grab all locks if we detect that we are actually
+	 * going to do something.
+	 */
+	if (new_bw_state->pipe_sagv_mask != old_bw_state->pipe_sagv_mask) {
+		ret = intel_atomic_serialize_global_state(&new_bw_state->base);
+		if (ret) {
+			DRM_DEBUG_KMS("Could not serialize global state\n");
+			return;
+		}
+	}
+}
+
+/*
+ * This function to be used before swap state
+ */
+bool intel_can_enable_sagv_for_state(struct intel_atomic_state *state)
+{
+	struct drm_device *dev = state->base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	int i;
+	struct intel_crtc *crtc;
+	struct intel_crtc_state *new_crtc_state;
+	struct intel_bw_state *new_bw_state  = intel_atomic_get_bw_state(state);
+
+	if (IS_ERR(new_bw_state)) {
+		WARN(1, "Could not get bw_state\n");
+		return false;
+	}
+
+	if (!intel_has_sagv(dev_priv)) {
+		DRM_DEBUG_KMS("No SAGV support detected\n");
+		return false;
+	}
+
+	/*
+	 * Should have this calculated by that time,
+	 * means something got changed or wrong in the driver
+	 * currently, supposed places which call this function are:
+	 * intel_atomic_commit_tail, intel_atomic_bw_check,
+	 * skl_allocate_pipe_ddb, skl_write_plane_wm.
+	 * All of those are supposed to be called after
+	 * skl_compute_wm->intel_compute_sagv_mask is called.
+	 */
+	drm_WARN_ON(&dev_priv->drm, !state->sagv_calculated);
+
+	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+		u32 mask = BIT(crtc->pipe);
+		bool state_sagv_masked = (mask & new_bw_state->pipe_sagv_mask) == 0;
+
+		if (!new_crtc_state->hw.active)
+			continue;
+
+		if (state_sagv_masked)
 			return false;
 	}
 
@@ -3842,6 +3980,34 @@ static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv)
 	return ddb_size;
 }
 
+/*
+ * To be used after we swap state
+ */
+bool intel_can_enable_sagv(struct drm_i915_private *dev_priv)
+{
+	int i;
+	struct intel_global_state *global_state;
+	struct intel_bw_state *bw_state;
+
+	global_state = dev_priv->bw_obj.state;
+	if (IS_ERR(global_state)) {
+		WARN(1, "Could not get global state\n");
+		return false;
+	}
+
+	bw_state = to_intel_bw_state(global_state);
+
+	for (i = 0; i < I915_MAX_PIPES; i++) {
+		int active_pipe_bit = dev_priv->active_pipes & BIT(i);
+		if (active_pipe_bit) {
+			if ((bw_state->pipe_sagv_mask & BIT(i)) == 0)
+				return false;
+		}
+	}
+
+	return true;
+}
+
 static u8 skl_compute_dbuf_slices(const struct intel_crtc_state *crtc_state,
 				  u32 active_pipes);
 
@@ -4028,6 +4194,7 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
 		u32 latency = dev_priv->wm.skl_latency[level];
 
 		skl_compute_plane_wm(crtc_state, level, latency, &wp, &wm, &wm);
+
 		if (wm.min_ddb_alloc == U16_MAX)
 			break;
 
@@ -4554,12 +4721,93 @@ skl_plane_wm_level(struct intel_plane *plane,
 		   int level,
 		   int color_plane)
 {
+	struct drm_atomic_state *state = crtc_state->uapi.state;
+	struct drm_crtc *crtc = crtc_state->uapi.crtc;
+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 	const struct skl_plane_wm *wm =
 		&crtc_state->wm.skl.optimal.planes[plane->id];
 
+	if (!level) {
+		bool can_sagv = false;
+
+		/*
+		 * If we haven't yet swapped our state, we should use
+		 * the state to determine SAGV, otherwise use global
+		 * state as atomic state pointer might become stale
+		 * and zeroed out.
+		 */
+		if (state) {
+			struct intel_atomic_state *intel_state =
+				to_intel_atomic_state(state);
+			can_sagv = intel_can_enable_sagv_for_state(intel_state);
+		} else {
+			can_sagv = intel_can_enable_sagv(dev_priv);
+		}
+
+		if (can_sagv)
+			return color_plane ? &wm->uv_sagv_wm0 : &wm->sagv_wm0;
+	}
+
 	return color_plane ? &wm->uv_wm[level] : &wm->wm[level];
 }
 
+static int
+tgl_check_pipe_fits_sagv_wm(struct intel_crtc_state *crtc_state)
+{
+	struct drm_crtc *crtc = crtc_state->uapi.crtc;
+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
+	u16 alloc_size;
+	u64 total_data_rate;
+	enum plane_id plane_id;
+	int num_active;
+	u64 plane_data_rate[I915_MAX_PLANES] = {};
+	u32 blocks;
+
+	/*
+	 * No need to check gen here, we call this only for gen12
+	 */
+	total_data_rate =
+		icl_get_total_relative_data_rate(crtc_state,
+						 plane_data_rate);
+
+	skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state,
+					   total_data_rate,
+					   alloc, &num_active);
+	alloc_size = skl_ddb_entry_size(alloc);
+	if (alloc_size == 0)
+		return -ENOSPC;
+
+	/*
+	 * Do check if we can fit L0 + sagv_block_time and
+	 * disable SAGV if we can't.
+	 */
+	blocks = 0;
+	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
+		/*
+		 * The only place, where we can't use skl_plane_wm_level
+		 * accessor, because if actually calls intel_can_enable_sagv
+		 * which depends on that function.
+		 */
+		const struct skl_plane_wm *wm =
+			&crtc_state->wm.skl.optimal.planes[plane_id];
+
+		blocks += wm->sagv_wm0.min_ddb_alloc;
+		blocks += wm->uv_sagv_wm0.min_ddb_alloc;
+
+		if (blocks > alloc_size) {
+			DRM_DEBUG_KMS("Not enough ddb blocks(%d<%d) for SAGV on pipe %c\n",
+				      alloc_size, blocks, pipe_name(intel_crtc->pipe));
+			return -ENOSPC;
+		}
+	}
+	DRM_DEBUG_KMS("%d total blocks required for SAGV, ddb entry size %d\n",
+		      blocks, alloc_size);
+	return 0;
+}
+
+
 static int
 skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
 {
@@ -5143,11 +5391,19 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
 static void
 skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
 		      const struct skl_wm_params *wm_params,
-		      struct skl_wm_level *levels)
+		      struct skl_plane_wm *plane_wm,
+		      bool yuv)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 	int level, max_level = ilk_wm_max_level(dev_priv);
+	/*
+	 * Check which kind of plane is it and based on that calculate
+	 * correspondent WM levels.
+	 */
+	struct skl_wm_level *levels = yuv ? plane_wm->uv_wm : plane_wm->wm;
 	struct skl_wm_level *result_prev = &levels[0];
+	struct skl_wm_level *sagv_wm = yuv ?
+				&plane_wm->uv_sagv_wm0 : &plane_wm->sagv_wm0;
 
 	for (level = 0; level <= max_level; level++) {
 		struct skl_wm_level *result = &levels[level];
@@ -5158,6 +5414,27 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
 
 		result_prev = result;
 	}
+	/*
+	 * For Gen12 if it is an L0 we need to also
+	 * consider sagv_block_time when calculating
+	 * L0 watermark - we will need that when making
+	 * a decision whether enable SAGV or not.
+	 * For older gens we agreed to copy L0 value for
+	 * compatibility.
+	 */
+	if ((INTEL_GEN(dev_priv) >= 12)) {
+		u32 latency = dev_priv->wm.skl_latency[0];
+
+		latency += dev_priv->sagv_block_time_us;
+		skl_compute_plane_wm(crtc_state, 0, latency,
+				     wm_params, &levels[0],
+				     sagv_wm);
+		DRM_DEBUG_KMS("%d L0 blocks required for SAGV vs %d for non-SAGV\n",
+			      sagv_wm->min_ddb_alloc, levels[0].min_ddb_alloc);
+	} else {
+		/* Since all members are POD */
+		*sagv_wm = levels[0];
+	}
 }
 
 static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
@@ -5232,7 +5509,7 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
 	if (ret)
 		return ret;
 
-	skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
+	skl_compute_wm_levels(crtc_state, &wm_params, wm, false);
 	skl_compute_transition_wm(crtc_state, &wm_params, wm);
 
 	return 0;
@@ -5254,7 +5531,7 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
 	if (ret)
 		return ret;
 
-	skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
+	skl_compute_wm_levels(crtc_state, &wm_params, wm, true);
 
 	return 0;
 }
@@ -5585,10 +5862,29 @@ skl_print_wm_changes(struct intel_atomic_state *state)
 		for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
 			enum plane_id plane_id = plane->id;
 			const struct skl_plane_wm *old_wm, *new_wm;
+			u16 old_plane_res_l, new_plane_res_l;
+			u8  old_plane_res_b, new_plane_res_b;
+			u16 old_min_ddb_alloc, new_min_ddb_alloc;
 
 			old_wm = &old_pipe_wm->planes[plane_id];
 			new_wm = &new_pipe_wm->planes[plane_id];
 
+			old_plane_res_l = intel_can_enable_sagv(dev_priv) ?
+					  old_wm->sagv_wm0.plane_res_l : old_wm->wm[0].plane_res_l;
+			old_plane_res_b = intel_can_enable_sagv(dev_priv) ?
+					  old_wm->sagv_wm0.plane_res_b : old_wm->wm[0].plane_res_b;
+
+			new_plane_res_l = intel_can_enable_sagv_for_state(state) ?
+					  new_wm->sagv_wm0.plane_res_l : new_wm->wm[0].plane_res_l;
+			new_plane_res_b = intel_can_enable_sagv_for_state(state) ?
+					  new_wm->sagv_wm0.plane_res_b : new_wm->wm[0].plane_res_b;
+
+			old_min_ddb_alloc = intel_can_enable_sagv(dev_priv) ?
+					    old_wm->sagv_wm0.min_ddb_alloc : old_wm->wm[0].min_ddb_alloc;
+
+			new_min_ddb_alloc = intel_can_enable_sagv_for_state(state) ?
+					    new_wm->sagv_wm0.min_ddb_alloc : new_wm->wm[0].min_ddb_alloc;
+
 			if (skl_plane_wm_equals(dev_priv, old_wm, new_wm))
 				continue;
 
@@ -5611,7 +5907,7 @@ skl_print_wm_changes(struct intel_atomic_state *state)
 				    "[PLANE:%d:%s]   lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d"
 				      " -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d\n",
 				    plane->base.base.id, plane->base.name,
-				    enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].plane_res_l,
+				    enast(old_wm->wm[0].ignore_lines), old_plane_res_l,
 				    enast(old_wm->wm[1].ignore_lines), old_wm->wm[1].plane_res_l,
 				    enast(old_wm->wm[2].ignore_lines), old_wm->wm[2].plane_res_l,
 				    enast(old_wm->wm[3].ignore_lines), old_wm->wm[3].plane_res_l,
@@ -5621,7 +5917,7 @@ skl_print_wm_changes(struct intel_atomic_state *state)
 				    enast(old_wm->wm[7].ignore_lines), old_wm->wm[7].plane_res_l,
 				    enast(old_wm->trans_wm.ignore_lines), old_wm->trans_wm.plane_res_l,
 
-				    enast(new_wm->wm[0].ignore_lines), new_wm->wm[0].plane_res_l,
+				    enast(new_wm->wm[0].ignore_lines), new_plane_res_l,
 				    enast(new_wm->wm[1].ignore_lines), new_wm->wm[1].plane_res_l,
 				    enast(new_wm->wm[2].ignore_lines), new_wm->wm[2].plane_res_l,
 				    enast(new_wm->wm[3].ignore_lines), new_wm->wm[3].plane_res_l,
@@ -5635,12 +5931,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
 				    "[PLANE:%d:%s]  blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
 				    " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
 				    plane->base.base.id, plane->base.name,
-				    old_wm->wm[0].plane_res_b, old_wm->wm[1].plane_res_b,
+				    old_plane_res_b, old_wm->wm[1].plane_res_b,
 				    old_wm->wm[2].plane_res_b, old_wm->wm[3].plane_res_b,
 				    old_wm->wm[4].plane_res_b, old_wm->wm[5].plane_res_b,
 				    old_wm->wm[6].plane_res_b, old_wm->wm[7].plane_res_b,
 				    old_wm->trans_wm.plane_res_b,
-				    new_wm->wm[0].plane_res_b, new_wm->wm[1].plane_res_b,
+				    new_plane_res_b, new_wm->wm[1].plane_res_b,
 				    new_wm->wm[2].plane_res_b, new_wm->wm[3].plane_res_b,
 				    new_wm->wm[4].plane_res_b, new_wm->wm[5].plane_res_b,
 				    new_wm->wm[6].plane_res_b, new_wm->wm[7].plane_res_b,
@@ -5650,12 +5946,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
 				    "[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
 				    " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
 				    plane->base.base.id, plane->base.name,
-				    old_wm->wm[0].min_ddb_alloc, old_wm->wm[1].min_ddb_alloc,
+				    old_min_ddb_alloc, old_wm->wm[1].min_ddb_alloc,
 				    old_wm->wm[2].min_ddb_alloc, old_wm->wm[3].min_ddb_alloc,
 				    old_wm->wm[4].min_ddb_alloc, old_wm->wm[5].min_ddb_alloc,
 				    old_wm->wm[6].min_ddb_alloc, old_wm->wm[7].min_ddb_alloc,
 				    old_wm->trans_wm.min_ddb_alloc,
-				    new_wm->wm[0].min_ddb_alloc, new_wm->wm[1].min_ddb_alloc,
+				    new_min_ddb_alloc, new_wm->wm[1].min_ddb_alloc,
 				    new_wm->wm[2].min_ddb_alloc, new_wm->wm[3].min_ddb_alloc,
 				    new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc,
 				    new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc,
@@ -5755,7 +6051,8 @@ skl_ddb_add_affected_pipes(struct intel_atomic_state *state)
  * default value of the watermarks registers is not zero.
  */
 static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
-				      struct intel_crtc *crtc)
+				      struct intel_crtc *crtc,
+				      int *num_affected_planes)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	const struct intel_crtc_state *old_crtc_state =
@@ -5764,6 +6061,8 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
 		intel_atomic_get_new_crtc_state(state, crtc);
 	struct intel_plane *plane;
 
+	*num_affected_planes = 0;
+
 	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
 		struct intel_plane_state *plane_state;
 		enum plane_id plane_id = plane->id;
@@ -5787,11 +6086,64 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
 			return PTR_ERR(plane_state);
 
 		new_crtc_state->update_planes |= BIT(plane_id);
+		*num_affected_planes += 1;
 	}
 
 	return 0;
 }
 
+static void tgl_compute_sagv_mask(struct intel_atomic_state *state)
+{
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+	struct intel_crtc *crtc;
+	struct intel_crtc_state *new_crtc_state;
+	struct intel_crtc_state *old_crtc_state;
+	int ret;
+	int i;
+	struct intel_plane *plane;
+	struct intel_bw_state *new_bw_state  = intel_atomic_get_bw_state(state);
+
+	if (IS_ERR(new_bw_state)) {
+		WARN(1, "Could not get bw_state\n");
+		return;
+	}
+
+	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+					    new_crtc_state, i) {
+		int pipe_bit = BIT(crtc->pipe);
+		bool skip = true;
+
+		/*
+		 * If we had set this mast already once for this state,
+		 * no need to waste CPU cycles for doing this again.
+		 */
+		for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
+			enum plane_id plane_id = plane->id;
+
+			if (!skl_plane_wm_equals(dev_priv,
+						 &old_crtc_state->wm.skl.optimal.planes[plane_id],
+						 &new_crtc_state->wm.skl.optimal.planes[plane_id])) {
+				skip = false;
+				break;
+			}
+		}
+
+		/*
+		 * Check if wm levels are actually the same as for previous
+		 * state, which means we can just skip doing this long check
+		 * and just  copy correspondent bit from previous state.
+		 */
+		if (skip)
+			continue;
+
+		ret = tgl_check_pipe_fits_sagv_wm(new_crtc_state);
+		if (!ret)
+			new_bw_state->pipe_sagv_mask |= pipe_bit;
+		else
+			new_bw_state->pipe_sagv_mask &= ~pipe_bit;
+	}
+}
+
 static int
 skl_compute_wm(struct intel_atomic_state *state)
 {
@@ -5799,6 +6151,7 @@ skl_compute_wm(struct intel_atomic_state *state)
 	struct intel_crtc_state *new_crtc_state;
 	struct intel_crtc_state *old_crtc_state;
 	int ret, i;
+	int affected_planes; int total_affected_planes = 0;
 
 	ret = skl_ddb_add_affected_pipes(state);
 	if (ret)
@@ -5815,11 +6168,15 @@ skl_compute_wm(struct intel_atomic_state *state)
 		if (ret)
 			return ret;
 
-		ret = skl_wm_add_affected_planes(state, crtc);
+		ret = skl_wm_add_affected_planes(state, crtc, &affected_planes);
 		if (ret)
 			return ret;
+
+		total_affected_planes += affected_planes;
 	}
 
+	intel_compute_sagv_mask(state, total_affected_planes);
+
 	ret = skl_compute_ddb(state);
 	if (ret)
 		return ret;
@@ -5939,6 +6296,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
 				val = I915_READ(CUR_WM(pipe, level));
 
 			skl_wm_level_from_reg_val(val, &wm->wm[level]);
+			if (level == 0)
+				memcpy(&wm->sagv_wm0, &wm->wm[level],
+				       sizeof(struct skl_wm_level));
 		}
 
 		if (plane_id != PLANE_CURSOR)
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index d60a85421c5a..561a17a5d4e0 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -41,7 +41,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
 			      struct skl_pipe_wm *out);
 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
-bool intel_can_enable_sagv(struct intel_atomic_state *state);
+bool intel_can_enable_sagv(struct drm_i915_private *dev_priv);
+bool intel_can_enable_sagv_for_state(struct intel_atomic_state *state);
+bool intel_has_sagv(struct drm_i915_private *dev_priv);
 int intel_enable_sagv(struct drm_i915_private *dev_priv);
 int intel_disable_sagv(struct drm_i915_private *dev_priv);
 bool skl_wm_level_equals(const struct skl_wm_level *l1,
-- 
2.24.1.485.gad05a3d8e5

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v16 5/7] drm/i915: Added required new PCode commands

[Stanislav Lisovskiy]

We need a new PCode request commands and reply codes
to be added as a prepartion patch for QGV points
restricting for new SAGV support.

v2: - Extracted those changes into separate patch
      (Ville Syrjälä)

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h       | 4 ++++
 drivers/gpu/drm/i915/intel_sideband.c | 2 ++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b09c1d6dc0aa..b3924e9d25bc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8997,6 +8997,7 @@ enum {
 #define     GEN7_PCODE_ILLEGAL_DATA		0x3
 #define     GEN11_PCODE_ILLEGAL_SUBCOMMAND	0x4
 #define     GEN11_PCODE_LOCKED			0x6
+#define     GEN11_PCODE_REJECTED		0x11
 #define     GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
 #define   GEN6_PCODE_WRITE_RC6VIDS		0x4
 #define   GEN6_PCODE_READ_RC6VIDS		0x5
@@ -9018,6 +9019,7 @@ enum {
 #define   ICL_PCODE_MEM_SUBSYSYSTEM_INFO	0xd
 #define     ICL_PCODE_MEM_SS_READ_GLOBAL_INFO	(0x0 << 8)
 #define     ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point)	(((point) << 16) | (0x1 << 8))
+#define   ICL_PCODE_SAGV_DE_MEM_SS_CONFIG	0xe
 #define   GEN6_PCODE_READ_D_COMP		0x10
 #define   GEN6_PCODE_WRITE_D_COMP		0x11
 #define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17
@@ -9030,6 +9032,8 @@ enum {
 #define     GEN9_SAGV_IS_DISABLED		0x1
 #define     GEN9_SAGV_ENABLE			0x3
 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US	0x23
+#define GEN11_PCODE_POINTS_RESTRICTED		0x0
+#define GEN11_PCODE_POINTS_RESTRICTED_MASK	0x1
 #define GEN6_PCODE_DATA				_MMIO(0x138128)
 #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
 #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT	16
diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index 1447e7516cb7..1e7dd6b6f103 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -370,6 +370,8 @@ static inline int gen7_check_mailbox_status(u32 mbox)
 		return -ENXIO;
 	case GEN11_PCODE_LOCKED:
 		return -EBUSY;
+	case GEN11_PCODE_REJECTED:
+		return -EACCES;
 	case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
 		return -EOVERFLOW;
 	default:
-- 
2.24.1.485.gad05a3d8e5

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[Intel-gfx] [PATCH v16 6/7] drm/i915: Restrict qgv points which don't have enough bandwidth.

[Stanislav Lisovskiy]

According to BSpec 53998, we should try to
restrict qgv points, which can't provide
enough bandwidth for desired display configuration.

Currently we are just comparing against all of
those and take minimum(worst case).

v2: Fixed wrong PCode reply mask, removed hardcoded
    values.

v3: Forbid simultaneous legacy SAGV PCode requests and
    restricting qgv points. Put the actual restriction
    to commit function, added serialization(thanks to Ville)
    to prevent commit being applied out of order in case of
    nonblocking and/or nomodeset commits.

v4:
    - Minor code refactoring, fixed few typos(thanks to James Ausmus)
    - Change the naming of qgv point
      masking/unmasking functions(James Ausmus).
    - Simplify the masking/unmasking operation itself,
      as we don't need to mask only single point per request(James Ausmus)
    - Reject and stick to highest bandwidth point if SAGV
      can't be enabled(BSpec)

v5:
    - Add new mailbox reply codes, which seems to happen during boot
      time for TGL and indicate that QGV setting is not yet available.

v6:
    - Increase number of supported QGV points to be in sync with BSpec.

v7: - Rebased and resolved conflict to fix build failure.
    - Fix NUM_QGV_POINTS to 8 and moved that to header file(James Ausmus)

v8: - Don't report an error if we can't restrict qgv points, as SAGV
      can be disabled by BIOS, which is completely legal. So don't
      make CI panic. Instead if we detect that there is only 1 QGV
      point accessible just analyze if we can fit the required bandwidth
      requirements, but no need in restricting.

v9: - Fix wrong QGV transition if we have 0 planes and no SAGV
      simultaneously.

v10: - Fix CDCLK corruption, because of global state getting serialized
       without modeset, which caused copying of non-calculated cdclk
       to be copied to dev_priv(thanks to Ville for the hint).

v11: - Remove unneeded headers and spaces(Matthew Roper)
     - Remove unneeded intel_qgv_info qi struct from bw check and zero
       out the needed one(Matthew Roper)
     - Changed QGV error message to have more clear meaning(Matthew Roper)
     - Use state->modeset_set instead of any_ms(Matthew Roper)
     - Moved NUM_SAGV_POINTS from i915_reg.h to i915_drv.h where it's used
     - Keep using crtc_state->hw.active instead of .enable(Matthew Roper)
     - Moved unrelated changes to other patch(using latency as parameter
       for plane wm calculation, moved to SAGV refactoring patch)

v12: - Fix rebase conflict with own temporary SAGV/QGV fix.
     - Remove unnecessary mask being zero check when unmasking
       qgv points as this is completely legal(Matt Roper)
     - Check if we are setting the same mask as already being set
       in hardware to prevent error from PCode.
     - Fix error message when restricting/unrestricting qgv points
       to "mask/unmask" which sounds more accurate(Matt Roper)
     - Move sagv status setting to icl_get_bw_info from atomic check
       as this should be calculated only once.(Matt Roper)
     - Edited comments for the case when we can't enable SAGV and
       use only 1 QGV point with highest bandwidth to be more
       understandable.(Matt Roper)

v13: - Moved max_data_rate in bw check to closer scope(Ville Syrjälä)
     - Changed comment for zero new_mask in qgv points masking function
       to better reflect reality(Ville Syrjälä)
     - Simplified bit mask operation in qgv points masking function
       (Ville Syrjälä)
     - Moved intel_qgv_points_mask closer to gen11 SAGV disabling,
       however this still can't be under modeset condition(Ville Syrjälä)
     - Packed qgv_points_mask as u8 and moved closer to pipe_sagv_mask
       (Ville Syrjälä)
     - Extracted PCode changes to separate patch.(Ville Syrjälä)
     - Now treat num_planes 0 same as 1 to avoid confusion and
       returning max_bw as 0, which would prevent choosing QGV
       point having max bandwidth in case if SAGV is not allowed,
       as per BSpec(Ville Syrjälä)
     - Do the actual qgv_points_mask swap in the same place as
       all other global state parts like cdclk are swapped.
       In the next patch, this all will be moved to bw state as
       global state, once new global state patch series from Ville
       lands

v14: - Now using global state to serialize access to qgv points
     - Added global state locking back, otherwise we seem to read
       bw state in a wrong way.

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Ville Syrjälä <ville.syrjala@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c      | 171 +++++++++++++------
 drivers/gpu/drm/i915/display/intel_bw.h      |   9 +
 drivers/gpu/drm/i915/display/intel_display.c | 109 ++++++++++++
 drivers/gpu/drm/i915/i915_drv.h              |   3 +
 4 files changed, 243 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index ff57277e8880..867bcaa3213b 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -8,6 +8,9 @@
 #include "intel_bw.h"
 #include "intel_display_types.h"
 #include "intel_sideband.h"
+#include "intel_atomic.h"
+#include "intel_pm.h"
+
 
 /* Parameters for Qclk Geyserville (QGV) */
 struct intel_qgv_point {
@@ -113,6 +116,26 @@ static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
 	return 0;
 }
 
+int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
+				  u32 points_mask)
+{
+	int ret;
+
+	/* bspec says to keep retrying for at least 1 ms */
+	ret = skl_pcode_request(dev_priv, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
+				points_mask,
+				GEN11_PCODE_POINTS_RESTRICTED_MASK,
+				GEN11_PCODE_POINTS_RESTRICTED,
+				1);
+
+	if (ret < 0) {
+		DRM_ERROR("Failed to disable qgv points (%d)\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
 static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
 			      struct intel_qgv_info *qi)
 {
@@ -240,6 +263,16 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel
 			break;
 	}
 
+	/*
+	 * In case if SAGV is disabled in BIOS, we always get 1
+	 * SAGV point, but we can't send PCode commands to restrict it
+	 * as it will fail and pointless anyway.
+	 */
+	if (qi.num_points == 1)
+		dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
+	else
+		dev_priv->sagv_status = I915_SAGV_ENABLED;
+
 	return 0;
 }
 
@@ -259,7 +292,7 @@ static unsigned int icl_max_bw(struct drm_i915_private *dev_priv,
 		if (qgv_point >= bi->num_qgv_points)
 			return UINT_MAX;
 
-		if (num_planes >= bi->num_planes)
+		if (num_planes >= bi->num_planes || !num_planes)
 			return bi->deratedbw[qgv_point];
 	}
 
@@ -277,34 +310,6 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
 		icl_get_bw_info(dev_priv, &icl_sa_info);
 }
 
-static unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv,
-					int num_planes)
-{
-	if (INTEL_GEN(dev_priv) >= 11) {
-		/*
-		 * Any bw group has same amount of QGV points
-		 */
-		const struct intel_bw_info *bi =
-			&dev_priv->max_bw[0];
-		unsigned int min_bw = UINT_MAX;
-		int i;
-
-		/*
-		 * FIXME with SAGV disabled maybe we can assume
-		 * point 1 will always be used? Seems to match
-		 * the behaviour observed in the wild.
-		 */
-		for (i = 0; i < bi->num_qgv_points; i++) {
-			unsigned int bw = icl_max_bw(dev_priv, num_planes, i);
-
-			min_bw = min(bw, min_bw);
-		}
-		return min_bw;
-	} else {
-		return UINT_MAX;
-	}
-}
-
 static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state)
 {
 	/*
@@ -417,11 +422,16 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
 {
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 	struct intel_crtc_state *new_crtc_state, *old_crtc_state;
-	struct intel_bw_state *bw_state = NULL;
-	unsigned int data_rate, max_data_rate;
+	struct intel_bw_state *new_bw_state = NULL;
+	struct intel_bw_state *old_bw_state = NULL;
+	unsigned int data_rate;
 	unsigned int num_active_planes;
 	struct intel_crtc *crtc;
 	int i, ret;
+	u32 allowed_points = 0;
+	unsigned int max_bw_point = 0, max_bw = 0;
+	unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points;
+	u32 mask = (1 << num_qgv_points) - 1;
 
 	/* FIXME earlier gens need some checks too */
 	if (INTEL_GEN(dev_priv) < 11)
@@ -446,41 +456,104 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
 		    old_active_planes == new_active_planes)
 			continue;
 
-		bw_state  = intel_atomic_get_bw_state(state);
-		if (IS_ERR(bw_state))
-			return PTR_ERR(bw_state);
+		new_bw_state = intel_atomic_get_bw_state(state);
+		if (IS_ERR(new_bw_state))
+			return PTR_ERR(new_bw_state);
 
-		bw_state->data_rate[crtc->pipe] = new_data_rate;
-		bw_state->num_active_planes[crtc->pipe] = new_active_planes;
+		new_bw_state->data_rate[crtc->pipe] = new_data_rate;
+		new_bw_state->num_active_planes[crtc->pipe] = new_active_planes;
 
 		drm_dbg_kms(&dev_priv->drm,
 			    "pipe %c data rate %u num active planes %u\n",
 			    pipe_name(crtc->pipe),
-			    bw_state->data_rate[crtc->pipe],
-			    bw_state->num_active_planes[crtc->pipe]);
+			    new_bw_state->data_rate[crtc->pipe],
+			    new_bw_state->num_active_planes[crtc->pipe]);
 	}
 
-	if (!bw_state)
+	if (!new_bw_state)
 		return 0;
 
-	ret = intel_atomic_lock_global_state(&bw_state->base);
-	if (ret)
+	ret = intel_atomic_lock_global_state(&new_bw_state->base);
+	if (ret) {
+		DRM_DEBUG_KMS("Could not lock global state\n");
 		return ret;
+	}
 
-	data_rate = intel_bw_data_rate(dev_priv, bw_state);
-	num_active_planes = intel_bw_num_active_planes(dev_priv, bw_state);
-
-	max_data_rate = intel_max_data_rate(dev_priv, num_active_planes);
+	data_rate = intel_bw_data_rate(dev_priv, new_bw_state);
+	num_active_planes = intel_bw_num_active_planes(dev_priv, new_bw_state);
 
 	data_rate = DIV_ROUND_UP(data_rate, 1000);
 
-	if (data_rate > max_data_rate) {
-		drm_dbg_kms(&dev_priv->drm,
-			    "Bandwidth %u MB/s exceeds max available %d MB/s (%d active planes)\n",
-			    data_rate, max_data_rate, num_active_planes);
+	for (i = 0; i < num_qgv_points; i++) {
+		unsigned int max_data_rate;
+
+		max_data_rate = icl_max_bw(dev_priv, num_active_planes, i);
+		/*
+		 * We need to know which qgv point gives us
+		 * maximum bandwidth in order to disable SAGV
+		 * if we find that we exceed SAGV block time
+		 * with watermarks. By that moment we already
+		 * have those, as it is calculated earlier in
+		 * intel_atomic_check,
+		 */
+		if (max_data_rate > max_bw) {
+			max_bw_point = i;
+			max_bw = max_data_rate;
+		}
+		if (max_data_rate >= data_rate)
+			allowed_points |= BIT(i);
+		DRM_DEBUG_KMS("QGV point %d: max bw %d required %d\n",
+			      i, max_data_rate, data_rate);
+	}
+
+	/*
+	 * BSpec states that we always should have at least one allowed point
+	 * left, so if we couldn't - simply reject the configuration for obvious
+	 * reasons.
+	 */
+	if (allowed_points == 0) {
+		DRM_DEBUG_KMS("No QGV points provide sufficient memory"
+			      " bandwidth for display configuration.\n");
 		return -EINVAL;
 	}
 
+	/*
+	 * Leave only single point with highest bandwidth, if
+	 * we can't enable SAGV due to the increased memory latency it may
+	 * cause.
+	 */
+	if (!intel_can_enable_sagv_for_state(state)) {
+		allowed_points = 1 << max_bw_point;
+		DRM_DEBUG_KMS("No SAGV, using single QGV point %d\n",
+			      max_bw_point);
+	}
+	/*
+	 * We store the ones which need to be masked as that is what PCode
+	 * actually accepts as a parameter.
+	 */
+	new_bw_state->qgv_points_mask = (~allowed_points) & mask;
+
+	DRM_DEBUG_KMS("New state %p qgv mask %x\n",
+		      state, new_bw_state->qgv_points_mask);
+
+	old_bw_state = intel_atomic_get_old_bw_state(state);
+	if (IS_ERR(old_bw_state)) {
+		DRM_DEBUG_KMS("Could not get old bw state!\n");
+		return PTR_ERR(old_bw_state);
+	}
+
+	/*
+	 * If the actual mask had changed we need to make sure that
+	 * the commits are serialized(in case this is a nomodeset, nonblocking)
+	 */
+	if (new_bw_state->qgv_points_mask != old_bw_state->qgv_points_mask) {
+		ret = intel_atomic_serialize_global_state(&new_bw_state->base);
+		if (ret) {
+			DRM_DEBUG_KMS("Could not serialize global state\n");
+			return ret;
+		}
+	}
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index 6c33d3af50a9..64e8c16934a6 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -24,6 +24,13 @@ struct intel_bw_state {
 	 */
 	u8 pipe_sagv_mask;
 
+	/*
+	 * Current QGV points mask, which restricts
+	 * some particular SAGV states, not to confuse
+	 * with pipe_sagv_mask.
+	 */
+	u8 qgv_points_mask;
+
 	unsigned int data_rate[I915_MAX_PIPES];
 	u8 num_active_planes[I915_MAX_PIPES];
 };
@@ -44,5 +51,7 @@ int intel_bw_init(struct drm_i915_private *dev_priv);
 int intel_bw_atomic_check(struct intel_atomic_state *state);
 void intel_bw_crtc_update(struct intel_bw_state *bw_state,
 			  const struct intel_crtc_state *crtc_state);
+int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
+				  u32 points_mask);
 
 #endif /* __INTEL_BW_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ef2e9155090f..fdc03f09dc64 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15676,6 +15676,105 @@ static void intel_atomic_cleanup_work(struct work_struct *work)
 	intel_atomic_helper_free_state(i915);
 }
 
+static void intel_qgv_points_mask(struct intel_atomic_state *state)
+{
+	struct drm_device *dev = state->base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	int ret;
+	struct intel_bw_state *new_bw_state = NULL;
+	struct intel_bw_state *old_bw_state = NULL;
+	u32 new_mask = 0;
+	unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points;
+	unsigned int mask = (1 << num_qgv_points) - 1;
+
+	new_bw_state = intel_atomic_get_bw_state(state);
+	if (IS_ERR(new_bw_state)) {
+		WARN(1, "Could not get new bw_state!\n");
+		return;
+	}
+
+	old_bw_state = intel_atomic_get_old_bw_state(state);
+	if (IS_ERR(old_bw_state)) {
+		WARN(1, "Could not get old bw_state!\n");
+		return;
+	}
+
+	new_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask;
+
+	/*
+	 * If new mask is zero - means there is nothing to mask,
+	 * we can only unmask, which should be done in unmask.
+	 */
+	if (!new_mask)
+		return;
+
+	WARN_ON(new_mask == mask);
+
+	/*
+	 * Just return if we can't control SAGV or don't have it.
+	 */
+	if (!intel_has_sagv(dev_priv))
+		return;
+
+	/*
+	 * Restrict required qgv points before updating the configuration.
+	 * According to BSpec we can't mask and unmask qgv points at the same
+	 * time. Also masking should be done before updating the configuration
+	 * and unmasking afterwards.
+	 */
+	ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
+	if (ret < 0)
+		DRM_DEBUG_KMS("Could not mask required qgv points(%d)\n",
+			      ret);
+}
+
+static void intel_qgv_points_unmask(struct intel_atomic_state *state)
+{
+	struct drm_device *dev = state->base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	int ret;
+	struct intel_bw_state *new_bw_state = NULL;
+	struct intel_bw_state *old_bw_state = NULL;
+	u32 new_mask = 0;
+
+	new_bw_state = intel_atomic_get_bw_state(state);
+	if (IS_ERR(new_bw_state)) {
+		WARN(1, "Could not get new bw_state!\n");
+		return;
+	}
+
+	old_bw_state = intel_atomic_get_old_bw_state(state);
+	if (IS_ERR(old_bw_state)) {
+		WARN(1, "Could not get new bw_state!\n");
+		return;
+	}
+
+	new_mask = new_bw_state->qgv_points_mask;
+
+	/*
+	 * Just return if we can't control SAGV or don't have it.
+	 */
+	if (!intel_has_sagv(dev_priv))
+		return;
+
+	/*
+	 * Nothing to unmask
+	 */
+	if (new_mask == old_bw_state->qgv_points_mask)
+		return;
+
+	/*
+	 * Allow required qgv points after updating the configuration.
+	 * According to BSpec we can't mask and unmask qgv points at the same
+	 * time. Also masking should be done before updating the configuration
+	 * and unmasking afterwards.
+	 */
+	ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
+	if (ret < 0)
+		DRM_DEBUG_KMS("Could not unmask required qgv points(%d)\n",
+			      ret);
+}
+
 static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 {
 	struct drm_device *dev = state->base.dev;
@@ -15709,6 +15808,14 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
 		crtc->config = new_crtc_state;
 
+	/*
+	 * Now we need to check if SAGV needs to be disabled(i.e QGV points
+	 * modified even, when no modeset is done(for example plane updates
+	 * can now trigger that).
+	 */
+	if ((INTEL_GEN(dev_priv) >= 11))
+		intel_qgv_points_mask(state);
+
 	if (state->modeset) {
 		drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
 
@@ -15823,6 +15930,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	if (INTEL_GEN(dev_priv) < 11) {
 		if (state->modeset && intel_can_enable_sagv(dev_priv))
 			intel_enable_sagv(dev_priv);
+	} else {
+		intel_qgv_points_unmask(state);
 	}
 
 	drm_atomic_helper_commit_hw_done(&state->base);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3330b538d379..c066bbef1609 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -841,6 +841,9 @@ enum intel_pipe_crc_source {
 	INTEL_PIPE_CRC_SOURCE_MAX,
 };
 
+/* BSpec precisely defines this */
+#define NUM_SAGV_POINTS 8
+
 #define INTEL_PIPE_CRC_ENTRIES_NR	128
 struct intel_pipe_crc {
 	spinlock_t lock;
-- 
2.24.1.485.gad05a3d8e5

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[Intel-gfx] [PATCH v16 7/7] drm/i915: Enable SAGV support for Gen12

[Stanislav Lisovskiy]

Flip the switch and enable SAGV support
for Gen12 also.

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e8f10a413808..31c3dc19fbdd 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3624,10 +3624,6 @@ static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
 bool
 intel_has_sagv(struct drm_i915_private *dev_priv)
 {
-	/* HACK! */
-	if (IS_GEN(dev_priv, 12))
-		return false;
-
 	return (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) &&
 		dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
 }
-- 
2.24.1.485.gad05a3d8e5

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Refactor Gen11+ SAGV support

[Patchwork]

== Series Details ==

Series: Refactor Gen11+ SAGV support
URL   : https://patchwork.freedesktop.org/series/73584/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
1c72d442abeb drm/i915: Start passing latency as parameter
b0f9bed0c1be drm/i915: Introduce skl_plane_wm_level accessor.
f8c8b7d5f472 drm/i915: Init obj state in intel_atomic_get_old/new_global_obj_state
-:12: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#12: 
also in intel_atomic_get_old_global_obj_state and intel_atomic_get_new_global_obj_state

-:45: WARNING:LINE_SPACING: Missing a blank line after declarations
#45: FILE: drivers/gpu/drm/i915/display/intel_bw.c:395:
+	struct intel_global_state *bw_state;
+	bw_state = intel_atomic_get_new_global_obj_state(state, &dev_priv->bw_obj);

total: 0 errors, 2 warnings, 0 checks, 49 lines checked
fe62c40aa234 drm/i915: Refactor intel_can_enable_sagv
-:77: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#77: 
      when using skl_plane_wm_level accessor, as we had previously for Gen11+

-:203: CHECK:LINE_SPACING: Please don't use multiple blank lines
#203: FILE: drivers/gpu/drm/i915/display/intel_global_state.h:87:
 
+

-:298: CHECK:LINE_SPACING: Please don't use multiple blank lines
#298: FILE: drivers/gpu/drm/i915/intel_pm.c:3812:
+
+

-:357: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 'state->active_pipes == dev_priv->active_pipes'
#357: FILE: drivers/gpu/drm/i915/intel_pm.c:3871:
+	if ((state->active_pipes == dev_priv->active_pipes) &&
+	    (total_affected_planes == 0))

-:357: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 'total_affected_planes == 0'
#357: FILE: drivers/gpu/drm/i915/intel_pm.c:3871:
+	if ((state->active_pipes == dev_priv->active_pipes) &&
+	    (total_affected_planes == 0))

-:456: WARNING:LINE_SPACING: Missing a blank line after declarations
#456: FILE: drivers/gpu/drm/i915/intel_pm.c:4002:
+		int active_pipe_bit = dev_priv->active_pipes & BIT(i);
+		if (active_pipe_bit) {

-:566: CHECK:LINE_SPACING: Please don't use multiple blank lines
#566: FILE: drivers/gpu/drm/i915/intel_pm.c:4810:
+
+

-:659: WARNING:LONG_LINE: line over 100 characters
#659: FILE: drivers/gpu/drm/i915/intel_pm.c:5883:
+					    old_wm->sagv_wm0.min_ddb_alloc : old_wm->wm[0].min_ddb_alloc;

-:662: WARNING:LONG_LINE: line over 100 characters
#662: FILE: drivers/gpu/drm/i915/intel_pm.c:5886:
+					    new_wm->sagv_wm0.min_ddb_alloc : new_wm->wm[0].min_ddb_alloc;

-:774: WARNING:LONG_LINE: line over 100 characters
#774: FILE: drivers/gpu/drm/i915/intel_pm.c:6125:
+						 &new_crtc_state->wm.skl.optimal.planes[plane_id])) {

total: 0 errors, 5 warnings, 5 checks, 702 lines checked
5c948ee6e68b drm/i915: Added required new PCode commands
d54a20f1dbff drm/i915: Restrict qgv points which don't have enough bandwidth.
ce7aae32b76b drm/i915: Enable SAGV support for Gen12

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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Refactor Gen11+ SAGV support

[Patchwork]

== Series Details ==

Series: Refactor Gen11+ SAGV support
URL   : https://patchwork.freedesktop.org/series/73584/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915: Start passing latency as parameter
Okay!

Commit: drm/i915: Introduce skl_plane_wm_level accessor.
Okay!

Commit: drm/i915: Init obj state in intel_atomic_get_old/new_global_obj_state
Okay!

Commit: drm/i915: Refactor intel_can_enable_sagv
+drivers/gpu/drm/i915/intel_pm.c:3851:6: warning: symbol 'intel_compute_sagv_mask' was not declared. Should it be static?

Commit: drm/i915: Added required new PCode commands
Okay!

Commit: drm/i915: Restrict qgv points which don't have enough bandwidth.
Okay!

Commit: drm/i915: Enable SAGV support for Gen12
Okay!

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[Intel-gfx] ✓ Fi.CI.BAT: success for Refactor Gen11+ SAGV support

[Patchwork]

== Series Details ==

Series: Refactor Gen11+ SAGV support
URL   : https://patchwork.freedesktop.org/series/73584/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7963 -> Patchwork_16601
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16601/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_16601:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@kms_busy@basic@flip}:
    - fi-icl-guc:         [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7963/fi-icl-guc/igt@kms_busy@basic@flip.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16601/fi-icl-guc/igt@kms_busy@basic@flip.html
    - {fi-tgl-u}:         [PASS][3] -> [INCOMPLETE][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7963/fi-tgl-u/igt@kms_busy@basic@flip.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16601/fi-tgl-u/igt@kms_busy@basic@flip.html
    - fi-skl-guc:         [PASS][5] -> [INCOMPLETE][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7963/fi-skl-guc/igt@kms_busy@basic@flip.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16601/fi-skl-guc/igt@kms_busy@basic@flip.html
    - fi-icl-y:           [PASS][7] -> [INCOMPLETE][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7963/fi-icl-y/igt@kms_busy@basic@flip.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16601/fi-icl-y/igt@kms_busy@basic@flip.html
    - fi-skl-6700k2:      [PASS][9] -> [INCOMPLETE][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7963/fi-skl-6700k2/igt@kms_busy@basic@flip.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16601/fi-skl-6700k2/igt@kms_busy@basic@flip.html
    - fi-icl-u2:          [PASS][11] -> [INCOMPLETE][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7963/fi-icl-u2/igt@kms_busy@basic@flip.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16601/fi-icl-u2/igt@kms_busy@basic@flip.html
    - {fi-tgl-dsi}:       [PASS][13] -> [INCOMPLETE][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7963/fi-tgl-dsi/igt@kms_busy@basic@flip.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16601/fi-tgl-dsi/igt@kms_busy@basic@flip.html
    - fi-icl-dsi:         [PASS][15] -> [INCOMPLETE][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7963/fi-icl-dsi/igt@kms_busy@basic@flip.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16601/fi-icl-dsi/igt@kms_busy@basic@flip.html

  * igt@runner@aborted:
    - {fi-ehl-1}:         NOTRUN -> [FAIL][17]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16601/fi-ehl-1/igt@runner@aborted.html

  
Known issues
------------

  Here are the changes found in Patchwork_16601 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@debugfs_test@read_all_entries:
    - fi-icl-u3:          [PASS][18] -> [DMESG-WARN][19] ([i915#585]) +3 similar issues
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7963/fi-icl-u3/igt@debugfs_test@read_all_entries.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16601/fi-icl-u3/igt@debugfs_test@read_all_entries.html

  
#### Possible fixes ####

  * igt@gem_exec_parallel@contexts:
    - {fi-ehl-1}:         [INCOMPLETE][20] ([i915#937]) -> [PASS][21]
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7963/fi-ehl-1/igt@gem_exec_parallel@contexts.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16601/fi-ehl-1/igt@gem_exec_parallel@contexts.html

  
#### Warnings ####

  * igt@runner@aborted:
    - fi-kbl-8809g:       [FAIL][22] ([i915#1209]) -> [FAIL][23] ([i915#192] / [i915#193] / [i915#194])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7963/fi-kbl-8809g/igt@runner@aborted.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16601/fi-kbl-8809g/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#1209]: https://gitlab.freedesktop.org/drm/intel/issues/1209
  [i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192
  [i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193
  [i915#194]: https://gitlab.freedesktop.org/drm/intel/issues/194
  [i915#283]: https://gitlab.freedesktop.org/drm/intel/issues/283
  [i915#585]: https://gitlab.freedesktop.org/drm/intel/issues/585
  [i915#937]: https://gitlab.freedesktop.org/drm/intel/issues/937


Participating hosts (50 -> 30)
------------------------------

  Missing    (20): fi-kbl-soraka fi-ilk-m540 fi-bxt-dsi fi-bsw-n3050 fi-byt-j1900 fi-hsw-4200u fi-hsw-peppy fi-glk-dsi fi-bsw-cyan fi-cfl-8700k fi-apl-guc fi-cfl-guc fi-ctg-p8600 fi-kbl-x1275 fi-cfl-8109u fi-bsw-kefka fi-skl-lmem fi-bdw-samus fi-skl-6600u fi-kbl-r 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7963 -> Patchwork_16601

  CI-20190529: 20190529
  CI_DRM_7963: e0d737598eb749378a5dc4ed3dfafc6f79d512cb @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5448: 116020b1f83c1b3994c76882df7f77b6731d78ba @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_16601: ce7aae32b76b920bba50abdd8229982f18539845 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

ce7aae32b76b drm/i915: Enable SAGV support for Gen12
d54a20f1dbff drm/i915: Restrict qgv points which don't have enough bandwidth.
5c948ee6e68b drm/i915: Added required new PCode commands
fe62c40aa234 drm/i915: Refactor intel_can_enable_sagv
f8c8b7d5f472 drm/i915: Init obj state in intel_atomic_get_old/new_global_obj_state
b0f9bed0c1be drm/i915: Introduce skl_plane_wm_level accessor.
1c72d442abeb drm/i915: Start passing latency as parameter

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16601/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v16 4/7] drm/i915: Refactor intel_can_enable_sagv

[Stanislav Lisovskiy]

Currently intel_can_enable_sagv function contains
a mix of workarounds for different platforms
some of them are not valid for gens >= 11 already,
so lets split it into separate functions.

v2:
    - Rework watermark calculation algorithm to
      attempt to calculate Level 0 watermark
      with added sagv block time latency and
      check if it fits in DBuf in order to
      determine if SAGV can be enabled already
      at this stage, just as BSpec 49325 states.
      if that fails rollback to usual Level 0
      latency and disable SAGV.
    - Remove unneeded tabs(James Ausmus)

v3: Rebased the patch

v4: - Added back interlaced check for Gen12 and
      added separate function for TGL SAGV check
      (thanks to James Ausmus for spotting)
    - Removed unneeded gen check
    - Extracted Gen12 SAGV decision making code
      to a separate function from skl_compute_wm

v5: - Added SAGV global state to dev_priv, because
      we need to track all pipes, not only those
      in atomic state. Each pipe has now correspondent
      bit mask reflecting, whether it can tolerate
      SAGV or not(thanks to Ville Syrjala for suggestions).
    - Now using active flag instead of enable in crc
      usage check.

v6: - Fixed rebase conflicts

v7: - kms_cursor_legacy seems to get broken because of multiple memcpy
      calls when copying level 0 water marks for enabled SAGV, to
      fix this now simply using that field right away, without copying,
      for that introduced a new wm_level accessor which decides which
      wm_level to return based on SAGV state.

v8: - Protect crtc_sagv_mask same way as we do for other global state
      changes: i.e check if changes are needed, then grab all crtc locks
      to serialize the changes(Ville Syrjälä)
    - Add crtc_sagv_mask caching in order to avoid needless recalculations
      (Matthew Roper)
    - Put back Gen12 SAGV switch in order to get it enabled in separate
      patch(Matthew Roper)
    - Rename *_set_sagv_mask to *_compute_sagv_mask(Matthew Roper)
    - Check if there are no active pipes in intel_can_enable_sagv
      instead of platform specific functions(Matthew Roper), same
      for intel_has_sagv check.

v9  - Switched to u8 for crtc_sagv_mask(Ville Syrjälä)
    - crtc_sagv_mask now is pipe_sagv_mask(Ville Syrjälä)
    - Extracted sagv checking logic from skl/icl/tgl_compute_sagv_mask
    - Extracted skl_plane_wm_level function and passing latency to
      separate patches(Ville Syrjälä)
    - Removed part of unneeded copy-paste from tgl_check_pipe_fits_sagv_wm
      (Ville Syrjälä)
    - Now using simple assignment for sagv_wm0 as it contains only
      pod types and no pointers(Ville Syrjälä)
    - Fixed intel_can_enable_sagv not to do double duty, now it only
      check SAGV bits by ANDing those between local and global state.
      The SAGV masks are now computed after watermarks are available,
      in order to be able to figure out if ddb ranges are fitting nicely.
      (Ville Syrjälä)
    - Now having uv_sagv_wm0 and sagv_wm0, otherwise we have wrong logic
      when using skl_plane_wm_level accessor, as we had previously for Gen11+
      color plane and regular wm levels, so probably both has to be recalculated
      with additional SAGV block time for Level 0.

v10: - Starting to use new global state for storing pipe_sagv_mask

v11: - Fixed rebase conflict with recent drm-tip
     - Check if we really need to recalculate SAGV mask, otherwise
       bail out without making any changes.
     - Use cached SAGV result, instead of recalculating it everytime,
       if bw_state hasn't changed.

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Ville Syrjälä <ville.syrjala@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.h       |  18 +
 drivers/gpu/drm/i915/display/intel_display.c  |  22 +-
 .../drm/i915/display/intel_display_types.h    |   2 +
 .../gpu/drm/i915/display/intel_global_state.h |   1 +
 drivers/gpu/drm/i915/intel_pm.c               | 449 ++++++++++++++++--
 drivers/gpu/drm/i915/intel_pm.h               |   4 +-
 6 files changed, 454 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index ac004d6f4276..fb1760125f9d 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -18,6 +18,24 @@ struct intel_crtc_state;
 struct intel_bw_state {
 	struct intel_global_state base;
 
+	/*
+	 * Contains a bit mask, used to determine, whether correspondent
+	 * pipe allows SAGV or not.
+	 */
+	u8 pipe_sagv_mask;
+
+	/*
+	 * Used to determine if we already had calculated
+	 * SAGV mask for this state once.
+	 */
+	bool sagv_calculated;
+
+	/*
+	 * Contains final SAGV decision based on current mask,
+	 * to prevent doing the same job over and over again.
+	 */
+	bool can_sagv;
+
 	unsigned int data_rate[I915_MAX_PIPES];
 	u8 num_active_planes[I915_MAX_PIPES];
 };
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 24542281a73e..ef2e9155090f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14105,7 +14105,10 @@ static void verify_wm_state(struct intel_crtc *crtc,
 		/* Watermarks */
 		for (level = 0; level <= max_level; level++) {
 			if (skl_wm_level_equals(&hw_plane_wm->wm[level],
-						&sw_plane_wm->wm[level]))
+						&sw_plane_wm->wm[level]) ||
+			   (skl_wm_level_equals(&hw_plane_wm->wm[level],
+						&sw_plane_wm->sagv_wm0) &&
+			   (level == 0)))
 				continue;
 
 			drm_err(&dev_priv->drm,
@@ -14160,7 +14163,10 @@ static void verify_wm_state(struct intel_crtc *crtc,
 		/* Watermarks */
 		for (level = 0; level <= max_level; level++) {
 			if (skl_wm_level_equals(&hw_plane_wm->wm[level],
-						&sw_plane_wm->wm[level]))
+						&sw_plane_wm->wm[level]) ||
+			   (skl_wm_level_equals(&hw_plane_wm->wm[level],
+						&sw_plane_wm->sagv_wm0) &&
+			   (level == 0)))
 				continue;
 
 			drm_err(&dev_priv->drm,
@@ -15712,8 +15718,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 		 * SKL workaround: bspec recommends we disable the SAGV when we
 		 * have more then one pipe enabled
 		 */
-		if (!intel_can_enable_sagv(state))
-			intel_disable_sagv(dev_priv);
+		if (INTEL_GEN(dev_priv) < 11)
+			if (!intel_can_enable_sagv(dev_priv))
+				intel_disable_sagv(dev_priv);
 
 		intel_modeset_verify_disabled(dev_priv, state);
 	}
@@ -15813,8 +15820,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	if (state->modeset)
 		intel_verify_planes(state);
 
-	if (state->modeset && intel_can_enable_sagv(state))
-		intel_enable_sagv(dev_priv);
+	if (INTEL_GEN(dev_priv) < 11) {
+		if (state->modeset && intel_can_enable_sagv(dev_priv))
+			intel_enable_sagv(dev_priv);
+	}
 
 	drm_atomic_helper_commit_hw_done(&state->base);
 
@@ -15966,7 +15975,6 @@ static int intel_atomic_commit(struct drm_device *dev,
 
 	if (state->global_state_changed) {
 		assert_global_state_locked(dev_priv);
-
 		dev_priv->active_pipes = state->active_pipes;
 	}
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 283c622f8ba1..a9a2e0cc8e81 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -651,6 +651,8 @@ struct skl_plane_wm {
 	struct skl_wm_level wm[8];
 	struct skl_wm_level uv_wm[8];
 	struct skl_wm_level trans_wm;
+	struct skl_wm_level sagv_wm0;
+	struct skl_wm_level uv_sagv_wm0;
 	bool is_planar;
 };
 
diff --git a/drivers/gpu/drm/i915/display/intel_global_state.h b/drivers/gpu/drm/i915/display/intel_global_state.h
index e6163a469029..481bf5ea90a3 100644
--- a/drivers/gpu/drm/i915/display/intel_global_state.h
+++ b/drivers/gpu/drm/i915/display/intel_global_state.h
@@ -84,4 +84,5 @@ void intel_atomic_clear_global_state(struct intel_atomic_state *state);
 int intel_atomic_lock_global_state(struct intel_global_state *obj_state);
 int intel_atomic_serialize_global_state(struct intel_global_state *obj_state);
 
+
 #endif
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e1d167429489..2aafd2b07e4a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -42,6 +42,7 @@
 #include "i915_drv.h"
 #include "i915_irq.h"
 #include "i915_trace.h"
+#include "display/intel_bw.h"
 #include "intel_pm.h"
 #include "intel_sideband.h"
 #include "../../../platform/x86/intel_ips.h"
@@ -3620,7 +3621,7 @@ static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
 	return IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv);
 }
 
-static bool
+bool
 intel_has_sagv(struct drm_i915_private *dev_priv)
 {
 	/* HACK! */
@@ -3743,39 +3744,24 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
 	return 0;
 }
 
-bool intel_can_enable_sagv(struct intel_atomic_state *state)
+static bool skl_can_enable_sagv_on_pipe(struct intel_atomic_state *state,
+					enum pipe pipe)
 {
 	struct drm_device *dev = state->base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct intel_crtc *crtc;
 	struct intel_plane *plane;
 	struct intel_crtc_state *crtc_state;
-	enum pipe pipe;
 	int level, latency;
 
-	if (!intel_has_sagv(dev_priv))
-		return false;
-
-	/*
-	 * If there are no active CRTCs, no additional checks need be performed
-	 */
-	if (hweight8(state->active_pipes) == 0)
-		return true;
-
-	/*
-	 * SKL+ workaround: bspec recommends we disable SAGV when we have
-	 * more then one pipe enabled
-	 */
-	if (hweight8(state->active_pipes) > 1)
-		return false;
-
-	/* Since we're now guaranteed to only have one active CRTC... */
-	pipe = ffs(state->active_pipes) - 1;
 	crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
 	crtc_state = to_intel_crtc_state(crtc->base.state);
 
-	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
+	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
+		DRM_DEBUG_KMS("No SAGV for interlaced mode on pipe %c\n",
+			      pipe_name(pipe));
 		return false;
+	}
 
 	for_each_intel_plane_on_crtc(dev, crtc, plane) {
 		struct skl_plane_wm *wm =
@@ -3802,13 +3788,174 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
 		 * incur memory latencies higher than sagv_block_time_us we
 		 * can't enable SAGV.
 		 */
-		if (latency < dev_priv->sagv_block_time_us)
+		if (latency < dev_priv->sagv_block_time_us) {
+			DRM_DEBUG_KMS("Latency %d < sagv block time %d, no SAGV for pipe %c\n",
+				      latency, dev_priv->sagv_block_time_us, pipe_name(pipe));
 			return false;
+		}
 	}
 
 	return true;
 }
 
+static void skl_compute_sagv_mask(struct intel_atomic_state *state)
+{
+	struct intel_crtc *crtc;
+	enum pipe pipe;
+	struct intel_bw_state *new_bw_state = intel_atomic_get_bw_state(state);
+
+	if (IS_ERR(new_bw_state)) {
+		WARN(1, "Could not get bw_state\n");
+		return;
+	}
+
+
+	if (state->active_pipes != 1) {
+		new_bw_state->pipe_sagv_mask = 0;
+		DRM_DEBUG_KMS("No SAGV for multiple pipes on Gen 9\n");
+		return;
+	}
+
+	/* Since we're now guaranteed to only have one active CRTC... */
+	pipe = ffs(state->active_pipes) - 1;
+
+	if (skl_can_enable_sagv_on_pipe(state, pipe))
+		new_bw_state->pipe_sagv_mask |= BIT(crtc->pipe);
+	else
+		new_bw_state->pipe_sagv_mask &= ~BIT(crtc->pipe);
+}
+
+static void tgl_compute_sagv_mask(struct intel_atomic_state *state);
+
+static void icl_compute_sagv_mask(struct intel_atomic_state *state)
+{
+	struct intel_crtc *crtc;
+	struct intel_crtc_state *new_crtc_state;
+	int i;
+	struct intel_bw_state *new_bw_state = intel_atomic_get_bw_state(state);
+
+	if (IS_ERR(new_bw_state)) {
+		WARN(1, "Could not get bw_state\n");
+		return;
+	}
+
+	for_each_new_intel_crtc_in_state(state, crtc,
+					 new_crtc_state, i) {
+		if (skl_can_enable_sagv_on_pipe(state, crtc->pipe))
+			new_bw_state->pipe_sagv_mask |= BIT(crtc->pipe);
+		else
+			new_bw_state->pipe_sagv_mask &= ~BIT(crtc->pipe);
+	}
+}
+
+void intel_compute_sagv_mask(struct intel_atomic_state *state, int total_affected_planes)
+{
+	int ret;
+	struct drm_device *dev = state->base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct intel_bw_state *new_bw_state = intel_atomic_get_bw_state(state);
+	struct intel_bw_state *old_bw_state = intel_atomic_get_old_bw_state(state);
+
+	if (IS_ERR(new_bw_state) || IS_ERR(old_bw_state)) {
+		WARN(1, "Could not get bw_state\n");
+		return;
+	}
+
+	new_bw_state->sagv_calculated = false;
+
+	/*
+	 * If active_pipes had changed, means we have added/removed crtc,
+	 * if total_affected_planes had changed - means we have changed wm/ddb.
+	 * Both require SAGV recalculation - otherwise just return and SAGV mask
+	 * will stay the same.
+	 * Also we will have crtc locks grabbed only in mentioned above cases.
+	 */
+	if ((state->active_pipes == dev_priv->active_pipes) &&
+	    (total_affected_planes == 0)) {
+		new_bw_state->sagv_calculated = true;
+		return;
+	}
+
+	/*
+	 * Now once we got wm levels calculated,
+	 * check if we can have SAGV.
+	 */
+	if (INTEL_GEN(dev_priv) >= 12)
+		tgl_compute_sagv_mask(state);
+	else if (INTEL_GEN(dev_priv) == 11)
+		icl_compute_sagv_mask(state);
+	else
+		skl_compute_sagv_mask(state);
+
+	/*
+	 * For SAGV we need to account all the pipes,
+	 * not only the ones which are in state currently.
+	 * Grab all locks if we detect that we are actually
+	 * going to do something.
+	 */
+	if (new_bw_state->pipe_sagv_mask != old_bw_state->pipe_sagv_mask) {
+		ret = intel_atomic_serialize_global_state(&new_bw_state->base);
+		if (ret) {
+			DRM_DEBUG_KMS("Could not serialize global state\n");
+			return;
+		}
+	}
+}
+
+bool intel_calculate_sagv_result(struct drm_i915_private *dev_priv,
+				 struct intel_bw_state *bw_state)
+{
+	bool sagv_result = true;
+	enum pipe pipe;
+
+	for_each_pipe(dev_priv, pipe) {
+		/*
+		 * TODO: We are depending on active_pipes here,
+		 * probably it should be part of some other global state
+		 * obj, like modeset_state or smth, which we should depend on.
+		 * Don't want to clone it here, really.
+		 */
+		int active_pipe_bit = dev_priv->active_pipes & BIT(pipe);
+		if (active_pipe_bit) {
+			if ((bw_state->pipe_sagv_mask & BIT(pipe)) == 0) {
+				sagv_result = false;
+				break;
+			}
+		}
+	}
+
+	return sagv_result;
+}
+
+/*
+ * This function to be used before swap state
+ */
+bool intel_can_enable_sagv_for_state(struct intel_atomic_state *state)
+{
+	struct drm_device *dev = state->base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct intel_bw_state *bw_state  = intel_atomic_get_bw_state(state);
+
+	if (IS_ERR(bw_state)) {
+		WARN(1, "Could not get bw_state\n");
+		return false;
+	}
+
+	if (!intel_has_sagv(dev_priv)) {
+		DRM_DEBUG_KMS("No SAGV support detected\n");
+		return false;
+	}
+
+	if (bw_state->sagv_calculated)
+		goto out;
+
+	bw_state->can_sagv = intel_calculate_sagv_result(dev_priv, bw_state);
+	bw_state->sagv_calculated = true;
+
+out:
+	return bw_state->can_sagv;
+}
+
 /*
  * Calculate initial DBuf slice offset, based on slice size
  * and mask(i.e if slice size is 1024 and second slice is enabled
@@ -3842,6 +3989,46 @@ static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv)
 	return ddb_size;
 }
 
+/*
+ * To be used after we swap state
+ */
+bool intel_can_enable_sagv(struct drm_i915_private *dev_priv)
+{
+	struct intel_global_state *global_state;
+	struct intel_bw_state *bw_state;
+
+	global_state = dev_priv->bw_obj.state;
+	if (IS_ERR(global_state)) {
+		WARN(1, "Could not get global state\n");
+		return false;
+	}
+
+	/*
+	 * TODO: Should we still may be lock global state here?
+	 */
+	bw_state = to_intel_bw_state(global_state);
+
+	/*
+	 * Should have this calculated by that time,
+	 * means something got changed or wrong in the driver
+	 * currently, supposed places which call this function are:
+	 * intel_atomic_commit_tail, intel_atomic_bw_check,
+	 * skl_allocate_pipe_ddb, skl_write_plane_wm.
+	 * All of those are supposed to be called after
+	 * skl_compute_wm->intel_compute_sagv_mask is called.
+	 */
+	drm_WARN_ON(&dev_priv->drm, !bw_state->sagv_calculated);
+
+	if (bw_state->sagv_calculated)
+		goto out;
+
+	bw_state->can_sagv = intel_calculate_sagv_result(dev_priv, bw_state);
+	bw_state->sagv_calculated = true;
+
+out:
+	return bw_state->can_sagv;
+}
+
 static u8 skl_compute_dbuf_slices(const struct intel_crtc_state *crtc_state,
 				  u32 active_pipes);
 
@@ -4028,6 +4215,7 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
 		u32 latency = dev_priv->wm.skl_latency[level];
 
 		skl_compute_plane_wm(crtc_state, level, latency, &wp, &wm, &wm);
+
 		if (wm.min_ddb_alloc == U16_MAX)
 			break;
 
@@ -4554,12 +4742,93 @@ skl_plane_wm_level(struct intel_plane *plane,
 		   int level,
 		   int color_plane)
 {
+	struct drm_atomic_state *state = crtc_state->uapi.state;
+	struct drm_crtc *crtc = crtc_state->uapi.crtc;
+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 	const struct skl_plane_wm *wm =
 		&crtc_state->wm.skl.optimal.planes[plane->id];
 
+	if (!level) {
+		bool can_sagv = false;
+
+		/*
+		 * If we haven't yet swapped our state, we should use
+		 * the state to determine SAGV, otherwise use global
+		 * state as atomic state pointer might become stale
+		 * and zeroed out.
+		 */
+		if (state) {
+			struct intel_atomic_state *intel_state =
+				to_intel_atomic_state(state);
+			can_sagv = intel_can_enable_sagv_for_state(intel_state);
+		} else {
+			can_sagv = intel_can_enable_sagv(dev_priv);
+		}
+
+		if (can_sagv)
+			return color_plane ? &wm->uv_sagv_wm0 : &wm->sagv_wm0;
+	}
+
 	return color_plane ? &wm->uv_wm[level] : &wm->wm[level];
 }
 
+static int
+tgl_check_pipe_fits_sagv_wm(struct intel_crtc_state *crtc_state)
+{
+	struct drm_crtc *crtc = crtc_state->uapi.crtc;
+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
+	u16 alloc_size;
+	u64 total_data_rate;
+	enum plane_id plane_id;
+	int num_active;
+	u64 plane_data_rate[I915_MAX_PLANES] = {};
+	u32 blocks;
+
+	/*
+	 * No need to check gen here, we call this only for gen12
+	 */
+	total_data_rate =
+		icl_get_total_relative_data_rate(crtc_state,
+						 plane_data_rate);
+
+	skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state,
+					   total_data_rate,
+					   alloc, &num_active);
+	alloc_size = skl_ddb_entry_size(alloc);
+	if (alloc_size == 0)
+		return -ENOSPC;
+
+	/*
+	 * Do check if we can fit L0 + sagv_block_time and
+	 * disable SAGV if we can't.
+	 */
+	blocks = 0;
+	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
+		/*
+		 * The only place, where we can't use skl_plane_wm_level
+		 * accessor, because if actually calls intel_can_enable_sagv
+		 * which depends on that function.
+		 */
+		const struct skl_plane_wm *wm =
+			&crtc_state->wm.skl.optimal.planes[plane_id];
+
+		blocks += wm->sagv_wm0.min_ddb_alloc;
+		blocks += wm->uv_sagv_wm0.min_ddb_alloc;
+
+		if (blocks > alloc_size) {
+			DRM_DEBUG_KMS("Not enough ddb blocks(%d<%d) for SAGV on pipe %c\n",
+				      alloc_size, blocks, pipe_name(intel_crtc->pipe));
+			return -ENOSPC;
+		}
+	}
+	DRM_DEBUG_KMS("%d total blocks required for SAGV, ddb entry size %d\n",
+		      blocks, alloc_size);
+	return 0;
+}
+
+
 static int
 skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
 {
@@ -5143,11 +5412,19 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
 static void
 skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
 		      const struct skl_wm_params *wm_params,
-		      struct skl_wm_level *levels)
+		      struct skl_plane_wm *plane_wm,
+		      bool yuv)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 	int level, max_level = ilk_wm_max_level(dev_priv);
+	/*
+	 * Check which kind of plane is it and based on that calculate
+	 * correspondent WM levels.
+	 */
+	struct skl_wm_level *levels = yuv ? plane_wm->uv_wm : plane_wm->wm;
 	struct skl_wm_level *result_prev = &levels[0];
+	struct skl_wm_level *sagv_wm = yuv ?
+				&plane_wm->uv_sagv_wm0 : &plane_wm->sagv_wm0;
 
 	for (level = 0; level <= max_level; level++) {
 		struct skl_wm_level *result = &levels[level];
@@ -5158,6 +5435,27 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
 
 		result_prev = result;
 	}
+	/*
+	 * For Gen12 if it is an L0 we need to also
+	 * consider sagv_block_time when calculating
+	 * L0 watermark - we will need that when making
+	 * a decision whether enable SAGV or not.
+	 * For older gens we agreed to copy L0 value for
+	 * compatibility.
+	 */
+	if ((INTEL_GEN(dev_priv) >= 12)) {
+		u32 latency = dev_priv->wm.skl_latency[0];
+
+		latency += dev_priv->sagv_block_time_us;
+		skl_compute_plane_wm(crtc_state, 0, latency,
+				     wm_params, &levels[0],
+				     sagv_wm);
+		DRM_DEBUG_KMS("%d L0 blocks required for SAGV vs %d for non-SAGV\n",
+			      sagv_wm->min_ddb_alloc, levels[0].min_ddb_alloc);
+	} else {
+		/* Since all members are POD */
+		*sagv_wm = levels[0];
+	}
 }
 
 static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
@@ -5232,7 +5530,7 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
 	if (ret)
 		return ret;
 
-	skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
+	skl_compute_wm_levels(crtc_state, &wm_params, wm, false);
 	skl_compute_transition_wm(crtc_state, &wm_params, wm);
 
 	return 0;
@@ -5254,7 +5552,7 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
 	if (ret)
 		return ret;
 
-	skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
+	skl_compute_wm_levels(crtc_state, &wm_params, wm, true);
 
 	return 0;
 }
@@ -5585,10 +5883,29 @@ skl_print_wm_changes(struct intel_atomic_state *state)
 		for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
 			enum plane_id plane_id = plane->id;
 			const struct skl_plane_wm *old_wm, *new_wm;
+			u16 old_plane_res_l, new_plane_res_l;
+			u8  old_plane_res_b, new_plane_res_b;
+			u16 old_min_ddb_alloc, new_min_ddb_alloc;
 
 			old_wm = &old_pipe_wm->planes[plane_id];
 			new_wm = &new_pipe_wm->planes[plane_id];
 
+			old_plane_res_l = intel_can_enable_sagv(dev_priv) ?
+					  old_wm->sagv_wm0.plane_res_l : old_wm->wm[0].plane_res_l;
+			old_plane_res_b = intel_can_enable_sagv(dev_priv) ?
+					  old_wm->sagv_wm0.plane_res_b : old_wm->wm[0].plane_res_b;
+
+			new_plane_res_l = intel_can_enable_sagv_for_state(state) ?
+					  new_wm->sagv_wm0.plane_res_l : new_wm->wm[0].plane_res_l;
+			new_plane_res_b = intel_can_enable_sagv_for_state(state) ?
+					  new_wm->sagv_wm0.plane_res_b : new_wm->wm[0].plane_res_b;
+
+			old_min_ddb_alloc = intel_can_enable_sagv(dev_priv) ?
+					    old_wm->sagv_wm0.min_ddb_alloc : old_wm->wm[0].min_ddb_alloc;
+
+			new_min_ddb_alloc = intel_can_enable_sagv_for_state(state) ?
+					    new_wm->sagv_wm0.min_ddb_alloc : new_wm->wm[0].min_ddb_alloc;
+
 			if (skl_plane_wm_equals(dev_priv, old_wm, new_wm))
 				continue;
 
@@ -5611,7 +5928,7 @@ skl_print_wm_changes(struct intel_atomic_state *state)
 				    "[PLANE:%d:%s]   lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d"
 				      " -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d\n",
 				    plane->base.base.id, plane->base.name,
-				    enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].plane_res_l,
+				    enast(old_wm->wm[0].ignore_lines), old_plane_res_l,
 				    enast(old_wm->wm[1].ignore_lines), old_wm->wm[1].plane_res_l,
 				    enast(old_wm->wm[2].ignore_lines), old_wm->wm[2].plane_res_l,
 				    enast(old_wm->wm[3].ignore_lines), old_wm->wm[3].plane_res_l,
@@ -5621,7 +5938,7 @@ skl_print_wm_changes(struct intel_atomic_state *state)
 				    enast(old_wm->wm[7].ignore_lines), old_wm->wm[7].plane_res_l,
 				    enast(old_wm->trans_wm.ignore_lines), old_wm->trans_wm.plane_res_l,
 
-				    enast(new_wm->wm[0].ignore_lines), new_wm->wm[0].plane_res_l,
+				    enast(new_wm->wm[0].ignore_lines), new_plane_res_l,
 				    enast(new_wm->wm[1].ignore_lines), new_wm->wm[1].plane_res_l,
 				    enast(new_wm->wm[2].ignore_lines), new_wm->wm[2].plane_res_l,
 				    enast(new_wm->wm[3].ignore_lines), new_wm->wm[3].plane_res_l,
@@ -5635,12 +5952,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
 				    "[PLANE:%d:%s]  blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
 				    " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
 				    plane->base.base.id, plane->base.name,
-				    old_wm->wm[0].plane_res_b, old_wm->wm[1].plane_res_b,
+				    old_plane_res_b, old_wm->wm[1].plane_res_b,
 				    old_wm->wm[2].plane_res_b, old_wm->wm[3].plane_res_b,
 				    old_wm->wm[4].plane_res_b, old_wm->wm[5].plane_res_b,
 				    old_wm->wm[6].plane_res_b, old_wm->wm[7].plane_res_b,
 				    old_wm->trans_wm.plane_res_b,
-				    new_wm->wm[0].plane_res_b, new_wm->wm[1].plane_res_b,
+				    new_plane_res_b, new_wm->wm[1].plane_res_b,
 				    new_wm->wm[2].plane_res_b, new_wm->wm[3].plane_res_b,
 				    new_wm->wm[4].plane_res_b, new_wm->wm[5].plane_res_b,
 				    new_wm->wm[6].plane_res_b, new_wm->wm[7].plane_res_b,
@@ -5650,12 +5967,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
 				    "[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
 				    " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
 				    plane->base.base.id, plane->base.name,
-				    old_wm->wm[0].min_ddb_alloc, old_wm->wm[1].min_ddb_alloc,
+				    old_min_ddb_alloc, old_wm->wm[1].min_ddb_alloc,
 				    old_wm->wm[2].min_ddb_alloc, old_wm->wm[3].min_ddb_alloc,
 				    old_wm->wm[4].min_ddb_alloc, old_wm->wm[5].min_ddb_alloc,
 				    old_wm->wm[6].min_ddb_alloc, old_wm->wm[7].min_ddb_alloc,
 				    old_wm->trans_wm.min_ddb_alloc,
-				    new_wm->wm[0].min_ddb_alloc, new_wm->wm[1].min_ddb_alloc,
+				    new_min_ddb_alloc, new_wm->wm[1].min_ddb_alloc,
 				    new_wm->wm[2].min_ddb_alloc, new_wm->wm[3].min_ddb_alloc,
 				    new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc,
 				    new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc,
@@ -5755,7 +6072,8 @@ skl_ddb_add_affected_pipes(struct intel_atomic_state *state)
  * default value of the watermarks registers is not zero.
  */
 static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
-				      struct intel_crtc *crtc)
+				      struct intel_crtc *crtc,
+				      int *num_affected_planes)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	const struct intel_crtc_state *old_crtc_state =
@@ -5764,6 +6082,8 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
 		intel_atomic_get_new_crtc_state(state, crtc);
 	struct intel_plane *plane;
 
+	*num_affected_planes = 0;
+
 	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
 		struct intel_plane_state *plane_state;
 		enum plane_id plane_id = plane->id;
@@ -5787,11 +6107,64 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
 			return PTR_ERR(plane_state);
 
 		new_crtc_state->update_planes |= BIT(plane_id);
+		*num_affected_planes += 1;
 	}
 
 	return 0;
 }
 
+static void tgl_compute_sagv_mask(struct intel_atomic_state *state)
+{
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+	struct intel_crtc *crtc;
+	struct intel_crtc_state *new_crtc_state;
+	struct intel_crtc_state *old_crtc_state;
+	int ret;
+	int i;
+	struct intel_plane *plane;
+	struct intel_bw_state *new_bw_state  = intel_atomic_get_bw_state(state);
+
+	if (IS_ERR(new_bw_state)) {
+		WARN(1, "Could not get bw_state\n");
+		return;
+	}
+
+	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+					    new_crtc_state, i) {
+		int pipe_bit = BIT(crtc->pipe);
+		bool skip = true;
+
+		/*
+		 * If we had set this mast already once for this state,
+		 * no need to waste CPU cycles for doing this again.
+		 */
+		for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
+			enum plane_id plane_id = plane->id;
+
+			if (!skl_plane_wm_equals(dev_priv,
+						 &old_crtc_state->wm.skl.optimal.planes[plane_id],
+						 &new_crtc_state->wm.skl.optimal.planes[plane_id])) {
+				skip = false;
+				break;
+			}
+		}
+
+		/*
+		 * Check if wm levels are actually the same as for previous
+		 * state, which means we can just skip doing this long check
+		 * and just  copy correspondent bit from previous state.
+		 */
+		if (skip)
+			continue;
+
+		ret = tgl_check_pipe_fits_sagv_wm(new_crtc_state);
+		if (!ret)
+			new_bw_state->pipe_sagv_mask |= pipe_bit;
+		else
+			new_bw_state->pipe_sagv_mask &= ~pipe_bit;
+	}
+}
+
 static int
 skl_compute_wm(struct intel_atomic_state *state)
 {
@@ -5799,6 +6172,7 @@ skl_compute_wm(struct intel_atomic_state *state)
 	struct intel_crtc_state *new_crtc_state;
 	struct intel_crtc_state *old_crtc_state;
 	int ret, i;
+	int affected_planes; int total_affected_planes = 0;
 
 	ret = skl_ddb_add_affected_pipes(state);
 	if (ret)
@@ -5815,11 +6189,15 @@ skl_compute_wm(struct intel_atomic_state *state)
 		if (ret)
 			return ret;
 
-		ret = skl_wm_add_affected_planes(state, crtc);
+		ret = skl_wm_add_affected_planes(state, crtc, &affected_planes);
 		if (ret)
 			return ret;
+
+		total_affected_planes += affected_planes;
 	}
 
+	intel_compute_sagv_mask(state, total_affected_planes);
+
 	ret = skl_compute_ddb(state);
 	if (ret)
 		return ret;
@@ -5939,6 +6317,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
 				val = I915_READ(CUR_WM(pipe, level));
 
 			skl_wm_level_from_reg_val(val, &wm->wm[level]);
+			if (level == 0)
+				memcpy(&wm->sagv_wm0, &wm->wm[level],
+				       sizeof(struct skl_wm_level));
 		}
 
 		if (plane_id != PLANE_CURSOR)
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index d60a85421c5a..561a17a5d4e0 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -41,7 +41,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
 			      struct skl_pipe_wm *out);
 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
-bool intel_can_enable_sagv(struct intel_atomic_state *state);
+bool intel_can_enable_sagv(struct drm_i915_private *dev_priv);
+bool intel_can_enable_sagv_for_state(struct intel_atomic_state *state);
+bool intel_has_sagv(struct drm_i915_private *dev_priv);
 int intel_enable_sagv(struct drm_i915_private *dev_priv);
 int intel_disable_sagv(struct drm_i915_private *dev_priv);
 bool skl_wm_level_equals(const struct skl_wm_level *l1,
-- 
2.24.1.485.gad05a3d8e5

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[Intel-gfx] ✗ Fi.CI.BUILD: failure for Refactor Gen11+ SAGV support (rev2)

[Patchwork]

== Series Details ==

Series: Refactor Gen11+ SAGV support (rev2)
URL   : https://patchwork.freedesktop.org/series/73584/
State : failure

== Summary ==

Applying: drm/i915: Start passing latency as parameter
Applying: drm/i915: Introduce skl_plane_wm_level accessor.
Applying: drm/i915: Init obj state in intel_atomic_get_old/new_global_obj_state
Applying: drm/i915: Refactor intel_can_enable_sagv
Applying: drm/i915: Added required new PCode commands
Applying: drm/i915: Restrict qgv points which don't have enough bandwidth.
Using index info to reconstruct a base tree...
M	drivers/gpu/drm/i915/display/intel_bw.h
M	drivers/gpu/drm/i915/display/intel_display.c
M	drivers/gpu/drm/i915/i915_drv.h
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/i915_drv.h
Auto-merging drivers/gpu/drm/i915/display/intel_display.c
Auto-merging drivers/gpu/drm/i915/display/intel_bw.h
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/display/intel_bw.h
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch' to see the failed patch
Patch failed at 0006 drm/i915: Restrict qgv points which don't have enough bandwidth.
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Refactor Gen11+ SAGV support

[Patchwork]

== Series Details ==

Series: Refactor Gen11+ SAGV support
URL   : https://patchwork.freedesktop.org/series/73856/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915: Start passing latency as parameter
Okay!

Commit: drm/i915: Introduce skl_plane_wm_level accessor.
Okay!

Commit: drm/i915: Add intel_bw_get_*_state helpers
Okay!

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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Refactor Gen11+ SAGV support

[Patchwork]

== Series Details ==

Series: Refactor Gen11+ SAGV support
URL   : https://patchwork.freedesktop.org/series/73703/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915: Start passing latency as parameter
Okay!

Commit: drm/i915: Introduce skl_plane_wm_level accessor.
Okay!

Commit: drm/i915: Init obj state in intel_atomic_get_old/new_global_obj_state
Okay!

Commit: drm/i915: Refactor intel_can_enable_sagv
+drivers/gpu/drm/i915/intel_pm.c:3851:6: warning: symbol 'intel_compute_sagv_mask' was not declared. Should it be static?
+drivers/gpu/drm/i915/intel_pm.c:3905:6: warning: symbol 'intel_calculate_sagv_result' was not declared. Should it be static?

Commit: drm/i915: Added required new PCode commands
Okay!

Commit: drm/i915: Restrict qgv points which don't have enough bandwidth.
Okay!

Commit: drm/i915: Enable SAGV support for Gen12
Okay!

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