* [Intel-gfx] [PATCH v11] drm/i915/dsb: Pre allocate and late cleanup of cmd buffer @ 2020-05-20 13:07 Animesh Manna 2020-05-20 14:55 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dsb: Pre allocate and late cleanup of cmd buffer (rev10) Patchwork ` (2 more replies) 0 siblings, 3 replies; 4+ messages in thread From: Animesh Manna @ 2020-05-20 13:07 UTC (permalink / raw) To: intel-gfx; +Cc: Jani Nikula, Daniel Vetter, Maarten Lankhorst Pre-allocate command buffer in atomic_commit using intel_dsb_prepare function which also includes pinning and map in cpu domain. No functional change is dsb write/commit functions. Now dsb get/put function is removed and ref-count mechanism is not needed. Below dsb api added to do respective job mentioned below. intel_dsb_prepare - Allocate, pin and map the buffer. intel_dsb_cleanup - Unpin and release the gem object. RFC: Initial patch for design review. v2: included _init() part in _prepare(). [Daniel, Ville] v3: dsb_cleanup called after cleanup_planes. [Daniel] v4: dsb structure is moved to intel_crtc_state from intel_crtc. [Maarten] v5: dsb get/put/ref-count mechanism removed. [Maarten] v6: Based on review feedback following changes are added, - replaced intel_dsb structure by pointer in intel_crtc_state. [Maarten] - passing intel_crtc_state to dsp-api to simplify the code. [Maarten] - few dsb functions prototype modified to simplify code. v7: added few cosmetic changes suggested by Jani and null check for crtc_state in dsb_cleanup removed as suggested by Maarten. v8: changed the function parameter to intel_crtc_state* of ivb_load_lut_ext_max() from intel_crtc. [Maarten] v9: error handling improved in _write() and prepare(). [Maarten] Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> --- drivers/gpu/drm/i915/display/intel_atomic.c | 3 + drivers/gpu/drm/i915/display/intel_color.c | 66 ++--- drivers/gpu/drm/i915/display/intel_display.c | 58 +++- .../drm/i915/display/intel_display_types.h | 6 +- drivers/gpu/drm/i915/display/intel_dsb.c | 250 ++++++++---------- drivers/gpu/drm/i915/display/intel_dsb.h | 17 +- 6 files changed, 206 insertions(+), 194 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c index d043057d2fa0..3cb866f22e74 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic.c +++ b/drivers/gpu/drm/i915/display/intel_atomic.c @@ -252,6 +252,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc) crtc_state->wm.need_postvbl_update = false; crtc_state->fb_bits = 0; crtc_state->update_planes = 0; + crtc_state->dsb = NULL; return &crtc_state->uapi; } @@ -292,6 +293,8 @@ intel_crtc_destroy_state(struct drm_crtc *crtc, { struct intel_crtc_state *crtc_state = to_intel_crtc_state(state); + drm_WARN_ON(crtc->dev, crtc_state->dsb); + __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi); intel_crtc_free_hw_state(crtc_state); kfree(crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 98ece9cd7cdd..945bb03bdd4d 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -714,16 +714,16 @@ static void bdw_load_lut_10(struct intel_crtc *crtc, intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), 0); } -static void ivb_load_lut_ext_max(struct intel_crtc *crtc) +static void ivb_load_lut_ext_max(const struct intel_crtc_state *crtc_state) { + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - struct intel_dsb *dsb = intel_dsb_get(crtc); enum pipe pipe = crtc->pipe; /* Program the max register to clamp values > 1.0. */ - intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16); - intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16); - intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16); + intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16); + intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16); + intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16); /* * Program the gc max 2 register to clamp values > 1.0. @@ -731,15 +731,13 @@ static void ivb_load_lut_ext_max(struct intel_crtc *crtc) * from 3.0 to 7.0 */ if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { - intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 0), + intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 0), 1 << 16); - intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 1), + intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 1), 1 << 16); - intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 2), + intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 2), 1 << 16); } - - intel_dsb_put(dsb); } static void ivb_load_luts(const struct intel_crtc_state *crtc_state) @@ -753,7 +751,7 @@ static void ivb_load_luts(const struct intel_crtc_state *crtc_state) } else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) { ivb_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE | PAL_PREC_INDEX_VALUE(0)); - ivb_load_lut_ext_max(crtc); + ivb_load_lut_ext_max(crtc_state); ivb_load_lut_10(crtc, gamma_lut, PAL_PREC_SPLIT_MODE | PAL_PREC_INDEX_VALUE(512)); } else { @@ -761,7 +759,7 @@ static void ivb_load_luts(const struct intel_crtc_state *crtc_state) ivb_load_lut_10(crtc, blob, PAL_PREC_INDEX_VALUE(0)); - ivb_load_lut_ext_max(crtc); + ivb_load_lut_ext_max(crtc_state); } } @@ -776,7 +774,7 @@ static void bdw_load_luts(const struct intel_crtc_state *crtc_state) } else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) { bdw_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE | PAL_PREC_INDEX_VALUE(0)); - ivb_load_lut_ext_max(crtc); + ivb_load_lut_ext_max(crtc_state); bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_SPLIT_MODE | PAL_PREC_INDEX_VALUE(512)); } else { @@ -784,7 +782,7 @@ static void bdw_load_luts(const struct intel_crtc_state *crtc_state) bdw_load_lut_10(crtc, blob, PAL_PREC_INDEX_VALUE(0)); - ivb_load_lut_ext_max(crtc); + ivb_load_lut_ext_max(crtc_state); } } @@ -877,7 +875,7 @@ static void glk_load_luts(const struct intel_crtc_state *crtc_state) ilk_load_lut_8(crtc, gamma_lut); } else { bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0)); - ivb_load_lut_ext_max(crtc); + ivb_load_lut_ext_max(crtc_state); } } @@ -900,14 +898,12 @@ icl_load_gcmax(const struct intel_crtc_state *crtc_state, const struct drm_color_lut *color) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct intel_dsb *dsb = intel_dsb_get(crtc); enum pipe pipe = crtc->pipe; /* FIXME LUT entries are 16 bit only, so we can prog 0xFFFF max */ - intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 0), color->red); - intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 1), color->green); - intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 2), color->blue); - intel_dsb_put(dsb); + intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 0), color->red); + intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 1), color->green); + intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 2), color->blue); } static void @@ -916,7 +912,6 @@ icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state) struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); const struct drm_property_blob *blob = crtc_state->hw.gamma_lut; const struct drm_color_lut *lut = blob->data; - struct intel_dsb *dsb = intel_dsb_get(crtc); enum pipe pipe = crtc->pipe; int i; @@ -927,19 +922,17 @@ icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state) * 9 entries, corresponding to values 0, 1/(8 * 128 * 256), * 2/(8 * 128 * 256) ... 8/(8 * 128 * 256). */ - intel_dsb_reg_write(dsb, PREC_PAL_MULTI_SEG_INDEX(pipe), + intel_dsb_reg_write(crtc_state, PREC_PAL_MULTI_SEG_INDEX(pipe), PAL_PREC_AUTO_INCREMENT); for (i = 0; i < 9; i++) { const struct drm_color_lut *entry = &lut[i]; - intel_dsb_indexed_reg_write(dsb, PREC_PAL_MULTI_SEG_DATA(pipe), + intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_MULTI_SEG_DATA(pipe), ilk_lut_12p4_ldw(entry)); - intel_dsb_indexed_reg_write(dsb, PREC_PAL_MULTI_SEG_DATA(pipe), + intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_MULTI_SEG_DATA(pipe), ilk_lut_12p4_udw(entry)); } - - intel_dsb_put(dsb); } static void @@ -949,7 +942,6 @@ icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state) const struct drm_property_blob *blob = crtc_state->hw.gamma_lut; const struct drm_color_lut *lut = blob->data; const struct drm_color_lut *entry; - struct intel_dsb *dsb = intel_dsb_get(crtc); enum pipe pipe = crtc->pipe; int i; @@ -963,12 +955,13 @@ icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state) * PAL_PREC_INDEX[0] and PAL_PREC_INDEX[1] map to seg2[1], * seg2[0] being unused by the hardware. */ - intel_dsb_reg_write(dsb, PREC_PAL_INDEX(pipe), PAL_PREC_AUTO_INCREMENT); + intel_dsb_reg_write(crtc_state, PREC_PAL_INDEX(pipe), + PAL_PREC_AUTO_INCREMENT); for (i = 1; i < 257; i++) { entry = &lut[i * 8]; - intel_dsb_indexed_reg_write(dsb, PREC_PAL_DATA(pipe), + intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe), ilk_lut_12p4_ldw(entry)); - intel_dsb_indexed_reg_write(dsb, PREC_PAL_DATA(pipe), + intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe), ilk_lut_12p4_udw(entry)); } @@ -986,24 +979,22 @@ icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state) */ for (i = 0; i < 256; i++) { entry = &lut[i * 8 * 128]; - intel_dsb_indexed_reg_write(dsb, PREC_PAL_DATA(pipe), + intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe), ilk_lut_12p4_ldw(entry)); - intel_dsb_indexed_reg_write(dsb, PREC_PAL_DATA(pipe), + intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe), ilk_lut_12p4_udw(entry)); } /* The last entry in the LUT is to be programmed in GCMAX */ entry = &lut[256 * 8 * 128]; icl_load_gcmax(crtc_state, entry); - ivb_load_lut_ext_max(crtc); - intel_dsb_put(dsb); + ivb_load_lut_ext_max(crtc_state); } static void icl_load_luts(const struct intel_crtc_state *crtc_state) { const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct intel_dsb *dsb = intel_dsb_get(crtc); if (crtc_state->hw.degamma_lut) glk_load_degamma_lut(crtc_state); @@ -1018,11 +1009,10 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state) break; default: bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0)); - ivb_load_lut_ext_max(crtc); + ivb_load_lut_ext_max(crtc_state); } - intel_dsb_commit(dsb); - intel_dsb_put(dsb); + intel_dsb_commit(crtc_state); } static u32 chv_cgm_degamma_ldw(const struct drm_color_lut *color) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 432b4eeaf9f6..514483ffd247 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -14873,8 +14873,24 @@ static int intel_atomic_check(struct drm_device *dev, static int intel_atomic_prepare_commit(struct intel_atomic_state *state) { - return drm_atomic_helper_prepare_planes(state->base.dev, - &state->base); + struct intel_crtc_state *crtc_state; + struct intel_crtc *crtc; + int i, ret; + + ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base); + if (ret < 0) + return ret; + + for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { + bool mode_changed = needs_modeset(crtc_state); + + if (mode_changed || crtc_state->update_pipe || + crtc_state->uapi.color_mgmt_changed) { + intel_dsb_prepare(crtc_state); + } + } + + return 0; } u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc) @@ -15327,15 +15343,27 @@ static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_stat &wait_reset); } +static void intel_cleanup_dsbs(struct intel_atomic_state *state) +{ + struct intel_crtc_state *old_crtc_state, *new_crtc_state; + struct intel_crtc *crtc; + int i; + + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, + new_crtc_state, i) + intel_dsb_cleanup(old_crtc_state); +} + static void intel_atomic_cleanup_work(struct work_struct *work) { - struct drm_atomic_state *state = - container_of(work, struct drm_atomic_state, commit_work); - struct drm_i915_private *i915 = to_i915(state->dev); + struct intel_atomic_state *state = + container_of(work, struct intel_atomic_state, base.commit_work); + struct drm_i915_private *i915 = to_i915(state->base.dev); - drm_atomic_helper_cleanup_planes(&i915->drm, state); - drm_atomic_helper_commit_cleanup_done(state); - drm_atomic_state_put(state); + intel_cleanup_dsbs(state); + drm_atomic_helper_cleanup_planes(&i915->drm, &state->base); + drm_atomic_helper_commit_cleanup_done(&state->base); + drm_atomic_state_put(&state->base); intel_atomic_helper_free_state(i915); } @@ -15469,6 +15497,13 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) modeset_put_power_domains(dev_priv, put_domains[i]); intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state); + + /* + * DSB cleanup is done in cleanup_work aligning with framebuffer + * cleanup. So copy and reset the dsb structure to sync with + * commit_done and later do dsb cleanup in cleanup_work. + */ + old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb); } /* Underruns don't always raise interrupts, so check manually */ @@ -15618,8 +15653,15 @@ static int intel_atomic_commit(struct drm_device *dev, intel_atomic_swap_global_state(state); if (ret) { + struct intel_crtc_state *new_crtc_state; + struct intel_crtc *crtc; + int i; + i915_sw_fence_commit(&state->commit_ready); + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) + intel_dsb_cleanup(new_crtc_state); + drm_atomic_helper_cleanup_planes(dev, &state->base); intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); return ret; diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 87876fce91a5..ca579005d818 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1078,6 +1078,9 @@ struct intel_crtc_state { /* Only valid on TGL+ */ enum transcoder mst_master_transcoder; + + /* For DSB related info */ + struct intel_dsb *dsb; }; enum intel_pipe_crc_source { @@ -1147,9 +1150,6 @@ struct intel_crtc { /* scalers available on this crtc */ int num_scalers; - /* per pipe DSB related info */ - struct intel_dsb dsb; - #ifdef CONFIG_DEBUG_FS struct intel_pipe_crc pipe_crc; #endif diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 29fec6a92d17..475106e91fa7 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -34,152 +34,52 @@ #define DSB_BYTE_EN_SHIFT 20 #define DSB_REG_VALUE_MASK 0xfffff -static bool is_dsb_busy(struct intel_dsb *dsb) +static bool is_dsb_busy(struct drm_i915_private *i915, enum pipe pipe, + enum dsb_id id) { - struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - enum pipe pipe = crtc->pipe; - - return DSB_STATUS & intel_de_read(dev_priv, DSB_CTRL(pipe, dsb->id)); + return DSB_STATUS & intel_de_read(i915, DSB_CTRL(pipe, id)); } -static bool intel_dsb_enable_engine(struct intel_dsb *dsb) +static bool intel_dsb_enable_engine(struct drm_i915_private *i915, + enum pipe pipe, enum dsb_id id) { - struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - enum pipe pipe = crtc->pipe; u32 dsb_ctrl; - dsb_ctrl = intel_de_read(dev_priv, DSB_CTRL(pipe, dsb->id)); + dsb_ctrl = intel_de_read(i915, DSB_CTRL(pipe, id)); if (DSB_STATUS & dsb_ctrl) { - drm_dbg_kms(&dev_priv->drm, "DSB engine is busy.\n"); + drm_dbg_kms(&i915->drm, "DSB engine is busy.\n"); return false; } dsb_ctrl |= DSB_ENABLE; - intel_de_write(dev_priv, DSB_CTRL(pipe, dsb->id), dsb_ctrl); + intel_de_write(i915, DSB_CTRL(pipe, id), dsb_ctrl); - intel_de_posting_read(dev_priv, DSB_CTRL(pipe, dsb->id)); + intel_de_posting_read(i915, DSB_CTRL(pipe, id)); return true; } -static bool intel_dsb_disable_engine(struct intel_dsb *dsb) +static bool intel_dsb_disable_engine(struct drm_i915_private *i915, + enum pipe pipe, enum dsb_id id) { - struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - enum pipe pipe = crtc->pipe; u32 dsb_ctrl; - dsb_ctrl = intel_de_read(dev_priv, DSB_CTRL(pipe, dsb->id)); + dsb_ctrl = intel_de_read(i915, DSB_CTRL(pipe, id)); if (DSB_STATUS & dsb_ctrl) { - drm_dbg_kms(&dev_priv->drm, "DSB engine is busy.\n"); + drm_dbg_kms(&i915->drm, "DSB engine is busy.\n"); return false; } dsb_ctrl &= ~DSB_ENABLE; - intel_de_write(dev_priv, DSB_CTRL(pipe, dsb->id), dsb_ctrl); + intel_de_write(i915, DSB_CTRL(pipe, id), dsb_ctrl); - intel_de_posting_read(dev_priv, DSB_CTRL(pipe, dsb->id)); + intel_de_posting_read(i915, DSB_CTRL(pipe, id)); return true; } -/** - * intel_dsb_get() - Allocate DSB context and return a DSB instance. - * @crtc: intel_crtc structure to get pipe info. - * - * This function provides handle of a DSB instance, for the further DSB - * operations. - * - * Returns: address of Intel_dsb instance requested for. - * Failure: Returns the same DSB instance, but without a command buffer. - */ - -struct intel_dsb * -intel_dsb_get(struct intel_crtc *crtc) -{ - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *i915 = to_i915(dev); - struct intel_dsb *dsb = &crtc->dsb; - struct drm_i915_gem_object *obj; - struct i915_vma *vma; - u32 *buf; - intel_wakeref_t wakeref; - - if (!HAS_DSB(i915)) - return dsb; - - if (dsb->refcount++ != 0) - return dsb; - - wakeref = intel_runtime_pm_get(&i915->runtime_pm); - - obj = i915_gem_object_create_internal(i915, DSB_BUF_SIZE); - if (IS_ERR(obj)) { - drm_err(&i915->drm, "Gem object creation failed\n"); - goto out; - } - - vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0); - if (IS_ERR(vma)) { - drm_err(&i915->drm, "Vma creation failed\n"); - i915_gem_object_put(obj); - goto out; - } - - buf = i915_gem_object_pin_map(vma->obj, I915_MAP_WC); - if (IS_ERR(buf)) { - drm_err(&i915->drm, "Command buffer creation failed\n"); - goto out; - } - - dsb->id = DSB1; - dsb->vma = vma; - dsb->cmd_buf = buf; - -out: - /* - * On error dsb->cmd_buf will continue to be NULL, making the writes - * pass-through. Leave the dangling ref to be removed later by the - * corresponding intel_dsb_put(): the important error message will - * already be logged above. - */ - - intel_runtime_pm_put(&i915->runtime_pm, wakeref); - - return dsb; -} - -/** - * intel_dsb_put() - To destroy DSB context. - * @dsb: intel_dsb structure. - * - * This function destroys the DSB context allocated by a dsb_get(), by - * unpinning and releasing the VMA object associated with it. - */ - -void intel_dsb_put(struct intel_dsb *dsb) -{ - struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb); - struct drm_i915_private *i915 = to_i915(crtc->base.dev); - - if (!HAS_DSB(i915)) - return; - - if (drm_WARN_ON(&i915->drm, dsb->refcount == 0)) - return; - - if (--dsb->refcount == 0) { - i915_vma_unpin_and_release(&dsb->vma, I915_VMA_RELEASE_MAP); - dsb->cmd_buf = NULL; - dsb->free_pos = 0; - dsb->ins_start_offset = 0; - } -} - /** * intel_dsb_indexed_reg_write() -Write to the DSB context for auto * increment register. - * @dsb: intel_dsb structure. + * @crtc_state: intel_crtc_state structure * @reg: register address. * @val: value. * @@ -189,19 +89,20 @@ void intel_dsb_put(struct intel_dsb *dsb) * is done through mmio write. */ -void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg, - u32 val) +void intel_dsb_indexed_reg_write(const struct intel_crtc_state *crtc_state, + i915_reg_t reg, u32 val) { - struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb); + struct intel_dsb *dsb = crtc_state->dsb; + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - u32 *buf = dsb->cmd_buf; + u32 *buf; u32 reg_val; - if (!buf) { + if (!dsb) { intel_de_write(dev_priv, reg, val); return; } - + buf = dsb->cmd_buf; if (drm_WARN_ON(&dev_priv->drm, dsb->free_pos >= DSB_BUF_SIZE)) { drm_dbg_kms(&dev_priv->drm, "DSB buffer overflow\n"); return; @@ -256,7 +157,7 @@ void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg, /** * intel_dsb_reg_write() -Write to the DSB context for normal * register. - * @dsb: intel_dsb structure. + * @crtc_state: intel_crtc_state structure * @reg: register address. * @val: value. * @@ -265,17 +166,19 @@ void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg, * and rest all erroneous condition register programming is done * through mmio write. */ -void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val) +void intel_dsb_reg_write(const struct intel_crtc_state *crtc_state, + i915_reg_t reg, u32 val) { - struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb); + struct intel_dsb *dsb = crtc_state->dsb; + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); u32 *buf = dsb->cmd_buf; - if (!buf) { + if (!dsb) { intel_de_write(dev_priv, reg, val); return; } - + buf = dsb->cmd_buf; if (drm_WARN_ON(&dev_priv->drm, dsb->free_pos >= DSB_BUF_SIZE)) { drm_dbg_kms(&dev_priv->drm, "DSB buffer overflow\n"); return; @@ -290,26 +193,27 @@ void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val) /** * intel_dsb_commit() - Trigger workload execution of DSB. - * @dsb: intel_dsb structure. + * @crtc_state: intel_crtc_state structure * * This function is used to do actual write to hardware using DSB. * On errors, fall back to MMIO. Also this function help to reset the context. */ -void intel_dsb_commit(struct intel_dsb *dsb) +void intel_dsb_commit(const struct intel_crtc_state *crtc_state) { - struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb); + struct intel_dsb *dsb = crtc_state->dsb; + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); enum pipe pipe = crtc->pipe; u32 tail; - if (!dsb->free_pos) + if (!(dsb && dsb->free_pos)) return; - if (!intel_dsb_enable_engine(dsb)) + if (!intel_dsb_enable_engine(dev_priv, pipe, dsb->id)) goto reset; - if (is_dsb_busy(dsb)) { + if (is_dsb_busy(dev_priv, pipe, dsb->id)) { drm_err(&dev_priv->drm, "HEAD_PTR write failed - dsb engine is busy.\n"); goto reset; @@ -322,7 +226,7 @@ void intel_dsb_commit(struct intel_dsb *dsb) memset(&dsb->cmd_buf[dsb->free_pos], 0, (tail - dsb->free_pos * 4)); - if (is_dsb_busy(dsb)) { + if (is_dsb_busy(dev_priv, pipe, dsb->id)) { drm_err(&dev_priv->drm, "TAIL_PTR write failed - dsb engine is busy.\n"); goto reset; @@ -332,7 +236,7 @@ void intel_dsb_commit(struct intel_dsb *dsb) i915_ggtt_offset(dsb->vma), tail); intel_de_write(dev_priv, DSB_TAIL(pipe, dsb->id), i915_ggtt_offset(dsb->vma) + tail); - if (wait_for(!is_dsb_busy(dsb), 1)) { + if (wait_for(!is_dsb_busy(dev_priv, pipe, dsb->id), 1)) { drm_err(&dev_priv->drm, "Timed out waiting for DSB workload completion.\n"); goto reset; @@ -341,5 +245,79 @@ void intel_dsb_commit(struct intel_dsb *dsb) reset: dsb->free_pos = 0; dsb->ins_start_offset = 0; - intel_dsb_disable_engine(dsb); + intel_dsb_disable_engine(dev_priv, pipe, dsb->id); +} + +/** + * intel_dsb_prepare() - Allocate, pin and map the DSB command buffer. + * @crtc_state: intel_crtc_state structure to prepare associated dsb instance. + * + * This function prepare the command buffer which is used to store dsb + * instructions with data. + */ +void intel_dsb_prepare(struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct intel_dsb *dsb; + struct drm_i915_gem_object *obj; + struct i915_vma *vma; + u32 *buf; + intel_wakeref_t wakeref; + + if (!HAS_DSB(i915)) + return; + + dsb = kmalloc(sizeof(*dsb), GFP_KERNEL); + + wakeref = intel_runtime_pm_get(&i915->runtime_pm); + + obj = i915_gem_object_create_internal(i915, DSB_BUF_SIZE); + if (IS_ERR(obj)) { + drm_err(&i915->drm, "Gem object creation failed\n"); + kfree(dsb); + goto out; + } + + vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0); + if (IS_ERR(vma)) { + drm_err(&i915->drm, "Vma creation failed\n"); + i915_gem_object_put(obj); + kfree(dsb); + goto out; + } + + buf = i915_gem_object_pin_map(vma->obj, I915_MAP_WC); + if (IS_ERR(buf)) { + drm_err(&i915->drm, "Command buffer creation failed\n"); + i915_vma_unpin_and_release(&vma, I915_VMA_RELEASE_MAP); + kfree(dsb); + goto out; + } + + dsb->id = DSB1; + dsb->vma = vma; + dsb->cmd_buf = buf; + dsb->free_pos = 0; + dsb->ins_start_offset = 0; + crtc_state->dsb = dsb; +out: + intel_runtime_pm_put(&i915->runtime_pm, wakeref); +} + +/** + * intel_dsb_cleanup() - To cleanup DSB context. + * @crtc_state: intel_crtc_state structure to cleanup associated dsb instance. + * + * This function cleanup the DSB context by unpinning and releasing + * the VMA object associated with it. + */ +void intel_dsb_cleanup(struct intel_crtc_state *crtc_state) +{ + if (!crtc_state->dsb) + return; + + i915_vma_unpin_and_release(&crtc_state->dsb->vma, I915_VMA_RELEASE_MAP); + kfree(crtc_state->dsb); + crtc_state->dsb = NULL; } diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h index 395ef9ce558e..654a11f24b80 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.h +++ b/drivers/gpu/drm/i915/display/intel_dsb.h @@ -10,7 +10,7 @@ #include "i915_reg.h" -struct intel_crtc; +struct intel_crtc_state; struct i915_vma; enum dsb_id { @@ -22,7 +22,6 @@ enum dsb_id { }; struct intel_dsb { - long refcount; enum dsb_id id; u32 *cmd_buf; struct i915_vma *vma; @@ -41,12 +40,12 @@ struct intel_dsb { u32 ins_start_offset; }; -struct intel_dsb * -intel_dsb_get(struct intel_crtc *crtc); -void intel_dsb_put(struct intel_dsb *dsb); -void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val); -void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg, - u32 val); -void intel_dsb_commit(struct intel_dsb *dsb); +void intel_dsb_prepare(struct intel_crtc_state *crtc_state); +void intel_dsb_cleanup(struct intel_crtc_state *crtc_state); +void intel_dsb_reg_write(const struct intel_crtc_state *crtc_state, + i915_reg_t reg, u32 val); +void intel_dsb_indexed_reg_write(const struct intel_crtc_state *crtc_state, + i915_reg_t reg, u32 val); +void intel_dsb_commit(const struct intel_crtc_state *crtc_state); #endif -- 2.26.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 4+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dsb: Pre allocate and late cleanup of cmd buffer (rev10) 2020-05-20 13:07 [Intel-gfx] [PATCH v11] drm/i915/dsb: Pre allocate and late cleanup of cmd buffer Animesh Manna @ 2020-05-20 14:55 ` Patchwork 2020-05-21 6:09 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2020-05-23 9:52 ` [Intel-gfx] [PATCH v11] drm/i915/dsb: Pre allocate and late cleanup of cmd buffer Shankar, Uma 2 siblings, 0 replies; 4+ messages in thread From: Patchwork @ 2020-05-20 14:55 UTC (permalink / raw) To: Animesh Manna; +Cc: intel-gfx == Series Details == Series: drm/i915/dsb: Pre allocate and late cleanup of cmd buffer (rev10) URL : https://patchwork.freedesktop.org/series/73036/ State : success == Summary == CI Bug Log - changes from CI_DRM_8511 -> Patchwork_17732 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17732/index.html Known issues ------------ Here are the changes found in Patchwork_17732 that come from known issues: ### IGT changes ### #### Possible fixes #### * igt@i915_pm_rpm@module-reload: - fi-kbl-guc: [SKIP][1] ([fdo#109271]) -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17732/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html #### Warnings #### * igt@i915_pm_rpm@module-reload: - fi-kbl-x1275: [SKIP][3] ([fdo#109271]) -> [FAIL][4] ([i915#62]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17732/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 Participating hosts (48 -> 44) ------------------------------ Missing (4): fi-byt-clapper fi-byt-squawks fi-bsw-cyan fi-hsw-4200u Build changes ------------- * Linux: CI_DRM_8511 -> Patchwork_17732 CI-20190529: 20190529 CI_DRM_8511: 504ee538bd65abff745914a6f0b7aad62bbc1d11 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5664: 404e2fa06b9c5986dec3fa210234fe8b034b157e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17732: 8c8cb1efb20f5c596ec7ace6e9a023abb400ccd6 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 8c8cb1efb20f drm/i915/dsb: Pre allocate and late cleanup of cmd buffer == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17732/index.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 4+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dsb: Pre allocate and late cleanup of cmd buffer (rev10) 2020-05-20 13:07 [Intel-gfx] [PATCH v11] drm/i915/dsb: Pre allocate and late cleanup of cmd buffer Animesh Manna 2020-05-20 14:55 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dsb: Pre allocate and late cleanup of cmd buffer (rev10) Patchwork @ 2020-05-21 6:09 ` Patchwork 2020-05-23 9:52 ` [Intel-gfx] [PATCH v11] drm/i915/dsb: Pre allocate and late cleanup of cmd buffer Shankar, Uma 2 siblings, 0 replies; 4+ messages in thread From: Patchwork @ 2020-05-21 6:09 UTC (permalink / raw) To: Animesh Manna; +Cc: intel-gfx == Series Details == Series: drm/i915/dsb: Pre allocate and late cleanup of cmd buffer (rev10) URL : https://patchwork.freedesktop.org/series/73036/ State : success == Summary == CI Bug Log - changes from CI_DRM_8511_full -> Patchwork_17732_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17732_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_ctx_persistence@engines-hostile@vcs0: - shard-iclb: [PASS][1] -> [FAIL][2] ([i915#1622]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-iclb3/igt@gem_ctx_persistence@engines-hostile@vcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17732/shard-iclb4/igt@gem_ctx_persistence@engines-hostile@vcs0.html * igt@gem_workarounds@suspend-resume: - shard-skl: [PASS][3] -> [INCOMPLETE][4] ([i915#69]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-skl8/igt@gem_workarounds@suspend-resume.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17732/shard-skl4/igt@gem_workarounds@suspend-resume.html * igt@gem_workarounds@suspend-resume-fd: - shard-kbl: [PASS][5] -> [INCOMPLETE][6] ([i915#155]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-kbl7/igt@gem_workarounds@suspend-resume-fd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17732/shard-kbl2/igt@gem_workarounds@suspend-resume-fd.html * igt@i915_suspend@sysfs-reader: - shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([i915#180]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-kbl6/igt@i915_suspend@sysfs-reader.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17732/shard-kbl2/igt@i915_suspend@sysfs-reader.html * igt@kms_cursor_crc@pipe-b-cursor-suspend: - shard-skl: [PASS][9] -> [INCOMPLETE][10] ([i915#300]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-skl7/igt@kms_cursor_crc@pipe-b-cursor-suspend.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17732/shard-skl5/igt@kms_cursor_crc@pipe-b-cursor-suspend.html * igt@kms_cursor_crc@pipe-c-cursor-128x128-offscreen: - shard-skl: [PASS][11] -> [FAIL][12] ([i915#54]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-skl5/igt@kms_cursor_crc@pipe-c-cursor-128x128-offscreen.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17732/shard-skl5/igt@kms_cursor_crc@pipe-c-cursor-128x128-offscreen.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#180] / [i915#95]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-apl2/igt@kms_frontbuffer_tracking@fbc-suspend.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17732/shard-apl6/igt@kms_frontbuffer_tracking@fbc-suspend.html * igt@kms_psr@psr2_no_drrs: - shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109441]) +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-iclb2/igt@kms_psr@psr2_no_drrs.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17732/shard-iclb6/igt@kms_psr@psr2_no_drrs.html * igt@kms_setmode@basic: - shard-kbl: [PASS][17] -> [FAIL][18] ([i915#31]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-kbl1/igt@kms_setmode@basic.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17732/shard-kbl1/igt@kms_setmode@basic.html #### Possible fixes #### * igt@gem_ctx_persistence@engines-hostile@rcs0: - shard-iclb: [FAIL][19] ([i915#1622]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-iclb3/igt@gem_ctx_persistence@engines-hostile@rcs0.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17732/shard-iclb4/igt@gem_ctx_persistence@engines-hostile@rcs0.html * igt@gem_ctx_persistence@legacy-engines-mixed-process@blt: - shard-skl: [FAIL][21] ([i915#1528]) -> [PASS][22] +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-skl3/igt@gem_ctx_persistence@legacy-engines-mixed-process@blt.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17732/shard-skl9/igt@gem_ctx_persistence@legacy-engines-mixed-process@blt.html * {igt@gem_exec_schedule@pi-distinct-iova@bcs0}: - shard-glk: [FAIL][23] ([i915#859]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-glk6/igt@gem_exec_schedule@pi-distinct-iova@bcs0.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17732/shard-glk2/igt@gem_exec_schedule@pi-distinct-iova@bcs0.html * igt@i915_pm_dc@dc6-psr: - shard-iclb: [FAIL][25] ([i915#454]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-iclb6/igt@i915_pm_dc@dc6-psr.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17732/shard-iclb2/igt@i915_pm_dc@dc6-psr.html * igt@i915_suspend@fence-restore-untiled: - shard-kbl: [DMESG-WARN][27] ([i915#180]) -> [PASS][28] +1 similar issue [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-kbl3/igt@i915_suspend@fence-restore-untiled.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17732/shard-kbl3/igt@i915_suspend@fence-restore-untiled.html * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic: - shard-glk: [FAIL][29] ([i915#72]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-glk1/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17732/shard-glk7/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html * {igt@kms_flip@flip-vs-expired-vblank@a-edp1}: - shard-skl: [FAIL][31] ([i915#79]) -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-skl4/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17732/shard-skl3/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html * {igt@kms_flip@flip-vs-suspend-interruptible@c-dp1}: - shard-apl: [DMESG-WARN][33] ([i915#180]) -> [PASS][34] +6 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17732/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html * igt@kms_hdr@bpc-switch-suspend: - shard-skl: [FAIL][35] ([i915#1188]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-skl3/igt@kms_hdr@bpc-switch-suspend.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17732/shard-skl3/igt@kms_hdr@bpc-switch-suspend.html * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [FAIL][37] ([fdo#108145] / [i915#265]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17732/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt@kms_psr@psr2_primary_mmap_cpu: - shard-iclb: [SKIP][39] ([fdo#109441]) -> [PASS][40] +1 similar issue [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-iclb6/igt@kms_psr@psr2_primary_mmap_cpu.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17732/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html * igt@kms_setmode@basic: - shard-apl: [FAIL][41] ([i915#31]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-apl2/igt@kms_setmode@basic.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17732/shard-apl6/igt@kms_setmode@basic.html #### Warnings #### * igt@kms_color@pipe-d-ctm-0-75: - shard-tglb: [FAIL][43] ([i915#1149] / [i915#315]) -> [INCOMPLETE][44] ([i915#1149]) [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-tglb6/igt@kms_color@pipe-d-ctm-0-75.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17732/shard-tglb5/igt@kms_color@pipe-d-ctm-0-75.html * igt@kms_content_protection@atomic: - shard-apl: [FAIL][45] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][46] ([i915#1319]) [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-apl2/igt@kms_content_protection@atomic.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17732/shard-apl6/igt@kms_content_protection@atomic.html * igt@kms_psr2_su@frontbuffer: - shard-iclb: [SKIP][47] -> [SKIP][48] ([fdo#109642] / [fdo#111068]) [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-iclb2/igt@kms_psr2_su@frontbuffer.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17732/shard-iclb7/igt@kms_psr2_su@frontbuffer.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1622]: https://gitlab.freedesktop.org/drm/intel/issues/1622 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1883]: https://gitlab.freedesktop.org/drm/intel/issues/1883 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#300]: https://gitlab.freedesktop.org/drm/intel/issues/300 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#859]: https://gitlab.freedesktop.org/drm/intel/issues/859 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8511 -> Patchwork_17732 CI-20190529: 20190529 CI_DRM_8511: 504ee538bd65abff745914a6f0b7aad62bbc1d11 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5664: 404e2fa06b9c5986dec3fa210234fe8b034b157e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17732: 8c8cb1efb20f5c596ec7ace6e9a023abb400ccd6 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17732/index.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Intel-gfx] [PATCH v11] drm/i915/dsb: Pre allocate and late cleanup of cmd buffer 2020-05-20 13:07 [Intel-gfx] [PATCH v11] drm/i915/dsb: Pre allocate and late cleanup of cmd buffer Animesh Manna 2020-05-20 14:55 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dsb: Pre allocate and late cleanup of cmd buffer (rev10) Patchwork 2020-05-21 6:09 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork @ 2020-05-23 9:52 ` Shankar, Uma 2 siblings, 0 replies; 4+ messages in thread From: Shankar, Uma @ 2020-05-23 9:52 UTC (permalink / raw) To: Manna, Animesh, intel-gfx; +Cc: Nikula, Jani, Daniel Vetter, Lankhorst, Maarten > -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Animesh > Manna > Sent: Wednesday, May 20, 2020 6:38 PM > To: intel-gfx@lists.freedesktop.org > Cc: Nikula, Jani <jani.nikula@intel.com>; Daniel Vetter <daniel.vetter@ffwll.ch>; > Lankhorst, Maarten <maarten.lankhorst@intel.com> > Subject: [Intel-gfx] [PATCH v11] drm/i915/dsb: Pre allocate and late cleanup of > cmd buffer > > Pre-allocate command buffer in atomic_commit using intel_dsb_prepare > function which also includes pinning and map in cpu domain. > > No functional change is dsb write/commit functions. > > Now dsb get/put function is removed and ref-count mechanism is not needed. > Below dsb api added to do respective job mentioned below. > > intel_dsb_prepare - Allocate, pin and map the buffer. > intel_dsb_cleanup - Unpin and release the gem object. > > RFC: Initial patch for design review. > v2: included _init() part in _prepare(). [Daniel, Ville] > v3: dsb_cleanup called after cleanup_planes. [Daniel] > v4: dsb structure is moved to intel_crtc_state from intel_crtc. [Maarten] > v5: dsb get/put/ref-count mechanism removed. [Maarten] > v6: Based on review feedback following changes are added, > - replaced intel_dsb structure by pointer in intel_crtc_state. [Maarten] > - passing intel_crtc_state to dsp-api to simplify the code. [Maarten] > - few dsb functions prototype modified to simplify code. > v7: added few cosmetic changes suggested by Jani and null check for crtc_state in > dsb_cleanup removed as suggested by Maarten. > v8: changed the function parameter to intel_crtc_state* of > ivb_load_lut_ext_max() from intel_crtc. [Maarten] > v9: error handling improved in _write() and prepare(). [Maarten] > > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Cc: Jani Nikula <jani.nikula@intel.com> > Cc: Daniel Vetter <daniel.vetter@ffwll.ch> > Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> > Reviewed-by: Maarten Lankhorst <maarten.lankhorst@intel.com> > Signed-off-by: Animesh Manna <animesh.manna@intel.com> Pushed the patch to dinq. Thanks for the patch and reviews. Regards, Uma Shankar > drivers/gpu/drm/i915/display/intel_atomic.c | 3 + > drivers/gpu/drm/i915/display/intel_color.c | 66 ++--- > drivers/gpu/drm/i915/display/intel_display.c | 58 +++- > .../drm/i915/display/intel_display_types.h | 6 +- > drivers/gpu/drm/i915/display/intel_dsb.c | 250 ++++++++---------- > drivers/gpu/drm/i915/display/intel_dsb.h | 17 +- > 6 files changed, 206 insertions(+), 194 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c > b/drivers/gpu/drm/i915/display/intel_atomic.c > index d043057d2fa0..3cb866f22e74 100644 > --- a/drivers/gpu/drm/i915/display/intel_atomic.c > +++ b/drivers/gpu/drm/i915/display/intel_atomic.c > @@ -252,6 +252,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc) > crtc_state->wm.need_postvbl_update = false; > crtc_state->fb_bits = 0; > crtc_state->update_planes = 0; > + crtc_state->dsb = NULL; > > return &crtc_state->uapi; > } > @@ -292,6 +293,8 @@ intel_crtc_destroy_state(struct drm_crtc *crtc, { > struct intel_crtc_state *crtc_state = to_intel_crtc_state(state); > > + drm_WARN_ON(crtc->dev, crtc_state->dsb); > + > __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi); > intel_crtc_free_hw_state(crtc_state); > kfree(crtc_state); > diff --git a/drivers/gpu/drm/i915/display/intel_color.c > b/drivers/gpu/drm/i915/display/intel_color.c > index 98ece9cd7cdd..945bb03bdd4d 100644 > --- a/drivers/gpu/drm/i915/display/intel_color.c > +++ b/drivers/gpu/drm/i915/display/intel_color.c > @@ -714,16 +714,16 @@ static void bdw_load_lut_10(struct intel_crtc *crtc, > intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), 0); } > > -static void ivb_load_lut_ext_max(struct intel_crtc *crtc) > +static void ivb_load_lut_ext_max(const struct intel_crtc_state > +*crtc_state) > { > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > - struct intel_dsb *dsb = intel_dsb_get(crtc); > enum pipe pipe = crtc->pipe; > > /* Program the max register to clamp values > 1.0. */ > - intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16); > - intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16); > - intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16); > + intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << > 16); > + intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << > 16); > + intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << > +16); > > /* > * Program the gc max 2 register to clamp values > 1.0. > @@ -731,15 +731,13 @@ static void ivb_load_lut_ext_max(struct intel_crtc > *crtc) > * from 3.0 to 7.0 > */ > if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { > - intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 0), > + intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, > 0), > 1 << 16); > - intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 1), > + intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, > 1), > 1 << 16); > - intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 2), > + intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, > 2), > 1 << 16); > } > - > - intel_dsb_put(dsb); > } > > static void ivb_load_luts(const struct intel_crtc_state *crtc_state) @@ -753,7 > +751,7 @@ static void ivb_load_luts(const struct intel_crtc_state *crtc_state) > } else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) { > ivb_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE | > PAL_PREC_INDEX_VALUE(0)); > - ivb_load_lut_ext_max(crtc); > + ivb_load_lut_ext_max(crtc_state); > ivb_load_lut_10(crtc, gamma_lut, PAL_PREC_SPLIT_MODE | > PAL_PREC_INDEX_VALUE(512)); > } else { > @@ -761,7 +759,7 @@ static void ivb_load_luts(const struct intel_crtc_state > *crtc_state) > > ivb_load_lut_10(crtc, blob, > PAL_PREC_INDEX_VALUE(0)); > - ivb_load_lut_ext_max(crtc); > + ivb_load_lut_ext_max(crtc_state); > } > } > > @@ -776,7 +774,7 @@ static void bdw_load_luts(const struct intel_crtc_state > *crtc_state) > } else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) { > bdw_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE | > PAL_PREC_INDEX_VALUE(0)); > - ivb_load_lut_ext_max(crtc); > + ivb_load_lut_ext_max(crtc_state); > bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_SPLIT_MODE | > PAL_PREC_INDEX_VALUE(512)); > } else { > @@ -784,7 +782,7 @@ static void bdw_load_luts(const struct intel_crtc_state > *crtc_state) > > bdw_load_lut_10(crtc, blob, > PAL_PREC_INDEX_VALUE(0)); > - ivb_load_lut_ext_max(crtc); > + ivb_load_lut_ext_max(crtc_state); > } > } > > @@ -877,7 +875,7 @@ static void glk_load_luts(const struct intel_crtc_state > *crtc_state) > ilk_load_lut_8(crtc, gamma_lut); > } else { > bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0)); > - ivb_load_lut_ext_max(crtc); > + ivb_load_lut_ext_max(crtc_state); > } > } > > @@ -900,14 +898,12 @@ icl_load_gcmax(const struct intel_crtc_state > *crtc_state, > const struct drm_color_lut *color) { > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > - struct intel_dsb *dsb = intel_dsb_get(crtc); > enum pipe pipe = crtc->pipe; > > /* FIXME LUT entries are 16 bit only, so we can prog 0xFFFF max */ > - intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 0), color->red); > - intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 1), color->green); > - intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 2), color->blue); > - intel_dsb_put(dsb); > + intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 0), color->red); > + intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 1), color- > >green); > + intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 2), > +color->blue); > } > > static void > @@ -916,7 +912,6 @@ icl_program_gamma_superfine_segment(const struct > intel_crtc_state *crtc_state) > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > const struct drm_property_blob *blob = crtc_state->hw.gamma_lut; > const struct drm_color_lut *lut = blob->data; > - struct intel_dsb *dsb = intel_dsb_get(crtc); > enum pipe pipe = crtc->pipe; > int i; > > @@ -927,19 +922,17 @@ icl_program_gamma_superfine_segment(const struct > intel_crtc_state *crtc_state) > * 9 entries, corresponding to values 0, 1/(8 * 128 * 256), > * 2/(8 * 128 * 256) ... 8/(8 * 128 * 256). > */ > - intel_dsb_reg_write(dsb, PREC_PAL_MULTI_SEG_INDEX(pipe), > + intel_dsb_reg_write(crtc_state, PREC_PAL_MULTI_SEG_INDEX(pipe), > PAL_PREC_AUTO_INCREMENT); > > for (i = 0; i < 9; i++) { > const struct drm_color_lut *entry = &lut[i]; > > - intel_dsb_indexed_reg_write(dsb, > PREC_PAL_MULTI_SEG_DATA(pipe), > + intel_dsb_indexed_reg_write(crtc_state, > +PREC_PAL_MULTI_SEG_DATA(pipe), > ilk_lut_12p4_ldw(entry)); > - intel_dsb_indexed_reg_write(dsb, > PREC_PAL_MULTI_SEG_DATA(pipe), > + intel_dsb_indexed_reg_write(crtc_state, > +PREC_PAL_MULTI_SEG_DATA(pipe), > ilk_lut_12p4_udw(entry)); > } > - > - intel_dsb_put(dsb); > } > > static void > @@ -949,7 +942,6 @@ icl_program_gamma_multi_segment(const struct > intel_crtc_state *crtc_state) > const struct drm_property_blob *blob = crtc_state->hw.gamma_lut; > const struct drm_color_lut *lut = blob->data; > const struct drm_color_lut *entry; > - struct intel_dsb *dsb = intel_dsb_get(crtc); > enum pipe pipe = crtc->pipe; > int i; > > @@ -963,12 +955,13 @@ icl_program_gamma_multi_segment(const struct > intel_crtc_state *crtc_state) > * PAL_PREC_INDEX[0] and PAL_PREC_INDEX[1] map to seg2[1], > * seg2[0] being unused by the hardware. > */ > - intel_dsb_reg_write(dsb, PREC_PAL_INDEX(pipe), > PAL_PREC_AUTO_INCREMENT); > + intel_dsb_reg_write(crtc_state, PREC_PAL_INDEX(pipe), > + PAL_PREC_AUTO_INCREMENT); > for (i = 1; i < 257; i++) { > entry = &lut[i * 8]; > - intel_dsb_indexed_reg_write(dsb, PREC_PAL_DATA(pipe), > + intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe), > ilk_lut_12p4_ldw(entry)); > - intel_dsb_indexed_reg_write(dsb, PREC_PAL_DATA(pipe), > + intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe), > ilk_lut_12p4_udw(entry)); > } > > @@ -986,24 +979,22 @@ icl_program_gamma_multi_segment(const struct > intel_crtc_state *crtc_state) > */ > for (i = 0; i < 256; i++) { > entry = &lut[i * 8 * 128]; > - intel_dsb_indexed_reg_write(dsb, PREC_PAL_DATA(pipe), > + intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe), > ilk_lut_12p4_ldw(entry)); > - intel_dsb_indexed_reg_write(dsb, PREC_PAL_DATA(pipe), > + intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe), > ilk_lut_12p4_udw(entry)); > } > > /* The last entry in the LUT is to be programmed in GCMAX */ > entry = &lut[256 * 8 * 128]; > icl_load_gcmax(crtc_state, entry); > - ivb_load_lut_ext_max(crtc); > - intel_dsb_put(dsb); > + ivb_load_lut_ext_max(crtc_state); > } > > static void icl_load_luts(const struct intel_crtc_state *crtc_state) { > const struct drm_property_blob *gamma_lut = crtc_state- > >hw.gamma_lut; > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > - struct intel_dsb *dsb = intel_dsb_get(crtc); > > if (crtc_state->hw.degamma_lut) > glk_load_degamma_lut(crtc_state); > @@ -1018,11 +1009,10 @@ static void icl_load_luts(const struct intel_crtc_state > *crtc_state) > break; > default: > bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0)); > - ivb_load_lut_ext_max(crtc); > + ivb_load_lut_ext_max(crtc_state); > } > > - intel_dsb_commit(dsb); > - intel_dsb_put(dsb); > + intel_dsb_commit(crtc_state); > } > > static u32 chv_cgm_degamma_ldw(const struct drm_color_lut *color) diff --git > a/drivers/gpu/drm/i915/display/intel_display.c > b/drivers/gpu/drm/i915/display/intel_display.c > index 432b4eeaf9f6..514483ffd247 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -14873,8 +14873,24 @@ static int intel_atomic_check(struct drm_device > *dev, > > static int intel_atomic_prepare_commit(struct intel_atomic_state *state) { > - return drm_atomic_helper_prepare_planes(state->base.dev, > - &state->base); > + struct intel_crtc_state *crtc_state; > + struct intel_crtc *crtc; > + int i, ret; > + > + ret = drm_atomic_helper_prepare_planes(state->base.dev, &state- > >base); > + if (ret < 0) > + return ret; > + > + for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { > + bool mode_changed = needs_modeset(crtc_state); > + > + if (mode_changed || crtc_state->update_pipe || > + crtc_state->uapi.color_mgmt_changed) { > + intel_dsb_prepare(crtc_state); > + } > + } > + > + return 0; > } > > u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc) @@ -15327,15 > +15343,27 @@ static void intel_atomic_commit_fence_wait(struct > intel_atomic_state *intel_stat > &wait_reset); > } > > +static void intel_cleanup_dsbs(struct intel_atomic_state *state) { > + struct intel_crtc_state *old_crtc_state, *new_crtc_state; > + struct intel_crtc *crtc; > + int i; > + > + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, > + new_crtc_state, i) > + intel_dsb_cleanup(old_crtc_state); > +} > + > static void intel_atomic_cleanup_work(struct work_struct *work) { > - struct drm_atomic_state *state = > - container_of(work, struct drm_atomic_state, commit_work); > - struct drm_i915_private *i915 = to_i915(state->dev); > + struct intel_atomic_state *state = > + container_of(work, struct intel_atomic_state, > base.commit_work); > + struct drm_i915_private *i915 = to_i915(state->base.dev); > > - drm_atomic_helper_cleanup_planes(&i915->drm, state); > - drm_atomic_helper_commit_cleanup_done(state); > - drm_atomic_state_put(state); > + intel_cleanup_dsbs(state); > + drm_atomic_helper_cleanup_planes(&i915->drm, &state->base); > + drm_atomic_helper_commit_cleanup_done(&state->base); > + drm_atomic_state_put(&state->base); > > intel_atomic_helper_free_state(i915); > } > @@ -15469,6 +15497,13 @@ static void intel_atomic_commit_tail(struct > intel_atomic_state *state) > modeset_put_power_domains(dev_priv, > put_domains[i]); > > intel_modeset_verify_crtc(crtc, state, old_crtc_state, > new_crtc_state); > + > + /* > + * DSB cleanup is done in cleanup_work aligning with framebuffer > + * cleanup. So copy and reset the dsb structure to sync with > + * commit_done and later do dsb cleanup in cleanup_work. > + */ > + old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb); > } > > /* Underruns don't always raise interrupts, so check manually */ @@ - > 15618,8 +15653,15 @@ static int intel_atomic_commit(struct drm_device *dev, > intel_atomic_swap_global_state(state); > > if (ret) { > + struct intel_crtc_state *new_crtc_state; > + struct intel_crtc *crtc; > + int i; > + > i915_sw_fence_commit(&state->commit_ready); > > + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) > + intel_dsb_cleanup(new_crtc_state); > + > drm_atomic_helper_cleanup_planes(dev, &state->base); > intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); > return ret; > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h > b/drivers/gpu/drm/i915/display/intel_display_types.h > index 87876fce91a5..ca579005d818 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -1078,6 +1078,9 @@ struct intel_crtc_state { > > /* Only valid on TGL+ */ > enum transcoder mst_master_transcoder; > + > + /* For DSB related info */ > + struct intel_dsb *dsb; > }; > > enum intel_pipe_crc_source { > @@ -1147,9 +1150,6 @@ struct intel_crtc { > /* scalers available on this crtc */ > int num_scalers; > > - /* per pipe DSB related info */ > - struct intel_dsb dsb; > - > #ifdef CONFIG_DEBUG_FS > struct intel_pipe_crc pipe_crc; > #endif > diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c > b/drivers/gpu/drm/i915/display/intel_dsb.c > index 29fec6a92d17..475106e91fa7 100644 > --- a/drivers/gpu/drm/i915/display/intel_dsb.c > +++ b/drivers/gpu/drm/i915/display/intel_dsb.c > @@ -34,152 +34,52 @@ > #define DSB_BYTE_EN_SHIFT 20 > #define DSB_REG_VALUE_MASK 0xfffff > > -static bool is_dsb_busy(struct intel_dsb *dsb) > +static bool is_dsb_busy(struct drm_i915_private *i915, enum pipe pipe, > + enum dsb_id id) > { > - struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb); > - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > - enum pipe pipe = crtc->pipe; > - > - return DSB_STATUS & intel_de_read(dev_priv, DSB_CTRL(pipe, dsb->id)); > + return DSB_STATUS & intel_de_read(i915, DSB_CTRL(pipe, id)); > } > > -static bool intel_dsb_enable_engine(struct intel_dsb *dsb) > +static bool intel_dsb_enable_engine(struct drm_i915_private *i915, > + enum pipe pipe, enum dsb_id id) > { > - struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb); > - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > - enum pipe pipe = crtc->pipe; > u32 dsb_ctrl; > > - dsb_ctrl = intel_de_read(dev_priv, DSB_CTRL(pipe, dsb->id)); > + dsb_ctrl = intel_de_read(i915, DSB_CTRL(pipe, id)); > if (DSB_STATUS & dsb_ctrl) { > - drm_dbg_kms(&dev_priv->drm, "DSB engine is busy.\n"); > + drm_dbg_kms(&i915->drm, "DSB engine is busy.\n"); > return false; > } > > dsb_ctrl |= DSB_ENABLE; > - intel_de_write(dev_priv, DSB_CTRL(pipe, dsb->id), dsb_ctrl); > + intel_de_write(i915, DSB_CTRL(pipe, id), dsb_ctrl); > > - intel_de_posting_read(dev_priv, DSB_CTRL(pipe, dsb->id)); > + intel_de_posting_read(i915, DSB_CTRL(pipe, id)); > return true; > } > > -static bool intel_dsb_disable_engine(struct intel_dsb *dsb) > +static bool intel_dsb_disable_engine(struct drm_i915_private *i915, > + enum pipe pipe, enum dsb_id id) > { > - struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb); > - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > - enum pipe pipe = crtc->pipe; > u32 dsb_ctrl; > > - dsb_ctrl = intel_de_read(dev_priv, DSB_CTRL(pipe, dsb->id)); > + dsb_ctrl = intel_de_read(i915, DSB_CTRL(pipe, id)); > if (DSB_STATUS & dsb_ctrl) { > - drm_dbg_kms(&dev_priv->drm, "DSB engine is busy.\n"); > + drm_dbg_kms(&i915->drm, "DSB engine is busy.\n"); > return false; > } > > dsb_ctrl &= ~DSB_ENABLE; > - intel_de_write(dev_priv, DSB_CTRL(pipe, dsb->id), dsb_ctrl); > + intel_de_write(i915, DSB_CTRL(pipe, id), dsb_ctrl); > > - intel_de_posting_read(dev_priv, DSB_CTRL(pipe, dsb->id)); > + intel_de_posting_read(i915, DSB_CTRL(pipe, id)); > return true; > } > > -/** > - * intel_dsb_get() - Allocate DSB context and return a DSB instance. > - * @crtc: intel_crtc structure to get pipe info. > - * > - * This function provides handle of a DSB instance, for the further DSB > - * operations. > - * > - * Returns: address of Intel_dsb instance requested for. > - * Failure: Returns the same DSB instance, but without a command buffer. > - */ > - > -struct intel_dsb * > -intel_dsb_get(struct intel_crtc *crtc) > -{ > - struct drm_device *dev = crtc->base.dev; > - struct drm_i915_private *i915 = to_i915(dev); > - struct intel_dsb *dsb = &crtc->dsb; > - struct drm_i915_gem_object *obj; > - struct i915_vma *vma; > - u32 *buf; > - intel_wakeref_t wakeref; > - > - if (!HAS_DSB(i915)) > - return dsb; > - > - if (dsb->refcount++ != 0) > - return dsb; > - > - wakeref = intel_runtime_pm_get(&i915->runtime_pm); > - > - obj = i915_gem_object_create_internal(i915, DSB_BUF_SIZE); > - if (IS_ERR(obj)) { > - drm_err(&i915->drm, "Gem object creation failed\n"); > - goto out; > - } > - > - vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0); > - if (IS_ERR(vma)) { > - drm_err(&i915->drm, "Vma creation failed\n"); > - i915_gem_object_put(obj); > - goto out; > - } > - > - buf = i915_gem_object_pin_map(vma->obj, I915_MAP_WC); > - if (IS_ERR(buf)) { > - drm_err(&i915->drm, "Command buffer creation failed\n"); > - goto out; > - } > - > - dsb->id = DSB1; > - dsb->vma = vma; > - dsb->cmd_buf = buf; > - > -out: > - /* > - * On error dsb->cmd_buf will continue to be NULL, making the writes > - * pass-through. Leave the dangling ref to be removed later by the > - * corresponding intel_dsb_put(): the important error message will > - * already be logged above. > - */ > - > - intel_runtime_pm_put(&i915->runtime_pm, wakeref); > - > - return dsb; > -} > - > -/** > - * intel_dsb_put() - To destroy DSB context. > - * @dsb: intel_dsb structure. > - * > - * This function destroys the DSB context allocated by a dsb_get(), by > - * unpinning and releasing the VMA object associated with it. > - */ > - > -void intel_dsb_put(struct intel_dsb *dsb) -{ > - struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb); > - struct drm_i915_private *i915 = to_i915(crtc->base.dev); > - > - if (!HAS_DSB(i915)) > - return; > - > - if (drm_WARN_ON(&i915->drm, dsb->refcount == 0)) > - return; > - > - if (--dsb->refcount == 0) { > - i915_vma_unpin_and_release(&dsb->vma, > I915_VMA_RELEASE_MAP); > - dsb->cmd_buf = NULL; > - dsb->free_pos = 0; > - dsb->ins_start_offset = 0; > - } > -} > - > /** > * intel_dsb_indexed_reg_write() -Write to the DSB context for auto > * increment register. > - * @dsb: intel_dsb structure. > + * @crtc_state: intel_crtc_state structure > * @reg: register address. > * @val: value. > * > @@ -189,19 +89,20 @@ void intel_dsb_put(struct intel_dsb *dsb) > * is done through mmio write. > */ > > -void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg, > - u32 val) > +void intel_dsb_indexed_reg_write(const struct intel_crtc_state *crtc_state, > + i915_reg_t reg, u32 val) > { > - struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb); > + struct intel_dsb *dsb = crtc_state->dsb; > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > - u32 *buf = dsb->cmd_buf; > + u32 *buf; > u32 reg_val; > > - if (!buf) { > + if (!dsb) { > intel_de_write(dev_priv, reg, val); > return; > } > - > + buf = dsb->cmd_buf; > if (drm_WARN_ON(&dev_priv->drm, dsb->free_pos >= DSB_BUF_SIZE)) { > drm_dbg_kms(&dev_priv->drm, "DSB buffer overflow\n"); > return; > @@ -256,7 +157,7 @@ void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, > i915_reg_t reg, > /** > * intel_dsb_reg_write() -Write to the DSB context for normal > * register. > - * @dsb: intel_dsb structure. > + * @crtc_state: intel_crtc_state structure > * @reg: register address. > * @val: value. > * > @@ -265,17 +166,19 @@ void intel_dsb_indexed_reg_write(struct intel_dsb > *dsb, i915_reg_t reg, > * and rest all erroneous condition register programming is done > * through mmio write. > */ > -void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val) > +void intel_dsb_reg_write(const struct intel_crtc_state *crtc_state, > + i915_reg_t reg, u32 val) > { > - struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb); > + struct intel_dsb *dsb = crtc_state->dsb; > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > u32 *buf = dsb->cmd_buf; > > - if (!buf) { > + if (!dsb) { > intel_de_write(dev_priv, reg, val); > return; > } > - > + buf = dsb->cmd_buf; > if (drm_WARN_ON(&dev_priv->drm, dsb->free_pos >= DSB_BUF_SIZE)) { > drm_dbg_kms(&dev_priv->drm, "DSB buffer overflow\n"); > return; > @@ -290,26 +193,27 @@ void intel_dsb_reg_write(struct intel_dsb *dsb, > i915_reg_t reg, u32 val) > > /** > * intel_dsb_commit() - Trigger workload execution of DSB. > - * @dsb: intel_dsb structure. > + * @crtc_state: intel_crtc_state structure > * > * This function is used to do actual write to hardware using DSB. > * On errors, fall back to MMIO. Also this function help to reset the context. > */ > -void intel_dsb_commit(struct intel_dsb *dsb) > +void intel_dsb_commit(const struct intel_crtc_state *crtc_state) > { > - struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb); > + struct intel_dsb *dsb = crtc_state->dsb; > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > struct drm_device *dev = crtc->base.dev; > struct drm_i915_private *dev_priv = to_i915(dev); > enum pipe pipe = crtc->pipe; > u32 tail; > > - if (!dsb->free_pos) > + if (!(dsb && dsb->free_pos)) > return; > > - if (!intel_dsb_enable_engine(dsb)) > + if (!intel_dsb_enable_engine(dev_priv, pipe, dsb->id)) > goto reset; > > - if (is_dsb_busy(dsb)) { > + if (is_dsb_busy(dev_priv, pipe, dsb->id)) { > drm_err(&dev_priv->drm, > "HEAD_PTR write failed - dsb engine is busy.\n"); > goto reset; > @@ -322,7 +226,7 @@ void intel_dsb_commit(struct intel_dsb *dsb) > memset(&dsb->cmd_buf[dsb->free_pos], 0, > (tail - dsb->free_pos * 4)); > > - if (is_dsb_busy(dsb)) { > + if (is_dsb_busy(dev_priv, pipe, dsb->id)) { > drm_err(&dev_priv->drm, > "TAIL_PTR write failed - dsb engine is busy.\n"); > goto reset; > @@ -332,7 +236,7 @@ void intel_dsb_commit(struct intel_dsb *dsb) > i915_ggtt_offset(dsb->vma), tail); > intel_de_write(dev_priv, DSB_TAIL(pipe, dsb->id), > i915_ggtt_offset(dsb->vma) + tail); > - if (wait_for(!is_dsb_busy(dsb), 1)) { > + if (wait_for(!is_dsb_busy(dev_priv, pipe, dsb->id), 1)) { > drm_err(&dev_priv->drm, > "Timed out waiting for DSB workload completion.\n"); > goto reset; > @@ -341,5 +245,79 @@ void intel_dsb_commit(struct intel_dsb *dsb) > reset: > dsb->free_pos = 0; > dsb->ins_start_offset = 0; > - intel_dsb_disable_engine(dsb); > + intel_dsb_disable_engine(dev_priv, pipe, dsb->id); } > + > +/** > + * intel_dsb_prepare() - Allocate, pin and map the DSB command buffer. > + * @crtc_state: intel_crtc_state structure to prepare associated dsb instance. > + * > + * This function prepare the command buffer which is used to store dsb > + * instructions with data. > + */ > +void intel_dsb_prepare(struct intel_crtc_state *crtc_state) { > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > + struct drm_i915_private *i915 = to_i915(crtc->base.dev); > + struct intel_dsb *dsb; > + struct drm_i915_gem_object *obj; > + struct i915_vma *vma; > + u32 *buf; > + intel_wakeref_t wakeref; > + > + if (!HAS_DSB(i915)) > + return; > + > + dsb = kmalloc(sizeof(*dsb), GFP_KERNEL); > + > + wakeref = intel_runtime_pm_get(&i915->runtime_pm); > + > + obj = i915_gem_object_create_internal(i915, DSB_BUF_SIZE); > + if (IS_ERR(obj)) { > + drm_err(&i915->drm, "Gem object creation failed\n"); > + kfree(dsb); > + goto out; > + } > + > + vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0); > + if (IS_ERR(vma)) { > + drm_err(&i915->drm, "Vma creation failed\n"); > + i915_gem_object_put(obj); > + kfree(dsb); > + goto out; > + } > + > + buf = i915_gem_object_pin_map(vma->obj, I915_MAP_WC); > + if (IS_ERR(buf)) { > + drm_err(&i915->drm, "Command buffer creation failed\n"); > + i915_vma_unpin_and_release(&vma, I915_VMA_RELEASE_MAP); > + kfree(dsb); > + goto out; > + } > + > + dsb->id = DSB1; > + dsb->vma = vma; > + dsb->cmd_buf = buf; > + dsb->free_pos = 0; > + dsb->ins_start_offset = 0; > + crtc_state->dsb = dsb; > +out: > + intel_runtime_pm_put(&i915->runtime_pm, wakeref); } > + > +/** > + * intel_dsb_cleanup() - To cleanup DSB context. > + * @crtc_state: intel_crtc_state structure to cleanup associated dsb instance. > + * > + * This function cleanup the DSB context by unpinning and releasing > + * the VMA object associated with it. > + */ > +void intel_dsb_cleanup(struct intel_crtc_state *crtc_state) { > + if (!crtc_state->dsb) > + return; > + > + i915_vma_unpin_and_release(&crtc_state->dsb->vma, > I915_VMA_RELEASE_MAP); > + kfree(crtc_state->dsb); > + crtc_state->dsb = NULL; > } > diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h > b/drivers/gpu/drm/i915/display/intel_dsb.h > index 395ef9ce558e..654a11f24b80 100644 > --- a/drivers/gpu/drm/i915/display/intel_dsb.h > +++ b/drivers/gpu/drm/i915/display/intel_dsb.h > @@ -10,7 +10,7 @@ > > #include "i915_reg.h" > > -struct intel_crtc; > +struct intel_crtc_state; > struct i915_vma; > > enum dsb_id { > @@ -22,7 +22,6 @@ enum dsb_id { > }; > > struct intel_dsb { > - long refcount; > enum dsb_id id; > u32 *cmd_buf; > struct i915_vma *vma; > @@ -41,12 +40,12 @@ struct intel_dsb { > u32 ins_start_offset; > }; > > -struct intel_dsb * > -intel_dsb_get(struct intel_crtc *crtc); -void intel_dsb_put(struct intel_dsb *dsb); > -void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val); -void > intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg, > - u32 val); > -void intel_dsb_commit(struct intel_dsb *dsb); > +void intel_dsb_prepare(struct intel_crtc_state *crtc_state); void > +intel_dsb_cleanup(struct intel_crtc_state *crtc_state); void > +intel_dsb_reg_write(const struct intel_crtc_state *crtc_state, > + i915_reg_t reg, u32 val); > +void intel_dsb_indexed_reg_write(const struct intel_crtc_state *crtc_state, > + i915_reg_t reg, u32 val); > +void intel_dsb_commit(const struct intel_crtc_state *crtc_state); > > #endif > -- > 2.26.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2020-05-23 9:52 UTC | newest] Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-05-20 13:07 [Intel-gfx] [PATCH v11] drm/i915/dsb: Pre allocate and late cleanup of cmd buffer Animesh Manna 2020-05-20 14:55 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dsb: Pre allocate and late cleanup of cmd buffer (rev10) Patchwork 2020-05-21 6:09 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2020-05-23 9:52 ` [Intel-gfx] [PATCH v11] drm/i915/dsb: Pre allocate and late cleanup of cmd buffer Shankar, Uma
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