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* [Intel-gfx] [CI 1/2] drm/i915/gt: Disable preparser around xcs invalidations on tgl
@ 2020-07-28 15:21 Chris Wilson
  2020-07-28 15:21 ` [Intel-gfx] [CI 2/2] drm/i915/selftests: Add compiler paranoia for checking HWSP values Chris Wilson
                   ` (4 more replies)
  0 siblings, 5 replies; 6+ messages in thread
From: Chris Wilson @ 2020-07-28 15:21 UTC (permalink / raw)
  To: intel-gfx

Unlike rcs where we have conclusive evidence from our selftesting that
disabling the preparser before performing the TLB invalidate and
relocations does impact upon the GPU execution, the evidence for the
same requirement on xcs is much more circumstantial. Let's apply the
preparser disable between batches as we invalidate the TLB as a dose of
healthy paranoia, just in case.

References: https://gitlab.freedesktop.org/drm/intel/-/issues/2169
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 29c0fde8b4df..353b1717fe84 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -4764,14 +4764,21 @@ static int gen12_emit_flush(struct i915_request *request, u32 mode)
 	intel_engine_mask_t aux_inv = 0;
 	u32 cmd, *cs;
 
+	cmd = 4;
+	if (mode & EMIT_INVALIDATE)
+		cmd += 2;
 	if (mode & EMIT_INVALIDATE)
 		aux_inv = request->engine->mask & ~BIT(BCS0);
+	if (aux_inv)
+		cmd += 2 * hweight8(aux_inv) + 2;
 
-	cs = intel_ring_begin(request,
-			      4 + (aux_inv ? 2 * hweight8(aux_inv) + 2 : 0));
+	cs = intel_ring_begin(request, cmd);
 	if (IS_ERR(cs))
 		return PTR_ERR(cs);
 
+	if (mode & EMIT_INVALIDATE)
+		*cs++ = preparser_disable(true);
+
 	cmd = MI_FLUSH_DW + 1;
 
 	/* We always require a command barrier so that subsequent
@@ -4804,6 +4811,10 @@ static int gen12_emit_flush(struct i915_request *request, u32 mode)
 		}
 		*cs++ = MI_NOOP;
 	}
+
+	if (mode & EMIT_INVALIDATE)
+		*cs++ = preparser_disable(false);
+
 	intel_ring_advance(request, cs);
 
 	return 0;
-- 
2.20.1

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^ permalink raw reply related	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2020-07-29  0:20 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-07-28 15:21 [Intel-gfx] [CI 1/2] drm/i915/gt: Disable preparser around xcs invalidations on tgl Chris Wilson
2020-07-28 15:21 ` [Intel-gfx] [CI 2/2] drm/i915/selftests: Add compiler paranoia for checking HWSP values Chris Wilson
2020-07-28 17:14 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/2] drm/i915/gt: Disable preparser around xcs invalidations on tgl Patchwork
2020-07-28 17:15 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-07-28 17:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-07-29  0:20 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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