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From: Chris Wilson <chris@chris-wilson.co.uk>
To: Mika Kuoppala <mika.kuoppala@linux.intel.com>,
	intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 3/5] drm/i915/gt: Lift stop_ring() to reset_prepare
Date: Tue, 19 Jan 2021 10:39:45 +0000	[thread overview]
Message-ID: <161105278514.19402.10766596756611532191@build.alporthouse.com> (raw)
In-Reply-To: <87y2gpjjwy.fsf@gaia.fi.intel.com>

Quoting Mika Kuoppala (2021-01-19 10:33:17)
> Chris Wilson <chris@chris-wilson.co.uk> writes:
> 
> > Push the sleeping stop_ring() out of the reset resume function to reset
> > prepare; we are not allowed to sleep in the former.
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > ---
> >  .../gpu/drm/i915/gt/intel_ring_submission.c   | 97 +++++++------------
> >  1 file changed, 36 insertions(+), 61 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> > index 8d0964d2d597..44159595d909 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> > @@ -157,21 +157,6 @@ static void ring_setup_status_page(struct intel_engine_cs *engine)
> >       flush_cs_tlb(engine);
> >  }
> >  
> > -static bool stop_ring(struct intel_engine_cs *engine)
> > -{
> > -     intel_engine_stop_cs(engine);
> > -
> > -     ENGINE_WRITE(engine, RING_HEAD, ENGINE_READ(engine, RING_TAIL));
> > -
> > -     ENGINE_WRITE(engine, RING_HEAD, 0);
> > -     ENGINE_WRITE(engine, RING_TAIL, 0);
> > -
> > -     /* The ring must be empty before it is disabled */
> > -     ENGINE_WRITE(engine, RING_CTL, 0);
> > -
> > -     return (ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) == 0;
> > -}
> > -
> >  static struct i915_address_space *vm_alias(struct i915_address_space *vm)
> >  {
> >       if (i915_is_ggtt(vm))
> > @@ -213,31 +198,6 @@ static int xcs_resume(struct intel_engine_cs *engine)
> >  
> >       intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL);
> >  
> > -     /* WaClearRingBufHeadRegAtInit:ctg,elk */
> > -     if (!stop_ring(engine)) {
> > -             /* G45 ring initialization often fails to reset head to zero */
> > -             drm_dbg(&dev_priv->drm, "%s head not reset to zero "
> > -                     "ctl %08x head %08x tail %08x start %08x\n",
> > -                     engine->name,
> > -                     ENGINE_READ(engine, RING_CTL),
> > -                     ENGINE_READ(engine, RING_HEAD),
> > -                     ENGINE_READ(engine, RING_TAIL),
> > -                     ENGINE_READ(engine, RING_START));
> > -
> > -             if (!stop_ring(engine)) {
> > -                     drm_err(&dev_priv->drm,
> > -                             "failed to set %s head to zero "
> > -                             "ctl %08x head %08x tail %08x start %08x\n",
> > -                             engine->name,
> > -                             ENGINE_READ(engine, RING_CTL),
> > -                             ENGINE_READ(engine, RING_HEAD),
> > -                             ENGINE_READ(engine, RING_TAIL),
> > -                             ENGINE_READ(engine, RING_START));
> > -                     ret = -EIO;
> > -                     goto out;
> > -             }
> > -     }
> > -
> >       if (HWS_NEEDS_PHYSICAL(dev_priv))
> >               ring_setup_phys_status_page(engine);
> >       else
> > @@ -339,11 +299,21 @@ static void xcs_sanitize(struct intel_engine_cs *engine)
> >       clflush_cache_range(engine->status_page.addr, PAGE_SIZE);
> >  }
> >  
> > +static bool stop_ring(struct intel_engine_cs *engine)
> > +{
> > +     ENGINE_WRITE_FW(engine, RING_HEAD, ENGINE_READ_FW(engine, RING_TAIL));
> > +
> 
> Not related to this patch but this makes me wondering if the actual
> disable should be at this point before zeroing as manipulating the
> head again might kick the hardware forward.

We move HEAD to TAIL, with the intent of kicking the HW to the end and
"emptying the ring".

If we move HEAD to 0 first, it will start executing random stuff. And by
the time we set TAIL to 0, HEAD will have moved on.

So I think this is correct: set HEAD to TAIL to empty the ring.
-Chris
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  reply	other threads:[~2021-01-19 10:39 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-19  9:40 [Intel-gfx] [PATCH 1/5] drm/i915/gt: One more flush for Baytrail clear residuals Chris Wilson
2021-01-19  9:40 ` [Intel-gfx] [PATCH 2/5] drm/i915/selftests: Prepare the selftests for engine resets with ring submission Chris Wilson
2021-01-19 10:26   ` Mika Kuoppala
2021-01-19  9:40 ` [Intel-gfx] [PATCH 3/5] drm/i915/gt: Lift stop_ring() to reset_prepare Chris Wilson
2021-01-19 10:33   ` Mika Kuoppala
2021-01-19 10:39     ` Chris Wilson [this message]
2021-01-19  9:40 ` [Intel-gfx] [PATCH 4/5] drm/i915/gt: Pull ring submission resume under its caller forcewake Chris Wilson
2021-01-19 10:55   ` Mika Kuoppala
2021-01-19  9:40 ` [Intel-gfx] [PATCH 5/5] drm/i915: Mark per-engine-reset as supported on gen7 Chris Wilson
2021-01-19 11:00   ` Mika Kuoppala
2021-01-19 11:06     ` Chris Wilson
2021-01-19 10:21 ` [Intel-gfx] [PATCH 1/5] drm/i915/gt: One more flush for Baytrail clear residuals Abodunrin, Akeem G
2021-01-19 10:25 ` Mika Kuoppala
2021-01-19 10:34   ` Chris Wilson
2021-01-19 10:59     ` Mika Kuoppala
2021-01-19 13:08 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/5] " Patchwork
2021-01-19 13:41 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork

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