From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Subject: Re: [Intel-gfx] [PATCH 1/5] drm/i915/gt: One more flush for Baytrail clear residuals
Date: Tue, 19 Jan 2021 12:25:14 +0200 [thread overview]
Message-ID: <87pn21gr5h.fsf@gaia.fi.intel.com> (raw)
In-Reply-To: <20210119094053.6919-1-chris@chris-wilson.co.uk>
Chris Wilson <chris@chris-wilson.co.uk> writes:
> CI reports that Baytail requires one more invalidate after CACHE_MODE
> for it to be happy.
>
> Fixes: ace44e13e577 ("drm/i915/gt: Clear CACHE_MODE prior to clearing residuals")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
> ---
> drivers/gpu/drm/i915/gt/gen7_renderclear.c | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
> index 39478712769f..8551e6de50e8 100644
> --- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c
> +++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
> @@ -353,19 +353,21 @@ static void gen7_emit_pipeline_flush(struct batch_chunk *batch)
>
> static void gen7_emit_pipeline_invalidate(struct batch_chunk *batch)
> {
> - u32 *cs = batch_alloc_items(batch, 0, 8);
> + u32 *cs = batch_alloc_items(batch, 0, 10);
>
> /* ivb: Stall before STATE_CACHE_INVALIDATE */
> - *cs++ = GFX_OP_PIPE_CONTROL(4);
> + *cs++ = GFX_OP_PIPE_CONTROL(5);
> *cs++ = PIPE_CONTROL_STALL_AT_SCOREBOARD |
> PIPE_CONTROL_CS_STALL;
> *cs++ = 0;
> *cs++ = 0;
> + *cs++ = 0;
dw[5] seems to be only for gen8+. Does it make a difference?
-Mika
>
> - *cs++ = GFX_OP_PIPE_CONTROL(4);
> + *cs++ = GFX_OP_PIPE_CONTROL(5);
> *cs++ = PIPE_CONTROL_STATE_CACHE_INVALIDATE;
> *cs++ = 0;
> *cs++ = 0;
> + *cs++ = 0;
>
> batch_advance(batch, cs);
> }
> @@ -397,6 +399,7 @@ static void emit_batch(struct i915_vma * const vma,
> batch_add(&cmds, 0xffff0000);
> batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_1));
> batch_add(&cmds, 0xffff0000 | PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
> + gen7_emit_pipeline_invalidate(&cmds);
> gen7_emit_pipeline_flush(&cmds);
>
> /* Switch to the media pipeline and our base address */
> --
> 2.20.1
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next prev parent reply other threads:[~2021-01-19 10:28 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-19 9:40 [Intel-gfx] [PATCH 1/5] drm/i915/gt: One more flush for Baytrail clear residuals Chris Wilson
2021-01-19 9:40 ` [Intel-gfx] [PATCH 2/5] drm/i915/selftests: Prepare the selftests for engine resets with ring submission Chris Wilson
2021-01-19 10:26 ` Mika Kuoppala
2021-01-19 9:40 ` [Intel-gfx] [PATCH 3/5] drm/i915/gt: Lift stop_ring() to reset_prepare Chris Wilson
2021-01-19 10:33 ` Mika Kuoppala
2021-01-19 10:39 ` Chris Wilson
2021-01-19 9:40 ` [Intel-gfx] [PATCH 4/5] drm/i915/gt: Pull ring submission resume under its caller forcewake Chris Wilson
2021-01-19 10:55 ` Mika Kuoppala
2021-01-19 9:40 ` [Intel-gfx] [PATCH 5/5] drm/i915: Mark per-engine-reset as supported on gen7 Chris Wilson
2021-01-19 11:00 ` Mika Kuoppala
2021-01-19 11:06 ` Chris Wilson
2021-01-19 10:21 ` [Intel-gfx] [PATCH 1/5] drm/i915/gt: One more flush for Baytrail clear residuals Abodunrin, Akeem G
2021-01-19 10:25 ` Mika Kuoppala [this message]
2021-01-19 10:34 ` Chris Wilson
2021-01-19 10:59 ` Mika Kuoppala
2021-01-19 13:08 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/5] " Patchwork
2021-01-19 13:41 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
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