* [Intel-gfx] [PATCH 1/3] drm/i915/dp: pass crtc_state to intel_ddi_dp_level() @ 2021-08-13 11:51 Jani Nikula 2021-08-13 11:51 ` [Intel-gfx] [PATCH 2/3] drm/i915/dg2: use existing mechanisms for SNPS PHY translations Jani Nikula ` (6 more replies) 0 siblings, 7 replies; 13+ messages in thread From: Jani Nikula @ 2021-08-13 11:51 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula, Manasi Navare, Matt Roper Needed in the future. Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index e932fd0fe7e2..8cf5d1572ee0 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1371,7 +1371,8 @@ static int translate_signal_level(struct intel_dp *intel_dp, return 0; } -static int intel_ddi_dp_level(struct intel_dp *intel_dp) +static int intel_ddi_dp_level(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state) { u8 train_set = intel_dp->train_set[0]; u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | @@ -1385,7 +1386,7 @@ dg2_set_signal_levels(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; - int level = intel_ddi_dp_level(intel_dp); + int level = intel_ddi_dp_level(intel_dp, crtc_state); intel_snps_phy_ddi_vswing_sequence(encoder, level); } @@ -1395,7 +1396,7 @@ tgl_set_signal_levels(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; - int level = intel_ddi_dp_level(intel_dp); + int level = intel_ddi_dp_level(intel_dp, crtc_state); tgl_ddi_vswing_sequence(encoder, crtc_state, level); } @@ -1405,7 +1406,7 @@ icl_set_signal_levels(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; - int level = intel_ddi_dp_level(intel_dp); + int level = intel_ddi_dp_level(intel_dp, crtc_state); icl_ddi_vswing_sequence(encoder, crtc_state, level); } @@ -1415,7 +1416,7 @@ bxt_set_signal_levels(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; - int level = intel_ddi_dp_level(intel_dp); + int level = intel_ddi_dp_level(intel_dp, crtc_state); bxt_ddi_vswing_sequence(encoder, crtc_state, level); } @@ -1426,7 +1427,7 @@ hsw_set_signal_levels(struct intel_dp *intel_dp, { struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - int level = intel_ddi_dp_level(intel_dp); + int level = intel_ddi_dp_level(intel_dp, crtc_state); enum port port = encoder->port; u32 signal_levels; @@ -2328,7 +2329,7 @@ static void dg2_ddi_pre_enable_dp(struct intel_atomic_state *state, enum phy phy = intel_port_to_phy(dev_priv, encoder->port); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); - int level = intel_ddi_dp_level(intel_dp); + int level = intel_ddi_dp_level(intel_dp, crtc_state); intel_dp_set_link_params(intel_dp, crtc_state->port_clock, crtc_state->lane_count); @@ -2441,7 +2442,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, enum phy phy = intel_port_to_phy(dev_priv, encoder->port); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); - int level = intel_ddi_dp_level(intel_dp); + int level = intel_ddi_dp_level(intel_dp, crtc_state); intel_dp_set_link_params(intel_dp, crtc_state->port_clock, @@ -2584,7 +2585,7 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, enum phy phy = intel_port_to_phy(dev_priv, port); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); - int level = intel_ddi_dp_level(intel_dp); + int level = intel_ddi_dp_level(intel_dp, crtc_state); if (DISPLAY_VER(dev_priv) < 11) drm_WARN_ON(&dev_priv->drm, -- 2.20.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [Intel-gfx] [PATCH 2/3] drm/i915/dg2: use existing mechanisms for SNPS PHY translations 2021-08-13 11:51 [Intel-gfx] [PATCH 1/3] drm/i915/dp: pass crtc_state to intel_ddi_dp_level() Jani Nikula @ 2021-08-13 11:51 ` Jani Nikula 2021-08-13 17:59 ` Matt Roper 2021-08-13 11:51 ` [Intel-gfx] [PATCH 3/3] drm/i915/dg2: add SNPS PHY translations for UHBR link rates Jani Nikula ` (5 subsequent siblings) 6 siblings, 1 reply; 13+ messages in thread From: Jani Nikula @ 2021-08-13 11:51 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula, Manasi Navare, Matt Roper We use encoder->get_buf_trans() in many places, for example intel_ddi_dp_voltage_max(), and the hook was set to some old platform's function for DG2 SNPS PHY. Convert SNPS PHY to use the same translation mechanisms as everything else. Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 6 +- .../drm/i915/display/intel_ddi_buf_trans.c | 31 +++++++++- .../drm/i915/display/intel_ddi_buf_trans.h | 7 +++ drivers/gpu/drm/i915/display/intel_snps_phy.c | 61 ++++++------------- drivers/gpu/drm/i915/display/intel_snps_phy.h | 3 +- 5 files changed, 59 insertions(+), 49 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 8cf5d1572ee0..9e46cf5c4378 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1388,7 +1388,7 @@ dg2_set_signal_levels(struct intel_dp *intel_dp, struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; int level = intel_ddi_dp_level(intel_dp, crtc_state); - intel_snps_phy_ddi_vswing_sequence(encoder, level); + intel_snps_phy_ddi_vswing_sequence(encoder, crtc_state, level); } static void @@ -2388,7 +2388,7 @@ static void dg2_ddi_pre_enable_dp(struct intel_atomic_state *state, */ /* 5.e Configure voltage swing and related IO settings */ - intel_snps_phy_ddi_vswing_sequence(encoder, level); + intel_snps_phy_ddi_vswing_sequence(encoder, crtc_state, level); /* * 5.f Configure and enable DDI_BUF_CTL @@ -3057,7 +3057,7 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, connector->base.id, connector->name); if (IS_DG2(dev_priv)) - intel_snps_phy_ddi_vswing_sequence(encoder, U32_MAX); + intel_snps_phy_ddi_vswing_sequence(encoder, crtc_state, level); else if (DISPLAY_VER(dev_priv) >= 12) tgl_ddi_vswing_sequence(encoder, crtc_state, level); else if (DISPLAY_VER(dev_priv) == 11) diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c index ba2c08f1a797..ebb39624bfc9 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c @@ -983,6 +983,25 @@ static const struct intel_ddi_buf_trans adlp_dkl_phy_ddi_translations_dp_hbr2_hb .num_entries = ARRAY_SIZE(_adlp_dkl_phy_ddi_translations_dp_hbr2_hbr3), }; +static const union intel_ddi_buf_trans_entry _dg2_snps_translations[] = { + { .snps = { 26, 0, 0 } }, /* VS 0, pre-emph 0 */ + { .snps = { 33, 0, 6 } }, /* VS 0, pre-emph 1 */ + { .snps = { 38, 0, 12 } }, /* VS 0, pre-emph 2 */ + { .snps = { 43, 0, 19 } }, /* VS 0, pre-emph 3 */ + { .snps = { 39, 0, 0 } }, /* VS 1, pre-emph 0 */ + { .snps = { 44, 0, 8 } }, /* VS 1, pre-emph 1 */ + { .snps = { 47, 0, 15 } }, /* VS 1, pre-emph 2 */ + { .snps = { 52, 0, 0 } }, /* VS 2, pre-emph 0 */ + { .snps = { 51, 0, 10 } }, /* VS 2, pre-emph 1 */ + { .snps = { 62, 0, 0 } }, /* VS 3, pre-emph 0 */ +}; + +static const struct intel_ddi_buf_trans dg2_snps_translations = { + .entries = _dg2_snps_translations, + .num_entries = ARRAY_SIZE(_dg2_snps_translations), + .hdmi_default_entry = ARRAY_SIZE(_dg2_snps_translations) - 1, +}; + bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table) { return table == &tgl_combo_phy_ddi_translations_edp_hbr2_hobl; @@ -1563,6 +1582,14 @@ adlp_get_dkl_buf_trans(struct intel_encoder *encoder, return adlp_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries); } +static const struct intel_ddi_buf_trans * +dg2_get_snps_buf_trans(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + int *n_entries) +{ + return intel_get_buf_trans(&dg2_snps_translations, n_entries); +} + int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *default_entry) @@ -1588,7 +1615,9 @@ void intel_ddi_buf_trans_init(struct intel_encoder *encoder) struct drm_i915_private *i915 = to_i915(encoder->base.dev); enum phy phy = intel_port_to_phy(i915, encoder->port); - if (IS_ALDERLAKE_P(i915)) { + if (IS_DG2(i915)) { + encoder->get_buf_trans = dg2_get_snps_buf_trans; + } else if (IS_ALDERLAKE_P(i915)) { if (intel_phy_is_combo(i915, phy)) encoder->get_buf_trans = adlp_get_combo_buf_trans; else diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h index 2acd720f9d4f..94d338287f61 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h @@ -45,12 +45,19 @@ struct tgl_dkl_phy_ddi_buf_trans { u32 dkl_de_emphasis_control; }; +struct dg2_snps_phy_buf_trans { + u8 snps_vswing; + u8 snps_pre_cursor; + u8 snps_post_cursor; +}; + union intel_ddi_buf_trans_entry { struct hsw_ddi_buf_trans hsw; struct bxt_ddi_buf_trans bxt; struct icl_ddi_buf_trans icl; struct icl_mg_phy_ddi_buf_trans mg; struct tgl_dkl_phy_ddi_buf_trans dkl; + struct dg2_snps_phy_buf_trans snps; }; struct intel_ddi_buf_trans { diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c index 18b52b64af95..d81f71296297 100644 --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c @@ -5,6 +5,7 @@ #include <linux/util_macros.h> +#include "intel_ddi_buf_trans.h" #include "intel_de.h" #include "intel_display_types.h" #include "intel_snps_phy.h" @@ -50,58 +51,30 @@ void intel_snps_phy_update_psr_power_state(struct drm_i915_private *dev_priv, SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR, val); } -static const u32 dg2_ddi_translations[] = { - /* VS 0, pre-emph 0 */ - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 26), - - /* VS 0, pre-emph 1 */ - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 33) | - REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 6), - - /* VS 0, pre-emph 2 */ - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 38) | - REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 12), - - /* VS 0, pre-emph 3 */ - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 43) | - REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 19), - - /* VS 1, pre-emph 0 */ - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 39), - - /* VS 1, pre-emph 1 */ - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 44) | - REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 8), - - /* VS 1, pre-emph 2 */ - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 47) | - REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 15), - - /* VS 2, pre-emph 0 */ - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 52), - - /* VS 2, pre-emph 1 */ - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 51) | - REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 10), - - /* VS 3, pre-emph 0 */ - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 62), -}; - void intel_snps_phy_ddi_vswing_sequence(struct intel_encoder *encoder, - u32 level) + const struct intel_crtc_state *crtc_state, + int level) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + const struct intel_ddi_buf_trans *ddi_translations; enum phy phy = intel_port_to_phy(dev_priv, encoder->port); int n_entries, ln; - n_entries = ARRAY_SIZE(dg2_ddi_translations); - if (level >= n_entries) + ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); + if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) + return; + if (drm_WARN_ON_ONCE(&dev_priv->drm, level < 0 || level >= n_entries)) level = n_entries - 1; - for (ln = 0; ln < 4; ln++) - intel_de_write(dev_priv, SNPS_PHY_TX_EQ(ln, phy), - dg2_ddi_translations[level]); + for (ln = 0; ln < 4; ln++) { + u32 val = 0; + + val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, ddi_translations->entries[level].snps.snps_vswing); + val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_PRE, ddi_translations->entries[level].snps.snps_pre_cursor); + val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, ddi_translations->entries[level].snps.snps_post_cursor); + + intel_de_write(dev_priv, SNPS_PHY_TX_EQ(ln, phy), val); + } } /* diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.h b/drivers/gpu/drm/i915/display/intel_snps_phy.h index 6261ff88ef5c..a68547a6fee5 100644 --- a/drivers/gpu/drm/i915/display/intel_snps_phy.h +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.h @@ -30,6 +30,7 @@ int intel_mpllb_calc_port_clock(struct intel_encoder *encoder, int intel_snps_phy_check_hdmi_link_rate(int clock); void intel_snps_phy_ddi_vswing_sequence(struct intel_encoder *encoder, - u32 level); + const struct intel_crtc_state *crtc_state, + int level); #endif /* __INTEL_SNPS_PHY_H__ */ -- 2.20.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH 2/3] drm/i915/dg2: use existing mechanisms for SNPS PHY translations 2021-08-13 11:51 ` [Intel-gfx] [PATCH 2/3] drm/i915/dg2: use existing mechanisms for SNPS PHY translations Jani Nikula @ 2021-08-13 17:59 ` Matt Roper 2021-08-13 19:36 ` Jani Nikula 0 siblings, 1 reply; 13+ messages in thread From: Matt Roper @ 2021-08-13 17:59 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx, Manasi Navare On Fri, Aug 13, 2021 at 02:51:50PM +0300, Jani Nikula wrote: > We use encoder->get_buf_trans() in many places, for example > intel_ddi_dp_voltage_max(), and the hook was set to some old platform's > function for DG2 SNPS PHY. Convert SNPS PHY to use the same translation > mechanisms as everything else. > > Cc: Manasi Navare <manasi.d.navare@intel.com> > Cc: Matt Roper <matthew.d.roper@intel.com> > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 6 +- > .../drm/i915/display/intel_ddi_buf_trans.c | 31 +++++++++- > .../drm/i915/display/intel_ddi_buf_trans.h | 7 +++ > drivers/gpu/drm/i915/display/intel_snps_phy.c | 61 ++++++------------- > drivers/gpu/drm/i915/display/intel_snps_phy.h | 3 +- > 5 files changed, 59 insertions(+), 49 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index 8cf5d1572ee0..9e46cf5c4378 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -1388,7 +1388,7 @@ dg2_set_signal_levels(struct intel_dp *intel_dp, > struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; > int level = intel_ddi_dp_level(intel_dp, crtc_state); > > - intel_snps_phy_ddi_vswing_sequence(encoder, level); > + intel_snps_phy_ddi_vswing_sequence(encoder, crtc_state, level); > } > > static void > @@ -2388,7 +2388,7 @@ static void dg2_ddi_pre_enable_dp(struct intel_atomic_state *state, > */ > > /* 5.e Configure voltage swing and related IO settings */ > - intel_snps_phy_ddi_vswing_sequence(encoder, level); > + intel_snps_phy_ddi_vswing_sequence(encoder, crtc_state, level); > > /* > * 5.f Configure and enable DDI_BUF_CTL > @@ -3057,7 +3057,7 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, > connector->base.id, connector->name); > > if (IS_DG2(dev_priv)) > - intel_snps_phy_ddi_vswing_sequence(encoder, U32_MAX); > + intel_snps_phy_ddi_vswing_sequence(encoder, crtc_state, level); > else if (DISPLAY_VER(dev_priv) >= 12) > tgl_ddi_vswing_sequence(encoder, crtc_state, level); > else if (DISPLAY_VER(dev_priv) == 11) > diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > index ba2c08f1a797..ebb39624bfc9 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > @@ -983,6 +983,25 @@ static const struct intel_ddi_buf_trans adlp_dkl_phy_ddi_translations_dp_hbr2_hb > .num_entries = ARRAY_SIZE(_adlp_dkl_phy_ddi_translations_dp_hbr2_hbr3), > }; > > +static const union intel_ddi_buf_trans_entry _dg2_snps_translations[] = { > + { .snps = { 26, 0, 0 } }, /* VS 0, pre-emph 0 */ > + { .snps = { 33, 0, 6 } }, /* VS 0, pre-emph 1 */ > + { .snps = { 38, 0, 12 } }, /* VS 0, pre-emph 2 */ > + { .snps = { 43, 0, 19 } }, /* VS 0, pre-emph 3 */ > + { .snps = { 39, 0, 0 } }, /* VS 1, pre-emph 0 */ > + { .snps = { 44, 0, 8 } }, /* VS 1, pre-emph 1 */ > + { .snps = { 47, 0, 15 } }, /* VS 1, pre-emph 2 */ > + { .snps = { 52, 0, 0 } }, /* VS 2, pre-emph 0 */ > + { .snps = { 51, 0, 10 } }, /* VS 2, pre-emph 1 */ > + { .snps = { 62, 0, 0 } }, /* VS 3, pre-emph 0 */ > +}; > + > +static const struct intel_ddi_buf_trans dg2_snps_translations = { > + .entries = _dg2_snps_translations, > + .num_entries = ARRAY_SIZE(_dg2_snps_translations), > + .hdmi_default_entry = ARRAY_SIZE(_dg2_snps_translations) - 1, > +}; > + > bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table) > { > return table == &tgl_combo_phy_ddi_translations_edp_hbr2_hobl; > @@ -1563,6 +1582,14 @@ adlp_get_dkl_buf_trans(struct intel_encoder *encoder, > return adlp_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries); > } > > +static const struct intel_ddi_buf_trans * > +dg2_get_snps_buf_trans(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state, > + int *n_entries) > +{ > + return intel_get_buf_trans(&dg2_snps_translations, n_entries); > +} > + > int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state, > int *default_entry) > @@ -1588,7 +1615,9 @@ void intel_ddi_buf_trans_init(struct intel_encoder *encoder) > struct drm_i915_private *i915 = to_i915(encoder->base.dev); > enum phy phy = intel_port_to_phy(i915, encoder->port); > > - if (IS_ALDERLAKE_P(i915)) { > + if (IS_DG2(i915)) { > + encoder->get_buf_trans = dg2_get_snps_buf_trans; > + } else if (IS_ALDERLAKE_P(i915)) { > if (intel_phy_is_combo(i915, phy)) > encoder->get_buf_trans = adlp_get_combo_buf_trans; > else While we're at it, maybe change the 'else' to a IS_HASWELL check and then add a new 'else' with MISSING_CASE to make sure we don't miss this for future platforms? Up to you. Either way, Reviewed-by: Matt Roper <matthew.d.roper@intel.com> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h > index 2acd720f9d4f..94d338287f61 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h > +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h > @@ -45,12 +45,19 @@ struct tgl_dkl_phy_ddi_buf_trans { > u32 dkl_de_emphasis_control; > }; > > +struct dg2_snps_phy_buf_trans { > + u8 snps_vswing; > + u8 snps_pre_cursor; > + u8 snps_post_cursor; > +}; > + > union intel_ddi_buf_trans_entry { > struct hsw_ddi_buf_trans hsw; > struct bxt_ddi_buf_trans bxt; > struct icl_ddi_buf_trans icl; > struct icl_mg_phy_ddi_buf_trans mg; > struct tgl_dkl_phy_ddi_buf_trans dkl; > + struct dg2_snps_phy_buf_trans snps; > }; > > struct intel_ddi_buf_trans { > diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c > index 18b52b64af95..d81f71296297 100644 > --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c > @@ -5,6 +5,7 @@ > > #include <linux/util_macros.h> > > +#include "intel_ddi_buf_trans.h" > #include "intel_de.h" > #include "intel_display_types.h" > #include "intel_snps_phy.h" > @@ -50,58 +51,30 @@ void intel_snps_phy_update_psr_power_state(struct drm_i915_private *dev_priv, > SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR, val); > } > > -static const u32 dg2_ddi_translations[] = { > - /* VS 0, pre-emph 0 */ > - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 26), > - > - /* VS 0, pre-emph 1 */ > - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 33) | > - REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 6), > - > - /* VS 0, pre-emph 2 */ > - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 38) | > - REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 12), > - > - /* VS 0, pre-emph 3 */ > - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 43) | > - REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 19), > - > - /* VS 1, pre-emph 0 */ > - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 39), > - > - /* VS 1, pre-emph 1 */ > - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 44) | > - REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 8), > - > - /* VS 1, pre-emph 2 */ > - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 47) | > - REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 15), > - > - /* VS 2, pre-emph 0 */ > - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 52), > - > - /* VS 2, pre-emph 1 */ > - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 51) | > - REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 10), > - > - /* VS 3, pre-emph 0 */ > - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 62), > -}; > - > void intel_snps_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > - u32 level) > + const struct intel_crtc_state *crtc_state, > + int level) > { > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + const struct intel_ddi_buf_trans *ddi_translations; > enum phy phy = intel_port_to_phy(dev_priv, encoder->port); > int n_entries, ln; > > - n_entries = ARRAY_SIZE(dg2_ddi_translations); > - if (level >= n_entries) > + ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); > + if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) > + return; > + if (drm_WARN_ON_ONCE(&dev_priv->drm, level < 0 || level >= n_entries)) > level = n_entries - 1; > > - for (ln = 0; ln < 4; ln++) > - intel_de_write(dev_priv, SNPS_PHY_TX_EQ(ln, phy), > - dg2_ddi_translations[level]); > + for (ln = 0; ln < 4; ln++) { > + u32 val = 0; > + > + val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, ddi_translations->entries[level].snps.snps_vswing); > + val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_PRE, ddi_translations->entries[level].snps.snps_pre_cursor); > + val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, ddi_translations->entries[level].snps.snps_post_cursor); > + > + intel_de_write(dev_priv, SNPS_PHY_TX_EQ(ln, phy), val); > + } > } > > /* > diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.h b/drivers/gpu/drm/i915/display/intel_snps_phy.h > index 6261ff88ef5c..a68547a6fee5 100644 > --- a/drivers/gpu/drm/i915/display/intel_snps_phy.h > +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.h > @@ -30,6 +30,7 @@ int intel_mpllb_calc_port_clock(struct intel_encoder *encoder, > > int intel_snps_phy_check_hdmi_link_rate(int clock); > void intel_snps_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > - u32 level); > + const struct intel_crtc_state *crtc_state, > + int level); > > #endif /* __INTEL_SNPS_PHY_H__ */ > -- > 2.20.1 > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH 2/3] drm/i915/dg2: use existing mechanisms for SNPS PHY translations 2021-08-13 17:59 ` Matt Roper @ 2021-08-13 19:36 ` Jani Nikula 2021-08-13 19:54 ` Jani Nikula 0 siblings, 1 reply; 13+ messages in thread From: Jani Nikula @ 2021-08-13 19:36 UTC (permalink / raw) To: Matt Roper; +Cc: intel-gfx, Manasi Navare On Fri, 13 Aug 2021, Matt Roper <matthew.d.roper@intel.com> wrote: > On Fri, Aug 13, 2021 at 02:51:50PM +0300, Jani Nikula wrote: >> We use encoder->get_buf_trans() in many places, for example >> intel_ddi_dp_voltage_max(), and the hook was set to some old platform's >> function for DG2 SNPS PHY. Convert SNPS PHY to use the same translation >> mechanisms as everything else. >> >> Cc: Manasi Navare <manasi.d.navare@intel.com> >> Cc: Matt Roper <matthew.d.roper@intel.com> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com> >> --- >> drivers/gpu/drm/i915/display/intel_ddi.c | 6 +- >> .../drm/i915/display/intel_ddi_buf_trans.c | 31 +++++++++- >> .../drm/i915/display/intel_ddi_buf_trans.h | 7 +++ >> drivers/gpu/drm/i915/display/intel_snps_phy.c | 61 ++++++------------- >> drivers/gpu/drm/i915/display/intel_snps_phy.h | 3 +- >> 5 files changed, 59 insertions(+), 49 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c >> index 8cf5d1572ee0..9e46cf5c4378 100644 >> --- a/drivers/gpu/drm/i915/display/intel_ddi.c >> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c >> @@ -1388,7 +1388,7 @@ dg2_set_signal_levels(struct intel_dp *intel_dp, >> struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; >> int level = intel_ddi_dp_level(intel_dp, crtc_state); >> >> - intel_snps_phy_ddi_vswing_sequence(encoder, level); >> + intel_snps_phy_ddi_vswing_sequence(encoder, crtc_state, level); >> } >> >> static void >> @@ -2388,7 +2388,7 @@ static void dg2_ddi_pre_enable_dp(struct intel_atomic_state *state, >> */ >> >> /* 5.e Configure voltage swing and related IO settings */ >> - intel_snps_phy_ddi_vswing_sequence(encoder, level); >> + intel_snps_phy_ddi_vswing_sequence(encoder, crtc_state, level); >> >> /* >> * 5.f Configure and enable DDI_BUF_CTL >> @@ -3057,7 +3057,7 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, >> connector->base.id, connector->name); >> >> if (IS_DG2(dev_priv)) >> - intel_snps_phy_ddi_vswing_sequence(encoder, U32_MAX); >> + intel_snps_phy_ddi_vswing_sequence(encoder, crtc_state, level); >> else if (DISPLAY_VER(dev_priv) >= 12) >> tgl_ddi_vswing_sequence(encoder, crtc_state, level); >> else if (DISPLAY_VER(dev_priv) == 11) >> diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c >> index ba2c08f1a797..ebb39624bfc9 100644 >> --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c >> +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c >> @@ -983,6 +983,25 @@ static const struct intel_ddi_buf_trans adlp_dkl_phy_ddi_translations_dp_hbr2_hb >> .num_entries = ARRAY_SIZE(_adlp_dkl_phy_ddi_translations_dp_hbr2_hbr3), >> }; >> >> +static const union intel_ddi_buf_trans_entry _dg2_snps_translations[] = { >> + { .snps = { 26, 0, 0 } }, /* VS 0, pre-emph 0 */ >> + { .snps = { 33, 0, 6 } }, /* VS 0, pre-emph 1 */ >> + { .snps = { 38, 0, 12 } }, /* VS 0, pre-emph 2 */ >> + { .snps = { 43, 0, 19 } }, /* VS 0, pre-emph 3 */ >> + { .snps = { 39, 0, 0 } }, /* VS 1, pre-emph 0 */ >> + { .snps = { 44, 0, 8 } }, /* VS 1, pre-emph 1 */ >> + { .snps = { 47, 0, 15 } }, /* VS 1, pre-emph 2 */ >> + { .snps = { 52, 0, 0 } }, /* VS 2, pre-emph 0 */ >> + { .snps = { 51, 0, 10 } }, /* VS 2, pre-emph 1 */ >> + { .snps = { 62, 0, 0 } }, /* VS 3, pre-emph 0 */ >> +}; >> + >> +static const struct intel_ddi_buf_trans dg2_snps_translations = { >> + .entries = _dg2_snps_translations, >> + .num_entries = ARRAY_SIZE(_dg2_snps_translations), >> + .hdmi_default_entry = ARRAY_SIZE(_dg2_snps_translations) - 1, >> +}; >> + >> bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table) >> { >> return table == &tgl_combo_phy_ddi_translations_edp_hbr2_hobl; >> @@ -1563,6 +1582,14 @@ adlp_get_dkl_buf_trans(struct intel_encoder *encoder, >> return adlp_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries); >> } >> >> +static const struct intel_ddi_buf_trans * >> +dg2_get_snps_buf_trans(struct intel_encoder *encoder, >> + const struct intel_crtc_state *crtc_state, >> + int *n_entries) >> +{ >> + return intel_get_buf_trans(&dg2_snps_translations, n_entries); >> +} >> + >> int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder, >> const struct intel_crtc_state *crtc_state, >> int *default_entry) >> @@ -1588,7 +1615,9 @@ void intel_ddi_buf_trans_init(struct intel_encoder *encoder) >> struct drm_i915_private *i915 = to_i915(encoder->base.dev); >> enum phy phy = intel_port_to_phy(i915, encoder->port); >> >> - if (IS_ALDERLAKE_P(i915)) { >> + if (IS_DG2(i915)) { >> + encoder->get_buf_trans = dg2_get_snps_buf_trans; >> + } else if (IS_ALDERLAKE_P(i915)) { >> if (intel_phy_is_combo(i915, phy)) >> encoder->get_buf_trans = adlp_get_combo_buf_trans; >> else > > While we're at it, maybe change the 'else' to a IS_HASWELL check and > then add a new 'else' with MISSING_CASE to make sure we don't miss this > for future platforms? > > Up to you. Either way, > > Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Thanks! I decided to push these as-is, and will send a follow-up to add the MISSING_CASE. BR, Jani. > > >> diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h >> index 2acd720f9d4f..94d338287f61 100644 >> --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h >> +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h >> @@ -45,12 +45,19 @@ struct tgl_dkl_phy_ddi_buf_trans { >> u32 dkl_de_emphasis_control; >> }; >> >> +struct dg2_snps_phy_buf_trans { >> + u8 snps_vswing; >> + u8 snps_pre_cursor; >> + u8 snps_post_cursor; >> +}; >> + >> union intel_ddi_buf_trans_entry { >> struct hsw_ddi_buf_trans hsw; >> struct bxt_ddi_buf_trans bxt; >> struct icl_ddi_buf_trans icl; >> struct icl_mg_phy_ddi_buf_trans mg; >> struct tgl_dkl_phy_ddi_buf_trans dkl; >> + struct dg2_snps_phy_buf_trans snps; >> }; >> >> struct intel_ddi_buf_trans { >> diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c >> index 18b52b64af95..d81f71296297 100644 >> --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c >> +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c >> @@ -5,6 +5,7 @@ >> >> #include <linux/util_macros.h> >> >> +#include "intel_ddi_buf_trans.h" >> #include "intel_de.h" >> #include "intel_display_types.h" >> #include "intel_snps_phy.h" >> @@ -50,58 +51,30 @@ void intel_snps_phy_update_psr_power_state(struct drm_i915_private *dev_priv, >> SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR, val); >> } >> >> -static const u32 dg2_ddi_translations[] = { >> - /* VS 0, pre-emph 0 */ >> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 26), >> - >> - /* VS 0, pre-emph 1 */ >> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 33) | >> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 6), >> - >> - /* VS 0, pre-emph 2 */ >> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 38) | >> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 12), >> - >> - /* VS 0, pre-emph 3 */ >> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 43) | >> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 19), >> - >> - /* VS 1, pre-emph 0 */ >> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 39), >> - >> - /* VS 1, pre-emph 1 */ >> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 44) | >> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 8), >> - >> - /* VS 1, pre-emph 2 */ >> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 47) | >> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 15), >> - >> - /* VS 2, pre-emph 0 */ >> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 52), >> - >> - /* VS 2, pre-emph 1 */ >> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 51) | >> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 10), >> - >> - /* VS 3, pre-emph 0 */ >> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 62), >> -}; >> - >> void intel_snps_phy_ddi_vswing_sequence(struct intel_encoder *encoder, >> - u32 level) >> + const struct intel_crtc_state *crtc_state, >> + int level) >> { >> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); >> + const struct intel_ddi_buf_trans *ddi_translations; >> enum phy phy = intel_port_to_phy(dev_priv, encoder->port); >> int n_entries, ln; >> >> - n_entries = ARRAY_SIZE(dg2_ddi_translations); >> - if (level >= n_entries) >> + ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); >> + if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) >> + return; >> + if (drm_WARN_ON_ONCE(&dev_priv->drm, level < 0 || level >= n_entries)) >> level = n_entries - 1; >> >> - for (ln = 0; ln < 4; ln++) >> - intel_de_write(dev_priv, SNPS_PHY_TX_EQ(ln, phy), >> - dg2_ddi_translations[level]); >> + for (ln = 0; ln < 4; ln++) { >> + u32 val = 0; >> + >> + val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, ddi_translations->entries[level].snps.snps_vswing); >> + val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_PRE, ddi_translations->entries[level].snps.snps_pre_cursor); >> + val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, ddi_translations->entries[level].snps.snps_post_cursor); >> + >> + intel_de_write(dev_priv, SNPS_PHY_TX_EQ(ln, phy), val); >> + } >> } >> >> /* >> diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.h b/drivers/gpu/drm/i915/display/intel_snps_phy.h >> index 6261ff88ef5c..a68547a6fee5 100644 >> --- a/drivers/gpu/drm/i915/display/intel_snps_phy.h >> +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.h >> @@ -30,6 +30,7 @@ int intel_mpllb_calc_port_clock(struct intel_encoder *encoder, >> >> int intel_snps_phy_check_hdmi_link_rate(int clock); >> void intel_snps_phy_ddi_vswing_sequence(struct intel_encoder *encoder, >> - u32 level); >> + const struct intel_crtc_state *crtc_state, >> + int level); >> >> #endif /* __INTEL_SNPS_PHY_H__ */ >> -- >> 2.20.1 >> -- Jani Nikula, Intel Open Source Graphics Center ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH 2/3] drm/i915/dg2: use existing mechanisms for SNPS PHY translations 2021-08-13 19:36 ` Jani Nikula @ 2021-08-13 19:54 ` Jani Nikula 2021-08-13 19:59 ` Matt Roper 0 siblings, 1 reply; 13+ messages in thread From: Jani Nikula @ 2021-08-13 19:54 UTC (permalink / raw) To: Matt Roper; +Cc: intel-gfx, Manasi Navare On Fri, 13 Aug 2021, Jani Nikula <jani.nikula@intel.com> wrote: > On Fri, 13 Aug 2021, Matt Roper <matthew.d.roper@intel.com> wrote: >> On Fri, Aug 13, 2021 at 02:51:50PM +0300, Jani Nikula wrote: >>> We use encoder->get_buf_trans() in many places, for example >>> intel_ddi_dp_voltage_max(), and the hook was set to some old platform's >>> function for DG2 SNPS PHY. Convert SNPS PHY to use the same translation >>> mechanisms as everything else. >>> >>> Cc: Manasi Navare <manasi.d.navare@intel.com> >>> Cc: Matt Roper <matthew.d.roper@intel.com> >>> Signed-off-by: Jani Nikula <jani.nikula@intel.com> >>> --- >>> drivers/gpu/drm/i915/display/intel_ddi.c | 6 +- >>> .../drm/i915/display/intel_ddi_buf_trans.c | 31 +++++++++- >>> .../drm/i915/display/intel_ddi_buf_trans.h | 7 +++ >>> drivers/gpu/drm/i915/display/intel_snps_phy.c | 61 ++++++------------- >>> drivers/gpu/drm/i915/display/intel_snps_phy.h | 3 +- >>> 5 files changed, 59 insertions(+), 49 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c >>> index 8cf5d1572ee0..9e46cf5c4378 100644 >>> --- a/drivers/gpu/drm/i915/display/intel_ddi.c >>> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c >>> @@ -1388,7 +1388,7 @@ dg2_set_signal_levels(struct intel_dp *intel_dp, >>> struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; >>> int level = intel_ddi_dp_level(intel_dp, crtc_state); >>> >>> - intel_snps_phy_ddi_vswing_sequence(encoder, level); >>> + intel_snps_phy_ddi_vswing_sequence(encoder, crtc_state, level); >>> } >>> >>> static void >>> @@ -2388,7 +2388,7 @@ static void dg2_ddi_pre_enable_dp(struct intel_atomic_state *state, >>> */ >>> >>> /* 5.e Configure voltage swing and related IO settings */ >>> - intel_snps_phy_ddi_vswing_sequence(encoder, level); >>> + intel_snps_phy_ddi_vswing_sequence(encoder, crtc_state, level); >>> >>> /* >>> * 5.f Configure and enable DDI_BUF_CTL >>> @@ -3057,7 +3057,7 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, >>> connector->base.id, connector->name); >>> >>> if (IS_DG2(dev_priv)) >>> - intel_snps_phy_ddi_vswing_sequence(encoder, U32_MAX); >>> + intel_snps_phy_ddi_vswing_sequence(encoder, crtc_state, level); >>> else if (DISPLAY_VER(dev_priv) >= 12) >>> tgl_ddi_vswing_sequence(encoder, crtc_state, level); >>> else if (DISPLAY_VER(dev_priv) == 11) >>> diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c >>> index ba2c08f1a797..ebb39624bfc9 100644 >>> --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c >>> +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c >>> @@ -983,6 +983,25 @@ static const struct intel_ddi_buf_trans adlp_dkl_phy_ddi_translations_dp_hbr2_hb >>> .num_entries = ARRAY_SIZE(_adlp_dkl_phy_ddi_translations_dp_hbr2_hbr3), >>> }; >>> >>> +static const union intel_ddi_buf_trans_entry _dg2_snps_translations[] = { >>> + { .snps = { 26, 0, 0 } }, /* VS 0, pre-emph 0 */ >>> + { .snps = { 33, 0, 6 } }, /* VS 0, pre-emph 1 */ >>> + { .snps = { 38, 0, 12 } }, /* VS 0, pre-emph 2 */ >>> + { .snps = { 43, 0, 19 } }, /* VS 0, pre-emph 3 */ >>> + { .snps = { 39, 0, 0 } }, /* VS 1, pre-emph 0 */ >>> + { .snps = { 44, 0, 8 } }, /* VS 1, pre-emph 1 */ >>> + { .snps = { 47, 0, 15 } }, /* VS 1, pre-emph 2 */ >>> + { .snps = { 52, 0, 0 } }, /* VS 2, pre-emph 0 */ >>> + { .snps = { 51, 0, 10 } }, /* VS 2, pre-emph 1 */ >>> + { .snps = { 62, 0, 0 } }, /* VS 3, pre-emph 0 */ >>> +}; >>> + >>> +static const struct intel_ddi_buf_trans dg2_snps_translations = { >>> + .entries = _dg2_snps_translations, >>> + .num_entries = ARRAY_SIZE(_dg2_snps_translations), >>> + .hdmi_default_entry = ARRAY_SIZE(_dg2_snps_translations) - 1, >>> +}; >>> + >>> bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table) >>> { >>> return table == &tgl_combo_phy_ddi_translations_edp_hbr2_hobl; >>> @@ -1563,6 +1582,14 @@ adlp_get_dkl_buf_trans(struct intel_encoder *encoder, >>> return adlp_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries); >>> } >>> >>> +static const struct intel_ddi_buf_trans * >>> +dg2_get_snps_buf_trans(struct intel_encoder *encoder, >>> + const struct intel_crtc_state *crtc_state, >>> + int *n_entries) >>> +{ >>> + return intel_get_buf_trans(&dg2_snps_translations, n_entries); >>> +} >>> + >>> int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder, >>> const struct intel_crtc_state *crtc_state, >>> int *default_entry) >>> @@ -1588,7 +1615,9 @@ void intel_ddi_buf_trans_init(struct intel_encoder *encoder) >>> struct drm_i915_private *i915 = to_i915(encoder->base.dev); >>> enum phy phy = intel_port_to_phy(i915, encoder->port); >>> >>> - if (IS_ALDERLAKE_P(i915)) { >>> + if (IS_DG2(i915)) { >>> + encoder->get_buf_trans = dg2_get_snps_buf_trans; >>> + } else if (IS_ALDERLAKE_P(i915)) { >>> if (intel_phy_is_combo(i915, phy)) >>> encoder->get_buf_trans = adlp_get_combo_buf_trans; >>> else >> >> While we're at it, maybe change the 'else' to a IS_HASWELL check and >> then add a new 'else' with MISSING_CASE to make sure we don't miss this >> for future platforms? >> >> Up to you. Either way, >> >> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> > > Thanks! I decided to push these as-is, and will send a follow-up to add > the MISSING_CASE. I wrote the patch, but realized the DISPLAY_VER(i915) >= 12 case will catch most new platforms anyway. Do you still think it's worth it? BR, Jani. > > BR, > Jani. > > >> >> >>> diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h >>> index 2acd720f9d4f..94d338287f61 100644 >>> --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h >>> +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h >>> @@ -45,12 +45,19 @@ struct tgl_dkl_phy_ddi_buf_trans { >>> u32 dkl_de_emphasis_control; >>> }; >>> >>> +struct dg2_snps_phy_buf_trans { >>> + u8 snps_vswing; >>> + u8 snps_pre_cursor; >>> + u8 snps_post_cursor; >>> +}; >>> + >>> union intel_ddi_buf_trans_entry { >>> struct hsw_ddi_buf_trans hsw; >>> struct bxt_ddi_buf_trans bxt; >>> struct icl_ddi_buf_trans icl; >>> struct icl_mg_phy_ddi_buf_trans mg; >>> struct tgl_dkl_phy_ddi_buf_trans dkl; >>> + struct dg2_snps_phy_buf_trans snps; >>> }; >>> >>> struct intel_ddi_buf_trans { >>> diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c >>> index 18b52b64af95..d81f71296297 100644 >>> --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c >>> +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c >>> @@ -5,6 +5,7 @@ >>> >>> #include <linux/util_macros.h> >>> >>> +#include "intel_ddi_buf_trans.h" >>> #include "intel_de.h" >>> #include "intel_display_types.h" >>> #include "intel_snps_phy.h" >>> @@ -50,58 +51,30 @@ void intel_snps_phy_update_psr_power_state(struct drm_i915_private *dev_priv, >>> SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR, val); >>> } >>> >>> -static const u32 dg2_ddi_translations[] = { >>> - /* VS 0, pre-emph 0 */ >>> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 26), >>> - >>> - /* VS 0, pre-emph 1 */ >>> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 33) | >>> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 6), >>> - >>> - /* VS 0, pre-emph 2 */ >>> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 38) | >>> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 12), >>> - >>> - /* VS 0, pre-emph 3 */ >>> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 43) | >>> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 19), >>> - >>> - /* VS 1, pre-emph 0 */ >>> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 39), >>> - >>> - /* VS 1, pre-emph 1 */ >>> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 44) | >>> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 8), >>> - >>> - /* VS 1, pre-emph 2 */ >>> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 47) | >>> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 15), >>> - >>> - /* VS 2, pre-emph 0 */ >>> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 52), >>> - >>> - /* VS 2, pre-emph 1 */ >>> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 51) | >>> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 10), >>> - >>> - /* VS 3, pre-emph 0 */ >>> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 62), >>> -}; >>> - >>> void intel_snps_phy_ddi_vswing_sequence(struct intel_encoder *encoder, >>> - u32 level) >>> + const struct intel_crtc_state *crtc_state, >>> + int level) >>> { >>> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); >>> + const struct intel_ddi_buf_trans *ddi_translations; >>> enum phy phy = intel_port_to_phy(dev_priv, encoder->port); >>> int n_entries, ln; >>> >>> - n_entries = ARRAY_SIZE(dg2_ddi_translations); >>> - if (level >= n_entries) >>> + ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); >>> + if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) >>> + return; >>> + if (drm_WARN_ON_ONCE(&dev_priv->drm, level < 0 || level >= n_entries)) >>> level = n_entries - 1; >>> >>> - for (ln = 0; ln < 4; ln++) >>> - intel_de_write(dev_priv, SNPS_PHY_TX_EQ(ln, phy), >>> - dg2_ddi_translations[level]); >>> + for (ln = 0; ln < 4; ln++) { >>> + u32 val = 0; >>> + >>> + val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, ddi_translations->entries[level].snps.snps_vswing); >>> + val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_PRE, ddi_translations->entries[level].snps.snps_pre_cursor); >>> + val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, ddi_translations->entries[level].snps.snps_post_cursor); >>> + >>> + intel_de_write(dev_priv, SNPS_PHY_TX_EQ(ln, phy), val); >>> + } >>> } >>> >>> /* >>> diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.h b/drivers/gpu/drm/i915/display/intel_snps_phy.h >>> index 6261ff88ef5c..a68547a6fee5 100644 >>> --- a/drivers/gpu/drm/i915/display/intel_snps_phy.h >>> +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.h >>> @@ -30,6 +30,7 @@ int intel_mpllb_calc_port_clock(struct intel_encoder *encoder, >>> >>> int intel_snps_phy_check_hdmi_link_rate(int clock); >>> void intel_snps_phy_ddi_vswing_sequence(struct intel_encoder *encoder, >>> - u32 level); >>> + const struct intel_crtc_state *crtc_state, >>> + int level); >>> >>> #endif /* __INTEL_SNPS_PHY_H__ */ >>> -- >>> 2.20.1 >>> -- Jani Nikula, Intel Open Source Graphics Center ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH 2/3] drm/i915/dg2: use existing mechanisms for SNPS PHY translations 2021-08-13 19:54 ` Jani Nikula @ 2021-08-13 19:59 ` Matt Roper 0 siblings, 0 replies; 13+ messages in thread From: Matt Roper @ 2021-08-13 19:59 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx, Manasi Navare On Fri, Aug 13, 2021 at 10:54:25PM +0300, Jani Nikula wrote: > On Fri, 13 Aug 2021, Jani Nikula <jani.nikula@intel.com> wrote: > > On Fri, 13 Aug 2021, Matt Roper <matthew.d.roper@intel.com> wrote: > >> On Fri, Aug 13, 2021 at 02:51:50PM +0300, Jani Nikula wrote: > >>> We use encoder->get_buf_trans() in many places, for example > >>> intel_ddi_dp_voltage_max(), and the hook was set to some old platform's > >>> function for DG2 SNPS PHY. Convert SNPS PHY to use the same translation > >>> mechanisms as everything else. > >>> > >>> Cc: Manasi Navare <manasi.d.navare@intel.com> > >>> Cc: Matt Roper <matthew.d.roper@intel.com> > >>> Signed-off-by: Jani Nikula <jani.nikula@intel.com> > >>> --- > >>> drivers/gpu/drm/i915/display/intel_ddi.c | 6 +- > >>> .../drm/i915/display/intel_ddi_buf_trans.c | 31 +++++++++- > >>> .../drm/i915/display/intel_ddi_buf_trans.h | 7 +++ > >>> drivers/gpu/drm/i915/display/intel_snps_phy.c | 61 ++++++------------- > >>> drivers/gpu/drm/i915/display/intel_snps_phy.h | 3 +- > >>> 5 files changed, 59 insertions(+), 49 deletions(-) > >>> > >>> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > >>> index 8cf5d1572ee0..9e46cf5c4378 100644 > >>> --- a/drivers/gpu/drm/i915/display/intel_ddi.c > >>> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > >>> @@ -1388,7 +1388,7 @@ dg2_set_signal_levels(struct intel_dp *intel_dp, > >>> struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; > >>> int level = intel_ddi_dp_level(intel_dp, crtc_state); > >>> > >>> - intel_snps_phy_ddi_vswing_sequence(encoder, level); > >>> + intel_snps_phy_ddi_vswing_sequence(encoder, crtc_state, level); > >>> } > >>> > >>> static void > >>> @@ -2388,7 +2388,7 @@ static void dg2_ddi_pre_enable_dp(struct intel_atomic_state *state, > >>> */ > >>> > >>> /* 5.e Configure voltage swing and related IO settings */ > >>> - intel_snps_phy_ddi_vswing_sequence(encoder, level); > >>> + intel_snps_phy_ddi_vswing_sequence(encoder, crtc_state, level); > >>> > >>> /* > >>> * 5.f Configure and enable DDI_BUF_CTL > >>> @@ -3057,7 +3057,7 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, > >>> connector->base.id, connector->name); > >>> > >>> if (IS_DG2(dev_priv)) > >>> - intel_snps_phy_ddi_vswing_sequence(encoder, U32_MAX); > >>> + intel_snps_phy_ddi_vswing_sequence(encoder, crtc_state, level); > >>> else if (DISPLAY_VER(dev_priv) >= 12) > >>> tgl_ddi_vswing_sequence(encoder, crtc_state, level); > >>> else if (DISPLAY_VER(dev_priv) == 11) > >>> diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > >>> index ba2c08f1a797..ebb39624bfc9 100644 > >>> --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > >>> +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > >>> @@ -983,6 +983,25 @@ static const struct intel_ddi_buf_trans adlp_dkl_phy_ddi_translations_dp_hbr2_hb > >>> .num_entries = ARRAY_SIZE(_adlp_dkl_phy_ddi_translations_dp_hbr2_hbr3), > >>> }; > >>> > >>> +static const union intel_ddi_buf_trans_entry _dg2_snps_translations[] = { > >>> + { .snps = { 26, 0, 0 } }, /* VS 0, pre-emph 0 */ > >>> + { .snps = { 33, 0, 6 } }, /* VS 0, pre-emph 1 */ > >>> + { .snps = { 38, 0, 12 } }, /* VS 0, pre-emph 2 */ > >>> + { .snps = { 43, 0, 19 } }, /* VS 0, pre-emph 3 */ > >>> + { .snps = { 39, 0, 0 } }, /* VS 1, pre-emph 0 */ > >>> + { .snps = { 44, 0, 8 } }, /* VS 1, pre-emph 1 */ > >>> + { .snps = { 47, 0, 15 } }, /* VS 1, pre-emph 2 */ > >>> + { .snps = { 52, 0, 0 } }, /* VS 2, pre-emph 0 */ > >>> + { .snps = { 51, 0, 10 } }, /* VS 2, pre-emph 1 */ > >>> + { .snps = { 62, 0, 0 } }, /* VS 3, pre-emph 0 */ > >>> +}; > >>> + > >>> +static const struct intel_ddi_buf_trans dg2_snps_translations = { > >>> + .entries = _dg2_snps_translations, > >>> + .num_entries = ARRAY_SIZE(_dg2_snps_translations), > >>> + .hdmi_default_entry = ARRAY_SIZE(_dg2_snps_translations) - 1, > >>> +}; > >>> + > >>> bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table) > >>> { > >>> return table == &tgl_combo_phy_ddi_translations_edp_hbr2_hobl; > >>> @@ -1563,6 +1582,14 @@ adlp_get_dkl_buf_trans(struct intel_encoder *encoder, > >>> return adlp_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries); > >>> } > >>> > >>> +static const struct intel_ddi_buf_trans * > >>> +dg2_get_snps_buf_trans(struct intel_encoder *encoder, > >>> + const struct intel_crtc_state *crtc_state, > >>> + int *n_entries) > >>> +{ > >>> + return intel_get_buf_trans(&dg2_snps_translations, n_entries); > >>> +} > >>> + > >>> int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder, > >>> const struct intel_crtc_state *crtc_state, > >>> int *default_entry) > >>> @@ -1588,7 +1615,9 @@ void intel_ddi_buf_trans_init(struct intel_encoder *encoder) > >>> struct drm_i915_private *i915 = to_i915(encoder->base.dev); > >>> enum phy phy = intel_port_to_phy(i915, encoder->port); > >>> > >>> - if (IS_ALDERLAKE_P(i915)) { > >>> + if (IS_DG2(i915)) { > >>> + encoder->get_buf_trans = dg2_get_snps_buf_trans; > >>> + } else if (IS_ALDERLAKE_P(i915)) { > >>> if (intel_phy_is_combo(i915, phy)) > >>> encoder->get_buf_trans = adlp_get_combo_buf_trans; > >>> else > >> > >> While we're at it, maybe change the 'else' to a IS_HASWELL check and > >> then add a new 'else' with MISSING_CASE to make sure we don't miss this > >> for future platforms? > >> > >> Up to you. Either way, > >> > >> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> > > > > Thanks! I decided to push these as-is, and will send a follow-up to add > > the MISSING_CASE. > > I wrote the patch, but realized the DISPLAY_VER(i915) >= 12 case will > catch most new platforms anyway. Do you still think it's worth it? Doesn't matter too much to me either way. We could change that ">=" to "==" so that that case stops catching anything that should be version 13 or beyond. Up to you though. Matt > > BR, > Jani. > > > > > > BR, > > Jani. > > > > > >> > >> > >>> diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h > >>> index 2acd720f9d4f..94d338287f61 100644 > >>> --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h > >>> +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h > >>> @@ -45,12 +45,19 @@ struct tgl_dkl_phy_ddi_buf_trans { > >>> u32 dkl_de_emphasis_control; > >>> }; > >>> > >>> +struct dg2_snps_phy_buf_trans { > >>> + u8 snps_vswing; > >>> + u8 snps_pre_cursor; > >>> + u8 snps_post_cursor; > >>> +}; > >>> + > >>> union intel_ddi_buf_trans_entry { > >>> struct hsw_ddi_buf_trans hsw; > >>> struct bxt_ddi_buf_trans bxt; > >>> struct icl_ddi_buf_trans icl; > >>> struct icl_mg_phy_ddi_buf_trans mg; > >>> struct tgl_dkl_phy_ddi_buf_trans dkl; > >>> + struct dg2_snps_phy_buf_trans snps; > >>> }; > >>> > >>> struct intel_ddi_buf_trans { > >>> diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c > >>> index 18b52b64af95..d81f71296297 100644 > >>> --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c > >>> +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c > >>> @@ -5,6 +5,7 @@ > >>> > >>> #include <linux/util_macros.h> > >>> > >>> +#include "intel_ddi_buf_trans.h" > >>> #include "intel_de.h" > >>> #include "intel_display_types.h" > >>> #include "intel_snps_phy.h" > >>> @@ -50,58 +51,30 @@ void intel_snps_phy_update_psr_power_state(struct drm_i915_private *dev_priv, > >>> SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR, val); > >>> } > >>> > >>> -static const u32 dg2_ddi_translations[] = { > >>> - /* VS 0, pre-emph 0 */ > >>> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 26), > >>> - > >>> - /* VS 0, pre-emph 1 */ > >>> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 33) | > >>> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 6), > >>> - > >>> - /* VS 0, pre-emph 2 */ > >>> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 38) | > >>> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 12), > >>> - > >>> - /* VS 0, pre-emph 3 */ > >>> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 43) | > >>> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 19), > >>> - > >>> - /* VS 1, pre-emph 0 */ > >>> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 39), > >>> - > >>> - /* VS 1, pre-emph 1 */ > >>> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 44) | > >>> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 8), > >>> - > >>> - /* VS 1, pre-emph 2 */ > >>> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 47) | > >>> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 15), > >>> - > >>> - /* VS 2, pre-emph 0 */ > >>> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 52), > >>> - > >>> - /* VS 2, pre-emph 1 */ > >>> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 51) | > >>> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 10), > >>> - > >>> - /* VS 3, pre-emph 0 */ > >>> - REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 62), > >>> -}; > >>> - > >>> void intel_snps_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > >>> - u32 level) > >>> + const struct intel_crtc_state *crtc_state, > >>> + int level) > >>> { > >>> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > >>> + const struct intel_ddi_buf_trans *ddi_translations; > >>> enum phy phy = intel_port_to_phy(dev_priv, encoder->port); > >>> int n_entries, ln; > >>> > >>> - n_entries = ARRAY_SIZE(dg2_ddi_translations); > >>> - if (level >= n_entries) > >>> + ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); > >>> + if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) > >>> + return; > >>> + if (drm_WARN_ON_ONCE(&dev_priv->drm, level < 0 || level >= n_entries)) > >>> level = n_entries - 1; > >>> > >>> - for (ln = 0; ln < 4; ln++) > >>> - intel_de_write(dev_priv, SNPS_PHY_TX_EQ(ln, phy), > >>> - dg2_ddi_translations[level]); > >>> + for (ln = 0; ln < 4; ln++) { > >>> + u32 val = 0; > >>> + > >>> + val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, ddi_translations->entries[level].snps.snps_vswing); > >>> + val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_PRE, ddi_translations->entries[level].snps.snps_pre_cursor); > >>> + val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, ddi_translations->entries[level].snps.snps_post_cursor); > >>> + > >>> + intel_de_write(dev_priv, SNPS_PHY_TX_EQ(ln, phy), val); > >>> + } > >>> } > >>> > >>> /* > >>> diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.h b/drivers/gpu/drm/i915/display/intel_snps_phy.h > >>> index 6261ff88ef5c..a68547a6fee5 100644 > >>> --- a/drivers/gpu/drm/i915/display/intel_snps_phy.h > >>> +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.h > >>> @@ -30,6 +30,7 @@ int intel_mpllb_calc_port_clock(struct intel_encoder *encoder, > >>> > >>> int intel_snps_phy_check_hdmi_link_rate(int clock); > >>> void intel_snps_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > >>> - u32 level); > >>> + const struct intel_crtc_state *crtc_state, > >>> + int level); > >>> > >>> #endif /* __INTEL_SNPS_PHY_H__ */ > >>> -- > >>> 2.20.1 > >>> > > -- > Jani Nikula, Intel Open Source Graphics Center -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 ^ permalink raw reply [flat|nested] 13+ messages in thread
* [Intel-gfx] [PATCH 3/3] drm/i915/dg2: add SNPS PHY translations for UHBR link rates 2021-08-13 11:51 [Intel-gfx] [PATCH 1/3] drm/i915/dp: pass crtc_state to intel_ddi_dp_level() Jani Nikula 2021-08-13 11:51 ` [Intel-gfx] [PATCH 2/3] drm/i915/dg2: use existing mechanisms for SNPS PHY translations Jani Nikula @ 2021-08-13 11:51 ` Jani Nikula 2021-08-13 18:01 ` Matt Roper 2021-08-13 12:57 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/dp: pass crtc_state to intel_ddi_dp_level() Patchwork ` (4 subsequent siblings) 6 siblings, 1 reply; 13+ messages in thread From: Jani Nikula @ 2021-08-13 11:51 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula, Manasi Navare, Matt Roper UHBR link rates use different tx equalization settings. Using this will require changes in the link training code too. Bspec: 53920 Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- .../drm/i915/display/intel_ddi_buf_trans.c | 29 ++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c index ebb39624bfc9..796dd04eae01 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c @@ -1002,6 +1002,30 @@ static const struct intel_ddi_buf_trans dg2_snps_translations = { .hdmi_default_entry = ARRAY_SIZE(_dg2_snps_translations) - 1, }; +static const union intel_ddi_buf_trans_entry _dg2_snps_translations_uhbr[] = { + { .snps = { 62, 0, 0 } }, /* preset 0 */ + { .snps = { 56, 0, 6 } }, /* preset 1 */ + { .snps = { 51, 0, 11 } }, /* preset 2 */ + { .snps = { 48, 0, 14 } }, /* preset 3 */ + { .snps = { 43, 0, 19 } }, /* preset 4 */ + { .snps = { 59, 3, 0 } }, /* preset 5 */ + { .snps = { 53, 3, 6 } }, /* preset 6 */ + { .snps = { 49, 3, 10 } }, /* preset 7 */ + { .snps = { 45, 3, 14 } }, /* preset 8 */ + { .snps = { 42, 3, 17 } }, /* preset 9 */ + { .snps = { 56, 6, 0 } }, /* preset 10 */ + { .snps = { 50, 6, 6 } }, /* preset 11 */ + { .snps = { 47, 6, 9 } }, /* preset 12 */ + { .snps = { 42, 6, 14 } }, /* preset 13 */ + { .snps = { 46, 8, 8 } }, /* preset 14 */ + { .snps = { 56, 3, 3 } }, /* preset 15 */ +}; + +static const struct intel_ddi_buf_trans dg2_snps_translations_uhbr = { + .entries = _dg2_snps_translations_uhbr, + .num_entries = ARRAY_SIZE(_dg2_snps_translations_uhbr), +}; + bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table) { return table == &tgl_combo_phy_ddi_translations_edp_hbr2_hobl; @@ -1587,7 +1611,10 @@ dg2_get_snps_buf_trans(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) { - return intel_get_buf_trans(&dg2_snps_translations, n_entries); + if (crtc_state->port_clock > 1000000) + return intel_get_buf_trans(&dg2_snps_translations_uhbr, n_entries); + else + return intel_get_buf_trans(&dg2_snps_translations, n_entries); } int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder, -- 2.20.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH 3/3] drm/i915/dg2: add SNPS PHY translations for UHBR link rates 2021-08-13 11:51 ` [Intel-gfx] [PATCH 3/3] drm/i915/dg2: add SNPS PHY translations for UHBR link rates Jani Nikula @ 2021-08-13 18:01 ` Matt Roper 0 siblings, 0 replies; 13+ messages in thread From: Matt Roper @ 2021-08-13 18:01 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx, Manasi Navare On Fri, Aug 13, 2021 at 02:51:51PM +0300, Jani Nikula wrote: > UHBR link rates use different tx equalization settings. Using this will > require changes in the link training code too. > > Bspec: 53920 > Cc: Manasi Navare <manasi.d.navare@intel.com> > Cc: Matt Roper <matthew.d.roper@intel.com> > Signed-off-by: Jani Nikula <jani.nikula@intel.com> Matches the bspec values. Reviewed-by: Matt Roper <matthew.d.roper@intel.com> > --- > .../drm/i915/display/intel_ddi_buf_trans.c | 29 ++++++++++++++++++- > 1 file changed, 28 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > index ebb39624bfc9..796dd04eae01 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > @@ -1002,6 +1002,30 @@ static const struct intel_ddi_buf_trans dg2_snps_translations = { > .hdmi_default_entry = ARRAY_SIZE(_dg2_snps_translations) - 1, > }; > > +static const union intel_ddi_buf_trans_entry _dg2_snps_translations_uhbr[] = { > + { .snps = { 62, 0, 0 } }, /* preset 0 */ > + { .snps = { 56, 0, 6 } }, /* preset 1 */ > + { .snps = { 51, 0, 11 } }, /* preset 2 */ > + { .snps = { 48, 0, 14 } }, /* preset 3 */ > + { .snps = { 43, 0, 19 } }, /* preset 4 */ > + { .snps = { 59, 3, 0 } }, /* preset 5 */ > + { .snps = { 53, 3, 6 } }, /* preset 6 */ > + { .snps = { 49, 3, 10 } }, /* preset 7 */ > + { .snps = { 45, 3, 14 } }, /* preset 8 */ > + { .snps = { 42, 3, 17 } }, /* preset 9 */ > + { .snps = { 56, 6, 0 } }, /* preset 10 */ > + { .snps = { 50, 6, 6 } }, /* preset 11 */ > + { .snps = { 47, 6, 9 } }, /* preset 12 */ > + { .snps = { 42, 6, 14 } }, /* preset 13 */ > + { .snps = { 46, 8, 8 } }, /* preset 14 */ > + { .snps = { 56, 3, 3 } }, /* preset 15 */ > +}; > + > +static const struct intel_ddi_buf_trans dg2_snps_translations_uhbr = { > + .entries = _dg2_snps_translations_uhbr, > + .num_entries = ARRAY_SIZE(_dg2_snps_translations_uhbr), > +}; > + > bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table) > { > return table == &tgl_combo_phy_ddi_translations_edp_hbr2_hobl; > @@ -1587,7 +1611,10 @@ dg2_get_snps_buf_trans(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state, > int *n_entries) > { > - return intel_get_buf_trans(&dg2_snps_translations, n_entries); > + if (crtc_state->port_clock > 1000000) > + return intel_get_buf_trans(&dg2_snps_translations_uhbr, n_entries); > + else > + return intel_get_buf_trans(&dg2_snps_translations, n_entries); > } > > int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder, > -- > 2.20.1 > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 ^ permalink raw reply [flat|nested] 13+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/dp: pass crtc_state to intel_ddi_dp_level() 2021-08-13 11:51 [Intel-gfx] [PATCH 1/3] drm/i915/dp: pass crtc_state to intel_ddi_dp_level() Jani Nikula 2021-08-13 11:51 ` [Intel-gfx] [PATCH 2/3] drm/i915/dg2: use existing mechanisms for SNPS PHY translations Jani Nikula 2021-08-13 11:51 ` [Intel-gfx] [PATCH 3/3] drm/i915/dg2: add SNPS PHY translations for UHBR link rates Jani Nikula @ 2021-08-13 12:57 ` Patchwork 2021-08-13 12:57 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork ` (3 subsequent siblings) 6 siblings, 0 replies; 13+ messages in thread From: Patchwork @ 2021-08-13 12:57 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx == Series Details == Series: series starting with [1/3] drm/i915/dp: pass crtc_state to intel_ddi_dp_level() URL : https://patchwork.freedesktop.org/series/93673/ State : warning == Summary == $ dim checkpatch origin/drm-tip 5fc36b81b2d1 drm/i915/dp: pass crtc_state to intel_ddi_dp_level() e6f596ec68d1 drm/i915/dg2: use existing mechanisms for SNPS PHY translations -:205: WARNING:LONG_LINE: line length of 110 exceeds 100 columns #205: FILE: drivers/gpu/drm/i915/display/intel_snps_phy.c:72: + val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, ddi_translations->entries[level].snps.snps_vswing); -:206: WARNING:LONG_LINE: line length of 113 exceeds 100 columns #206: FILE: drivers/gpu/drm/i915/display/intel_snps_phy.c:73: + val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_PRE, ddi_translations->entries[level].snps.snps_pre_cursor); -:207: WARNING:LONG_LINE: line length of 115 exceeds 100 columns #207: FILE: drivers/gpu/drm/i915/display/intel_snps_phy.c:74: + val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, ddi_translations->entries[level].snps.snps_post_cursor); total: 0 errors, 3 warnings, 0 checks, 181 lines checked 543840eff86e drm/i915/dg2: add SNPS PHY translations for UHBR link rates ^ permalink raw reply [flat|nested] 13+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/3] drm/i915/dp: pass crtc_state to intel_ddi_dp_level() 2021-08-13 11:51 [Intel-gfx] [PATCH 1/3] drm/i915/dp: pass crtc_state to intel_ddi_dp_level() Jani Nikula ` (2 preceding siblings ...) 2021-08-13 12:57 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/dp: pass crtc_state to intel_ddi_dp_level() Patchwork @ 2021-08-13 12:57 ` Patchwork 2021-08-13 13:27 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork ` (2 subsequent siblings) 6 siblings, 0 replies; 13+ messages in thread From: Patchwork @ 2021-08-13 12:57 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx == Series Details == Series: series starting with [1/3] drm/i915/dp: pass crtc_state to intel_ddi_dp_level() URL : https://patchwork.freedesktop.org/series/93673/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_display.c:1901:21: expected struct i915_vma *[assigned] vma +drivers/gpu/drm/i915/display/intel_display.c:1901:21: got void [noderef] __iomem *[assigned] iomem +drivers/gpu/drm/i915/display/intel_display.c:1901:21: warning: incorrect type in assignment (different address spaces) ^ permalink raw reply [flat|nested] 13+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/dp: pass crtc_state to intel_ddi_dp_level() 2021-08-13 11:51 [Intel-gfx] [PATCH 1/3] drm/i915/dp: pass crtc_state to intel_ddi_dp_level() Jani Nikula ` (3 preceding siblings ...) 2021-08-13 12:57 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork @ 2021-08-13 13:27 ` Patchwork 2021-08-13 16:44 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2021-08-13 17:48 ` [Intel-gfx] [PATCH 1/3] " Matt Roper 6 siblings, 0 replies; 13+ messages in thread From: Patchwork @ 2021-08-13 13:27 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 5989 bytes --] == Series Details == Series: series starting with [1/3] drm/i915/dp: pass crtc_state to intel_ddi_dp_level() URL : https://patchwork.freedesktop.org/series/93673/ State : success == Summary == CI Bug Log - changes from CI_DRM_10482 -> Patchwork_20815 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/index.html Known issues ------------ Here are the changes found in Patchwork_20815 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@amdgpu/amd_basic@query-info: - fi-tgl-1115g4: NOTRUN -> [SKIP][1] ([fdo#109315]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/fi-tgl-1115g4/igt@amdgpu/amd_basic@query-info.html * igt@amdgpu/amd_basic@semaphore: - fi-bdw-5557u: NOTRUN -> [SKIP][2] ([fdo#109271]) +29 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/fi-bdw-5557u/igt@amdgpu/amd_basic@semaphore.html * igt@amdgpu/amd_cs_nop@nop-gfx0: - fi-tgl-1115g4: NOTRUN -> [SKIP][3] ([fdo#109315] / [i915#2575]) +16 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/fi-tgl-1115g4/igt@amdgpu/amd_cs_nop@nop-gfx0.html * igt@core_hotunplug@unbind-rebind: - fi-bdw-5557u: NOTRUN -> [WARN][4] ([i915#3718]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/fi-bdw-5557u/igt@core_hotunplug@unbind-rebind.html * igt@gem_huc_copy@huc-copy: - fi-tgl-1115g4: NOTRUN -> [SKIP][5] ([i915#2190]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/fi-tgl-1115g4/igt@gem_huc_copy@huc-copy.html * igt@i915_pm_backlight@basic-brightness: - fi-tgl-1115g4: NOTRUN -> [SKIP][6] ([i915#1155]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/fi-tgl-1115g4/igt@i915_pm_backlight@basic-brightness.html * igt@i915_pm_rpm@basic-rte: - fi-tgl-1115g4: NOTRUN -> [FAIL][7] ([i915#579]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/fi-tgl-1115g4/igt@i915_pm_rpm@basic-rte.html - fi-bdw-5557u: NOTRUN -> [FAIL][8] ([i915#579]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/fi-bdw-5557u/igt@i915_pm_rpm@basic-rte.html * igt@i915_pm_rpm@module-reload: - fi-tgl-1115g4: NOTRUN -> [SKIP][9] ([i915#579]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/fi-tgl-1115g4/igt@i915_pm_rpm@module-reload.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-tgl-1115g4: NOTRUN -> [SKIP][10] ([fdo#111827]) +8 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/fi-tgl-1115g4/igt@kms_chamelium@common-hpd-after-suspend.html * igt@kms_chamelium@dp-crc-fast: - fi-bdw-5557u: NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +8 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/fi-bdw-5557u/igt@kms_chamelium@dp-crc-fast.html * igt@kms_force_connector_basic@force-load-detect: - fi-tgl-1115g4: NOTRUN -> [SKIP][12] ([fdo#109285]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/fi-tgl-1115g4/igt@kms_force_connector_basic@force-load-detect.html * igt@kms_psr@primary_mmap_gtt: - fi-tgl-1115g4: NOTRUN -> [SKIP][13] ([i915#1072]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/fi-tgl-1115g4/igt@kms_psr@primary_mmap_gtt.html * igt@prime_vgem@basic-userptr: - fi-tgl-1115g4: NOTRUN -> [SKIP][14] ([i915#3301]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/fi-tgl-1115g4/igt@prime_vgem@basic-userptr.html #### Possible fixes #### * igt@i915_selftest@live@hangcheck: - {fi-hsw-gt1}: [DMESG-WARN][15] ([i915#3303]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/fi-hsw-gt1/igt@i915_selftest@live@hangcheck.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/fi-hsw-gt1/igt@i915_selftest@live@hangcheck.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575 [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301 [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303 [i915#3718]: https://gitlab.freedesktop.org/drm/intel/issues/3718 [i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579 Participating hosts (35 -> 33) ------------------------------ Additional (2): fi-tgl-1115g4 fi-bdw-5557u Missing (4): fi-kbl-soraka fi-bdw-samus fi-bsw-cyan bat-jsl-1 Build changes ------------- * Linux: CI_DRM_10482 -> Patchwork_20815 CI-20190529: 20190529 CI_DRM_10482: 772cc2d9bb24a9f750e3a88c6b2172873830e095 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6175: c91f99c74b966f635d7e2eb898bf0f78383d281b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_20815: 543840eff86e022446182ed06609952f8d1dd182 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 543840eff86e drm/i915/dg2: add SNPS PHY translations for UHBR link rates e6f596ec68d1 drm/i915/dg2: use existing mechanisms for SNPS PHY translations 5fc36b81b2d1 drm/i915/dp: pass crtc_state to intel_ddi_dp_level() == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/index.html [-- Attachment #2: Type: text/html, Size: 7313 bytes --] ^ permalink raw reply [flat|nested] 13+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/dp: pass crtc_state to intel_ddi_dp_level() 2021-08-13 11:51 [Intel-gfx] [PATCH 1/3] drm/i915/dp: pass crtc_state to intel_ddi_dp_level() Jani Nikula ` (4 preceding siblings ...) 2021-08-13 13:27 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork @ 2021-08-13 16:44 ` Patchwork 2021-08-13 17:48 ` [Intel-gfx] [PATCH 1/3] " Matt Roper 6 siblings, 0 replies; 13+ messages in thread From: Patchwork @ 2021-08-13 16:44 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 30302 bytes --] == Series Details == Series: series starting with [1/3] drm/i915/dp: pass crtc_state to intel_ddi_dp_level() URL : https://patchwork.freedesktop.org/series/93673/ State : success == Summary == CI Bug Log - changes from CI_DRM_10482_full -> Patchwork_20815_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_20815_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_create@create-massive: - shard-snb: NOTRUN -> [DMESG-WARN][1] ([i915#3002]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-snb6/igt@gem_create@create-massive.html * igt@gem_ctx_persistence@legacy-engines-queued: - shard-snb: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1099]) +3 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-snb2/igt@gem_ctx_persistence@legacy-engines-queued.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-glk: [PASS][3] -> [FAIL][4] ([i915#2842]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-glk7/igt@gem_exec_fair@basic-none-share@rcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-glk9/igt@gem_exec_fair@basic-none-share@rcs0.html * igt@gem_exec_fair@basic-none@rcs0: - shard-kbl: [PASS][5] -> [FAIL][6] ([i915#2842]) +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-kbl3/igt@gem_exec_fair@basic-none@rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-kbl3/igt@gem_exec_fair@basic-none@rcs0.html * igt@gem_exec_fair@basic-none@vcs1: - shard-iclb: NOTRUN -> [FAIL][7] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-iclb2/igt@gem_exec_fair@basic-none@vcs1.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglb: [PASS][8] -> [FAIL][9] ([i915#2842]) +1 similar issue [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-tglb7/igt@gem_exec_fair@basic-pace-share@rcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-tglb5/igt@gem_exec_fair@basic-pace-share@rcs0.html * igt@gem_exec_fair@basic-pace@vcs0: - shard-kbl: [PASS][10] -> [SKIP][11] ([fdo#109271]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-kbl4/igt@gem_exec_fair@basic-pace@vcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-kbl3/igt@gem_exec_fair@basic-pace@vcs0.html * igt@gem_exec_whisper@basic-contexts-forked-all: - shard-glk: [PASS][12] -> [DMESG-WARN][13] ([i915#118] / [i915#95]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-glk3/igt@gem_exec_whisper@basic-contexts-forked-all.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-glk8/igt@gem_exec_whisper@basic-contexts-forked-all.html * igt@gem_pread@exhaustion: - shard-apl: NOTRUN -> [WARN][14] ([i915#2658]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-apl7/igt@gem_pread@exhaustion.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-apl7/igt@gem_workarounds@suspend-resume-context.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-apl3/igt@gem_workarounds@suspend-resume-context.html * igt@gen7_exec_parse@basic-offset: - shard-tglb: NOTRUN -> [SKIP][17] ([fdo#109289]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-tglb5/igt@gen7_exec_parse@basic-offset.html * igt@i915_pm_rpm@pc8-residency: - shard-tglb: NOTRUN -> [SKIP][18] ([i915#579]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-tglb5/igt@i915_pm_rpm@pc8-residency.html * igt@i915_suspend@forcewake: - shard-iclb: [PASS][19] -> [INCOMPLETE][20] ([i915#1185]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-iclb4/igt@i915_suspend@forcewake.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-iclb3/igt@i915_suspend@forcewake.html * igt@kms_atomic_transition@plane-all-modeset-transition: - shard-tglb: NOTRUN -> [SKIP][21] ([i915#1769]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-tglb5/igt@kms_atomic_transition@plane-all-modeset-transition.html * igt@kms_big_fb@yf-tiled-addfb-size-overflow: - shard-tglb: NOTRUN -> [SKIP][22] ([fdo#111615]) +2 similar issues [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-tglb2/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip: - shard-apl: NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#3777]) +2 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-apl8/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip.html * igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_mc_ccs: - shard-tglb: NOTRUN -> [SKIP][24] ([i915#3689] / [i915#3886]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-tglb5/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_rc_ccs_cc: - shard-kbl: NOTRUN -> [SKIP][25] ([fdo#109271] / [i915#3886]) +1 similar issue [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-kbl2/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-c-bad-pixel-format-yf_tiled_ccs: - shard-tglb: NOTRUN -> [SKIP][26] ([i915#3689]) [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-tglb5/igt@kms_ccs@pipe-c-bad-pixel-format-yf_tiled_ccs.html * igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_mc_ccs: - shard-apl: NOTRUN -> [SKIP][27] ([fdo#109271] / [i915#3886]) +7 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-apl2/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_ccs: - shard-snb: NOTRUN -> [SKIP][28] ([fdo#109271]) +331 similar issues [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-snb6/igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_ccs.html * igt@kms_chamelium@hdmi-audio-edid: - shard-kbl: NOTRUN -> [SKIP][29] ([fdo#109271] / [fdo#111827]) +5 similar issues [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-kbl2/igt@kms_chamelium@hdmi-audio-edid.html * igt@kms_chamelium@vga-hpd: - shard-apl: NOTRUN -> [SKIP][30] ([fdo#109271] / [fdo#111827]) +15 similar issues [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-apl2/igt@kms_chamelium@vga-hpd.html * igt@kms_chamelium@vga-hpd-fast: - shard-skl: NOTRUN -> [SKIP][31] ([fdo#109271] / [fdo#111827]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-skl7/igt@kms_chamelium@vga-hpd-fast.html * igt@kms_color@pipe-b-ctm-0-75: - shard-skl: [PASS][32] -> [DMESG-WARN][33] ([i915#1982]) [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-skl2/igt@kms_color@pipe-b-ctm-0-75.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-skl10/igt@kms_color@pipe-b-ctm-0-75.html * igt@kms_color_chamelium@pipe-c-ctm-red-to-blue: - shard-snb: NOTRUN -> [SKIP][34] ([fdo#109271] / [fdo#111827]) +14 similar issues [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-snb6/igt@kms_color_chamelium@pipe-c-ctm-red-to-blue.html * igt@kms_color_chamelium@pipe-d-ctm-blue-to-red: - shard-tglb: NOTRUN -> [SKIP][35] ([fdo#109284] / [fdo#111827]) +3 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-tglb5/igt@kms_color_chamelium@pipe-d-ctm-blue-to-red.html * igt@kms_content_protection@uevent: - shard-tglb: NOTRUN -> [SKIP][36] ([fdo#111828]) [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-tglb2/igt@kms_content_protection@uevent.html * igt@kms_cursor_crc@pipe-a-cursor-512x170-onscreen: - shard-skl: NOTRUN -> [SKIP][37] ([fdo#109271]) +6 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-skl7/igt@kms_cursor_crc@pipe-a-cursor-512x170-onscreen.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-skl: [PASS][38] -> [INCOMPLETE][39] ([i915#2828] / [i915#300]) [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-skl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-skl8/igt@kms_cursor_crc@pipe-a-cursor-suspend.html * igt@kms_cursor_crc@pipe-b-cursor-32x32-sliding: - shard-tglb: NOTRUN -> [SKIP][40] ([i915#3319]) [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-tglb5/igt@kms_cursor_crc@pipe-b-cursor-32x32-sliding.html * igt@kms_cursor_crc@pipe-b-cursor-max-size-rapid-movement: - shard-tglb: NOTRUN -> [SKIP][41] ([i915#3359]) +1 similar issue [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-tglb5/igt@kms_cursor_crc@pipe-b-cursor-max-size-rapid-movement.html * igt@kms_cursor_crc@pipe-c-cursor-512x512-rapid-movement: - shard-tglb: NOTRUN -> [SKIP][42] ([fdo#109279] / [i915#3359]) [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-tglb5/igt@kms_cursor_crc@pipe-c-cursor-512x512-rapid-movement.html * igt@kms_cursor_crc@pipe-d-cursor-suspend: - shard-kbl: NOTRUN -> [SKIP][43] ([fdo#109271]) +83 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-kbl2/igt@kms_cursor_crc@pipe-d-cursor-suspend.html * igt@kms_cursor_legacy@pipe-d-torture-bo: - shard-skl: NOTRUN -> [SKIP][44] ([fdo#109271] / [i915#533]) [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-skl7/igt@kms_cursor_legacy@pipe-d-torture-bo.html * igt@kms_flip@flip-vs-expired-vblank@c-edp1: - shard-skl: [PASS][45] -> [FAIL][46] ([i915#79]) [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-skl2/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-skl8/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1: - shard-kbl: [PASS][47] -> [DMESG-WARN][48] ([i915#180]) +7 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-plflip-blt: - shard-tglb: NOTRUN -> [SKIP][49] ([fdo#111825]) +10 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-plflip-blt.html * igt@kms_hdr@bpc-switch-suspend: - shard-apl: NOTRUN -> [DMESG-WARN][50] ([i915#180]) [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-apl6/igt@kms_hdr@bpc-switch-suspend.html * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence: - shard-kbl: NOTRUN -> [SKIP][51] ([fdo#109271] / [i915#533]) [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-kbl2/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence.html * igt@kms_pipe_crc_basic@read-crc-pipe-d: - shard-apl: NOTRUN -> [SKIP][52] ([fdo#109271] / [i915#533]) +1 similar issue [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-apl2/igt@kms_pipe_crc_basic@read-crc-pipe-d.html * igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb: - shard-skl: NOTRUN -> [FAIL][53] ([fdo#108145] / [i915#265]) [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html - shard-kbl: NOTRUN -> [FAIL][54] ([fdo#108145] / [i915#265]) +1 similar issue [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-kbl6/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html * igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb: - shard-apl: NOTRUN -> [FAIL][55] ([i915#265]) [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-apl6/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html - shard-kbl: NOTRUN -> [FAIL][56] ([i915#265]) [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-kbl2/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max: - shard-apl: NOTRUN -> [FAIL][57] ([fdo#108145] / [i915#265]) [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-apl6/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][58] -> [FAIL][59] ([fdo#108145] / [i915#265]) [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt@kms_psr2_sf@plane-move-sf-dmg-area-0: - shard-tglb: NOTRUN -> [SKIP][60] ([i915#2920]) [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-tglb5/igt@kms_psr2_sf@plane-move-sf-dmg-area-0.html * igt@kms_psr2_sf@plane-move-sf-dmg-area-2: - shard-apl: NOTRUN -> [SKIP][61] ([fdo#109271] / [i915#658]) +2 similar issues [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-apl6/igt@kms_psr2_sf@plane-move-sf-dmg-area-2.html * igt@kms_psr2_sf@plane-move-sf-dmg-area-3: - shard-kbl: NOTRUN -> [SKIP][62] ([fdo#109271] / [i915#658]) +1 similar issue [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-kbl2/igt@kms_psr2_sf@plane-move-sf-dmg-area-3.html * igt@kms_psr2_su@page_flip: - shard-iclb: [PASS][63] -> [SKIP][64] ([fdo#109642] / [fdo#111068] / [i915#658]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-iclb2/igt@kms_psr2_su@page_flip.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-iclb4/igt@kms_psr2_su@page_flip.html * igt@kms_psr@psr2_primary_mmap_gtt: - shard-tglb: NOTRUN -> [FAIL][65] ([i915#132] / [i915#3467]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-tglb5/igt@kms_psr@psr2_primary_mmap_gtt.html * igt@kms_vblank@pipe-d-wait-forked-hang: - shard-apl: NOTRUN -> [SKIP][66] ([fdo#109271]) +196 similar issues [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-apl2/igt@kms_vblank@pipe-d-wait-forked-hang.html * igt@kms_vrr@flip-suspend: - shard-tglb: NOTRUN -> [SKIP][67] ([fdo#109502]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-tglb5/igt@kms_vrr@flip-suspend.html * igt@kms_writeback@writeback-check-output: - shard-skl: NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#2437]) [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-skl7/igt@kms_writeback@writeback-check-output.html * igt@kms_writeback@writeback-fb-id: - shard-apl: NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#2437]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-apl7/igt@kms_writeback@writeback-fb-id.html * igt@perf@short-reads: - shard-skl: [PASS][70] -> [FAIL][71] ([i915#51]) [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-skl5/igt@perf@short-reads.html [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-skl2/igt@perf@short-reads.html * igt@perf_pmu@rc6-runtime-pm: - shard-tglb: NOTRUN -> [SKIP][72] ([fdo#111719]) [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-tglb5/igt@perf_pmu@rc6-runtime-pm.html * igt@prime_nv_test@nv_write_i915_gtt_mmap_read: - shard-tglb: NOTRUN -> [SKIP][73] ([fdo#109291]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-tglb2/igt@prime_nv_test@nv_write_i915_gtt_mmap_read.html * igt@prime_vgem@fence-read-hang: - shard-tglb: NOTRUN -> [SKIP][74] ([fdo#109295]) [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-tglb5/igt@prime_vgem@fence-read-hang.html * igt@runner@aborted: - shard-snb: NOTRUN -> [FAIL][75] ([i915#3002]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-snb6/igt@runner@aborted.html * igt@sysfs_clients@create: - shard-kbl: NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#2994]) [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-kbl6/igt@sysfs_clients@create.html * igt@sysfs_clients@fair-1: - shard-apl: NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#2994]) +3 similar issues [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-apl8/igt@sysfs_clients@fair-1.html #### Possible fixes #### * igt@gem_ctx_persistence@smoketest: - shard-tglb: [FAIL][78] ([i915#2896]) -> [PASS][79] [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-tglb2/igt@gem_ctx_persistence@smoketest.html [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-tglb6/igt@gem_ctx_persistence@smoketest.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-tglb: [FAIL][80] ([i915#2842]) -> [PASS][81] +1 similar issue [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-tglb5/igt@gem_exec_fair@basic-flow@rcs0.html [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-tglb3/igt@gem_exec_fair@basic-flow@rcs0.html * igt@gem_exec_fair@basic-none-rrul@rcs0: - shard-glk: [FAIL][82] ([i915#2842]) -> [PASS][83] [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-glk8/igt@gem_exec_fair@basic-none-rrul@rcs0.html [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-glk5/igt@gem_exec_fair@basic-none-rrul@rcs0.html * igt@gem_softpin@allocator-evict@rcs0: - shard-glk: [DMESG-WARN][84] ([i915#118] / [i915#95]) -> [PASS][85] [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-glk9/igt@gem_softpin@allocator-evict@rcs0.html [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-glk9/igt@gem_softpin@allocator-evict@rcs0.html * igt@gem_spin_batch@spin-each: - shard-skl: [FAIL][86] ([i915#2898]) -> [PASS][87] [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-skl3/igt@gem_spin_batch@spin-each.html [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-skl4/igt@gem_spin_batch@spin-each.html * igt@gen9_exec_parse@allowed-single: - shard-skl: [DMESG-WARN][88] ([i915#1436] / [i915#716]) -> [PASS][89] [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-skl8/igt@gen9_exec_parse@allowed-single.html [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-skl7/igt@gen9_exec_parse@allowed-single.html * igt@i915_selftest@live@hangcheck: - shard-snb: [INCOMPLETE][90] ([i915#3921]) -> [PASS][91] [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-snb6/igt@i915_selftest@live@hangcheck.html [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-snb7/igt@i915_selftest@live@hangcheck.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [INCOMPLETE][92] ([i915#2828]) -> [PASS][93] [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-kbl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html * igt@kms_cursor_crc@pipe-c-cursor-128x42-sliding: - shard-skl: [FAIL][94] ([i915#3444]) -> [PASS][95] [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-skl10/igt@kms_cursor_crc@pipe-c-cursor-128x42-sliding.html [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-skl8/igt@kms_cursor_crc@pipe-c-cursor-128x42-sliding.html * igt@kms_cursor_legacy@flip-vs-cursor-legacy: - shard-skl: [FAIL][96] ([i915#2346]) -> [PASS][97] [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1: - shard-skl: [FAIL][98] ([i915#79]) -> [PASS][99] [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-skl5/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html * igt@kms_flip@flip-vs-suspend-interruptible@c-dp1: - shard-apl: [DMESG-WARN][100] ([i915#180]) -> [PASS][101] +1 similar issue [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-apl1/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-apl7/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html * igt@kms_flip@flip-vs-suspend@c-dp1: - shard-kbl: [DMESG-WARN][102] ([i915#180]) -> [PASS][103] +3 similar issues [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-kbl1/igt@kms_flip@flip-vs-suspend@c-dp1.html [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-kbl2/igt@kms_flip@flip-vs-suspend@c-dp1.html * igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1: - shard-skl: [FAIL][104] ([i915#2122]) -> [PASS][105] [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-skl3/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-skl4/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html * igt@kms_hdr@bpc-switch-dpms: - shard-skl: [FAIL][106] ([i915#1188]) -> [PASS][107] [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-skl4/igt@kms_hdr@bpc-switch-dpms.html [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-skl5/igt@kms_hdr@bpc-switch-dpms.html * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min: - shard-skl: [FAIL][108] ([fdo#108145] / [i915#265]) -> [PASS][109] [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html * igt@kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: [SKIP][110] ([fdo#109441]) -> [PASS][111] +2 similar issues [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-iclb8/igt@kms_psr@psr2_cursor_mmap_cpu.html [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html * igt@kms_vblank@pipe-c-wait-forked-hang: - shard-tglb: [INCOMPLETE][112] -> [PASS][113] [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-tglb7/igt@kms_vblank@pipe-c-wait-forked-hang.html [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-tglb5/igt@kms_vblank@pipe-c-wait-forked-hang.html * igt@perf@blocking: - shard-skl: [FAIL][114] ([i915#1542]) -> [PASS][115] [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-skl6/igt@perf@blocking.html [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-skl7/igt@perf@blocking.html * igt@perf@polling-parameterized: - shard-glk: [FAIL][116] ([i915#1542]) -> [PASS][117] [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-glk8/igt@perf@polling-parameterized.html [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-glk5/igt@perf@polling-parameterized.html #### Warnings #### * igt@gem_exec_fair@basic-none-vip@rcs0: - shard-tglb: [SKIP][118] ([i915#2848]) -> [FAIL][119] ([i915#2842]) [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-tglb6/igt@gem_exec_fair@basic-none-vip@rcs0.html [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-tglb2/igt@gem_exec_fair@basic-none-vip@rcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-kbl: [FAIL][120] ([i915#2842]) -> [SKIP][121] ([fdo#109271]) [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-kbl4/igt@gem_exec_fair@basic-pace@vcs1.html [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-kbl3/igt@gem_exec_fair@basic-pace@vcs1.html * igt@i915_pm_dc@dc3co-vpb-simulation: - shard-iclb: [SKIP][122] ([i915#658]) -> [SKIP][123] ([i915#588]) [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-iclb8/igt@i915_pm_dc@dc3co-vpb-simulation.html [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html * igt@i915_pm_rc6_residency@rc6-idle: - shard-iclb: [WARN][124] ([i915#2684]) -> [WARN][125] ([i915#1804] / [i915#2684]) [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-iclb2/igt@i915_pm_rc6_residency@rc6-idle.html [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-iclb4/igt@i915_pm_rc6_residency@rc6-idle.html * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip: - shard-skl: [FAIL][126] -> [FAIL][127] ([i915#3722]) [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-skl10/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-skl8/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html * igt@kms_psr2_sf@plane-move-sf-dmg-area-0: - shard-iclb: [SKIP][128] ([i915#658]) -> [SKIP][129] ([i915#2920]) +1 similar issue [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-iclb1/igt@kms_psr2_sf@plane-move-sf-dmg-area-0.html [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-iclb2/igt@kms_psr2_sf@plane-move-sf-dmg-area-0.html * igt@kms_psr2_sf@plane-move-sf-dmg-area-3: - shard-iclb: [SKIP][130] ([i915#2920]) -> [SKIP][131] ([i915#658]) +1 similar issue [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-iclb2/igt@kms_psr2_sf@plane-move-sf-dmg-area-3.html [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-iclb4/igt@kms_psr2_sf@plane-move-sf-dmg-area-3.html * igt@runner@aborted: - shard-kbl: ([FAIL][132], [FAIL][133], [FAIL][134], [FAIL][135], [FAIL][136]) ([i915#180] / [i915#2505] / [i915#3002] / [i915#3363]) -> ([FAIL][137], [FAIL][138], [FAIL][139], [FAIL][140], [FAIL][141], [FAIL][142], [FAIL][143], [FAIL][144]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#2505] / [i915#3002] / [i915#3363]) [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-kbl1/igt@runner@aborted.html [133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-kbl6/igt@runner@aborted.html [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-kbl1/igt@runner@aborted.html [135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-kbl1/igt@runner@aborted.html [136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-kbl1/igt@runner@aborted.html [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-kbl4/igt@runner@aborted.html [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-kbl4/igt@runner@aborted.html [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-kbl4/igt@runner@aborted.html [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-kbl1/igt@runner@aborted.html [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-kbl1/igt@runner@aborted.html [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-kbl1/igt@runner@aborted.html [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-kbl4/igt@runner@aborted.html [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-kbl6/igt@runner@aborted.html - shard-apl: ([FAIL][145], [FAIL][146], [FAIL][147], [FAIL][148], [FAIL][149]) ([i915#180] / [i915#1814] / [i915#3002] / [i915#3363]) -> ([FAIL][150], [FAIL][151], [FAIL][152], [FAIL][153], [FAIL][154], [FAIL][155]) ([fdo#109271] / [i915#180] / [i915#1814] / [i915#3002] / [i915#3363]) [145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-apl7/igt@runner@aborted.html [146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-apl1/igt@runner@aborted.html [147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-apl2/igt@runner@aborted.html [148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-apl3/igt@runner@aborted.html [149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10482/shard-apl8/igt@runner@aborted.html [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-apl7/igt@runner@aborted.html [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-apl2/igt@runner@aborted.html [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/shard-apl6/igt@runner@aborted.html [153 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20815/index.html [-- Attachment #2: Type: text/html, Size: 33954 bytes --] ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] drm/i915/dp: pass crtc_state to intel_ddi_dp_level() 2021-08-13 11:51 [Intel-gfx] [PATCH 1/3] drm/i915/dp: pass crtc_state to intel_ddi_dp_level() Jani Nikula ` (5 preceding siblings ...) 2021-08-13 16:44 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork @ 2021-08-13 17:48 ` Matt Roper 6 siblings, 0 replies; 13+ messages in thread From: Matt Roper @ 2021-08-13 17:48 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx, Manasi Navare On Fri, Aug 13, 2021 at 02:51:49PM +0300, Jani Nikula wrote: > Needed in the future. > > Cc: Manasi Navare <manasi.d.navare@intel.com> > Cc: Matt Roper <matthew.d.roper@intel.com> > Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 19 ++++++++++--------- > 1 file changed, 10 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index e932fd0fe7e2..8cf5d1572ee0 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -1371,7 +1371,8 @@ static int translate_signal_level(struct intel_dp *intel_dp, > return 0; > } > > -static int intel_ddi_dp_level(struct intel_dp *intel_dp) > +static int intel_ddi_dp_level(struct intel_dp *intel_dp, > + const struct intel_crtc_state *crtc_state) > { > u8 train_set = intel_dp->train_set[0]; > u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | > @@ -1385,7 +1386,7 @@ dg2_set_signal_levels(struct intel_dp *intel_dp, > const struct intel_crtc_state *crtc_state) > { > struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; > - int level = intel_ddi_dp_level(intel_dp); > + int level = intel_ddi_dp_level(intel_dp, crtc_state); > > intel_snps_phy_ddi_vswing_sequence(encoder, level); > } > @@ -1395,7 +1396,7 @@ tgl_set_signal_levels(struct intel_dp *intel_dp, > const struct intel_crtc_state *crtc_state) > { > struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; > - int level = intel_ddi_dp_level(intel_dp); > + int level = intel_ddi_dp_level(intel_dp, crtc_state); > > tgl_ddi_vswing_sequence(encoder, crtc_state, level); > } > @@ -1405,7 +1406,7 @@ icl_set_signal_levels(struct intel_dp *intel_dp, > const struct intel_crtc_state *crtc_state) > { > struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; > - int level = intel_ddi_dp_level(intel_dp); > + int level = intel_ddi_dp_level(intel_dp, crtc_state); > > icl_ddi_vswing_sequence(encoder, crtc_state, level); > } > @@ -1415,7 +1416,7 @@ bxt_set_signal_levels(struct intel_dp *intel_dp, > const struct intel_crtc_state *crtc_state) > { > struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; > - int level = intel_ddi_dp_level(intel_dp); > + int level = intel_ddi_dp_level(intel_dp, crtc_state); > > bxt_ddi_vswing_sequence(encoder, crtc_state, level); > } > @@ -1426,7 +1427,7 @@ hsw_set_signal_levels(struct intel_dp *intel_dp, > { > struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > - int level = intel_ddi_dp_level(intel_dp); > + int level = intel_ddi_dp_level(intel_dp, crtc_state); > enum port port = encoder->port; > u32 signal_levels; > > @@ -2328,7 +2329,7 @@ static void dg2_ddi_pre_enable_dp(struct intel_atomic_state *state, > enum phy phy = intel_port_to_phy(dev_priv, encoder->port); > struct intel_digital_port *dig_port = enc_to_dig_port(encoder); > bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); > - int level = intel_ddi_dp_level(intel_dp); > + int level = intel_ddi_dp_level(intel_dp, crtc_state); > > intel_dp_set_link_params(intel_dp, crtc_state->port_clock, > crtc_state->lane_count); > @@ -2441,7 +2442,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, > enum phy phy = intel_port_to_phy(dev_priv, encoder->port); > struct intel_digital_port *dig_port = enc_to_dig_port(encoder); > bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); > - int level = intel_ddi_dp_level(intel_dp); > + int level = intel_ddi_dp_level(intel_dp, crtc_state); > > intel_dp_set_link_params(intel_dp, > crtc_state->port_clock, > @@ -2584,7 +2585,7 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, > enum phy phy = intel_port_to_phy(dev_priv, port); > struct intel_digital_port *dig_port = enc_to_dig_port(encoder); > bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); > - int level = intel_ddi_dp_level(intel_dp); > + int level = intel_ddi_dp_level(intel_dp, crtc_state); > > if (DISPLAY_VER(dev_priv) < 11) > drm_WARN_ON(&dev_priv->drm, > -- > 2.20.1 > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 ^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2021-08-13 19:59 UTC | newest] Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-08-13 11:51 [Intel-gfx] [PATCH 1/3] drm/i915/dp: pass crtc_state to intel_ddi_dp_level() Jani Nikula 2021-08-13 11:51 ` [Intel-gfx] [PATCH 2/3] drm/i915/dg2: use existing mechanisms for SNPS PHY translations Jani Nikula 2021-08-13 17:59 ` Matt Roper 2021-08-13 19:36 ` Jani Nikula 2021-08-13 19:54 ` Jani Nikula 2021-08-13 19:59 ` Matt Roper 2021-08-13 11:51 ` [Intel-gfx] [PATCH 3/3] drm/i915/dg2: add SNPS PHY translations for UHBR link rates Jani Nikula 2021-08-13 18:01 ` Matt Roper 2021-08-13 12:57 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/dp: pass crtc_state to intel_ddi_dp_level() Patchwork 2021-08-13 12:57 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2021-08-13 13:27 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2021-08-13 16:44 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2021-08-13 17:48 ` [Intel-gfx] [PATCH 1/3] " Matt Roper
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