* [Intel-gfx] [PATCH 1/3] drm/i915/display: Add missing checks for cdclk crawling
@ 2022-11-16 14:50 Anusha Srivatsa
2022-11-16 14:50 ` [Intel-gfx] [PATCH 2/3] drm/i915/display: Do both crawl and squash when changing cdclk Anusha Srivatsa
` (4 more replies)
0 siblings, 5 replies; 8+ messages in thread
From: Anusha Srivatsa @ 2022-11-16 14:50 UTC (permalink / raw)
To: intel-gfx
cdclk_sanitize() function was written assuming vco was a signed integer.
vco gets assigned to -1 (essentially ~0) for the case where PLL
might be enabled and vco is not a frequency that will ever
get used. In such a scenario the right thing to do is disable the
PLL and re-enable it again with a valid frequency.
However the vco is declared as a unsigned variable.
With the above assumption, driver takes crawl path when not needed.
Add explicit check to not crawl in the case of an invalid PLL.
v2: Move the check from .h to .c (MattR)
- Move check to bxt_set_cdclk() instead of
intel_modeset_calc_cdclk() which is directly in
the path of the sanitize() function (Ville)
v3: remove unwanted parenthesis(Ville)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index b74e36d76013..25d01271dc09 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1717,6 +1717,16 @@ static void dg2_cdclk_squash_program(struct drm_i915_private *i915,
intel_de_write(i915, CDCLK_SQUASH_CTL, squash_ctl);
}
+static bool cdclk_pll_is_unknown(unsigned int vco)
+{
+ /*
+ * Ensure driver does not take the crawl path for the
+ * case when the vco is set to ~0 in the
+ * sanitize path.
+ */
+ return vco == ~0;
+}
+
static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
const struct intel_cdclk_config *cdclk_config,
enum pipe pipe)
@@ -1749,7 +1759,8 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
return;
}
- if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0) {
+ if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0 &&
+ !cdclk_pll_is_unknown(dev_priv->display.cdclk.hw.vco)) {
if (dev_priv->display.cdclk.hw.vco != vco)
adlp_cdclk_pll_crawl(dev_priv, vco);
} else if (DISPLAY_VER(dev_priv) >= 11)
--
2.25.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Intel-gfx] [PATCH 2/3] drm/i915/display: Do both crawl and squash when changing cdclk
2022-11-16 14:50 [Intel-gfx] [PATCH 1/3] drm/i915/display: Add missing checks for cdclk crawling Anusha Srivatsa
@ 2022-11-16 14:50 ` Anusha Srivatsa
2022-11-16 18:43 ` Matt Roper
2022-11-16 14:50 ` [Intel-gfx] [PATCH 3/3] drm/i915/display: Add CDCLK Support for MTL Anusha Srivatsa
` (3 subsequent siblings)
4 siblings, 1 reply; 8+ messages in thread
From: Anusha Srivatsa @ 2022-11-16 14:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Balasubramani Vivekanandan
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
For MTL, changing cdclk from between certain frequencies has
both squash and crawl. Use the current cdclk config and
the new(desired) cdclk config to construtc a mid cdclk config.
Set the cdclk twice:
- Current cdclk -> mid cdclk
- mid cdclk -> desired cdclk
Driver should not take some Pcode mailbox communication
in the cdclk path for platforms that are Display 14 and later.
v2: Add check in intel_modeset_calc_cdclk() to avoid cdclk
change via modeset for platforms that support squash_crawl sequences(Ville)
v3: Add checks for:
- scenario where only slow clock is used and
cdclk is actually 0 (bringing up display).
- PLLs are on before looking up the waveform.
- Squash and crawl capability checks.(Ville)
v4: Rebase
- Move checks to be more consistent (Ville)
- Add comments (Bala)
v5:
- Further small changes. Move checks around.
- Make if-else better looking (Ville)
v6: MTl should not follow PUnit mailbox communication as the rest of
gen11+ platforms.(Anusha)
Cc: Clint Taylor <Clinton.A.Taylor@intel.com>
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 175 +++++++++++++++++----
1 file changed, 144 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 25d01271dc09..6e122d56428c 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1727,37 +1727,75 @@ static bool cdclk_pll_is_unknown(unsigned int vco)
return vco == ~0;
}
-static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_config *cdclk_config,
- enum pipe pipe)
+static int cdclk_squash_divider(u16 waveform)
+{
+ return hweight16(waveform ?: 0xffff);
+}
+
+static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i915,
+ const struct intel_cdclk_config *old_cdclk_config,
+ const struct intel_cdclk_config *new_cdclk_config,
+ struct intel_cdclk_config *mid_cdclk_config)
+{
+ u16 old_waveform, new_waveform, mid_waveform;
+ int size = 16;
+ int div = 2;
+
+ /* Return if both Squash and Crawl are not present */
+ if (!HAS_CDCLK_CRAWL(i915) || !HAS_CDCLK_SQUASH(i915))
+ return false;
+
+ old_waveform = cdclk_squash_waveform(i915, old_cdclk_config->cdclk);
+ new_waveform = cdclk_squash_waveform(i915, new_cdclk_config->cdclk);
+
+ /* Return if Squash only or Crawl only is the desired action */
+ if (old_cdclk_config->vco <= 0 || new_cdclk_config->vco <= 0 ||
+ old_cdclk_config->vco == new_cdclk_config->vco ||
+ old_waveform == new_waveform)
+ return false;
+
+ *mid_cdclk_config = *new_cdclk_config;
+
+ /*
+ * Populate the mid_cdclk_config accordingly.
+ * - If moving to a higher cdclk, the desired action is squashing.
+ * The mid cdclk config should have the new (squash) waveform.
+ * - If moving to a lower cdclk, the desired action is crawling.
+ * The mid cdclk config should have the new vco.
+ */
+
+ if (cdclk_squash_divider(new_waveform) > cdclk_squash_divider(old_waveform)) {
+ mid_cdclk_config->vco = old_cdclk_config->vco;
+ mid_waveform = new_waveform;
+ } else {
+ mid_cdclk_config->vco = new_cdclk_config->vco;
+ mid_waveform = old_waveform;
+ }
+
+ mid_cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) *
+ mid_cdclk_config->vco, size * div);
+
+ /* make sure the mid clock came out sane */
+
+ drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk <
+ min(old_cdclk_config->cdclk, new_cdclk_config->cdclk));
+ drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk >
+ i915->display.cdclk.max_cdclk_freq);
+ drm_WARN_ON(&i915->drm, cdclk_squash_waveform(i915, mid_cdclk_config->cdclk) !=
+ mid_waveform);
+
+ return true;
+}
+
+static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
+ const struct intel_cdclk_config *cdclk_config,
+ enum pipe pipe)
{
int cdclk = cdclk_config->cdclk;
int vco = cdclk_config->vco;
u32 val;
u16 waveform;
int clock;
- int ret;
-
- /* Inform power controller of upcoming frequency change. */
- if (DISPLAY_VER(dev_priv) >= 11)
- ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
- SKL_CDCLK_PREPARE_FOR_CHANGE,
- SKL_CDCLK_READY_FOR_CHANGE,
- SKL_CDCLK_READY_FOR_CHANGE, 3);
- else
- /*
- * BSpec requires us to wait up to 150usec, but that leads to
- * timeouts; the 2ms used here is based on experiment.
- */
- ret = snb_pcode_write_timeout(&dev_priv->uncore,
- HSW_PCODE_DE_WRITE_FREQ_REQ,
- 0x80000000, 150, 2);
- if (ret) {
- drm_err(&dev_priv->drm,
- "Failed to inform PCU about cdclk change (err %d, freq %d)\n",
- ret, cdclk);
- return;
- }
if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0 &&
!cdclk_pll_is_unknown(dev_priv->display.cdclk.hw.vco)) {
@@ -1793,11 +1831,62 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
if (pipe != INVALID_PIPE)
intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe));
+}
- if (DISPLAY_VER(dev_priv) >= 11) {
+static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
+ const struct intel_cdclk_config *cdclk_config,
+ enum pipe pipe)
+{
+ struct intel_cdclk_config mid_cdclk_config;
+ int cdclk = cdclk_config->cdclk;
+ int ret = 0;
+
+ /*
+ * Inform power controller of upcoming frequency change.
+ * Display versions 14 and beyond do not follow the PUnit
+ * mailbox communication, skip
+ * this step.
+ */
+ if (DISPLAY_VER(dev_priv) >= 14)
+ /* NOOP */;
+ else if (DISPLAY_VER(dev_priv) >= 11)
+ ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
+ SKL_CDCLK_PREPARE_FOR_CHANGE,
+ SKL_CDCLK_READY_FOR_CHANGE,
+ SKL_CDCLK_READY_FOR_CHANGE, 3);
+ else
+ /*
+ * BSpec requires us to wait up to 150usec, but that leads to
+ * timeouts; the 2ms used here is based on experiment.
+ */
+ ret = snb_pcode_write_timeout(&dev_priv->uncore,
+ HSW_PCODE_DE_WRITE_FREQ_REQ,
+ 0x80000000, 150, 2);
+
+ if (ret) {
+ drm_err(&dev_priv->drm,
+ "Failed to inform PCU about cdclk change (err %d, freq %d)\n",
+ ret, cdclk);
+ return;
+ }
+
+ if (cdclk_compute_crawl_and_squash_midpoint(dev_priv, &dev_priv->display.cdclk.hw,
+ cdclk_config, &mid_cdclk_config)) {
+ _bxt_set_cdclk(dev_priv, &mid_cdclk_config, pipe);
+ _bxt_set_cdclk(dev_priv, cdclk_config, pipe);
+ } else {
+ _bxt_set_cdclk(dev_priv, cdclk_config, pipe);
+ }
+
+ if (DISPLAY_VER(dev_priv) >= 14)
+ /*
+ * NOOP - No Pcode communication needed for
+ * Display versions 14 and beyond
+ */;
+ else if (DISPLAY_VER(dev_priv) >= 11)
ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
cdclk_config->voltage_level);
- } else {
+ else
/*
* The timeout isn't specified, the 2ms used here is based on
* experiment.
@@ -1808,7 +1897,6 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
HSW_PCODE_DE_WRITE_FREQ_REQ,
cdclk_config->voltage_level,
150, 2);
- }
if (ret) {
drm_err(&dev_priv->drm,
@@ -1965,6 +2053,26 @@ void intel_cdclk_uninit_hw(struct drm_i915_private *i915)
skl_cdclk_uninit_hw(i915);
}
+static bool intel_cdclk_can_crawl_and_squash(struct drm_i915_private *i915,
+ const struct intel_cdclk_config *a,
+ const struct intel_cdclk_config *b)
+{
+ u16 old_waveform;
+ u16 new_waveform;
+
+ if (a->vco == 0 || b->vco == 0)
+ return false;
+
+ if (!HAS_CDCLK_CRAWL(i915) || !HAS_CDCLK_SQUASH(i915))
+ return false;
+
+ old_waveform = cdclk_squash_waveform(i915, a->cdclk);
+ new_waveform = cdclk_squash_waveform(i915, b->cdclk);
+
+ return a->vco != b->vco &&
+ old_waveform != new_waveform;
+}
+
static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv,
const struct intel_cdclk_config *a,
const struct intel_cdclk_config *b)
@@ -2771,9 +2879,14 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
pipe = INVALID_PIPE;
}
- if (intel_cdclk_can_squash(dev_priv,
- &old_cdclk_state->actual,
- &new_cdclk_state->actual)) {
+ if (intel_cdclk_can_crawl_and_squash(dev_priv,
+ &old_cdclk_state->actual,
+ &new_cdclk_state->actual)) {
+ drm_dbg_kms(&dev_priv->drm,
+ "Can change cdclk via crawling and squashing\n");
+ } else if (intel_cdclk_can_squash(dev_priv,
+ &old_cdclk_state->actual,
+ &new_cdclk_state->actual)) {
drm_dbg_kms(&dev_priv->drm,
"Can change cdclk via squashing\n");
} else if (intel_cdclk_can_crawl(dev_priv,
--
2.25.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Intel-gfx] [PATCH 3/3] drm/i915/display: Add CDCLK Support for MTL
2022-11-16 14:50 [Intel-gfx] [PATCH 1/3] drm/i915/display: Add missing checks for cdclk crawling Anusha Srivatsa
2022-11-16 14:50 ` [Intel-gfx] [PATCH 2/3] drm/i915/display: Do both crawl and squash when changing cdclk Anusha Srivatsa
@ 2022-11-16 14:50 ` Anusha Srivatsa
2022-11-16 21:21 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/display: Add missing checks for cdclk crawling Patchwork
` (2 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Anusha Srivatsa @ 2022-11-16 14:50 UTC (permalink / raw)
To: intel-gfx
As per bSpec MTL has 38.4 MHz Reference clock.
Adding the cdclk tables and cdclk_funcs that MTL
will use.
v2: Revert to using bxt_get_cdclk()
BSpec: 65243
Cc: Clint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 22 +++++++++++++++++++++-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 6e122d56428c..6694e83287d9 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1346,6 +1346,16 @@ static const struct intel_cdclk_vals dg2_cdclk_table[] = {
{}
};
+static const struct intel_cdclk_vals mtl_cdclk_table[] = {
+ { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
+ { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
+ { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0x0000 },
+ {}
+};
+
static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
{
const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
@@ -3184,6 +3194,13 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
return freq;
}
+static const struct intel_cdclk_funcs mtl_cdclk_funcs = {
+ .get_cdclk = bxt_get_cdclk,
+ .set_cdclk = bxt_set_cdclk,
+ .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+ .calc_voltage_level = tgl_calc_voltage_level,
+};
+
static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
.get_cdclk = bxt_get_cdclk,
.set_cdclk = bxt_set_cdclk,
@@ -3319,7 +3336,10 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = {
*/
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
{
- if (IS_DG2(dev_priv)) {
+ if (IS_METEORLAKE(dev_priv)) {
+ dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
+ dev_priv->display.cdclk.table = mtl_cdclk_table;
+ } else if (IS_DG2(dev_priv)) {
dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
dev_priv->display.cdclk.table = dg2_cdclk_table;
} else if (IS_ALDERLAKE_P(dev_priv)) {
--
2.25.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH 2/3] drm/i915/display: Do both crawl and squash when changing cdclk
2022-11-16 14:50 ` [Intel-gfx] [PATCH 2/3] drm/i915/display: Do both crawl and squash when changing cdclk Anusha Srivatsa
@ 2022-11-16 18:43 ` Matt Roper
2022-11-16 19:55 ` Srivatsa, Anusha
0 siblings, 1 reply; 8+ messages in thread
From: Matt Roper @ 2022-11-16 18:43 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx, Balasubramani Vivekanandan
On Wed, Nov 16, 2022 at 06:50:07AM -0800, Anusha Srivatsa wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> For MTL, changing cdclk from between certain frequencies has
> both squash and crawl. Use the current cdclk config and
> the new(desired) cdclk config to construtc a mid cdclk config.
> Set the cdclk twice:
> - Current cdclk -> mid cdclk
> - mid cdclk -> desired cdclk
>
> Driver should not take some Pcode mailbox communication
> in the cdclk path for platforms that are Display 14 and later.
Nit: display _version_ 14 and later.
>
> v2: Add check in intel_modeset_calc_cdclk() to avoid cdclk
> change via modeset for platforms that support squash_crawl sequences(Ville)
>
> v3: Add checks for:
> - scenario where only slow clock is used and
> cdclk is actually 0 (bringing up display).
> - PLLs are on before looking up the waveform.
> - Squash and crawl capability checks.(Ville)
>
> v4: Rebase
> - Move checks to be more consistent (Ville)
> - Add comments (Bala)
> v5:
> - Further small changes. Move checks around.
> - Make if-else better looking (Ville)
>
> v6: MTl should not follow PUnit mailbox communication as the rest of
> gen11+ platforms.(Anusha)
>
> Cc: Clint Taylor <Clinton.A.Taylor@intel.com>
> Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 175 +++++++++++++++++----
> 1 file changed, 144 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 25d01271dc09..6e122d56428c 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1727,37 +1727,75 @@ static bool cdclk_pll_is_unknown(unsigned int vco)
> return vco == ~0;
> }
>
> -static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> - const struct intel_cdclk_config *cdclk_config,
> - enum pipe pipe)
> +static int cdclk_squash_divider(u16 waveform)
> +{
> + return hweight16(waveform ?: 0xffff);
> +}
> +
> +static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i915,
> + const struct intel_cdclk_config *old_cdclk_config,
> + const struct intel_cdclk_config *new_cdclk_config,
> + struct intel_cdclk_config *mid_cdclk_config)
> +{
> + u16 old_waveform, new_waveform, mid_waveform;
> + int size = 16;
> + int div = 2;
> +
> + /* Return if both Squash and Crawl are not present */
> + if (!HAS_CDCLK_CRAWL(i915) || !HAS_CDCLK_SQUASH(i915))
> + return false;
> +
> + old_waveform = cdclk_squash_waveform(i915, old_cdclk_config->cdclk);
> + new_waveform = cdclk_squash_waveform(i915, new_cdclk_config->cdclk);
> +
> + /* Return if Squash only or Crawl only is the desired action */
> + if (old_cdclk_config->vco <= 0 || new_cdclk_config->vco <= 0 ||
We still have "<= 0" checks here. As noted before, the < part can never
evaluate to true since vco is an unsigned value. I think you meant to
update this to include a check with your new cdclk_pll_is_unknown()
helper?
Also, the comment above this check says "if squash only or crawl only is
the desired action" which is what the "==" conditions below cover. But
the vco 0/unknown checks are technically to ensure we bail out if the
desired action is to do neither of the two (traditional modeset).
> + old_cdclk_config->vco == new_cdclk_config->vco ||
> + old_waveform == new_waveform)
> + return false;
> +
> + *mid_cdclk_config = *new_cdclk_config;
> +
> + /*
> + * Populate the mid_cdclk_config accordingly.
> + * - If moving to a higher cdclk, the desired action is squashing.
> + * The mid cdclk config should have the new (squash) waveform.
> + * - If moving to a lower cdclk, the desired action is crawling.
> + * The mid cdclk config should have the new vco.
> + */
> +
> + if (cdclk_squash_divider(new_waveform) > cdclk_squash_divider(old_waveform)) {
> + mid_cdclk_config->vco = old_cdclk_config->vco;
> + mid_waveform = new_waveform;
> + } else {
> + mid_cdclk_config->vco = new_cdclk_config->vco;
> + mid_waveform = old_waveform;
> + }
> +
> + mid_cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) *
> + mid_cdclk_config->vco, size * div);
> +
> + /* make sure the mid clock came out sane */
> +
> + drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk <
> + min(old_cdclk_config->cdclk, new_cdclk_config->cdclk));
> + drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk >
> + i915->display.cdclk.max_cdclk_freq);
> + drm_WARN_ON(&i915->drm, cdclk_squash_waveform(i915, mid_cdclk_config->cdclk) !=
> + mid_waveform);
> +
> + return true;
> +}
> +
> +static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
> + const struct intel_cdclk_config *cdclk_config,
> + enum pipe pipe)
> {
> int cdclk = cdclk_config->cdclk;
> int vco = cdclk_config->vco;
> u32 val;
> u16 waveform;
> int clock;
> - int ret;
> -
> - /* Inform power controller of upcoming frequency change. */
> - if (DISPLAY_VER(dev_priv) >= 11)
> - ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
> - SKL_CDCLK_PREPARE_FOR_CHANGE,
> - SKL_CDCLK_READY_FOR_CHANGE,
> - SKL_CDCLK_READY_FOR_CHANGE, 3);
> - else
> - /*
> - * BSpec requires us to wait up to 150usec, but that leads to
> - * timeouts; the 2ms used here is based on experiment.
> - */
> - ret = snb_pcode_write_timeout(&dev_priv->uncore,
> - HSW_PCODE_DE_WRITE_FREQ_REQ,
> - 0x80000000, 150, 2);
> - if (ret) {
> - drm_err(&dev_priv->drm,
> - "Failed to inform PCU about cdclk change (err %d, freq %d)\n",
> - ret, cdclk);
> - return;
> - }
>
> if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0 &&
> !cdclk_pll_is_unknown(dev_priv->display.cdclk.hw.vco)) {
> @@ -1793,11 +1831,62 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
>
> if (pipe != INVALID_PIPE)
> intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe));
> +}
>
> - if (DISPLAY_VER(dev_priv) >= 11) {
> +static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> + const struct intel_cdclk_config *cdclk_config,
> + enum pipe pipe)
> +{
> + struct intel_cdclk_config mid_cdclk_config;
> + int cdclk = cdclk_config->cdclk;
> + int ret = 0;
> +
> + /*
> + * Inform power controller of upcoming frequency change.
> + * Display versions 14 and beyond do not follow the PUnit
> + * mailbox communication, skip
> + * this step.
> + */
> + if (DISPLAY_VER(dev_priv) >= 14)
> + /* NOOP */;
> + else if (DISPLAY_VER(dev_priv) >= 11)
> + ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
> + SKL_CDCLK_PREPARE_FOR_CHANGE,
> + SKL_CDCLK_READY_FOR_CHANGE,
> + SKL_CDCLK_READY_FOR_CHANGE, 3);
> + else
> + /*
> + * BSpec requires us to wait up to 150usec, but that leads to
> + * timeouts; the 2ms used here is based on experiment.
> + */
> + ret = snb_pcode_write_timeout(&dev_priv->uncore,
> + HSW_PCODE_DE_WRITE_FREQ_REQ,
> + 0x80000000, 150, 2);
> +
> + if (ret) {
> + drm_err(&dev_priv->drm,
> + "Failed to inform PCU about cdclk change (err %d, freq %d)\n",
> + ret, cdclk);
> + return;
> + }
> +
> + if (cdclk_compute_crawl_and_squash_midpoint(dev_priv, &dev_priv->display.cdclk.hw,
> + cdclk_config, &mid_cdclk_config)) {
> + _bxt_set_cdclk(dev_priv, &mid_cdclk_config, pipe);
> + _bxt_set_cdclk(dev_priv, cdclk_config, pipe);
> + } else {
> + _bxt_set_cdclk(dev_priv, cdclk_config, pipe);
> + }
> +
> + if (DISPLAY_VER(dev_priv) >= 14)
> + /*
> + * NOOP - No Pcode communication needed for
> + * Display versions 14 and beyond
> + */;
> + else if (DISPLAY_VER(dev_priv) >= 11)
> ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
> cdclk_config->voltage_level);
> - } else {
> + else
> /*
> * The timeout isn't specified, the 2ms used here is based on
> * experiment.
> @@ -1808,7 +1897,6 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> HSW_PCODE_DE_WRITE_FREQ_REQ,
> cdclk_config->voltage_level,
> 150, 2);
> - }
>
> if (ret) {
> drm_err(&dev_priv->drm,
> @@ -1965,6 +2053,26 @@ void intel_cdclk_uninit_hw(struct drm_i915_private *i915)
> skl_cdclk_uninit_hw(i915);
> }
>
> +static bool intel_cdclk_can_crawl_and_squash(struct drm_i915_private *i915,
> + const struct intel_cdclk_config *a,
> + const struct intel_cdclk_config *b)
Do we need a check for PLL unknown here? We don't want to decide that
we can skip a modeset if the PLL is unknown, right?
Matt
> +{
> + u16 old_waveform;
> + u16 new_waveform;
> +
> + if (a->vco == 0 || b->vco == 0)
> + return false;
> +
> + if (!HAS_CDCLK_CRAWL(i915) || !HAS_CDCLK_SQUASH(i915))
> + return false;
> +
> + old_waveform = cdclk_squash_waveform(i915, a->cdclk);
> + new_waveform = cdclk_squash_waveform(i915, b->cdclk);
> +
> + return a->vco != b->vco &&
> + old_waveform != new_waveform;
> +}
> +
> static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv,
> const struct intel_cdclk_config *a,
> const struct intel_cdclk_config *b)
> @@ -2771,9 +2879,14 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
> pipe = INVALID_PIPE;
> }
>
> - if (intel_cdclk_can_squash(dev_priv,
> - &old_cdclk_state->actual,
> - &new_cdclk_state->actual)) {
> + if (intel_cdclk_can_crawl_and_squash(dev_priv,
> + &old_cdclk_state->actual,
> + &new_cdclk_state->actual)) {
> + drm_dbg_kms(&dev_priv->drm,
> + "Can change cdclk via crawling and squashing\n");
> + } else if (intel_cdclk_can_squash(dev_priv,
> + &old_cdclk_state->actual,
> + &new_cdclk_state->actual)) {
> drm_dbg_kms(&dev_priv->drm,
> "Can change cdclk via squashing\n");
> } else if (intel_cdclk_can_crawl(dev_priv,
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH 2/3] drm/i915/display: Do both crawl and squash when changing cdclk
2022-11-16 18:43 ` Matt Roper
@ 2022-11-16 19:55 ` Srivatsa, Anusha
0 siblings, 0 replies; 8+ messages in thread
From: Srivatsa, Anusha @ 2022-11-16 19:55 UTC (permalink / raw)
To: Roper, Matthew D; +Cc: intel-gfx, Vivekanandan, Balasubramani
> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@intel.com>
> Sent: Wednesday, November 16, 2022 10:44 AM
> To: Srivatsa, Anusha <anusha.srivatsa@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Vivekanandan, Balasubramani
> <balasubramani.vivekanandan@intel.com>
> Subject: Re: [Intel-gfx] [PATCH 2/3] drm/i915/display: Do both crawl and
> squash when changing cdclk
>
> On Wed, Nov 16, 2022 at 06:50:07AM -0800, Anusha Srivatsa wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > For MTL, changing cdclk from between certain frequencies has both
> > squash and crawl. Use the current cdclk config and the new(desired)
> > cdclk config to construtc a mid cdclk config.
> > Set the cdclk twice:
> > - Current cdclk -> mid cdclk
> > - mid cdclk -> desired cdclk
> >
> > Driver should not take some Pcode mailbox communication in the cdclk
> > path for platforms that are Display 14 and later.
>
> Nit: display _version_ 14 and later.
>
> >
> > v2: Add check in intel_modeset_calc_cdclk() to avoid cdclk change via
> > modeset for platforms that support squash_crawl sequences(Ville)
> >
> > v3: Add checks for:
> > - scenario where only slow clock is used and cdclk is actually 0
> > (bringing up display).
> > - PLLs are on before looking up the waveform.
> > - Squash and crawl capability checks.(Ville)
> >
> > v4: Rebase
> > - Move checks to be more consistent (Ville)
> > - Add comments (Bala)
> > v5:
> > - Further small changes. Move checks around.
> > - Make if-else better looking (Ville)
> >
> > v6: MTl should not follow PUnit mailbox communication as the rest of
> > gen11+ platforms.(Anusha)
> >
> > Cc: Clint Taylor <Clinton.A.Taylor@intel.com>
> > Cc: Balasubramani Vivekanandan
> <balasubramani.vivekanandan@intel.com>
> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_cdclk.c | 175
> > +++++++++++++++++----
> > 1 file changed, 144 insertions(+), 31 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index 25d01271dc09..6e122d56428c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -1727,37 +1727,75 @@ static bool cdclk_pll_is_unknown(unsigned int
> vco)
> > return vco == ~0;
> > }
> >
> > -static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> > - const struct intel_cdclk_config *cdclk_config,
> > - enum pipe pipe)
> > +static int cdclk_squash_divider(u16 waveform) {
> > + return hweight16(waveform ?: 0xffff); }
> > +
> > +static bool cdclk_compute_crawl_and_squash_midpoint(struct
> drm_i915_private *i915,
> > + const struct
> intel_cdclk_config *old_cdclk_config,
> > + const struct
> intel_cdclk_config *new_cdclk_config,
> > + struct intel_cdclk_config
> *mid_cdclk_config) {
> > + u16 old_waveform, new_waveform, mid_waveform;
> > + int size = 16;
> > + int div = 2;
> > +
> > + /* Return if both Squash and Crawl are not present */
> > + if (!HAS_CDCLK_CRAWL(i915) || !HAS_CDCLK_SQUASH(i915))
> > + return false;
> > +
> > + old_waveform = cdclk_squash_waveform(i915, old_cdclk_config-
> >cdclk);
> > + new_waveform = cdclk_squash_waveform(i915, new_cdclk_config-
> >cdclk);
> > +
> > + /* Return if Squash only or Crawl only is the desired action */
> > + if (old_cdclk_config->vco <= 0 || new_cdclk_config->vco <= 0 ||
>
> We still have "<= 0" checks here. As noted before, the < part can never
> evaluate to true since vco is an unsigned value. I think you meant to update
> this to include a check with your new cdclk_pll_is_unknown() helper?
Argh. No the check here should just be vco==0. For the case ~0 or the signed value, we have it covered in bxt_set_cdclk() where we end up not taking the crawl path.
> Also, the comment above this check says "if squash only or crawl only is the
> desired action" which is what the "==" conditions below cover. But the vco
> 0/unknown checks are technically to ensure we bail out if the desired action
> is to do neither of the two (traditional modeset).
>
> > + old_cdclk_config->vco == new_cdclk_config->vco ||
> > + old_waveform == new_waveform)
> > + return false;
> > +
> > + *mid_cdclk_config = *new_cdclk_config;
> > +
> > + /*
> > + * Populate the mid_cdclk_config accordingly.
> > + * - If moving to a higher cdclk, the desired action is squashing.
> > + * The mid cdclk config should have the new (squash) waveform.
> > + * - If moving to a lower cdclk, the desired action is crawling.
> > + * The mid cdclk config should have the new vco.
> > + */
> > +
> > + if (cdclk_squash_divider(new_waveform) >
> cdclk_squash_divider(old_waveform)) {
> > + mid_cdclk_config->vco = old_cdclk_config->vco;
> > + mid_waveform = new_waveform;
> > + } else {
> > + mid_cdclk_config->vco = new_cdclk_config->vco;
> > + mid_waveform = old_waveform;
> > + }
> > +
> > + mid_cdclk_config->cdclk =
> DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) *
> > + mid_cdclk_config->vco, size
> * div);
> > +
> > + /* make sure the mid clock came out sane */
> > +
> > + drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk <
> > + min(old_cdclk_config->cdclk, new_cdclk_config->cdclk));
> > + drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk >
> > + i915->display.cdclk.max_cdclk_freq);
> > + drm_WARN_ON(&i915->drm, cdclk_squash_waveform(i915,
> mid_cdclk_config->cdclk) !=
> > + mid_waveform);
> > +
> > + return true;
> > +}
> > +
> > +static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
> > + const struct intel_cdclk_config *cdclk_config,
> > + enum pipe pipe)
> > {
> > int cdclk = cdclk_config->cdclk;
> > int vco = cdclk_config->vco;
> > u32 val;
> > u16 waveform;
> > int clock;
> > - int ret;
> > -
> > - /* Inform power controller of upcoming frequency change. */
> > - if (DISPLAY_VER(dev_priv) >= 11)
> > - ret = skl_pcode_request(&dev_priv->uncore,
> SKL_PCODE_CDCLK_CONTROL,
> > - SKL_CDCLK_PREPARE_FOR_CHANGE,
> > - SKL_CDCLK_READY_FOR_CHANGE,
> > - SKL_CDCLK_READY_FOR_CHANGE, 3);
> > - else
> > - /*
> > - * BSpec requires us to wait up to 150usec, but that leads to
> > - * timeouts; the 2ms used here is based on experiment.
> > - */
> > - ret = snb_pcode_write_timeout(&dev_priv->uncore,
> > -
> HSW_PCODE_DE_WRITE_FREQ_REQ,
> > - 0x80000000, 150, 2);
> > - if (ret) {
> > - drm_err(&dev_priv->drm,
> > - "Failed to inform PCU about cdclk change (err %d,
> freq %d)\n",
> > - ret, cdclk);
> > - return;
> > - }
> >
> > if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco
> > 0 && vco > 0 &&
> > !cdclk_pll_is_unknown(dev_priv->display.cdclk.hw.vco)) { @@
> > -1793,11 +1831,62 @@ static void bxt_set_cdclk(struct drm_i915_private
> > *dev_priv,
> >
> > if (pipe != INVALID_PIPE)
> >
> intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv,
> > pipe));
> > +}
> >
> > - if (DISPLAY_VER(dev_priv) >= 11) {
> > +static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> > + const struct intel_cdclk_config *cdclk_config,
> > + enum pipe pipe)
> > +{
> > + struct intel_cdclk_config mid_cdclk_config;
> > + int cdclk = cdclk_config->cdclk;
> > + int ret = 0;
> > +
> > + /*
> > + * Inform power controller of upcoming frequency change.
> > + * Display versions 14 and beyond do not follow the PUnit
> > + * mailbox communication, skip
> > + * this step.
> > + */
> > + if (DISPLAY_VER(dev_priv) >= 14)
> > + /* NOOP */;
> > + else if (DISPLAY_VER(dev_priv) >= 11)
> > + ret = skl_pcode_request(&dev_priv->uncore,
> SKL_PCODE_CDCLK_CONTROL,
> > + SKL_CDCLK_PREPARE_FOR_CHANGE,
> > + SKL_CDCLK_READY_FOR_CHANGE,
> > + SKL_CDCLK_READY_FOR_CHANGE, 3);
> > + else
> > + /*
> > + * BSpec requires us to wait up to 150usec, but that leads to
> > + * timeouts; the 2ms used here is based on experiment.
> > + */
> > + ret = snb_pcode_write_timeout(&dev_priv->uncore,
> > +
> HSW_PCODE_DE_WRITE_FREQ_REQ,
> > + 0x80000000, 150, 2);
> > +
> > + if (ret) {
> > + drm_err(&dev_priv->drm,
> > + "Failed to inform PCU about cdclk change (err %d,
> freq %d)\n",
> > + ret, cdclk);
> > + return;
> > + }
> > +
> > + if (cdclk_compute_crawl_and_squash_midpoint(dev_priv,
> &dev_priv->display.cdclk.hw,
> > + cdclk_config,
> &mid_cdclk_config)) {
> > + _bxt_set_cdclk(dev_priv, &mid_cdclk_config, pipe);
> > + _bxt_set_cdclk(dev_priv, cdclk_config, pipe);
> > + } else {
> > + _bxt_set_cdclk(dev_priv, cdclk_config, pipe);
> > + }
> > +
> > + if (DISPLAY_VER(dev_priv) >= 14)
> > + /*
> > + * NOOP - No Pcode communication needed for
> > + * Display versions 14 and beyond
> > + */;
> > + else if (DISPLAY_VER(dev_priv) >= 11)
> > ret = snb_pcode_write(&dev_priv->uncore,
> SKL_PCODE_CDCLK_CONTROL,
> > cdclk_config->voltage_level);
> > - } else {
> > + else
> > /*
> > * The timeout isn't specified, the 2ms used here is based on
> > * experiment.
> > @@ -1808,7 +1897,6 @@ static void bxt_set_cdclk(struct drm_i915_private
> *dev_priv,
> >
> HSW_PCODE_DE_WRITE_FREQ_REQ,
> > cdclk_config->voltage_level,
> > 150, 2);
> > - }
> >
> > if (ret) {
> > drm_err(&dev_priv->drm,
> > @@ -1965,6 +2053,26 @@ void intel_cdclk_uninit_hw(struct
> drm_i915_private *i915)
> > skl_cdclk_uninit_hw(i915);
> > }
> >
> > +static bool intel_cdclk_can_crawl_and_squash(struct drm_i915_private
> *i915,
> > + const struct intel_cdclk_config *a,
> > + const struct intel_cdclk_config *b)
>
> Do we need a check for PLL unknown here? We don't want to decide that we
> can skip a modeset if the PLL is unknown, right?
This is called only from atomic_check() part of the code. The check is part of the crawl check in bxt_set_cdclk() which comes directly from bxt_sanitize code path where it is affected.
Anusha
>
> Matt
>
> > +{
> > + u16 old_waveform;
> > + u16 new_waveform;
> > +
> > + if (a->vco == 0 || b->vco == 0)
> > + return false;
> > +
> > + if (!HAS_CDCLK_CRAWL(i915) || !HAS_CDCLK_SQUASH(i915))
> > + return false;
> > +
> > + old_waveform = cdclk_squash_waveform(i915, a->cdclk);
> > + new_waveform = cdclk_squash_waveform(i915, b->cdclk);
> > +
> > + return a->vco != b->vco &&
> > + old_waveform != new_waveform; }
> > +
> > static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv,
> > const struct intel_cdclk_config *a,
> > const struct intel_cdclk_config *b) @@ -
> 2771,9 +2879,14 @@ int
> > intel_modeset_calc_cdclk(struct intel_atomic_state *state)
> > pipe = INVALID_PIPE;
> > }
> >
> > - if (intel_cdclk_can_squash(dev_priv,
> > - &old_cdclk_state->actual,
> > - &new_cdclk_state->actual)) {
> > + if (intel_cdclk_can_crawl_and_squash(dev_priv,
> > + &old_cdclk_state->actual,
> > + &new_cdclk_state->actual)) {
> > + drm_dbg_kms(&dev_priv->drm,
> > + "Can change cdclk via crawling and squashing\n");
> > + } else if (intel_cdclk_can_squash(dev_priv,
> > + &old_cdclk_state->actual,
> > + &new_cdclk_state->actual)) {
> > drm_dbg_kms(&dev_priv->drm,
> > "Can change cdclk via squashing\n");
> > } else if (intel_cdclk_can_crawl(dev_priv,
> > --
> > 2.25.1
> >
>
> --
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/display: Add missing checks for cdclk crawling
2022-11-16 14:50 [Intel-gfx] [PATCH 1/3] drm/i915/display: Add missing checks for cdclk crawling Anusha Srivatsa
2022-11-16 14:50 ` [Intel-gfx] [PATCH 2/3] drm/i915/display: Do both crawl and squash when changing cdclk Anusha Srivatsa
2022-11-16 14:50 ` [Intel-gfx] [PATCH 3/3] drm/i915/display: Add CDCLK Support for MTL Anusha Srivatsa
@ 2022-11-16 21:21 ` Patchwork
2022-11-16 21:58 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-11-17 7:55 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
4 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2022-11-16 21:21 UTC (permalink / raw)
To: Srivatsa, Anusha; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/i915/display: Add missing checks for cdclk crawling
URL : https://patchwork.freedesktop.org/series/110970/
State : warning
== Summary ==
Error: dim checkpatch failed
8b43fdea884d drm/i915/display: Add missing checks for cdclk crawling
0058d40d8134 drm/i915/display: Do both crawl and squash when changing cdclk
-:61: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#61: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:1736:
+ const struct intel_cdclk_config *old_cdclk_config,
-:62: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#62: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:1737:
+ const struct intel_cdclk_config *new_cdclk_config,
-:170: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional statements (8, 26)
#170: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:1850:
+ if (DISPLAY_VER(dev_priv) >= 14)
+ /* NOOP */;
-:201: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional statements (8, 19)
#201: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:1881:
+ if (DISPLAY_VER(dev_priv) >= 14)
[...]
+ */;
total: 0 errors, 4 warnings, 0 checks, 214 lines checked
b56ac994c40f drm/i915/display: Add CDCLK Support for MTL
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/display: Add missing checks for cdclk crawling
2022-11-16 14:50 [Intel-gfx] [PATCH 1/3] drm/i915/display: Add missing checks for cdclk crawling Anusha Srivatsa
` (2 preceding siblings ...)
2022-11-16 21:21 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/display: Add missing checks for cdclk crawling Patchwork
@ 2022-11-16 21:58 ` Patchwork
2022-11-17 7:55 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
4 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2022-11-16 21:58 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 8812 bytes --]
== Series Details ==
Series: series starting with [1/3] drm/i915/display: Add missing checks for cdclk crawling
URL : https://patchwork.freedesktop.org/series/110970/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12390 -> Patchwork_110970v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/index.html
Participating hosts (41 -> 40)
------------------------------
Additional (1): fi-kbl-soraka
Missing (2): bat-kbl-2 bat-jsl-3
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_110970v1:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@migrate:
- {bat-dg2-11}: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/bat-dg2-11/igt@i915_selftest@live@migrate.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/bat-dg2-11/igt@i915_selftest@live@migrate.html
Known issues
------------
Here are the changes found in Patchwork_110970v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_gttfill@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271]) +9 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/fi-kbl-soraka/igt@gem_exec_gttfill@basic.html
- fi-pnv-d510: [PASS][4] -> [FAIL][5] ([i915#7229])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/fi-pnv-d510/igt@gem_exec_gttfill@basic.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/fi-pnv-d510/igt@gem_exec_gttfill@basic.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#2190])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613]) +3 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/fi-kbl-soraka/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@parallel-random-engines:
- bat-adlp-4: NOTRUN -> [SKIP][8] ([i915#4613]) +3 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/bat-adlp-4/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@i915_pm_rps@basic-api:
- bat-adlp-4: NOTRUN -> [SKIP][9] ([i915#6621])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/bat-adlp-4/igt@i915_pm_rps@basic-api.html
* igt@i915_selftest@live@gem_contexts:
- fi-kbl-soraka: NOTRUN -> [INCOMPLETE][10] ([i915#7099])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/fi-kbl-soraka/igt@i915_selftest@live@gem_contexts.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][11] ([i915#1886])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/fi-hsw-4770/igt@kms_chamelium@common-hpd-after-suspend.html
- bat-adlp-4: NOTRUN -> [SKIP][13] ([fdo#111827])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/bat-adlp-4/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-soraka: NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827]) +7 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/fi-kbl-soraka/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-adlp-4: NOTRUN -> [SKIP][15] ([i915#3546])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/bat-adlp-4/igt@kms_pipe_crc_basic@suspend-read-crc.html
* igt@prime_vgem@basic-userptr:
- bat-adlp-4: NOTRUN -> [SKIP][16] ([fdo#109295] / [i915#3301] / [i915#3708])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/bat-adlp-4/igt@prime_vgem@basic-userptr.html
* igt@prime_vgem@basic-write:
- bat-adlp-4: NOTRUN -> [SKIP][17] ([fdo#109295] / [i915#3291] / [i915#3708]) +2 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/bat-adlp-4/igt@prime_vgem@basic-write.html
#### Possible fixes ####
* igt@i915_module_load@reload:
- {bat-rpls-2}: [INCOMPLETE][18] ([i915#6434]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/bat-rpls-2/igt@i915_module_load@reload.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/bat-rpls-2/igt@i915_module_load@reload.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- bat-adlp-4: [DMESG-WARN][20] ([i915#7077]) -> [PASS][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/bat-adlp-4/igt@i915_pm_rpm@basic-pci-d3-state.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/bat-adlp-4/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770: [INCOMPLETE][22] ([i915#4785]) -> [PASS][23]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
* igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-2:
- {bat-dg2-11}: [FAIL][24] -> [PASS][25]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-2.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-2.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6434]: https://gitlab.freedesktop.org/drm/intel/issues/6434
[i915#6559]: https://gitlab.freedesktop.org/drm/intel/issues/6559
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
[i915#7077]: https://gitlab.freedesktop.org/drm/intel/issues/7077
[i915#7099]: https://gitlab.freedesktop.org/drm/intel/issues/7099
[i915#7229]: https://gitlab.freedesktop.org/drm/intel/issues/7229
[i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
Build changes
-------------
* Linux: CI_DRM_12390 -> Patchwork_110970v1
CI-20190529: 20190529
CI_DRM_12390: b7288a4715c68710aadbd63112b699356e8a2b65 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7062: 6539ea5fe17fce683133c45f07fac316593ee1f7 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_110970v1: b7288a4715c68710aadbd63112b699356e8a2b65 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
6bbcf57779d8 drm/i915/display: Add CDCLK Support for MTL
87f0732c4080 drm/i915/display: Do both crawl and squash when changing cdclk
5454c80bd7dd drm/i915/display: Add missing checks for cdclk crawling
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/index.html
[-- Attachment #2: Type: text/html, Size: 9750 bytes --]
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/display: Add missing checks for cdclk crawling
2022-11-16 14:50 [Intel-gfx] [PATCH 1/3] drm/i915/display: Add missing checks for cdclk crawling Anusha Srivatsa
` (3 preceding siblings ...)
2022-11-16 21:58 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2022-11-17 7:55 ` Patchwork
4 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2022-11-17 7:55 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 26184 bytes --]
== Series Details ==
Series: series starting with [1/3] drm/i915/display: Add missing checks for cdclk crawling
URL : https://patchwork.freedesktop.org/series/110970/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12390_full -> Patchwork_110970v1_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in Patchwork_110970v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@feature_discovery@display-2x:
- shard-tglb: NOTRUN -> [SKIP][1] ([i915#1839])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-tglb7/igt@feature_discovery@display-2x.html
* igt@gem_create@create-massive:
- shard-skl: NOTRUN -> [DMESG-WARN][2] ([i915#4991])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-skl2/igt@gem_create@create-massive.html
* igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-iclb: [PASS][3] -> [SKIP][4] ([i915#4525])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-iclb1/igt@gem_exec_balancer@parallel-keep-in-fence.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-iclb6/igt@gem_exec_balancer@parallel-keep-in-fence.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][5] ([i915#2842])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-iclb1/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][6] -> [SKIP][7] ([i915#2190])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-tglb3/igt@gem_huc_copy@huc-copy.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-tglb6/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@random-engines:
- shard-skl: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4613]) +3 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-skl1/igt@gem_lmem_swapping@random-engines.html
* igt@gem_userptr_blits@unsync-overlap:
- shard-skl: NOTRUN -> [SKIP][9] ([fdo#109271]) +185 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-skl2/igt@gem_userptr_blits@unsync-overlap.html
* igt@gem_userptr_blits@vma-merge:
- shard-skl: NOTRUN -> [FAIL][10] ([i915#3318])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-skl1/igt@gem_userptr_blits@vma-merge.html
* igt@gen7_exec_parse@chained-batch:
- shard-tglb: NOTRUN -> [SKIP][11] ([fdo#109289]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-tglb7/igt@gen7_exec_parse@chained-batch.html
* igt@gen9_exec_parse@allowed-single:
- shard-apl: [PASS][12] -> [DMESG-WARN][13] ([i915#5566] / [i915#716])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-apl7/igt@gen9_exec_parse@allowed-single.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-apl2/igt@gen9_exec_parse@allowed-single.html
* igt@i915_module_load@load:
- shard-skl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#6227])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-skl2/igt@i915_module_load@load.html
* igt@i915_pm_dc@dc6-dpms:
- shard-tglb: NOTRUN -> [FAIL][15] ([i915#3989] / [i915#454])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-tglb7/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_dc@dc6-psr:
- shard-skl: NOTRUN -> [FAIL][16] ([i915#3989] / [i915#454])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-skl4/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_rc6_residency@rc6-idle@vcs0:
- shard-skl: NOTRUN -> [WARN][17] ([i915#1804])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-skl3/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
* igt@i915_pm_rpm@system-suspend:
- shard-tglb: [PASS][18] -> [INCOMPLETE][19] ([i915#2411])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-tglb8/igt@i915_pm_rpm@system-suspend.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-tglb8/igt@i915_pm_rpm@system-suspend.html
* igt@i915_selftest@live@gt_heartbeat:
- shard-skl: [PASS][20] -> [DMESG-FAIL][21] ([i915#5334])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl7/igt@i915_selftest@live@gt_heartbeat.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-skl7/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-tglb: NOTRUN -> [SKIP][22] ([fdo#111615])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-tglb7/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_big_joiner@invalid-modeset:
- shard-tglb: NOTRUN -> [SKIP][23] ([i915#2705])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-tglb7/igt@kms_big_joiner@invalid-modeset.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#3886]) +6 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-skl2/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-bad-aux-stride-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][25] ([fdo#111615] / [i915#3689])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-tglb7/igt@kms_ccs@pipe-b-bad-aux-stride-yf_tiled_ccs.html
* igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][26] ([i915#3689]) +1 similar issue
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-tglb7/igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_ccs.html
* igt@kms_chamelium@dp-hpd-storm-disable:
- shard-tglb: NOTRUN -> [SKIP][27] ([fdo#109284] / [fdo#111827]) +1 similar issue
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-tglb7/igt@kms_chamelium@dp-hpd-storm-disable.html
* igt@kms_color_chamelium@ctm-limited-range:
- shard-skl: NOTRUN -> [SKIP][28] ([fdo#109271] / [fdo#111827]) +8 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-skl1/igt@kms_color_chamelium@ctm-limited-range.html
* igt@kms_cursor_crc@cursor-rapid-movement-max-size:
- shard-tglb: NOTRUN -> [SKIP][29] ([i915#3555])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-tglb7/igt@kms_cursor_crc@cursor-rapid-movement-max-size.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-glk: [PASS][30] -> [FAIL][31] ([i915#72])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-glk6/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-glk5/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@cursor-vs-flip@legacy:
- shard-skl: [PASS][32] -> [DMESG-WARN][33] ([i915#1982]) +1 similar issue
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl5/igt@kms_cursor_legacy@cursor-vs-flip@legacy.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-skl1/igt@kms_cursor_legacy@cursor-vs-flip@legacy.html
* igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic:
- shard-skl: [PASS][34] -> [FAIL][35] ([i915#2346])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-skl5/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size:
- shard-apl: [PASS][36] -> [FAIL][37] ([i915#2346])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-apl2/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-apl8/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
- shard-glk: [PASS][38] -> [FAIL][39] ([i915#2346]) +1 similar issue
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-glk7/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-glk3/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
* igt@kms_display_modes@extended-mode-basic:
- shard-tglb: NOTRUN -> [SKIP][40] ([fdo#109274])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-tglb7/igt@kms_display_modes@extended-mode-basic.html
* igt@kms_fbcon_fbt@fbc:
- shard-tglb: NOTRUN -> [FAIL][41] ([i915#4767])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-tglb7/igt@kms_fbcon_fbt@fbc.html
* igt@kms_flip@flip-vs-expired-vblank@b-edp1:
- shard-skl: NOTRUN -> [FAIL][42] ([i915#79])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-skl1/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][43] ([i915#6375])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode:
- shard-iclb: NOTRUN -> [SKIP][44] ([i915#2587] / [i915#2672]) +2 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-iclb8/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-valid-mode:
- shard-tglb: NOTRUN -> [SKIP][45] ([i915#2587] / [i915#2672])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-tglb7/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][46] ([i915#3555]) +1 similar issue
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][47] ([i915#2672]) +4 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode:
- shard-iclb: NOTRUN -> [SKIP][48] ([i915#2672] / [i915#3555])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-iclb5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
- shard-tglb: NOTRUN -> [SKIP][49] ([fdo#109280] / [fdo#111825]) +1 similar issue
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite:
- shard-glk: [PASS][50] -> [FAIL][51] ([i915#2546])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-glk3/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-glk8/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc:
- shard-tglb: NOTRUN -> [SKIP][52] ([i915#6497]) +2 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc.html
* igt@kms_plane_alpha_blend@alpha-basic@pipe-a-edp-1:
- shard-skl: NOTRUN -> [FAIL][53] ([i915#4573]) +4 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-skl4/igt@kms_plane_alpha_blend@alpha-basic@pipe-a-edp-1.html
* igt@kms_plane_alpha_blend@alpha-basic@pipe-c-edp-1:
- shard-skl: NOTRUN -> [DMESG-FAIL][54] ([IGT#6])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-skl4/igt@kms_plane_alpha_blend@alpha-basic@pipe-c-edp-1.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-sf:
- shard-skl: NOTRUN -> [SKIP][55] ([fdo#109271] / [i915#658]) +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-skl2/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
- shard-tglb: NOTRUN -> [SKIP][56] ([i915#2920])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-tglb7/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
* igt@kms_psr2_su@page_flip-p010:
- shard-iclb: NOTRUN -> [SKIP][57] ([fdo#109642] / [fdo#111068] / [i915#658])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-iclb3/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_psr@psr2_cursor_plane_onoff:
- shard-iclb: [PASS][58] -> [SKIP][59] ([fdo#109441])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-iclb3/igt@kms_psr@psr2_cursor_plane_onoff.html
* igt@kms_psr@psr2_sprite_plane_onoff:
- shard-tglb: NOTRUN -> [FAIL][60] ([i915#132] / [i915#3467])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-tglb7/igt@kms_psr@psr2_sprite_plane_onoff.html
* igt@perf@polling:
- shard-skl: NOTRUN -> [FAIL][61] ([i915#1542])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-skl2/igt@perf@polling.html
* igt@sysfs_clients@fair-3:
- shard-skl: NOTRUN -> [SKIP][62] ([fdo#109271] / [i915#2994]) +1 similar issue
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-skl7/igt@sysfs_clients@fair-3.html
#### Possible fixes ####
* igt@gem_exec_balancer@parallel-contexts:
- shard-iclb: [SKIP][63] ([i915#4525]) -> [PASS][64] +1 similar issue
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-iclb8/igt@gem_exec_balancer@parallel-contexts.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-iclb1/igt@gem_exec_balancer@parallel-contexts.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [FAIL][65] ([i915#2842]) -> [PASS][66] +1 similar issue
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-apl2/igt@gem_exec_fair@basic-none-solo@rcs0.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-apl8/igt@gem_exec_fair@basic-none-solo@rcs0.html
- shard-glk: [FAIL][67] ([i915#2842]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-glk2/igt@gem_exec_fair@basic-none-solo@rcs0.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-glk5/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@i915_pm_rps@engine-order:
- shard-tglb: [FAIL][69] -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-tglb8/igt@i915_pm_rps@engine-order.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-tglb7/igt@i915_pm_rps@engine-order.html
* igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_rc_ccs:
- shard-tglb: [INCOMPLETE][71] -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-tglb8/igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_rc_ccs.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-tglb7/igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_rc_ccs.html
* igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling@pipe-a-default-mode:
- shard-iclb: [SKIP][73] ([i915#3555]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling@pipe-a-default-mode.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-iclb3/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling@pipe-a-default-mode.html
* igt@kms_plane_cursor@viewport@pipe-b-edp-1-size-256:
- shard-skl: [INCOMPLETE][75] -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-skl2/igt@kms_plane_cursor@viewport@pipe-b-edp-1-size-256.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-skl6/igt@kms_plane_cursor@viewport@pipe-b-edp-1-size-256.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1:
- shard-iclb: [SKIP][77] ([i915#5235]) -> [PASS][78] +2 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-iclb2/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-iclb3/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1.html
* igt@kms_psr@psr2_cursor_blt:
- shard-iclb: [SKIP][79] ([fdo#109441]) -> [PASS][80] +2 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-iclb1/igt@kms_psr@psr2_cursor_blt.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-iclb: [SKIP][81] ([i915#5519]) -> [PASS][82]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-iclb1/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-iclb2/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
#### Warnings ####
* igt@gem_exec_balancer@parallel-ordering:
- shard-iclb: [SKIP][83] ([i915#4525]) -> [FAIL][84] ([i915#6117])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-iclb8/igt@gem_exec_balancer@parallel-ordering.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-iclb1/igt@gem_exec_balancer@parallel-ordering.html
* igt@gem_pwrite@basic-exhaustion:
- shard-glk: [INCOMPLETE][85] ([i915#7248]) -> [WARN][86] ([i915#2658])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-glk7/igt@gem_pwrite@basic-exhaustion.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-glk2/igt@gem_pwrite@basic-exhaustion.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf:
- shard-iclb: [SKIP][87] ([i915#2920]) -> [SKIP][88] ([i915#658])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-iclb2/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-iclb5/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@overlay-plane-update-continuous-sf:
- shard-iclb: [SKIP][89] ([fdo#111068] / [i915#658]) -> [SKIP][90] ([i915#2920])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-iclb1/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
- shard-iclb: [SKIP][91] ([i915#2920]) -> [SKIP][92] ([fdo#111068] / [i915#658])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-iclb7/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
* igt@runner@aborted:
- shard-apl: ([FAIL][93], [FAIL][94]) ([i915#3002] / [i915#4312]) -> ([FAIL][95], [FAIL][96], [FAIL][97]) ([fdo#109271] / [i915#3002] / [i915#4312])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-apl2/igt@runner@aborted.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12390/shard-apl7/igt@runner@aborted.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-apl2/igt@runner@aborted.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-apl8/igt@runner@aborted.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/shard-apl2/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#6]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/6
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3467]: https://gitlab.freedesktop.org/drm/intel/issues/3467
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4573]: https://gitlab.freedesktop.org/drm/intel/issues/4573
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
[i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
[i915#6375]: https://gitlab.freedesktop.org/drm/intel/issues/6375
[i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
[i915#7248]: https://gitlab.freedesktop.org/drm/intel/issues/7248
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Build changes
-------------
* Linux: CI_DRM_12390 -> Patchwork_110970v1
CI-20190529: 20190529
CI_DRM_12390: b7288a4715c68710aadbd63112b699356e8a2b65 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7062: 6539ea5fe17fce683133c45f07fac316593ee1f7 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_110970v1: b7288a4715c68710aadbd63112b699356e8a2b65 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110970v1/index.html
[-- Attachment #2: Type: text/html, Size: 30883 bytes --]
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2022-11-17 7:55 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-11-16 14:50 [Intel-gfx] [PATCH 1/3] drm/i915/display: Add missing checks for cdclk crawling Anusha Srivatsa
2022-11-16 14:50 ` [Intel-gfx] [PATCH 2/3] drm/i915/display: Do both crawl and squash when changing cdclk Anusha Srivatsa
2022-11-16 18:43 ` Matt Roper
2022-11-16 19:55 ` Srivatsa, Anusha
2022-11-16 14:50 ` [Intel-gfx] [PATCH 3/3] drm/i915/display: Add CDCLK Support for MTL Anusha Srivatsa
2022-11-16 21:21 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/display: Add missing checks for cdclk crawling Patchwork
2022-11-16 21:58 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-11-17 7:55 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).