* [Intel-gfx] [PATCH 1/3] drm/i915/psr: move PSR debugfs to intel_psr.c
@ 2023-03-17 13:41 Jani Nikula
2023-03-17 13:41 ` [Intel-gfx] [PATCH 2/3] drm/i915/psr: switch PSR debugfs to struct intel_connector Jani Nikula
` (7 more replies)
0 siblings, 8 replies; 12+ messages in thread
From: Jani Nikula @ 2023-03-17 13:41 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Move the debugfs next to the implementation.
Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../drm/i915/display/intel_display_debugfs.c | 288 +----------------
drivers/gpu/drm/i915/display/intel_psr.c | 302 ++++++++++++++++++
drivers/gpu/drm/i915/display/intel_psr.h | 3 +
3 files changed, 308 insertions(+), 285 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 65585f19c6c8..4d8ebf3fed11 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -142,269 +142,6 @@ static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
return 0;
}
-static int i915_psr_sink_status_show(struct seq_file *m, void *data)
-{
- u8 val;
- static const char * const sink_status[] = {
- "inactive",
- "transition to active, capture and display",
- "active, display from RFB",
- "active, capture and display on sink device timings",
- "transition to inactive, capture and display, timing re-sync",
- "reserved",
- "reserved",
- "sink internal error",
- };
- struct drm_connector *connector = m->private;
- struct intel_dp *intel_dp =
- intel_attached_dp(to_intel_connector(connector));
- int ret;
-
- if (!CAN_PSR(intel_dp)) {
- seq_puts(m, "PSR Unsupported\n");
- return -ENODEV;
- }
-
- if (connector->status != connector_status_connected)
- return -ENODEV;
-
- ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val);
-
- if (ret == 1) {
- const char *str = "unknown";
-
- val &= DP_PSR_SINK_STATE_MASK;
- if (val < ARRAY_SIZE(sink_status))
- str = sink_status[val];
- seq_printf(m, "Sink PSR status: 0x%x [%s]\n", val, str);
- } else {
- return ret;
- }
-
- return 0;
-}
-DEFINE_SHOW_ATTRIBUTE(i915_psr_sink_status);
-
-static void
-psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- const char *status = "unknown";
- u32 val, status_val;
-
- if (intel_dp->psr.psr2_enabled) {
- static const char * const live_status[] = {
- "IDLE",
- "CAPTURE",
- "CAPTURE_FS",
- "SLEEP",
- "BUFON_FW",
- "ML_UP",
- "SU_STANDBY",
- "FAST_SLEEP",
- "DEEP_SLEEP",
- "BUF_ON",
- "TG_ON"
- };
- val = intel_de_read(dev_priv,
- EDP_PSR2_STATUS(intel_dp->psr.transcoder));
- status_val = REG_FIELD_GET(EDP_PSR2_STATUS_STATE_MASK, val);
- if (status_val < ARRAY_SIZE(live_status))
- status = live_status[status_val];
- } else {
- static const char * const live_status[] = {
- "IDLE",
- "SRDONACK",
- "SRDENT",
- "BUFOFF",
- "BUFON",
- "AUXACK",
- "SRDOFFACK",
- "SRDENT_ON",
- };
- val = intel_de_read(dev_priv,
- EDP_PSR_STATUS(intel_dp->psr.transcoder));
- status_val = (val & EDP_PSR_STATUS_STATE_MASK) >>
- EDP_PSR_STATUS_STATE_SHIFT;
- if (status_val < ARRAY_SIZE(live_status))
- status = live_status[status_val];
- }
-
- seq_printf(m, "Source PSR status: %s [0x%08x]\n", status, val);
-}
-
-static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct intel_psr *psr = &intel_dp->psr;
- intel_wakeref_t wakeref;
- const char *status;
- bool enabled;
- u32 val;
-
- seq_printf(m, "Sink support: %s", str_yes_no(psr->sink_support));
- if (psr->sink_support)
- seq_printf(m, " [0x%02x]", intel_dp->psr_dpcd[0]);
- seq_puts(m, "\n");
-
- if (!psr->sink_support)
- return 0;
-
- wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
- mutex_lock(&psr->lock);
-
- if (psr->enabled)
- status = psr->psr2_enabled ? "PSR2 enabled" : "PSR1 enabled";
- else
- status = "disabled";
- seq_printf(m, "PSR mode: %s\n", status);
-
- if (!psr->enabled) {
- seq_printf(m, "PSR sink not reliable: %s\n",
- str_yes_no(psr->sink_not_reliable));
-
- goto unlock;
- }
-
- if (psr->psr2_enabled) {
- val = intel_de_read(dev_priv,
- EDP_PSR2_CTL(intel_dp->psr.transcoder));
- enabled = val & EDP_PSR2_ENABLE;
- } else {
- val = intel_de_read(dev_priv,
- EDP_PSR_CTL(intel_dp->psr.transcoder));
- enabled = val & EDP_PSR_ENABLE;
- }
- seq_printf(m, "Source PSR ctl: %s [0x%08x]\n",
- str_enabled_disabled(enabled), val);
- psr_source_status(intel_dp, m);
- seq_printf(m, "Busy frontbuffer bits: 0x%08x\n",
- psr->busy_frontbuffer_bits);
-
- /*
- * SKL+ Perf counter is reset to 0 everytime DC state is entered
- */
- if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
- val = intel_de_read(dev_priv,
- EDP_PSR_PERF_CNT(intel_dp->psr.transcoder));
- val &= EDP_PSR_PERF_CNT_MASK;
- seq_printf(m, "Performance counter: %u\n", val);
- }
-
- if (psr->debug & I915_PSR_DEBUG_IRQ) {
- seq_printf(m, "Last attempted entry at: %lld\n",
- psr->last_entry_attempt);
- seq_printf(m, "Last exit at: %lld\n", psr->last_exit);
- }
-
- if (psr->psr2_enabled) {
- u32 su_frames_val[3];
- int frame;
-
- /*
- * Reading all 3 registers before hand to minimize crossing a
- * frame boundary between register reads
- */
- for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame += 3) {
- val = intel_de_read(dev_priv,
- PSR2_SU_STATUS(intel_dp->psr.transcoder, frame));
- su_frames_val[frame / 3] = val;
- }
-
- seq_puts(m, "Frame:\tPSR2 SU blocks:\n");
-
- for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame++) {
- u32 su_blocks;
-
- su_blocks = su_frames_val[frame / 3] &
- PSR2_SU_STATUS_MASK(frame);
- su_blocks = su_blocks >> PSR2_SU_STATUS_SHIFT(frame);
- seq_printf(m, "%d\t%d\n", frame, su_blocks);
- }
-
- seq_printf(m, "PSR2 selective fetch: %s\n",
- str_enabled_disabled(psr->psr2_sel_fetch_enabled));
- }
-
-unlock:
- mutex_unlock(&psr->lock);
- intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
-
- return 0;
-}
-
-static int i915_edp_psr_status(struct seq_file *m, void *data)
-{
- struct drm_i915_private *dev_priv = node_to_i915(m->private);
- struct intel_dp *intel_dp = NULL;
- struct intel_encoder *encoder;
-
- if (!HAS_PSR(dev_priv))
- return -ENODEV;
-
- /* Find the first EDP which supports PSR */
- for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
- intel_dp = enc_to_intel_dp(encoder);
- break;
- }
-
- if (!intel_dp)
- return -ENODEV;
-
- return intel_psr_status(m, intel_dp);
-}
-
-static int
-i915_edp_psr_debug_set(void *data, u64 val)
-{
- struct drm_i915_private *dev_priv = data;
- struct intel_encoder *encoder;
- intel_wakeref_t wakeref;
- int ret = -ENODEV;
-
- if (!HAS_PSR(dev_priv))
- return ret;
-
- for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
- struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-
- drm_dbg_kms(&dev_priv->drm, "Setting PSR debug to %llx\n", val);
-
- wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
-
- // TODO: split to each transcoder's PSR debug state
- ret = intel_psr_debug_set(intel_dp, val);
-
- intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
- }
-
- return ret;
-}
-
-static int
-i915_edp_psr_debug_get(void *data, u64 *val)
-{
- struct drm_i915_private *dev_priv = data;
- struct intel_encoder *encoder;
-
- if (!HAS_PSR(dev_priv))
- return -ENODEV;
-
- for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
- struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-
- // TODO: split to each transcoder's PSR debug state
- *val = READ_ONCE(intel_dp->psr.debug);
- return 0;
- }
-
- return -ENODEV;
-}
-
-DEFINE_SIMPLE_ATTRIBUTE(i915_edp_psr_debug_fops,
- i915_edp_psr_debug_get, i915_edp_psr_debug_set,
- "%llu\n");
-
static int i915_power_domain_info(struct seq_file *m, void *unused)
{
struct drm_i915_private *i915 = node_to_i915(m->private);
@@ -1320,7 +1057,6 @@ static const struct drm_info_list intel_display_debugfs_list[] = {
{"i915_opregion", i915_opregion, 0},
{"i915_vbt", i915_vbt, 0},
{"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
- {"i915_edp_psr_status", i915_edp_psr_status, 0},
{"i915_power_domain_info", i915_power_domain_info, 0},
{"i915_display_info", i915_display_info, 0},
{"i915_shared_dplls_info", i915_shared_dplls_info, 0},
@@ -1337,7 +1073,6 @@ static const struct {
{"i915_dp_test_data", &i915_displayport_test_data_fops},
{"i915_dp_test_type", &i915_displayport_test_type_fops},
{"i915_dp_test_active", &i915_displayport_test_active_fops},
- {"i915_edp_psr_debug", &i915_edp_psr_debug_fops},
};
void intel_display_debugfs_register(struct drm_i915_private *i915)
@@ -1361,6 +1096,7 @@ void intel_display_debugfs_register(struct drm_i915_private *i915)
intel_dmc_debugfs_register(i915);
intel_fbc_debugfs_register(i915);
intel_hpd_debugfs_register(i915);
+ intel_psr_debugfs_register(i915);
intel_wm_debugfs_register(i915);
}
@@ -1413,16 +1149,6 @@ static int i915_hdcp_sink_capability_show(struct seq_file *m, void *data)
}
DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability);
-static int i915_psr_status_show(struct seq_file *m, void *data)
-{
- struct drm_connector *connector = m->private;
- struct intel_dp *intel_dp =
- intel_attached_dp(to_intel_connector(connector));
-
- return intel_psr_status(m, intel_dp);
-}
-DEFINE_SHOW_ATTRIBUTE(i915_psr_status);
-
static int i915_lpsp_capability_show(struct seq_file *m, void *data)
{
struct drm_connector *connector = m->private;
@@ -1675,19 +1401,11 @@ void intel_connector_debugfs_add(struct intel_connector *intel_connector)
return;
intel_drrs_connector_debugfs_add(intel_connector);
+ intel_psr_connector_debugfs_add(intel_connector);
- if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
+ if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
debugfs_create_file("i915_panel_timings", S_IRUGO, root,
connector, &i915_panel_fops);
- debugfs_create_file("i915_psr_sink_status", S_IRUGO, root,
- connector, &i915_psr_sink_status_fops);
- }
-
- if (HAS_PSR(dev_priv) &&
- connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
- debugfs_create_file("i915_psr_status", 0444, root,
- connector, &i915_psr_status_fops);
- }
if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 44610b20cd29..9d3205d99b54 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2644,3 +2644,305 @@ void intel_psr_unlock(const struct intel_crtc_state *crtc_state)
break;
}
}
+
+static void
+psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ const char *status = "unknown";
+ u32 val, status_val;
+
+ if (intel_dp->psr.psr2_enabled) {
+ static const char * const live_status[] = {
+ "IDLE",
+ "CAPTURE",
+ "CAPTURE_FS",
+ "SLEEP",
+ "BUFON_FW",
+ "ML_UP",
+ "SU_STANDBY",
+ "FAST_SLEEP",
+ "DEEP_SLEEP",
+ "BUF_ON",
+ "TG_ON"
+ };
+ val = intel_de_read(dev_priv,
+ EDP_PSR2_STATUS(intel_dp->psr.transcoder));
+ status_val = REG_FIELD_GET(EDP_PSR2_STATUS_STATE_MASK, val);
+ if (status_val < ARRAY_SIZE(live_status))
+ status = live_status[status_val];
+ } else {
+ static const char * const live_status[] = {
+ "IDLE",
+ "SRDONACK",
+ "SRDENT",
+ "BUFOFF",
+ "BUFON",
+ "AUXACK",
+ "SRDOFFACK",
+ "SRDENT_ON",
+ };
+ val = intel_de_read(dev_priv,
+ EDP_PSR_STATUS(intel_dp->psr.transcoder));
+ status_val = (val & EDP_PSR_STATUS_STATE_MASK) >>
+ EDP_PSR_STATUS_STATE_SHIFT;
+ if (status_val < ARRAY_SIZE(live_status))
+ status = live_status[status_val];
+ }
+
+ seq_printf(m, "Source PSR status: %s [0x%08x]\n", status, val);
+}
+
+static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_psr *psr = &intel_dp->psr;
+ intel_wakeref_t wakeref;
+ const char *status;
+ bool enabled;
+ u32 val;
+
+ seq_printf(m, "Sink support: %s", str_yes_no(psr->sink_support));
+ if (psr->sink_support)
+ seq_printf(m, " [0x%02x]", intel_dp->psr_dpcd[0]);
+ seq_puts(m, "\n");
+
+ if (!psr->sink_support)
+ return 0;
+
+ wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
+ mutex_lock(&psr->lock);
+
+ if (psr->enabled)
+ status = psr->psr2_enabled ? "PSR2 enabled" : "PSR1 enabled";
+ else
+ status = "disabled";
+ seq_printf(m, "PSR mode: %s\n", status);
+
+ if (!psr->enabled) {
+ seq_printf(m, "PSR sink not reliable: %s\n",
+ str_yes_no(psr->sink_not_reliable));
+
+ goto unlock;
+ }
+
+ if (psr->psr2_enabled) {
+ val = intel_de_read(dev_priv,
+ EDP_PSR2_CTL(intel_dp->psr.transcoder));
+ enabled = val & EDP_PSR2_ENABLE;
+ } else {
+ val = intel_de_read(dev_priv,
+ EDP_PSR_CTL(intel_dp->psr.transcoder));
+ enabled = val & EDP_PSR_ENABLE;
+ }
+ seq_printf(m, "Source PSR ctl: %s [0x%08x]\n",
+ str_enabled_disabled(enabled), val);
+ psr_source_status(intel_dp, m);
+ seq_printf(m, "Busy frontbuffer bits: 0x%08x\n",
+ psr->busy_frontbuffer_bits);
+
+ /*
+ * SKL+ Perf counter is reset to 0 everytime DC state is entered
+ */
+ if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
+ val = intel_de_read(dev_priv,
+ EDP_PSR_PERF_CNT(intel_dp->psr.transcoder));
+ val &= EDP_PSR_PERF_CNT_MASK;
+ seq_printf(m, "Performance counter: %u\n", val);
+ }
+
+ if (psr->debug & I915_PSR_DEBUG_IRQ) {
+ seq_printf(m, "Last attempted entry at: %lld\n",
+ psr->last_entry_attempt);
+ seq_printf(m, "Last exit at: %lld\n", psr->last_exit);
+ }
+
+ if (psr->psr2_enabled) {
+ u32 su_frames_val[3];
+ int frame;
+
+ /*
+ * Reading all 3 registers before hand to minimize crossing a
+ * frame boundary between register reads
+ */
+ for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame += 3) {
+ val = intel_de_read(dev_priv,
+ PSR2_SU_STATUS(intel_dp->psr.transcoder, frame));
+ su_frames_val[frame / 3] = val;
+ }
+
+ seq_puts(m, "Frame:\tPSR2 SU blocks:\n");
+
+ for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame++) {
+ u32 su_blocks;
+
+ su_blocks = su_frames_val[frame / 3] &
+ PSR2_SU_STATUS_MASK(frame);
+ su_blocks = su_blocks >> PSR2_SU_STATUS_SHIFT(frame);
+ seq_printf(m, "%d\t%d\n", frame, su_blocks);
+ }
+
+ seq_printf(m, "PSR2 selective fetch: %s\n",
+ str_enabled_disabled(psr->psr2_sel_fetch_enabled));
+ }
+
+unlock:
+ mutex_unlock(&psr->lock);
+ intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
+
+ return 0;
+}
+
+static int i915_edp_psr_status_show(struct seq_file *m, void *data)
+{
+ struct drm_i915_private *dev_priv = m->private;
+ struct intel_dp *intel_dp = NULL;
+ struct intel_encoder *encoder;
+
+ if (!HAS_PSR(dev_priv))
+ return -ENODEV;
+
+ /* Find the first EDP which supports PSR */
+ for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
+ intel_dp = enc_to_intel_dp(encoder);
+ break;
+ }
+
+ if (!intel_dp)
+ return -ENODEV;
+
+ return intel_psr_status(m, intel_dp);
+}
+DEFINE_SHOW_ATTRIBUTE(i915_edp_psr_status);
+
+static int
+i915_edp_psr_debug_set(void *data, u64 val)
+{
+ struct drm_i915_private *dev_priv = data;
+ struct intel_encoder *encoder;
+ intel_wakeref_t wakeref;
+ int ret = -ENODEV;
+
+ if (!HAS_PSR(dev_priv))
+ return ret;
+
+ for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ drm_dbg_kms(&dev_priv->drm, "Setting PSR debug to %llx\n", val);
+
+ wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
+
+ // TODO: split to each transcoder's PSR debug state
+ ret = intel_psr_debug_set(intel_dp, val);
+
+ intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
+ }
+
+ return ret;
+}
+
+static int
+i915_edp_psr_debug_get(void *data, u64 *val)
+{
+ struct drm_i915_private *dev_priv = data;
+ struct intel_encoder *encoder;
+
+ if (!HAS_PSR(dev_priv))
+ return -ENODEV;
+
+ for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ // TODO: split to each transcoder's PSR debug state
+ *val = READ_ONCE(intel_dp->psr.debug);
+ return 0;
+ }
+
+ return -ENODEV;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(i915_edp_psr_debug_fops,
+ i915_edp_psr_debug_get, i915_edp_psr_debug_set,
+ "%llu\n");
+
+void intel_psr_debugfs_register(struct drm_i915_private *i915)
+{
+ struct drm_minor *minor = i915->drm.primary;
+
+ debugfs_create_file("i915_edp_psr_debug", 0644, minor->debugfs_root,
+ i915, &i915_edp_psr_debug_fops);
+
+ debugfs_create_file("i915_edp_psr_status", 0444, minor->debugfs_root,
+ i915, &i915_edp_psr_status_fops);
+}
+
+static int i915_psr_sink_status_show(struct seq_file *m, void *data)
+{
+ u8 val;
+ static const char * const sink_status[] = {
+ "inactive",
+ "transition to active, capture and display",
+ "active, display from RFB",
+ "active, capture and display on sink device timings",
+ "transition to inactive, capture and display, timing re-sync",
+ "reserved",
+ "reserved",
+ "sink internal error",
+ };
+ struct drm_connector *connector = m->private;
+ struct intel_dp *intel_dp =
+ intel_attached_dp(to_intel_connector(connector));
+ int ret;
+
+ if (!CAN_PSR(intel_dp)) {
+ seq_puts(m, "PSR Unsupported\n");
+ return -ENODEV;
+ }
+
+ if (connector->status != connector_status_connected)
+ return -ENODEV;
+
+ ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val);
+
+ if (ret == 1) {
+ const char *str = "unknown";
+
+ val &= DP_PSR_SINK_STATE_MASK;
+ if (val < ARRAY_SIZE(sink_status))
+ str = sink_status[val];
+ seq_printf(m, "Sink PSR status: 0x%x [%s]\n", val, str);
+ } else {
+ return ret;
+ }
+
+ return 0;
+}
+DEFINE_SHOW_ATTRIBUTE(i915_psr_sink_status);
+
+static int i915_psr_status_show(struct seq_file *m, void *data)
+{
+ struct drm_connector *connector = m->private;
+ struct intel_dp *intel_dp =
+ intel_attached_dp(to_intel_connector(connector));
+
+ return intel_psr_status(m, intel_dp);
+}
+DEFINE_SHOW_ATTRIBUTE(i915_psr_status);
+
+void intel_psr_connector_debugfs_add(struct intel_connector *intel_connector)
+{
+ struct drm_connector *connector = &intel_connector->base;
+ struct drm_i915_private *i915 = to_i915(connector->dev);
+ struct dentry *root = connector->debugfs_entry;
+
+ if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
+ return;
+
+ debugfs_create_file("i915_psr_sink_status", 0444, root,
+ connector, &i915_psr_sink_status_fops);
+
+ if (HAS_PSR(i915))
+ debugfs_create_file("i915_psr_status", 0444, root,
+ connector, &i915_psr_status_fops);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 7a38a9e7fa5b..0b95e8aa615f 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -13,6 +13,7 @@ struct drm_connector;
struct drm_connector_state;
struct drm_i915_private;
struct intel_atomic_state;
+struct intel_connector;
struct intel_crtc;
struct intel_crtc_state;
struct intel_dp;
@@ -61,5 +62,7 @@ void intel_psr_resume(struct intel_dp *intel_dp);
void intel_psr_lock(const struct intel_crtc_state *crtc_state);
void intel_psr_unlock(const struct intel_crtc_state *crtc_state);
+void intel_psr_connector_debugfs_add(struct intel_connector *connector);
+void intel_psr_debugfs_register(struct drm_i915_private *i915);
#endif /* __INTEL_PSR_H__ */
--
2.39.2
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH 2/3] drm/i915/psr: switch PSR debugfs to struct intel_connector
2023-03-17 13:41 [Intel-gfx] [PATCH 1/3] drm/i915/psr: move PSR debugfs to intel_psr.c Jani Nikula
@ 2023-03-17 13:41 ` Jani Nikula
2023-03-20 8:50 ` Hogander, Jouni
2023-03-17 13:41 ` [Intel-gfx] [PATCH 3/3] drm/i915/psr: clean up PSR debugfs sink status error handling Jani Nikula
` (6 subsequent siblings)
7 siblings, 1 reply; 12+ messages in thread
From: Jani Nikula @ 2023-03-17 13:41 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Prefer struct intel_connector over struct drm_connector.
Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 23 ++++++++++-------------
1 file changed, 10 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 9d3205d99b54..bd1a1a2524b5 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2879,7 +2879,8 @@ void intel_psr_debugfs_register(struct drm_i915_private *i915)
static int i915_psr_sink_status_show(struct seq_file *m, void *data)
{
- u8 val;
+ struct intel_connector *connector = m->private;
+ struct intel_dp *intel_dp = intel_attached_dp(connector);
static const char * const sink_status[] = {
"inactive",
"transition to active, capture and display",
@@ -2890,17 +2891,15 @@ static int i915_psr_sink_status_show(struct seq_file *m, void *data)
"reserved",
"sink internal error",
};
- struct drm_connector *connector = m->private;
- struct intel_dp *intel_dp =
- intel_attached_dp(to_intel_connector(connector));
int ret;
+ u8 val;
if (!CAN_PSR(intel_dp)) {
seq_puts(m, "PSR Unsupported\n");
return -ENODEV;
}
- if (connector->status != connector_status_connected)
+ if (connector->base.status != connector_status_connected)
return -ENODEV;
ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val);
@@ -2922,21 +2921,19 @@ DEFINE_SHOW_ATTRIBUTE(i915_psr_sink_status);
static int i915_psr_status_show(struct seq_file *m, void *data)
{
- struct drm_connector *connector = m->private;
- struct intel_dp *intel_dp =
- intel_attached_dp(to_intel_connector(connector));
+ struct intel_connector *connector = m->private;
+ struct intel_dp *intel_dp = intel_attached_dp(connector);
return intel_psr_status(m, intel_dp);
}
DEFINE_SHOW_ATTRIBUTE(i915_psr_status);
-void intel_psr_connector_debugfs_add(struct intel_connector *intel_connector)
+void intel_psr_connector_debugfs_add(struct intel_connector *connector)
{
- struct drm_connector *connector = &intel_connector->base;
- struct drm_i915_private *i915 = to_i915(connector->dev);
- struct dentry *root = connector->debugfs_entry;
+ struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct dentry *root = connector->base.debugfs_entry;
- if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
+ if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
return;
debugfs_create_file("i915_psr_sink_status", 0444, root,
--
2.39.2
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH 3/3] drm/i915/psr: clean up PSR debugfs sink status error handling
2023-03-17 13:41 [Intel-gfx] [PATCH 1/3] drm/i915/psr: move PSR debugfs to intel_psr.c Jani Nikula
2023-03-17 13:41 ` [Intel-gfx] [PATCH 2/3] drm/i915/psr: switch PSR debugfs to struct intel_connector Jani Nikula
@ 2023-03-17 13:41 ` Jani Nikula
2023-03-20 8:50 ` Hogander, Jouni
2023-03-17 18:07 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/psr: move PSR debugfs to intel_psr.c Patchwork
` (5 subsequent siblings)
7 siblings, 1 reply; 12+ messages in thread
From: Jani Nikula @ 2023-03-17 13:41 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Handle errors first and return early, and reduce indentation on the
happy day code path.
Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index bd1a1a2524b5..31084d95711d 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2891,6 +2891,7 @@ static int i915_psr_sink_status_show(struct seq_file *m, void *data)
"reserved",
"sink internal error",
};
+ const char *str;
int ret;
u8 val;
@@ -2903,17 +2904,16 @@ static int i915_psr_sink_status_show(struct seq_file *m, void *data)
return -ENODEV;
ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val);
+ if (ret != 1)
+ return ret < 0 ? ret : -EIO;
- if (ret == 1) {
- const char *str = "unknown";
+ val &= DP_PSR_SINK_STATE_MASK;
+ if (val < ARRAY_SIZE(sink_status))
+ str = sink_status[val];
+ else
+ str = "unknown";
- val &= DP_PSR_SINK_STATE_MASK;
- if (val < ARRAY_SIZE(sink_status))
- str = sink_status[val];
- seq_printf(m, "Sink PSR status: 0x%x [%s]\n", val, str);
- } else {
- return ret;
- }
+ seq_printf(m, "Sink PSR status: 0x%x [%s]\n", val, str);
return 0;
}
--
2.39.2
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/psr: move PSR debugfs to intel_psr.c
2023-03-17 13:41 [Intel-gfx] [PATCH 1/3] drm/i915/psr: move PSR debugfs to intel_psr.c Jani Nikula
2023-03-17 13:41 ` [Intel-gfx] [PATCH 2/3] drm/i915/psr: switch PSR debugfs to struct intel_connector Jani Nikula
2023-03-17 13:41 ` [Intel-gfx] [PATCH 3/3] drm/i915/psr: clean up PSR debugfs sink status error handling Jani Nikula
@ 2023-03-17 18:07 ` Patchwork
2023-03-17 18:07 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (4 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2023-03-17 18:07 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/i915/psr: move PSR debugfs to intel_psr.c
URL : https://patchwork.freedesktop.org/series/115315/
State : warning
== Summary ==
Error: patch https://patchwork.freedesktop.org/api/1.0/series/115315/revisions/1/mbox/ not applied
Committer identity unknown
*** Please tell me who you are.
Run
git config --global user.email "you@example.com"
git config --global user.name "Your Name"
to set your account's default identity.
Omit --global to set the identity only in this repository.
fatal: unable to auto-detect email address (got 'kbuild2@gfx-ci.(none)')
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/3] drm/i915/psr: move PSR debugfs to intel_psr.c
2023-03-17 13:41 [Intel-gfx] [PATCH 1/3] drm/i915/psr: move PSR debugfs to intel_psr.c Jani Nikula
` (2 preceding siblings ...)
2023-03-17 18:07 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/psr: move PSR debugfs to intel_psr.c Patchwork
@ 2023-03-17 18:07 ` Patchwork
2023-03-17 18:07 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
` (3 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2023-03-17 18:07 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/i915/psr: move PSR debugfs to intel_psr.c
URL : https://patchwork.freedesktop.org/series/115315/
State : warning
== Summary ==
Error: patch https://patchwork.freedesktop.org/api/1.0/series/115315/revisions/1/mbox/ not applied
Committer identity unknown
*** Please tell me who you are.
Run
git config --global user.email "you@example.com"
git config --global user.name "Your Name"
to set your account's default identity.
Omit --global to set the identity only in this repository.
fatal: unable to auto-detect email address (got 'kbuild2@gfx-ci.(none)')
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [1/3] drm/i915/psr: move PSR debugfs to intel_psr.c
2023-03-17 13:41 [Intel-gfx] [PATCH 1/3] drm/i915/psr: move PSR debugfs to intel_psr.c Jani Nikula
` (3 preceding siblings ...)
2023-03-17 18:07 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2023-03-17 18:07 ` Patchwork
2023-03-17 18:20 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2023-03-17 18:07 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/i915/psr: move PSR debugfs to intel_psr.c
URL : https://patchwork.freedesktop.org/series/115315/
State : warning
== Summary ==
Error: patch https://patchwork.freedesktop.org/api/1.0/series/115315/revisions/1/mbox/ not applied
Committer identity unknown
*** Please tell me who you are.
Run
git config --global user.email "you@example.com"
git config --global user.name "Your Name"
to set your account's default identity.
Omit --global to set the identity only in this repository.
fatal: unable to auto-detect email address (got 'kbuild2@gfx-ci.(none)')
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/psr: move PSR debugfs to intel_psr.c
2023-03-17 13:41 [Intel-gfx] [PATCH 1/3] drm/i915/psr: move PSR debugfs to intel_psr.c Jani Nikula
` (4 preceding siblings ...)
2023-03-17 18:07 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
@ 2023-03-17 18:20 ` Patchwork
2023-03-17 20:54 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2023-03-20 8:50 ` [Intel-gfx] [PATCH 1/3] " Hogander, Jouni
7 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2023-03-17 18:20 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 8629 bytes --]
== Series Details ==
Series: series starting with [1/3] drm/i915/psr: move PSR debugfs to intel_psr.c
URL : https://patchwork.freedesktop.org/series/115315/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12873 -> Patchwork_115315v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/index.html
Participating hosts (35 -> 34)
------------------------------
Additional (1): bat-dg1-6
Missing (2): bat-adlm-1 fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_115315v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_mmap@basic:
- bat-dg1-6: NOTRUN -> [SKIP][1] ([i915#4083])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/bat-dg1-6/igt@gem_mmap@basic.html
* igt@gem_render_tiled_blits@basic:
- bat-dg1-6: NOTRUN -> [SKIP][2] ([i915#4079]) +1 similar issue
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/bat-dg1-6/igt@gem_render_tiled_blits@basic.html
* igt@gem_tiled_fence_blits@basic:
- bat-dg1-6: NOTRUN -> [SKIP][3] ([i915#4077]) +2 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/bat-dg1-6/igt@gem_tiled_fence_blits@basic.html
* igt@i915_pm_backlight@basic-brightness:
- bat-dg1-6: NOTRUN -> [SKIP][4] ([i915#7561])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/bat-dg1-6/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_pm_rps@basic-api:
- bat-dg1-6: NOTRUN -> [SKIP][5] ([i915#6621])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/bat-dg1-6/igt@i915_pm_rps@basic-api.html
* igt@i915_selftest@live@requests:
- bat-rpls-1: [PASS][6] -> [ABORT][7] ([i915#4983] / [i915#7911] / [i915#7981])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12873/bat-rpls-1/igt@i915_selftest@live@requests.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/bat-rpls-1/igt@i915_selftest@live@requests.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg1-6: NOTRUN -> [SKIP][8] ([i915#4215])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/bat-dg1-6/igt@kms_addfb_basic@basic-y-tiled-legacy.html
* igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-dg1-6: NOTRUN -> [SKIP][9] ([i915#4212]) +7 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/bat-dg1-6/igt@kms_addfb_basic@tile-pitch-mismatch.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-dg1-6: NOTRUN -> [SKIP][10] ([i915#7828]) +8 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/bat-dg1-6/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
- fi-bsw-nick: NOTRUN -> [SKIP][11] ([fdo#109271]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/fi-bsw-nick/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
- bat-jsl-3: NOTRUN -> [SKIP][12] ([i915#7828])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/bat-jsl-3/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
- fi-bsw-n3050: NOTRUN -> [SKIP][13] ([fdo#109271])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/fi-bsw-n3050/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- bat-dg1-6: NOTRUN -> [SKIP][14] ([i915#4103] / [i915#4213]) +1 similar issue
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/bat-dg1-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-dg1-6: NOTRUN -> [SKIP][15] ([fdo#109285])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/bat-dg1-6/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_psr@sprite_plane_onoff:
- bat-dg1-6: NOTRUN -> [SKIP][16] ([i915#1072] / [i915#4078]) +3 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/bat-dg1-6/igt@kms_psr@sprite_plane_onoff.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-dg1-6: NOTRUN -> [SKIP][17] ([i915#3555])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/bat-dg1-6/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-gtt:
- bat-dg1-6: NOTRUN -> [SKIP][18] ([i915#3708] / [i915#4077]) +1 similar issue
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/bat-dg1-6/igt@prime_vgem@basic-gtt.html
* igt@prime_vgem@basic-read:
- bat-dg1-6: NOTRUN -> [SKIP][19] ([i915#3708]) +3 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/bat-dg1-6/igt@prime_vgem@basic-read.html
* igt@prime_vgem@basic-userptr:
- bat-dg1-6: NOTRUN -> [SKIP][20] ([i915#3708] / [i915#4873])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/bat-dg1-6/igt@prime_vgem@basic-userptr.html
#### Possible fixes ####
* igt@i915_selftest@live@execlists:
- fi-bsw-n3050: [ABORT][21] ([i915#7911]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12873/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
- fi-bsw-nick: [ABORT][23] ([i915#7911] / [i915#7913]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12873/fi-bsw-nick/igt@i915_selftest@live@execlists.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/fi-bsw-nick/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@gem_contexts:
- bat-jsl-3: [INCOMPLETE][25] -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12873/bat-jsl-3/igt@i915_selftest@live@gem_contexts.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/bat-jsl-3/igt@i915_selftest@live@gem_contexts.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7872]: https://gitlab.freedesktop.org/drm/intel/issues/7872
[i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7981]: https://gitlab.freedesktop.org/drm/intel/issues/7981
Build changes
-------------
* Linux: CI_DRM_12873 -> Patchwork_115315v1
CI-20190529: 20190529
CI_DRM_12873: b97925f47e2a20e1b79bc7c8cc236ded1bd431df @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7202: b4ec7dac375eed2dda89c64d4de94c4c9205b601 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_115315v1: b97925f47e2a20e1b79bc7c8cc236ded1bd431df @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
1b6bc4cc1ce1 drm/i915/psr: clean up PSR debugfs sink status error handling
cba2210994e0 drm/i915/psr: switch PSR debugfs to struct intel_connector
6f6ca008b102 drm/i915/psr: move PSR debugfs to intel_psr.c
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/index.html
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^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/psr: move PSR debugfs to intel_psr.c
2023-03-17 13:41 [Intel-gfx] [PATCH 1/3] drm/i915/psr: move PSR debugfs to intel_psr.c Jani Nikula
` (5 preceding siblings ...)
2023-03-17 18:20 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2023-03-17 20:54 ` Patchwork
2023-03-20 8:50 ` [Intel-gfx] [PATCH 1/3] " Hogander, Jouni
7 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2023-03-17 20:54 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 19574 bytes --]
== Series Details ==
Series: series starting with [1/3] drm/i915/psr: move PSR debugfs to intel_psr.c
URL : https://patchwork.freedesktop.org/series/115315/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12873_full -> Patchwork_115315v1_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (7 -> 8)
------------------------------
Additional (1): shard-rkl0
Known issues
------------
Here are the changes found in Patchwork_115315v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-glk: [PASS][1] -> [FAIL][2] ([i915#2842]) +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12873/shard-glk7/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/shard-glk9/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gen9_exec_parse@allowed-all:
- shard-glk: [PASS][3] -> [ABORT][4] ([i915#5566])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12873/shard-glk4/igt@gen9_exec_parse@allowed-all.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/shard-glk9/igt@gen9_exec_parse@allowed-all.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [PASS][5] -> [FAIL][6] ([i915#2346])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12873/shard-glk5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/shard-glk6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor-toggle:
- shard-apl: [PASS][7] -> [FAIL][8] ([i915#2346])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12873/shard-apl4/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/shard-apl7/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
* igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a1:
- shard-glk: [PASS][9] -> [FAIL][10] ([i915#79])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12873/shard-glk6/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a1.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/shard-glk1/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a1.html
* igt@perf@stress-open-close:
- shard-glk: [PASS][11] -> [ABORT][12] ([i915#5213])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12873/shard-glk5/igt@perf@stress-open-close.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/shard-glk3/igt@perf@stress-open-close.html
#### Possible fixes ####
* igt@api_intel_bb@object-reloc-keep-cache:
- {shard-rkl}: [SKIP][13] ([i915#3281]) -> [PASS][14] +9 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12873/shard-rkl-4/igt@api_intel_bb@object-reloc-keep-cache.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/shard-rkl-5/igt@api_intel_bb@object-reloc-keep-cache.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [FAIL][15] ([i915#2842]) -> [PASS][16] +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12873/shard-glk3/igt@gem_exec_fair@basic-throttle@rcs0.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/shard-glk2/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_lmem_swapping@heavy-verify-multi@lmem0:
- {shard-dg1}: [DMESG-WARN][17] ([i915#4391]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12873/shard-dg1-13/igt@gem_lmem_swapping@heavy-verify-multi@lmem0.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/shard-dg1-14/igt@gem_lmem_swapping@heavy-verify-multi@lmem0.html
* igt@gem_lmem_swapping@verify@lmem0:
- {shard-dg1}: [DMESG-WARN][19] -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12873/shard-dg1-13/igt@gem_lmem_swapping@verify@lmem0.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/shard-dg1-14/igt@gem_lmem_swapping@verify@lmem0.html
* igt@gem_mmap_gtt@coherency:
- {shard-rkl}: [SKIP][21] ([fdo#111656]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12873/shard-rkl-2/igt@gem_mmap_gtt@coherency.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/shard-rkl-5/igt@gem_mmap_gtt@coherency.html
* igt@gem_partial_pwrite_pread@writes-after-reads-uncached:
- {shard-rkl}: [SKIP][23] ([i915#3282]) -> [PASS][24] +6 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12873/shard-rkl-4/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/shard-rkl-5/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
* igt@gen9_exec_parse@bb-start-out:
- {shard-rkl}: [SKIP][25] ([i915#2527]) -> [PASS][26] +5 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12873/shard-rkl-2/igt@gen9_exec_parse@bb-start-out.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/shard-rkl-5/igt@gen9_exec_parse@bb-start-out.html
* igt@i915_hangman@engine-engine-error@bcs0:
- {shard-rkl}: [SKIP][27] ([i915#6258]) -> [PASS][28] +1 similar issue
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12873/shard-rkl-5/igt@i915_hangman@engine-engine-error@bcs0.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/shard-rkl-1/igt@i915_hangman@engine-engine-error@bcs0.html
* igt@i915_module_load@reload-with-fault-injection:
- {shard-tglu}: [DMESG-WARN][29] ([i915#2867]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12873/shard-tglu-2/igt@i915_module_load@reload-with-fault-injection.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/shard-tglu-6/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_dc@dc9-dpms:
- {shard-rkl}: [SKIP][31] ([i915#3361]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12873/shard-rkl-5/igt@i915_pm_dc@dc9-dpms.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/shard-rkl-1/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_pm_rc6_residency@rc6-idle@vcs0:
- {shard-rkl}: [WARN][33] ([i915#2681]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12873/shard-rkl-5/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/shard-rkl-4/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
- {shard-dg1}: [SKIP][35] ([i915#1397]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12873/shard-dg1-14/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/shard-dg1-18/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@i915_pm_rpm@system-suspend-modeset:
- {shard-rkl}: [SKIP][37] ([fdo#109308]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12873/shard-rkl-2/igt@i915_pm_rpm@system-suspend-modeset.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/shard-rkl-6/igt@i915_pm_rpm@system-suspend-modeset.html
* igt@i915_selftest@live@gt_heartbeat:
- shard-apl: [DMESG-FAIL][39] ([i915#5334]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12873/shard-apl2/igt@i915_selftest@live@gt_heartbeat.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/shard-apl2/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_atomic@atomic_plane_damage:
- {shard-rkl}: [SKIP][41] ([i915#4098]) -> [PASS][42] +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12873/shard-rkl-1/igt@kms_atomic@atomic_plane_damage.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/shard-rkl-6/igt@kms_atomic@atomic_plane_damage.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- {shard-rkl}: [SKIP][43] ([i915#1845] / [i915#4098]) -> [PASS][44] +17 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12873/shard-rkl-2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/shard-rkl-6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-vga1:
- shard-snb: [FAIL][45] ([i915#79]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12873/shard-snb7/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-vga1.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/shard-snb7/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-vga1.html
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-render:
- {shard-rkl}: [SKIP][47] ([i915#1849] / [i915#4098]) -> [PASS][48] +7 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12873/shard-rkl-1/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-render.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-render.html
* igt@kms_psr@sprite_mmap_gtt:
- {shard-rkl}: [SKIP][49] ([i915#1072]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12873/shard-rkl-1/igt@kms_psr@sprite_mmap_gtt.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/shard-rkl-6/igt@kms_psr@sprite_mmap_gtt.html
* igt@kms_universal_plane@universal-plane-pipe-a-functional:
- {shard-rkl}: [SKIP][51] ([i915#1845] / [i915#4070] / [i915#4098]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12873/shard-rkl-2/igt@kms_universal_plane@universal-plane-pipe-a-functional.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/shard-rkl-6/igt@kms_universal_plane@universal-plane-pipe-a-functional.html
* igt@perf@mi-rpc:
- {shard-rkl}: [SKIP][53] ([i915#2434]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12873/shard-rkl-6/igt@perf@mi-rpc.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/shard-rkl-5/igt@perf@mi-rpc.html
* igt@perf_pmu@idle@rcs0:
- {shard-rkl}: [FAIL][55] ([i915#4349]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12873/shard-rkl-1/igt@perf_pmu@idle@rcs0.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/shard-rkl-1/igt@perf_pmu@idle@rcs0.html
* igt@prime_vgem@basic-fence-read:
- {shard-rkl}: [SKIP][57] ([fdo#109295] / [i915#3291] / [i915#3708]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12873/shard-rkl-3/igt@prime_vgem@basic-fence-read.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/shard-rkl-5/igt@prime_vgem@basic-fence-read.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528
[i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5213]: https://gitlab.freedesktop.org/drm/intel/issues/5213
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6247]: https://gitlab.freedesktop.org/drm/intel/issues/6247
[i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
[i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252
[i915#6258]: https://gitlab.freedesktop.org/drm/intel/issues/6258
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
[i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
[i915#7037]: https://gitlab.freedesktop.org/drm/intel/issues/7037
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7651]: https://gitlab.freedesktop.org/drm/intel/issues/7651
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#7949]: https://gitlab.freedesktop.org/drm/intel/issues/7949
[i915#7957]: https://gitlab.freedesktop.org/drm/intel/issues/7957
[i915#8152]: https://gitlab.freedesktop.org/drm/intel/issues/8152
[i915#8211]: https://gitlab.freedesktop.org/drm/intel/issues/8211
[i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
[i915#8282]: https://gitlab.freedesktop.org/drm/intel/issues/8282
Build changes
-------------
* Linux: CI_DRM_12873 -> Patchwork_115315v1
CI-20190529: 20190529
CI_DRM_12873: b97925f47e2a20e1b79bc7c8cc236ded1bd431df @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7202: b4ec7dac375eed2dda89c64d4de94c4c9205b601 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_115315v1: b97925f47e2a20e1b79bc7c8cc236ded1bd431df @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115315v1/index.html
[-- Attachment #2: Type: text/html, Size: 15651 bytes --]
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] drm/i915/psr: move PSR debugfs to intel_psr.c
2023-03-17 13:41 [Intel-gfx] [PATCH 1/3] drm/i915/psr: move PSR debugfs to intel_psr.c Jani Nikula
` (6 preceding siblings ...)
2023-03-17 20:54 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2023-03-20 8:50 ` Hogander, Jouni
2023-03-20 10:14 ` Jani Nikula
7 siblings, 1 reply; 12+ messages in thread
From: Hogander, Jouni @ 2023-03-20 8:50 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx
On Fri, 2023-03-17 at 15:41 +0200, Jani Nikula wrote:
> Move the debugfs next to the implementation.
>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> .../drm/i915/display/intel_display_debugfs.c | 288 +---------------
> -
> drivers/gpu/drm/i915/display/intel_psr.c | 302
> ++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_psr.h | 3 +
> 3 files changed, 308 insertions(+), 285 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 65585f19c6c8..4d8ebf3fed11 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -142,269 +142,6 @@ static int i915_gem_framebuffer_info(struct
> seq_file *m, void *data)
> return 0;
> }
>
> -static int i915_psr_sink_status_show(struct seq_file *m, void *data)
> -{
> - u8 val;
> - static const char * const sink_status[] = {
> - "inactive",
> - "transition to active, capture and display",
> - "active, display from RFB",
> - "active, capture and display on sink device timings",
> - "transition to inactive, capture and display, timing
> re-sync",
> - "reserved",
> - "reserved",
> - "sink internal error",
> - };
> - struct drm_connector *connector = m->private;
> - struct intel_dp *intel_dp =
> - intel_attached_dp(to_intel_connector(connector));
> - int ret;
> -
> - if (!CAN_PSR(intel_dp)) {
> - seq_puts(m, "PSR Unsupported\n");
> - return -ENODEV;
> - }
> -
> - if (connector->status != connector_status_connected)
> - return -ENODEV;
> -
> - ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val);
> -
> - if (ret == 1) {
> - const char *str = "unknown";
> -
> - val &= DP_PSR_SINK_STATE_MASK;
> - if (val < ARRAY_SIZE(sink_status))
> - str = sink_status[val];
> - seq_printf(m, "Sink PSR status: 0x%x [%s]\n", val,
> str);
> - } else {
> - return ret;
> - }
> -
> - return 0;
> -}
> -DEFINE_SHOW_ATTRIBUTE(i915_psr_sink_status);
> -
> -static void
> -psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
> -{
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - const char *status = "unknown";
> - u32 val, status_val;
> -
> - if (intel_dp->psr.psr2_enabled) {
> - static const char * const live_status[] = {
> - "IDLE",
> - "CAPTURE",
> - "CAPTURE_FS",
> - "SLEEP",
> - "BUFON_FW",
> - "ML_UP",
> - "SU_STANDBY",
> - "FAST_SLEEP",
> - "DEEP_SLEEP",
> - "BUF_ON",
> - "TG_ON"
> - };
> - val = intel_de_read(dev_priv,
> - EDP_PSR2_STATUS(intel_dp-
> >psr.transcoder));
> - status_val =
> REG_FIELD_GET(EDP_PSR2_STATUS_STATE_MASK, val);
> - if (status_val < ARRAY_SIZE(live_status))
> - status = live_status[status_val];
> - } else {
> - static const char * const live_status[] = {
> - "IDLE",
> - "SRDONACK",
> - "SRDENT",
> - "BUFOFF",
> - "BUFON",
> - "AUXACK",
> - "SRDOFFACK",
> - "SRDENT_ON",
> - };
> - val = intel_de_read(dev_priv,
> - EDP_PSR_STATUS(intel_dp-
> >psr.transcoder));
> - status_val = (val & EDP_PSR_STATUS_STATE_MASK) >>
> - EDP_PSR_STATUS_STATE_SHIFT;
> - if (status_val < ARRAY_SIZE(live_status))
> - status = live_status[status_val];
> - }
> -
> - seq_printf(m, "Source PSR status: %s [0x%08x]\n", status,
> val);
> -}
> -
> -static int intel_psr_status(struct seq_file *m, struct intel_dp
> *intel_dp)
> -{
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - struct intel_psr *psr = &intel_dp->psr;
> - intel_wakeref_t wakeref;
> - const char *status;
> - bool enabled;
> - u32 val;
> -
> - seq_printf(m, "Sink support: %s", str_yes_no(psr-
> >sink_support));
> - if (psr->sink_support)
> - seq_printf(m, " [0x%02x]", intel_dp->psr_dpcd[0]);
> - seq_puts(m, "\n");
> -
> - if (!psr->sink_support)
> - return 0;
> -
> - wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
> - mutex_lock(&psr->lock);
> -
> - if (psr->enabled)
> - status = psr->psr2_enabled ? "PSR2 enabled" : "PSR1
> enabled";
> - else
> - status = "disabled";
> - seq_printf(m, "PSR mode: %s\n", status);
> -
> - if (!psr->enabled) {
> - seq_printf(m, "PSR sink not reliable: %s\n",
> - str_yes_no(psr->sink_not_reliable));
> -
> - goto unlock;
> - }
> -
> - if (psr->psr2_enabled) {
> - val = intel_de_read(dev_priv,
> - EDP_PSR2_CTL(intel_dp-
> >psr.transcoder));
> - enabled = val & EDP_PSR2_ENABLE;
> - } else {
> - val = intel_de_read(dev_priv,
> - EDP_PSR_CTL(intel_dp-
> >psr.transcoder));
> - enabled = val & EDP_PSR_ENABLE;
> - }
> - seq_printf(m, "Source PSR ctl: %s [0x%08x]\n",
> - str_enabled_disabled(enabled), val);
> - psr_source_status(intel_dp, m);
> - seq_printf(m, "Busy frontbuffer bits: 0x%08x\n",
> - psr->busy_frontbuffer_bits);
> -
> - /*
> - * SKL+ Perf counter is reset to 0 everytime DC state is
> entered
> - */
> - if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> - val = intel_de_read(dev_priv,
> - EDP_PSR_PERF_CNT(intel_dp-
> >psr.transcoder));
> - val &= EDP_PSR_PERF_CNT_MASK;
> - seq_printf(m, "Performance counter: %u\n", val);
> - }
> -
> - if (psr->debug & I915_PSR_DEBUG_IRQ) {
> - seq_printf(m, "Last attempted entry at: %lld\n",
> - psr->last_entry_attempt);
> - seq_printf(m, "Last exit at: %lld\n", psr-
> >last_exit);
> - }
> -
> - if (psr->psr2_enabled) {
> - u32 su_frames_val[3];
> - int frame;
> -
> - /*
> - * Reading all 3 registers before hand to minimize
> crossing a
> - * frame boundary between register reads
> - */
> - for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame
> += 3) {
> - val = intel_de_read(dev_priv,
> - PSR2_SU_STATUS(intel_dp-
> >psr.transcoder, frame));
> - su_frames_val[frame / 3] = val;
> - }
> -
> - seq_puts(m, "Frame:\tPSR2 SU blocks:\n");
> -
> - for (frame = 0; frame < PSR2_SU_STATUS_FRAMES;
> frame++) {
> - u32 su_blocks;
> -
> - su_blocks = su_frames_val[frame / 3] &
> - PSR2_SU_STATUS_MASK(frame);
> - su_blocks = su_blocks >>
> PSR2_SU_STATUS_SHIFT(frame);
> - seq_printf(m, "%d\t%d\n", frame, su_blocks);
> - }
> -
> - seq_printf(m, "PSR2 selective fetch: %s\n",
> - str_enabled_disabled(psr-
> >psr2_sel_fetch_enabled));
> - }
> -
> -unlock:
> - mutex_unlock(&psr->lock);
> - intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
> -
> - return 0;
> -}
> -
> -static int i915_edp_psr_status(struct seq_file *m, void *data)
> -{
> - struct drm_i915_private *dev_priv = node_to_i915(m->private);
> - struct intel_dp *intel_dp = NULL;
> - struct intel_encoder *encoder;
> -
> - if (!HAS_PSR(dev_priv))
> - return -ENODEV;
> -
> - /* Find the first EDP which supports PSR */
> - for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
> - intel_dp = enc_to_intel_dp(encoder);
> - break;
> - }
> -
> - if (!intel_dp)
> - return -ENODEV;
> -
> - return intel_psr_status(m, intel_dp);
> -}
> -
> -static int
> -i915_edp_psr_debug_set(void *data, u64 val)
> -{
> - struct drm_i915_private *dev_priv = data;
> - struct intel_encoder *encoder;
> - intel_wakeref_t wakeref;
> - int ret = -ENODEV;
> -
> - if (!HAS_PSR(dev_priv))
> - return ret;
> -
> - for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
> - struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> -
> - drm_dbg_kms(&dev_priv->drm, "Setting PSR debug to
> %llx\n", val);
> -
> - wakeref = intel_runtime_pm_get(&dev_priv-
> >runtime_pm);
> -
> - // TODO: split to each transcoder's PSR debug state
> - ret = intel_psr_debug_set(intel_dp, val);
> -
> - intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
> - }
> -
> - return ret;
> -}
> -
> -static int
> -i915_edp_psr_debug_get(void *data, u64 *val)
> -{
> - struct drm_i915_private *dev_priv = data;
> - struct intel_encoder *encoder;
> -
> - if (!HAS_PSR(dev_priv))
> - return -ENODEV;
> -
> - for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
> - struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> -
> - // TODO: split to each transcoder's PSR debug state
> - *val = READ_ONCE(intel_dp->psr.debug);
> - return 0;
> - }
> -
> - return -ENODEV;
> -}
> -
> -DEFINE_SIMPLE_ATTRIBUTE(i915_edp_psr_debug_fops,
> - i915_edp_psr_debug_get,
> i915_edp_psr_debug_set,
> - "%llu\n");
> -
> static int i915_power_domain_info(struct seq_file *m, void *unused)
> {
> struct drm_i915_private *i915 = node_to_i915(m->private);
> @@ -1320,7 +1057,6 @@ static const struct drm_info_list
> intel_display_debugfs_list[] = {
> {"i915_opregion", i915_opregion, 0},
> {"i915_vbt", i915_vbt, 0},
> {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
> - {"i915_edp_psr_status", i915_edp_psr_status, 0},
> {"i915_power_domain_info", i915_power_domain_info, 0},
> {"i915_display_info", i915_display_info, 0},
> {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
> @@ -1337,7 +1073,6 @@ static const struct {
> {"i915_dp_test_data", &i915_displayport_test_data_fops},
> {"i915_dp_test_type", &i915_displayport_test_type_fops},
> {"i915_dp_test_active", &i915_displayport_test_active_fops},
> - {"i915_edp_psr_debug", &i915_edp_psr_debug_fops},
> };
>
> void intel_display_debugfs_register(struct drm_i915_private *i915)
> @@ -1361,6 +1096,7 @@ void intel_display_debugfs_register(struct
> drm_i915_private *i915)
> intel_dmc_debugfs_register(i915);
> intel_fbc_debugfs_register(i915);
> intel_hpd_debugfs_register(i915);
> + intel_psr_debugfs_register(i915);
> intel_wm_debugfs_register(i915);
> }
>
> @@ -1413,16 +1149,6 @@ static int
> i915_hdcp_sink_capability_show(struct seq_file *m, void *data)
> }
> DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability);
>
> -static int i915_psr_status_show(struct seq_file *m, void *data)
> -{
> - struct drm_connector *connector = m->private;
> - struct intel_dp *intel_dp =
> - intel_attached_dp(to_intel_connector(connector));
> -
> - return intel_psr_status(m, intel_dp);
> -}
> -DEFINE_SHOW_ATTRIBUTE(i915_psr_status);
> -
> static int i915_lpsp_capability_show(struct seq_file *m, void *data)
> {
> struct drm_connector *connector = m->private;
> @@ -1675,19 +1401,11 @@ void intel_connector_debugfs_add(struct
> intel_connector *intel_connector)
> return;
>
> intel_drrs_connector_debugfs_add(intel_connector);
> + intel_psr_connector_debugfs_add(intel_connector);
>
> - if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
> + if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
> debugfs_create_file("i915_panel_timings", S_IRUGO,
> root,
> connector, &i915_panel_fops);
> - debugfs_create_file("i915_psr_sink_status", S_IRUGO,
> root,
> - connector,
> &i915_psr_sink_status_fops);
> - }
> -
> - if (HAS_PSR(dev_priv) &&
> - connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
> - debugfs_create_file("i915_psr_status", 0444, root,
> - connector,
> &i915_psr_status_fops);
> - }
>
> if (connector->connector_type ==
> DRM_MODE_CONNECTOR_DisplayPort ||
> connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 44610b20cd29..9d3205d99b54 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -2644,3 +2644,305 @@ void intel_psr_unlock(const struct
> intel_crtc_state *crtc_state)
> break;
> }
> }
> +
> +static void
> +psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + const char *status = "unknown";
> + u32 val, status_val;
> +
> + if (intel_dp->psr.psr2_enabled) {
> + static const char * const live_status[] = {
> + "IDLE",
> + "CAPTURE",
> + "CAPTURE_FS",
> + "SLEEP",
> + "BUFON_FW",
> + "ML_UP",
> + "SU_STANDBY",
> + "FAST_SLEEP",
> + "DEEP_SLEEP",
> + "BUF_ON",
> + "TG_ON"
> + };
> + val = intel_de_read(dev_priv,
> + EDP_PSR2_STATUS(intel_dp-
> >psr.transcoder));
> + status_val =
> REG_FIELD_GET(EDP_PSR2_STATUS_STATE_MASK, val);
> + if (status_val < ARRAY_SIZE(live_status))
> + status = live_status[status_val];
> + } else {
> + static const char * const live_status[] = {
> + "IDLE",
> + "SRDONACK",
> + "SRDENT",
> + "BUFOFF",
> + "BUFON",
> + "AUXACK",
> + "SRDOFFACK",
> + "SRDENT_ON",
> + };
> + val = intel_de_read(dev_priv,
> + EDP_PSR_STATUS(intel_dp-
> >psr.transcoder));
> + status_val = (val & EDP_PSR_STATUS_STATE_MASK) >>
> + EDP_PSR_STATUS_STATE_SHIFT;
> + if (status_val < ARRAY_SIZE(live_status))
> + status = live_status[status_val];
> + }
> +
> + seq_printf(m, "Source PSR status: %s [0x%08x]\n", status,
> val);
> +}
> +
> +static int intel_psr_status(struct seq_file *m, struct intel_dp
> *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + struct intel_psr *psr = &intel_dp->psr;
> + intel_wakeref_t wakeref;
> + const char *status;
> + bool enabled;
> + u32 val;
> +
> + seq_printf(m, "Sink support: %s", str_yes_no(psr-
> >sink_support));
> + if (psr->sink_support)
> + seq_printf(m, " [0x%02x]", intel_dp->psr_dpcd[0]);
> + seq_puts(m, "\n");
> +
> + if (!psr->sink_support)
> + return 0;
> +
> + wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
> + mutex_lock(&psr->lock);
> +
> + if (psr->enabled)
> + status = psr->psr2_enabled ? "PSR2 enabled" : "PSR1
> enabled";
> + else
> + status = "disabled";
> + seq_printf(m, "PSR mode: %s\n", status);
> +
> + if (!psr->enabled) {
> + seq_printf(m, "PSR sink not reliable: %s\n",
> + str_yes_no(psr->sink_not_reliable));
> +
> + goto unlock;
> + }
> +
> + if (psr->psr2_enabled) {
> + val = intel_de_read(dev_priv,
> + EDP_PSR2_CTL(intel_dp-
> >psr.transcoder));
> + enabled = val & EDP_PSR2_ENABLE;
> + } else {
> + val = intel_de_read(dev_priv,
> + EDP_PSR_CTL(intel_dp-
> >psr.transcoder));
> + enabled = val & EDP_PSR_ENABLE;
> + }
> + seq_printf(m, "Source PSR ctl: %s [0x%08x]\n",
> + str_enabled_disabled(enabled), val);
> + psr_source_status(intel_dp, m);
> + seq_printf(m, "Busy frontbuffer bits: 0x%08x\n",
> + psr->busy_frontbuffer_bits);
> +
> + /*
> + * SKL+ Perf counter is reset to 0 everytime DC state is
> entered
> + */
> + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> + val = intel_de_read(dev_priv,
> + EDP_PSR_PERF_CNT(intel_dp-
> >psr.transcoder));
> + val &= EDP_PSR_PERF_CNT_MASK;
> + seq_printf(m, "Performance counter: %u\n", val);
> + }
> +
> + if (psr->debug & I915_PSR_DEBUG_IRQ) {
> + seq_printf(m, "Last attempted entry at: %lld\n",
> + psr->last_entry_attempt);
> + seq_printf(m, "Last exit at: %lld\n", psr-
> >last_exit);
> + }
> +
> + if (psr->psr2_enabled) {
> + u32 su_frames_val[3];
> + int frame;
> +
> + /*
> + * Reading all 3 registers before hand to minimize
> crossing a
> + * frame boundary between register reads
> + */
> + for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame
> += 3) {
> + val = intel_de_read(dev_priv,
> + PSR2_SU_STATUS(intel_dp-
> >psr.transcoder, frame));
> + su_frames_val[frame / 3] = val;
> + }
> +
> + seq_puts(m, "Frame:\tPSR2 SU blocks:\n");
> +
> + for (frame = 0; frame < PSR2_SU_STATUS_FRAMES;
> frame++) {
> + u32 su_blocks;
> +
> + su_blocks = su_frames_val[frame / 3] &
> + PSR2_SU_STATUS_MASK(frame);
> + su_blocks = su_blocks >>
> PSR2_SU_STATUS_SHIFT(frame);
> + seq_printf(m, "%d\t%d\n", frame, su_blocks);
> + }
> +
> + seq_printf(m, "PSR2 selective fetch: %s\n",
> + str_enabled_disabled(psr-
> >psr2_sel_fetch_enabled));
> + }
> +
> +unlock:
> + mutex_unlock(&psr->lock);
> + intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
> +
> + return 0;
> +}
> +
> +static int i915_edp_psr_status_show(struct seq_file *m, void *data)
> +{
> + struct drm_i915_private *dev_priv = m->private;
> + struct intel_dp *intel_dp = NULL;
> + struct intel_encoder *encoder;
> +
> + if (!HAS_PSR(dev_priv))
> + return -ENODEV;
> +
> + /* Find the first EDP which supports PSR */
> + for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
> + intel_dp = enc_to_intel_dp(encoder);
> + break;
> + }
> +
> + if (!intel_dp)
> + return -ENODEV;
> +
> + return intel_psr_status(m, intel_dp);
> +}
> +DEFINE_SHOW_ATTRIBUTE(i915_edp_psr_status);
> +
> +static int
> +i915_edp_psr_debug_set(void *data, u64 val)
> +{
> + struct drm_i915_private *dev_priv = data;
> + struct intel_encoder *encoder;
> + intel_wakeref_t wakeref;
> + int ret = -ENODEV;
> +
> + if (!HAS_PSR(dev_priv))
> + return ret;
> +
> + for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
> + drm_dbg_kms(&dev_priv->drm, "Setting PSR debug to
> %llx\n", val);
> +
> + wakeref = intel_runtime_pm_get(&dev_priv-
> >runtime_pm);
> +
> + // TODO: split to each transcoder's PSR debug state
> + ret = intel_psr_debug_set(intel_dp, val);
> +
> + intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
> + }
> +
> + return ret;
> +}
> +
> +static int
> +i915_edp_psr_debug_get(void *data, u64 *val)
> +{
> + struct drm_i915_private *dev_priv = data;
> + struct intel_encoder *encoder;
> +
> + if (!HAS_PSR(dev_priv))
> + return -ENODEV;
> +
> + for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
> + // TODO: split to each transcoder's PSR debug state
> + *val = READ_ONCE(intel_dp->psr.debug);
> + return 0;
> + }
> +
> + return -ENODEV;
> +}
> +
> +DEFINE_SIMPLE_ATTRIBUTE(i915_edp_psr_debug_fops,
> + i915_edp_psr_debug_get,
> i915_edp_psr_debug_set,
> + "%llu\n");
> +
> +void intel_psr_debugfs_register(struct drm_i915_private *i915)
> +{
> + struct drm_minor *minor = i915->drm.primary;
> +
> + debugfs_create_file("i915_edp_psr_debug", 0644, minor-
> >debugfs_root,
> + i915, &i915_edp_psr_debug_fops);
> +
> + debugfs_create_file("i915_edp_psr_status", 0444, minor-
> >debugfs_root,
> + i915, &i915_edp_psr_status_fops);
> +}
> +
> +static int i915_psr_sink_status_show(struct seq_file *m, void *data)
> +{
> + u8 val;
> + static const char * const sink_status[] = {
> + "inactive",
> + "transition to active, capture and display",
> + "active, display from RFB",
> + "active, capture and display on sink device timings",
> + "transition to inactive, capture and display, timing
> re-sync",
> + "reserved",
> + "reserved",
> + "sink internal error",
> + };
> + struct drm_connector *connector = m->private;
> + struct intel_dp *intel_dp =
> + intel_attached_dp(to_intel_connector(connector));
> + int ret;
> +
> + if (!CAN_PSR(intel_dp)) {
> + seq_puts(m, "PSR Unsupported\n");
> + return -ENODEV;
> + }
> +
> + if (connector->status != connector_status_connected)
> + return -ENODEV;
> +
> + ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val);
> +
> + if (ret == 1) {
> + const char *str = "unknown";
> +
> + val &= DP_PSR_SINK_STATE_MASK;
> + if (val < ARRAY_SIZE(sink_status))
> + str = sink_status[val];
> + seq_printf(m, "Sink PSR status: 0x%x [%s]\n", val,
> str);
> + } else {
> + return ret;
> + }
> +
> + return 0;
> +}
> +DEFINE_SHOW_ATTRIBUTE(i915_psr_sink_status);
> +
> +static int i915_psr_status_show(struct seq_file *m, void *data)
> +{
> + struct drm_connector *connector = m->private;
> + struct intel_dp *intel_dp =
> + intel_attached_dp(to_intel_connector(connector));
> +
> + return intel_psr_status(m, intel_dp);
> +}
> +DEFINE_SHOW_ATTRIBUTE(i915_psr_status);
> +
> +void intel_psr_connector_debugfs_add(struct intel_connector
> *intel_connector)
> +{
> + struct drm_connector *connector = &intel_connector->base;
> + struct drm_i915_private *i915 = to_i915(connector->dev);
> + struct dentry *root = connector->debugfs_entry;
> +
> + if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
> + return;
> +
> + debugfs_create_file("i915_psr_sink_status", 0444, root,
> + connector, &i915_psr_sink_status_fops);
> +
> + if (HAS_PSR(i915))
> + debugfs_create_file("i915_psr_status", 0444, root,
> + connector,
> &i915_psr_status_fops);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> b/drivers/gpu/drm/i915/display/intel_psr.h
> index 7a38a9e7fa5b..0b95e8aa615f 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -13,6 +13,7 @@ struct drm_connector;
> struct drm_connector_state;
> struct drm_i915_private;
> struct intel_atomic_state;
> +struct intel_connector;
> struct intel_crtc;
> struct intel_crtc_state;
> struct intel_dp;
> @@ -61,5 +62,7 @@ void intel_psr_resume(struct intel_dp *intel_dp);
>
> void intel_psr_lock(const struct intel_crtc_state *crtc_state);
> void intel_psr_unlock(const struct intel_crtc_state *crtc_state);
> +void intel_psr_connector_debugfs_add(struct intel_connector
> *connector);
> +void intel_psr_debugfs_register(struct drm_i915_private *i915);
>
> #endif /* __INTEL_PSR_H__ */
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH 2/3] drm/i915/psr: switch PSR debugfs to struct intel_connector
2023-03-17 13:41 ` [Intel-gfx] [PATCH 2/3] drm/i915/psr: switch PSR debugfs to struct intel_connector Jani Nikula
@ 2023-03-20 8:50 ` Hogander, Jouni
0 siblings, 0 replies; 12+ messages in thread
From: Hogander, Jouni @ 2023-03-20 8:50 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx
On Fri, 2023-03-17 at 15:41 +0200, Jani Nikula wrote:
> Prefer struct intel_connector over struct drm_connector.
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
>
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 23 ++++++++++------------
> -
> 1 file changed, 10 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 9d3205d99b54..bd1a1a2524b5 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -2879,7 +2879,8 @@ void intel_psr_debugfs_register(struct
> drm_i915_private *i915)
>
> static int i915_psr_sink_status_show(struct seq_file *m, void *data)
> {
> - u8 val;
> + struct intel_connector *connector = m->private;
> + struct intel_dp *intel_dp = intel_attached_dp(connector);
> static const char * const sink_status[] = {
> "inactive",
> "transition to active, capture and display",
> @@ -2890,17 +2891,15 @@ static int i915_psr_sink_status_show(struct
> seq_file *m, void *data)
> "reserved",
> "sink internal error",
> };
> - struct drm_connector *connector = m->private;
> - struct intel_dp *intel_dp =
> - intel_attached_dp(to_intel_connector(connector));
> int ret;
> + u8 val;
>
> if (!CAN_PSR(intel_dp)) {
> seq_puts(m, "PSR Unsupported\n");
> return -ENODEV;
> }
>
> - if (connector->status != connector_status_connected)
> + if (connector->base.status != connector_status_connected)
> return -ENODEV;
>
> ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val);
> @@ -2922,21 +2921,19 @@ DEFINE_SHOW_ATTRIBUTE(i915_psr_sink_status);
>
> static int i915_psr_status_show(struct seq_file *m, void *data)
> {
> - struct drm_connector *connector = m->private;
> - struct intel_dp *intel_dp =
> - intel_attached_dp(to_intel_connector(connector));
> + struct intel_connector *connector = m->private;
> + struct intel_dp *intel_dp = intel_attached_dp(connector);
>
> return intel_psr_status(m, intel_dp);
> }
> DEFINE_SHOW_ATTRIBUTE(i915_psr_status);
>
> -void intel_psr_connector_debugfs_add(struct intel_connector
> *intel_connector)
> +void intel_psr_connector_debugfs_add(struct intel_connector
> *connector)
> {
> - struct drm_connector *connector = &intel_connector->base;
> - struct drm_i915_private *i915 = to_i915(connector->dev);
> - struct dentry *root = connector->debugfs_entry;
> + struct drm_i915_private *i915 = to_i915(connector->base.dev);
> + struct dentry *root = connector->base.debugfs_entry;
>
> - if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
> + if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
> return;
>
> debugfs_create_file("i915_psr_sink_status", 0444, root,
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH 3/3] drm/i915/psr: clean up PSR debugfs sink status error handling
2023-03-17 13:41 ` [Intel-gfx] [PATCH 3/3] drm/i915/psr: clean up PSR debugfs sink status error handling Jani Nikula
@ 2023-03-20 8:50 ` Hogander, Jouni
0 siblings, 0 replies; 12+ messages in thread
From: Hogander, Jouni @ 2023-03-20 8:50 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx
On Fri, 2023-03-17 at 15:41 +0200, Jani Nikula wrote:
> Handle errors first and return early, and reduce indentation on the
> happy day code path.
>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index bd1a1a2524b5..31084d95711d 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -2891,6 +2891,7 @@ static int i915_psr_sink_status_show(struct
> seq_file *m, void *data)
> "reserved",
> "sink internal error",
> };
> + const char *str;
> int ret;
> u8 val;
>
> @@ -2903,17 +2904,16 @@ static int i915_psr_sink_status_show(struct
> seq_file *m, void *data)
> return -ENODEV;
>
> ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val);
> + if (ret != 1)
> + return ret < 0 ? ret : -EIO;
>
> - if (ret == 1) {
> - const char *str = "unknown";
> + val &= DP_PSR_SINK_STATE_MASK;
> + if (val < ARRAY_SIZE(sink_status))
> + str = sink_status[val];
> + else
> + str = "unknown";
>
> - val &= DP_PSR_SINK_STATE_MASK;
> - if (val < ARRAY_SIZE(sink_status))
> - str = sink_status[val];
> - seq_printf(m, "Sink PSR status: 0x%x [%s]\n", val,
> str);
> - } else {
> - return ret;
> - }
> + seq_printf(m, "Sink PSR status: 0x%x [%s]\n", val, str);
>
> return 0;
> }
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] drm/i915/psr: move PSR debugfs to intel_psr.c
2023-03-20 8:50 ` [Intel-gfx] [PATCH 1/3] " Hogander, Jouni
@ 2023-03-20 10:14 ` Jani Nikula
0 siblings, 0 replies; 12+ messages in thread
From: Jani Nikula @ 2023-03-20 10:14 UTC (permalink / raw)
To: Hogander, Jouni, intel-gfx
On Mon, 20 Mar 2023, "Hogander, Jouni" <jouni.hogander@intel.com> wrote:
> On Fri, 2023-03-17 at 15:41 +0200, Jani Nikula wrote:
>> Move the debugfs next to the implementation.
>>
>
> Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Thanks, pushed the series to din.
BR,
Jani.
>
>> Cc: Jouni Högander <jouni.hogander@intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> .../drm/i915/display/intel_display_debugfs.c | 288 +---------------
>> -
>> drivers/gpu/drm/i915/display/intel_psr.c | 302
>> ++++++++++++++++++
>> drivers/gpu/drm/i915/display/intel_psr.h | 3 +
>> 3 files changed, 308 insertions(+), 285 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> index 65585f19c6c8..4d8ebf3fed11 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> @@ -142,269 +142,6 @@ static int i915_gem_framebuffer_info(struct
>> seq_file *m, void *data)
>> return 0;
>> }
>>
>> -static int i915_psr_sink_status_show(struct seq_file *m, void *data)
>> -{
>> - u8 val;
>> - static const char * const sink_status[] = {
>> - "inactive",
>> - "transition to active, capture and display",
>> - "active, display from RFB",
>> - "active, capture and display on sink device timings",
>> - "transition to inactive, capture and display, timing
>> re-sync",
>> - "reserved",
>> - "reserved",
>> - "sink internal error",
>> - };
>> - struct drm_connector *connector = m->private;
>> - struct intel_dp *intel_dp =
>> - intel_attached_dp(to_intel_connector(connector));
>> - int ret;
>> -
>> - if (!CAN_PSR(intel_dp)) {
>> - seq_puts(m, "PSR Unsupported\n");
>> - return -ENODEV;
>> - }
>> -
>> - if (connector->status != connector_status_connected)
>> - return -ENODEV;
>> -
>> - ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val);
>> -
>> - if (ret == 1) {
>> - const char *str = "unknown";
>> -
>> - val &= DP_PSR_SINK_STATE_MASK;
>> - if (val < ARRAY_SIZE(sink_status))
>> - str = sink_status[val];
>> - seq_printf(m, "Sink PSR status: 0x%x [%s]\n", val,
>> str);
>> - } else {
>> - return ret;
>> - }
>> -
>> - return 0;
>> -}
>> -DEFINE_SHOW_ATTRIBUTE(i915_psr_sink_status);
>> -
>> -static void
>> -psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
>> -{
>> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>> - const char *status = "unknown";
>> - u32 val, status_val;
>> -
>> - if (intel_dp->psr.psr2_enabled) {
>> - static const char * const live_status[] = {
>> - "IDLE",
>> - "CAPTURE",
>> - "CAPTURE_FS",
>> - "SLEEP",
>> - "BUFON_FW",
>> - "ML_UP",
>> - "SU_STANDBY",
>> - "FAST_SLEEP",
>> - "DEEP_SLEEP",
>> - "BUF_ON",
>> - "TG_ON"
>> - };
>> - val = intel_de_read(dev_priv,
>> - EDP_PSR2_STATUS(intel_dp-
>> >psr.transcoder));
>> - status_val =
>> REG_FIELD_GET(EDP_PSR2_STATUS_STATE_MASK, val);
>> - if (status_val < ARRAY_SIZE(live_status))
>> - status = live_status[status_val];
>> - } else {
>> - static const char * const live_status[] = {
>> - "IDLE",
>> - "SRDONACK",
>> - "SRDENT",
>> - "BUFOFF",
>> - "BUFON",
>> - "AUXACK",
>> - "SRDOFFACK",
>> - "SRDENT_ON",
>> - };
>> - val = intel_de_read(dev_priv,
>> - EDP_PSR_STATUS(intel_dp-
>> >psr.transcoder));
>> - status_val = (val & EDP_PSR_STATUS_STATE_MASK) >>
>> - EDP_PSR_STATUS_STATE_SHIFT;
>> - if (status_val < ARRAY_SIZE(live_status))
>> - status = live_status[status_val];
>> - }
>> -
>> - seq_printf(m, "Source PSR status: %s [0x%08x]\n", status,
>> val);
>> -}
>> -
>> -static int intel_psr_status(struct seq_file *m, struct intel_dp
>> *intel_dp)
>> -{
>> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>> - struct intel_psr *psr = &intel_dp->psr;
>> - intel_wakeref_t wakeref;
>> - const char *status;
>> - bool enabled;
>> - u32 val;
>> -
>> - seq_printf(m, "Sink support: %s", str_yes_no(psr-
>> >sink_support));
>> - if (psr->sink_support)
>> - seq_printf(m, " [0x%02x]", intel_dp->psr_dpcd[0]);
>> - seq_puts(m, "\n");
>> -
>> - if (!psr->sink_support)
>> - return 0;
>> -
>> - wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
>> - mutex_lock(&psr->lock);
>> -
>> - if (psr->enabled)
>> - status = psr->psr2_enabled ? "PSR2 enabled" : "PSR1
>> enabled";
>> - else
>> - status = "disabled";
>> - seq_printf(m, "PSR mode: %s\n", status);
>> -
>> - if (!psr->enabled) {
>> - seq_printf(m, "PSR sink not reliable: %s\n",
>> - str_yes_no(psr->sink_not_reliable));
>> -
>> - goto unlock;
>> - }
>> -
>> - if (psr->psr2_enabled) {
>> - val = intel_de_read(dev_priv,
>> - EDP_PSR2_CTL(intel_dp-
>> >psr.transcoder));
>> - enabled = val & EDP_PSR2_ENABLE;
>> - } else {
>> - val = intel_de_read(dev_priv,
>> - EDP_PSR_CTL(intel_dp-
>> >psr.transcoder));
>> - enabled = val & EDP_PSR_ENABLE;
>> - }
>> - seq_printf(m, "Source PSR ctl: %s [0x%08x]\n",
>> - str_enabled_disabled(enabled), val);
>> - psr_source_status(intel_dp, m);
>> - seq_printf(m, "Busy frontbuffer bits: 0x%08x\n",
>> - psr->busy_frontbuffer_bits);
>> -
>> - /*
>> - * SKL+ Perf counter is reset to 0 everytime DC state is
>> entered
>> - */
>> - if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
>> - val = intel_de_read(dev_priv,
>> - EDP_PSR_PERF_CNT(intel_dp-
>> >psr.transcoder));
>> - val &= EDP_PSR_PERF_CNT_MASK;
>> - seq_printf(m, "Performance counter: %u\n", val);
>> - }
>> -
>> - if (psr->debug & I915_PSR_DEBUG_IRQ) {
>> - seq_printf(m, "Last attempted entry at: %lld\n",
>> - psr->last_entry_attempt);
>> - seq_printf(m, "Last exit at: %lld\n", psr-
>> >last_exit);
>> - }
>> -
>> - if (psr->psr2_enabled) {
>> - u32 su_frames_val[3];
>> - int frame;
>> -
>> - /*
>> - * Reading all 3 registers before hand to minimize
>> crossing a
>> - * frame boundary between register reads
>> - */
>> - for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame
>> += 3) {
>> - val = intel_de_read(dev_priv,
>> - PSR2_SU_STATUS(intel_dp-
>> >psr.transcoder, frame));
>> - su_frames_val[frame / 3] = val;
>> - }
>> -
>> - seq_puts(m, "Frame:\tPSR2 SU blocks:\n");
>> -
>> - for (frame = 0; frame < PSR2_SU_STATUS_FRAMES;
>> frame++) {
>> - u32 su_blocks;
>> -
>> - su_blocks = su_frames_val[frame / 3] &
>> - PSR2_SU_STATUS_MASK(frame);
>> - su_blocks = su_blocks >>
>> PSR2_SU_STATUS_SHIFT(frame);
>> - seq_printf(m, "%d\t%d\n", frame, su_blocks);
>> - }
>> -
>> - seq_printf(m, "PSR2 selective fetch: %s\n",
>> - str_enabled_disabled(psr-
>> >psr2_sel_fetch_enabled));
>> - }
>> -
>> -unlock:
>> - mutex_unlock(&psr->lock);
>> - intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
>> -
>> - return 0;
>> -}
>> -
>> -static int i915_edp_psr_status(struct seq_file *m, void *data)
>> -{
>> - struct drm_i915_private *dev_priv = node_to_i915(m->private);
>> - struct intel_dp *intel_dp = NULL;
>> - struct intel_encoder *encoder;
>> -
>> - if (!HAS_PSR(dev_priv))
>> - return -ENODEV;
>> -
>> - /* Find the first EDP which supports PSR */
>> - for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
>> - intel_dp = enc_to_intel_dp(encoder);
>> - break;
>> - }
>> -
>> - if (!intel_dp)
>> - return -ENODEV;
>> -
>> - return intel_psr_status(m, intel_dp);
>> -}
>> -
>> -static int
>> -i915_edp_psr_debug_set(void *data, u64 val)
>> -{
>> - struct drm_i915_private *dev_priv = data;
>> - struct intel_encoder *encoder;
>> - intel_wakeref_t wakeref;
>> - int ret = -ENODEV;
>> -
>> - if (!HAS_PSR(dev_priv))
>> - return ret;
>> -
>> - for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
>> - struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>> -
>> - drm_dbg_kms(&dev_priv->drm, "Setting PSR debug to
>> %llx\n", val);
>> -
>> - wakeref = intel_runtime_pm_get(&dev_priv-
>> >runtime_pm);
>> -
>> - // TODO: split to each transcoder's PSR debug state
>> - ret = intel_psr_debug_set(intel_dp, val);
>> -
>> - intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
>> - }
>> -
>> - return ret;
>> -}
>> -
>> -static int
>> -i915_edp_psr_debug_get(void *data, u64 *val)
>> -{
>> - struct drm_i915_private *dev_priv = data;
>> - struct intel_encoder *encoder;
>> -
>> - if (!HAS_PSR(dev_priv))
>> - return -ENODEV;
>> -
>> - for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
>> - struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>> -
>> - // TODO: split to each transcoder's PSR debug state
>> - *val = READ_ONCE(intel_dp->psr.debug);
>> - return 0;
>> - }
>> -
>> - return -ENODEV;
>> -}
>> -
>> -DEFINE_SIMPLE_ATTRIBUTE(i915_edp_psr_debug_fops,
>> - i915_edp_psr_debug_get,
>> i915_edp_psr_debug_set,
>> - "%llu\n");
>> -
>> static int i915_power_domain_info(struct seq_file *m, void *unused)
>> {
>> struct drm_i915_private *i915 = node_to_i915(m->private);
>> @@ -1320,7 +1057,6 @@ static const struct drm_info_list
>> intel_display_debugfs_list[] = {
>> {"i915_opregion", i915_opregion, 0},
>> {"i915_vbt", i915_vbt, 0},
>> {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
>> - {"i915_edp_psr_status", i915_edp_psr_status, 0},
>> {"i915_power_domain_info", i915_power_domain_info, 0},
>> {"i915_display_info", i915_display_info, 0},
>> {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
>> @@ -1337,7 +1073,6 @@ static const struct {
>> {"i915_dp_test_data", &i915_displayport_test_data_fops},
>> {"i915_dp_test_type", &i915_displayport_test_type_fops},
>> {"i915_dp_test_active", &i915_displayport_test_active_fops},
>> - {"i915_edp_psr_debug", &i915_edp_psr_debug_fops},
>> };
>>
>> void intel_display_debugfs_register(struct drm_i915_private *i915)
>> @@ -1361,6 +1096,7 @@ void intel_display_debugfs_register(struct
>> drm_i915_private *i915)
>> intel_dmc_debugfs_register(i915);
>> intel_fbc_debugfs_register(i915);
>> intel_hpd_debugfs_register(i915);
>> + intel_psr_debugfs_register(i915);
>> intel_wm_debugfs_register(i915);
>> }
>>
>> @@ -1413,16 +1149,6 @@ static int
>> i915_hdcp_sink_capability_show(struct seq_file *m, void *data)
>> }
>> DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability);
>>
>> -static int i915_psr_status_show(struct seq_file *m, void *data)
>> -{
>> - struct drm_connector *connector = m->private;
>> - struct intel_dp *intel_dp =
>> - intel_attached_dp(to_intel_connector(connector));
>> -
>> - return intel_psr_status(m, intel_dp);
>> -}
>> -DEFINE_SHOW_ATTRIBUTE(i915_psr_status);
>> -
>> static int i915_lpsp_capability_show(struct seq_file *m, void *data)
>> {
>> struct drm_connector *connector = m->private;
>> @@ -1675,19 +1401,11 @@ void intel_connector_debugfs_add(struct
>> intel_connector *intel_connector)
>> return;
>>
>> intel_drrs_connector_debugfs_add(intel_connector);
>> + intel_psr_connector_debugfs_add(intel_connector);
>>
>> - if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
>> + if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
>> debugfs_create_file("i915_panel_timings", S_IRUGO,
>> root,
>> connector, &i915_panel_fops);
>> - debugfs_create_file("i915_psr_sink_status", S_IRUGO,
>> root,
>> - connector,
>> &i915_psr_sink_status_fops);
>> - }
>> -
>> - if (HAS_PSR(dev_priv) &&
>> - connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
>> - debugfs_create_file("i915_psr_status", 0444, root,
>> - connector,
>> &i915_psr_status_fops);
>> - }
>>
>> if (connector->connector_type ==
>> DRM_MODE_CONNECTOR_DisplayPort ||
>> connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
>> b/drivers/gpu/drm/i915/display/intel_psr.c
>> index 44610b20cd29..9d3205d99b54 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>> @@ -2644,3 +2644,305 @@ void intel_psr_unlock(const struct
>> intel_crtc_state *crtc_state)
>> break;
>> }
>> }
>> +
>> +static void
>> +psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
>> +{
>> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>> + const char *status = "unknown";
>> + u32 val, status_val;
>> +
>> + if (intel_dp->psr.psr2_enabled) {
>> + static const char * const live_status[] = {
>> + "IDLE",
>> + "CAPTURE",
>> + "CAPTURE_FS",
>> + "SLEEP",
>> + "BUFON_FW",
>> + "ML_UP",
>> + "SU_STANDBY",
>> + "FAST_SLEEP",
>> + "DEEP_SLEEP",
>> + "BUF_ON",
>> + "TG_ON"
>> + };
>> + val = intel_de_read(dev_priv,
>> + EDP_PSR2_STATUS(intel_dp-
>> >psr.transcoder));
>> + status_val =
>> REG_FIELD_GET(EDP_PSR2_STATUS_STATE_MASK, val);
>> + if (status_val < ARRAY_SIZE(live_status))
>> + status = live_status[status_val];
>> + } else {
>> + static const char * const live_status[] = {
>> + "IDLE",
>> + "SRDONACK",
>> + "SRDENT",
>> + "BUFOFF",
>> + "BUFON",
>> + "AUXACK",
>> + "SRDOFFACK",
>> + "SRDENT_ON",
>> + };
>> + val = intel_de_read(dev_priv,
>> + EDP_PSR_STATUS(intel_dp-
>> >psr.transcoder));
>> + status_val = (val & EDP_PSR_STATUS_STATE_MASK) >>
>> + EDP_PSR_STATUS_STATE_SHIFT;
>> + if (status_val < ARRAY_SIZE(live_status))
>> + status = live_status[status_val];
>> + }
>> +
>> + seq_printf(m, "Source PSR status: %s [0x%08x]\n", status,
>> val);
>> +}
>> +
>> +static int intel_psr_status(struct seq_file *m, struct intel_dp
>> *intel_dp)
>> +{
>> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>> + struct intel_psr *psr = &intel_dp->psr;
>> + intel_wakeref_t wakeref;
>> + const char *status;
>> + bool enabled;
>> + u32 val;
>> +
>> + seq_printf(m, "Sink support: %s", str_yes_no(psr-
>> >sink_support));
>> + if (psr->sink_support)
>> + seq_printf(m, " [0x%02x]", intel_dp->psr_dpcd[0]);
>> + seq_puts(m, "\n");
>> +
>> + if (!psr->sink_support)
>> + return 0;
>> +
>> + wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
>> + mutex_lock(&psr->lock);
>> +
>> + if (psr->enabled)
>> + status = psr->psr2_enabled ? "PSR2 enabled" : "PSR1
>> enabled";
>> + else
>> + status = "disabled";
>> + seq_printf(m, "PSR mode: %s\n", status);
>> +
>> + if (!psr->enabled) {
>> + seq_printf(m, "PSR sink not reliable: %s\n",
>> + str_yes_no(psr->sink_not_reliable));
>> +
>> + goto unlock;
>> + }
>> +
>> + if (psr->psr2_enabled) {
>> + val = intel_de_read(dev_priv,
>> + EDP_PSR2_CTL(intel_dp-
>> >psr.transcoder));
>> + enabled = val & EDP_PSR2_ENABLE;
>> + } else {
>> + val = intel_de_read(dev_priv,
>> + EDP_PSR_CTL(intel_dp-
>> >psr.transcoder));
>> + enabled = val & EDP_PSR_ENABLE;
>> + }
>> + seq_printf(m, "Source PSR ctl: %s [0x%08x]\n",
>> + str_enabled_disabled(enabled), val);
>> + psr_source_status(intel_dp, m);
>> + seq_printf(m, "Busy frontbuffer bits: 0x%08x\n",
>> + psr->busy_frontbuffer_bits);
>> +
>> + /*
>> + * SKL+ Perf counter is reset to 0 everytime DC state is
>> entered
>> + */
>> + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
>> + val = intel_de_read(dev_priv,
>> + EDP_PSR_PERF_CNT(intel_dp-
>> >psr.transcoder));
>> + val &= EDP_PSR_PERF_CNT_MASK;
>> + seq_printf(m, "Performance counter: %u\n", val);
>> + }
>> +
>> + if (psr->debug & I915_PSR_DEBUG_IRQ) {
>> + seq_printf(m, "Last attempted entry at: %lld\n",
>> + psr->last_entry_attempt);
>> + seq_printf(m, "Last exit at: %lld\n", psr-
>> >last_exit);
>> + }
>> +
>> + if (psr->psr2_enabled) {
>> + u32 su_frames_val[3];
>> + int frame;
>> +
>> + /*
>> + * Reading all 3 registers before hand to minimize
>> crossing a
>> + * frame boundary between register reads
>> + */
>> + for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame
>> += 3) {
>> + val = intel_de_read(dev_priv,
>> + PSR2_SU_STATUS(intel_dp-
>> >psr.transcoder, frame));
>> + su_frames_val[frame / 3] = val;
>> + }
>> +
>> + seq_puts(m, "Frame:\tPSR2 SU blocks:\n");
>> +
>> + for (frame = 0; frame < PSR2_SU_STATUS_FRAMES;
>> frame++) {
>> + u32 su_blocks;
>> +
>> + su_blocks = su_frames_val[frame / 3] &
>> + PSR2_SU_STATUS_MASK(frame);
>> + su_blocks = su_blocks >>
>> PSR2_SU_STATUS_SHIFT(frame);
>> + seq_printf(m, "%d\t%d\n", frame, su_blocks);
>> + }
>> +
>> + seq_printf(m, "PSR2 selective fetch: %s\n",
>> + str_enabled_disabled(psr-
>> >psr2_sel_fetch_enabled));
>> + }
>> +
>> +unlock:
>> + mutex_unlock(&psr->lock);
>> + intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
>> +
>> + return 0;
>> +}
>> +
>> +static int i915_edp_psr_status_show(struct seq_file *m, void *data)
>> +{
>> + struct drm_i915_private *dev_priv = m->private;
>> + struct intel_dp *intel_dp = NULL;
>> + struct intel_encoder *encoder;
>> +
>> + if (!HAS_PSR(dev_priv))
>> + return -ENODEV;
>> +
>> + /* Find the first EDP which supports PSR */
>> + for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
>> + intel_dp = enc_to_intel_dp(encoder);
>> + break;
>> + }
>> +
>> + if (!intel_dp)
>> + return -ENODEV;
>> +
>> + return intel_psr_status(m, intel_dp);
>> +}
>> +DEFINE_SHOW_ATTRIBUTE(i915_edp_psr_status);
>> +
>> +static int
>> +i915_edp_psr_debug_set(void *data, u64 val)
>> +{
>> + struct drm_i915_private *dev_priv = data;
>> + struct intel_encoder *encoder;
>> + intel_wakeref_t wakeref;
>> + int ret = -ENODEV;
>> +
>> + if (!HAS_PSR(dev_priv))
>> + return ret;
>> +
>> + for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
>> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>> +
>> + drm_dbg_kms(&dev_priv->drm, "Setting PSR debug to
>> %llx\n", val);
>> +
>> + wakeref = intel_runtime_pm_get(&dev_priv-
>> >runtime_pm);
>> +
>> + // TODO: split to each transcoder's PSR debug state
>> + ret = intel_psr_debug_set(intel_dp, val);
>> +
>> + intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
>> + }
>> +
>> + return ret;
>> +}
>> +
>> +static int
>> +i915_edp_psr_debug_get(void *data, u64 *val)
>> +{
>> + struct drm_i915_private *dev_priv = data;
>> + struct intel_encoder *encoder;
>> +
>> + if (!HAS_PSR(dev_priv))
>> + return -ENODEV;
>> +
>> + for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
>> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>> +
>> + // TODO: split to each transcoder's PSR debug state
>> + *val = READ_ONCE(intel_dp->psr.debug);
>> + return 0;
>> + }
>> +
>> + return -ENODEV;
>> +}
>> +
>> +DEFINE_SIMPLE_ATTRIBUTE(i915_edp_psr_debug_fops,
>> + i915_edp_psr_debug_get,
>> i915_edp_psr_debug_set,
>> + "%llu\n");
>> +
>> +void intel_psr_debugfs_register(struct drm_i915_private *i915)
>> +{
>> + struct drm_minor *minor = i915->drm.primary;
>> +
>> + debugfs_create_file("i915_edp_psr_debug", 0644, minor-
>> >debugfs_root,
>> + i915, &i915_edp_psr_debug_fops);
>> +
>> + debugfs_create_file("i915_edp_psr_status", 0444, minor-
>> >debugfs_root,
>> + i915, &i915_edp_psr_status_fops);
>> +}
>> +
>> +static int i915_psr_sink_status_show(struct seq_file *m, void *data)
>> +{
>> + u8 val;
>> + static const char * const sink_status[] = {
>> + "inactive",
>> + "transition to active, capture and display",
>> + "active, display from RFB",
>> + "active, capture and display on sink device timings",
>> + "transition to inactive, capture and display, timing
>> re-sync",
>> + "reserved",
>> + "reserved",
>> + "sink internal error",
>> + };
>> + struct drm_connector *connector = m->private;
>> + struct intel_dp *intel_dp =
>> + intel_attached_dp(to_intel_connector(connector));
>> + int ret;
>> +
>> + if (!CAN_PSR(intel_dp)) {
>> + seq_puts(m, "PSR Unsupported\n");
>> + return -ENODEV;
>> + }
>> +
>> + if (connector->status != connector_status_connected)
>> + return -ENODEV;
>> +
>> + ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val);
>> +
>> + if (ret == 1) {
>> + const char *str = "unknown";
>> +
>> + val &= DP_PSR_SINK_STATE_MASK;
>> + if (val < ARRAY_SIZE(sink_status))
>> + str = sink_status[val];
>> + seq_printf(m, "Sink PSR status: 0x%x [%s]\n", val,
>> str);
>> + } else {
>> + return ret;
>> + }
>> +
>> + return 0;
>> +}
>> +DEFINE_SHOW_ATTRIBUTE(i915_psr_sink_status);
>> +
>> +static int i915_psr_status_show(struct seq_file *m, void *data)
>> +{
>> + struct drm_connector *connector = m->private;
>> + struct intel_dp *intel_dp =
>> + intel_attached_dp(to_intel_connector(connector));
>> +
>> + return intel_psr_status(m, intel_dp);
>> +}
>> +DEFINE_SHOW_ATTRIBUTE(i915_psr_status);
>> +
>> +void intel_psr_connector_debugfs_add(struct intel_connector
>> *intel_connector)
>> +{
>> + struct drm_connector *connector = &intel_connector->base;
>> + struct drm_i915_private *i915 = to_i915(connector->dev);
>> + struct dentry *root = connector->debugfs_entry;
>> +
>> + if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
>> + return;
>> +
>> + debugfs_create_file("i915_psr_sink_status", 0444, root,
>> + connector, &i915_psr_sink_status_fops);
>> +
>> + if (HAS_PSR(i915))
>> + debugfs_create_file("i915_psr_status", 0444, root,
>> + connector,
>> &i915_psr_status_fops);
>> +}
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
>> b/drivers/gpu/drm/i915/display/intel_psr.h
>> index 7a38a9e7fa5b..0b95e8aa615f 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr.h
>> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
>> @@ -13,6 +13,7 @@ struct drm_connector;
>> struct drm_connector_state;
>> struct drm_i915_private;
>> struct intel_atomic_state;
>> +struct intel_connector;
>> struct intel_crtc;
>> struct intel_crtc_state;
>> struct intel_dp;
>> @@ -61,5 +62,7 @@ void intel_psr_resume(struct intel_dp *intel_dp);
>>
>> void intel_psr_lock(const struct intel_crtc_state *crtc_state);
>> void intel_psr_unlock(const struct intel_crtc_state *crtc_state);
>> +void intel_psr_connector_debugfs_add(struct intel_connector
>> *connector);
>> +void intel_psr_debugfs_register(struct drm_i915_private *i915);
>>
>> #endif /* __INTEL_PSR_H__ */
>
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2023-03-20 10:14 UTC | newest]
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2023-03-17 13:41 [Intel-gfx] [PATCH 1/3] drm/i915/psr: move PSR debugfs to intel_psr.c Jani Nikula
2023-03-17 13:41 ` [Intel-gfx] [PATCH 2/3] drm/i915/psr: switch PSR debugfs to struct intel_connector Jani Nikula
2023-03-20 8:50 ` Hogander, Jouni
2023-03-17 13:41 ` [Intel-gfx] [PATCH 3/3] drm/i915/psr: clean up PSR debugfs sink status error handling Jani Nikula
2023-03-20 8:50 ` Hogander, Jouni
2023-03-17 18:07 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/psr: move PSR debugfs to intel_psr.c Patchwork
2023-03-17 18:07 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-03-17 18:07 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2023-03-17 18:20 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-03-17 20:54 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2023-03-20 8:50 ` [Intel-gfx] [PATCH 1/3] " Hogander, Jouni
2023-03-20 10:14 ` Jani Nikula
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