* [Intel-gfx] [PATCH] drm/i915: sync I915_PMU_MAX_GTS to I915_MAX_GT
@ 2023-05-31 21:35 Matt Atwood
2023-05-31 21:48 ` Andi Shyti
` (4 more replies)
0 siblings, 5 replies; 15+ messages in thread
From: Matt Atwood @ 2023-05-31 21:35 UTC (permalink / raw)
To: intel-gfx
Set I915_PMU_MAX_GTS to value in I915_MAX_GT, theres no reason for these
values to be different.
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
---
drivers/gpu/drm/i915/i915_pmu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h
index 33d80fbaab8b..aa929d8c224a 100644
--- a/drivers/gpu/drm/i915/i915_pmu.h
+++ b/drivers/gpu/drm/i915/i915_pmu.h
@@ -38,7 +38,7 @@ enum {
__I915_NUM_PMU_SAMPLERS
};
-#define I915_PMU_MAX_GTS 2
+#define I915_PMU_MAX_GTS 4
/*
* How many different events we track in the global PMU mask.
--
2.40.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: sync I915_PMU_MAX_GTS to I915_MAX_GT
2023-05-31 21:35 [Intel-gfx] [PATCH] drm/i915: sync I915_PMU_MAX_GTS to I915_MAX_GT Matt Atwood
@ 2023-05-31 21:48 ` Andi Shyti
2023-05-31 22:07 ` Matt Atwood
2023-06-01 1:32 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for " Patchwork
` (3 subsequent siblings)
4 siblings, 1 reply; 15+ messages in thread
From: Andi Shyti @ 2023-05-31 21:48 UTC (permalink / raw)
To: Matt Atwood; +Cc: intel-gfx
Hi Matt,
On Wed, May 31, 2023 at 02:35:47PM -0700, Matt Atwood wrote:
> Set I915_PMU_MAX_GTS to value in I915_MAX_GT, theres no reason for these
> values to be different.
>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> ---
> drivers/gpu/drm/i915/i915_pmu.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h
> index 33d80fbaab8b..aa929d8c224a 100644
> --- a/drivers/gpu/drm/i915/i915_pmu.h
> +++ b/drivers/gpu/drm/i915/i915_pmu.h
> @@ -38,7 +38,7 @@ enum {
> __I915_NUM_PMU_SAMPLERS
> };
>
> -#define I915_PMU_MAX_GTS 2
> +#define I915_PMU_MAX_GTS 4
right! Why not having
#define I915_PMU_MAX_GTS I915_MAX_GT
or... why having I915_PMU_MAX_GTS at all?
Andi
> /*
> * How many different events we track in the global PMU mask.
> --
> 2.40.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: sync I915_PMU_MAX_GTS to I915_MAX_GT
2023-05-31 21:48 ` Andi Shyti
@ 2023-05-31 22:07 ` Matt Atwood
2023-05-31 22:15 ` Andi Shyti
0 siblings, 1 reply; 15+ messages in thread
From: Matt Atwood @ 2023-05-31 22:07 UTC (permalink / raw)
To: Andi Shyti, intel-gfx; +Cc: intel-gfx
On Wed, May 31, 2023 at 11:48:33PM +0200, Andi Shyti wrote:
> Hi Matt,
>
> On Wed, May 31, 2023 at 02:35:47PM -0700, Matt Atwood wrote:
> > Set I915_PMU_MAX_GTS to value in I915_MAX_GT, theres no reason for these
> > values to be different.
> >
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> > Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> > Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_pmu.h | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h
> > index 33d80fbaab8b..aa929d8c224a 100644
> > --- a/drivers/gpu/drm/i915/i915_pmu.h
> > +++ b/drivers/gpu/drm/i915/i915_pmu.h
> > @@ -38,7 +38,7 @@ enum {
> > __I915_NUM_PMU_SAMPLERS
> > };
> >
> > -#define I915_PMU_MAX_GTS 2
> > +#define I915_PMU_MAX_GTS 4
>
> right! Why not having
>
> #define I915_PMU_MAX_GTS I915_MAX_GT
>
> or... why having I915_PMU_MAX_GTS at all?
Originally I went the route of s/I915_PMU_MAX_GTS/I915_MAX_GT/g.
However, this introduces many changes to where you then move
I915_MAX_GT to and #include blocks in fiels that require these values.
In the end I decided it was better to keep define and just change the
value.
>
> Andi
>
> > /*
> > * How many different events we track in the global PMU mask.
> > --
> > 2.40.0
MattA
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: sync I915_PMU_MAX_GTS to I915_MAX_GT
2023-05-31 22:07 ` Matt Atwood
@ 2023-05-31 22:15 ` Andi Shyti
2023-06-01 17:40 ` Andi Shyti
0 siblings, 1 reply; 15+ messages in thread
From: Andi Shyti @ 2023-05-31 22:15 UTC (permalink / raw)
To: Matt Atwood; +Cc: intel-gfx
Hi Matt,
On Wed, May 31, 2023 at 03:07:22PM -0700, Matt Atwood wrote:
> On Wed, May 31, 2023 at 11:48:33PM +0200, Andi Shyti wrote:
> > Hi Matt,
> >
> > On Wed, May 31, 2023 at 02:35:47PM -0700, Matt Atwood wrote:
> > > Set I915_PMU_MAX_GTS to value in I915_MAX_GT, theres no reason for these
> > > values to be different.
> > >
> > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> > > Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> > > Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/i915_pmu.h | 2 +-
> > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h
> > > index 33d80fbaab8b..aa929d8c224a 100644
> > > --- a/drivers/gpu/drm/i915/i915_pmu.h
> > > +++ b/drivers/gpu/drm/i915/i915_pmu.h
> > > @@ -38,7 +38,7 @@ enum {
> > > __I915_NUM_PMU_SAMPLERS
> > > };
> > >
> > > -#define I915_PMU_MAX_GTS 2
> > > +#define I915_PMU_MAX_GTS 4
> >
> > right! Why not having
> >
> > #define I915_PMU_MAX_GTS I915_MAX_GT
> >
> > or... why having I915_PMU_MAX_GTS at all?
> Originally I went the route of s/I915_PMU_MAX_GTS/I915_MAX_GT/g.
> However, this introduces many changes to where you then move
> I915_MAX_GT to and #include blocks in fiels that require these values.
> In the end I decided it was better to keep define and just change the
> value.
OK, makes sense, then how about
#define I915_PMU_MAX_GTS I915_MAX_GT
i915_pmu.h has visibility on I915_MAX_GT.
Andi
> >
> > Andi
> >
> > > /*
> > > * How many different events we track in the global PMU mask.
> > > --
> > > 2.40.0
> MattA
^ permalink raw reply [flat|nested] 15+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: sync I915_PMU_MAX_GTS to I915_MAX_GT
2023-05-31 21:35 [Intel-gfx] [PATCH] drm/i915: sync I915_PMU_MAX_GTS to I915_MAX_GT Matt Atwood
2023-05-31 21:48 ` Andi Shyti
@ 2023-06-01 1:32 ` Patchwork
2023-06-01 1:46 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
4 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2023-06-01 1:32 UTC (permalink / raw)
To: Matt Atwood; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: sync I915_PMU_MAX_GTS to I915_MAX_GT
URL : https://patchwork.freedesktop.org/series/118672/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 15+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: sync I915_PMU_MAX_GTS to I915_MAX_GT
2023-05-31 21:35 [Intel-gfx] [PATCH] drm/i915: sync I915_PMU_MAX_GTS to I915_MAX_GT Matt Atwood
2023-05-31 21:48 ` Andi Shyti
2023-06-01 1:32 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for " Patchwork
@ 2023-06-01 1:46 ` Patchwork
2023-06-01 18:22 ` [Intel-gfx] [PATCH] " Dixit, Ashutosh
2023-06-02 16:19 ` [Intel-gfx] ✓ Fi.CI.IGT: success for " Patchwork
4 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2023-06-01 1:46 UTC (permalink / raw)
To: Matt Atwood; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 7785 bytes --]
== Series Details ==
Series: drm/i915: sync I915_PMU_MAX_GTS to I915_MAX_GT
URL : https://patchwork.freedesktop.org/series/118672/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13210 -> Patchwork_118672v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/index.html
Participating hosts (37 -> 38)
------------------------------
Additional (1): fi-kbl-soraka
Known issues
------------
Here are the changes found in Patchwork_118672v1 that come from known issues:
### CI changes ###
#### Possible fixes ####
* boot:
- fi-kbl-8809g: [FAIL][1] ([i915#8293] / [i915#8298]) -> [PASS][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13210/fi-kbl-8809g/boot.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/fi-kbl-8809g/boot.html
### IGT changes ###
#### Issues hit ####
* igt@core_hotunplug@unbind-rebind:
- fi-kbl-8809g: NOTRUN -> [ABORT][3] ([i915#8298] / [i915#8299] / [i915#8397])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/fi-kbl-8809g/igt@core_hotunplug@unbind-rebind.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-8809g: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/fi-kbl-8809g/igt@gem_huc_copy@huc-copy.html
- fi-kbl-soraka: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613]) +3 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/fi-kbl-soraka/igt@gem_lmem_swapping@basic.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-hsw-4770: [PASS][7] -> [SKIP][8] ([fdo#109271])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13210/fi-hsw-4770/igt@i915_pm_rpm@basic-pci-d3-state.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/fi-hsw-4770/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@i915_pm_rpm@basic-rte:
- fi-hsw-4770: [PASS][9] -> [FAIL][10] ([i915#7364])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13210/fi-hsw-4770/igt@i915_pm_rpm@basic-rte.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/fi-hsw-4770/igt@i915_pm_rpm@basic-rte.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][11] ([i915#1886] / [i915#7913])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@reset:
- bat-rpls-1: [PASS][12] -> [ABORT][13] ([i915#4983] / [i915#7461] / [i915#8347] / [i915#8384])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13210/bat-rpls-1/igt@i915_selftest@live@reset.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/bat-rpls-1/igt@i915_selftest@live@reset.html
* igt@i915_suspend@basic-s2idle-without-i915:
- bat-rpls-2: NOTRUN -> [ABORT][14] ([i915#6687])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/bat-rpls-2/igt@i915_suspend@basic-s2idle-without-i915.html
* igt@kms_addfb_basic@too-high:
- fi-kbl-8809g: NOTRUN -> [FAIL][15] ([i915#8296]) +2 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/fi-kbl-8809g/igt@kms_addfb_basic@too-high.html
* igt@kms_chamelium_frames@hdmi-crc-fast:
- fi-kbl-soraka: NOTRUN -> [SKIP][16] ([fdo#109271]) +14 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/fi-kbl-soraka/igt@kms_chamelium_frames@hdmi-crc-fast.html
* igt@kms_force_connector_basic@force-connector-state:
- fi-kbl-8809g: NOTRUN -> [DMESG-FAIL][17] ([i915#8299])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/fi-kbl-8809g/igt@kms_force_connector_basic@force-connector-state.html
* igt@kms_force_connector_basic@force-edid:
- fi-kbl-8809g: NOTRUN -> [CRASH][18] ([i915#8299])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/fi-kbl-8809g/igt@kms_force_connector_basic@force-edid.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-d-dp-1:
- bat-dg2-8: [PASS][19] -> [FAIL][20] ([i915#7932])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13210/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-d-dp-1.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-d-dp-1.html
* igt@kms_psr@cursor_plane_move:
- fi-kbl-8809g: NOTRUN -> [SKIP][21] ([fdo#109271]) +59 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/fi-kbl-8809g/igt@kms_psr@cursor_plane_move.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-kbl-soraka: NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#4579])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/fi-kbl-soraka/igt@kms_setmode@basic-clone-single-crtc.html
- fi-kbl-8809g: NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#4579])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/fi-kbl-8809g/igt@kms_setmode@basic-clone-single-crtc.html
#### Possible fixes ####
* igt@i915_selftest@live@reset:
- bat-rpls-2: [ABORT][24] ([i915#4983] / [i915#7461] / [i915#7913] / [i915#7981] / [i915#8347]) -> [PASS][25]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13210/bat-rpls-2/igt@i915_selftest@live@reset.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/bat-rpls-2/igt@i915_selftest@live@reset.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
[i915#7364]: https://gitlab.freedesktop.org/drm/intel/issues/7364
[i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932
[i915#7981]: https://gitlab.freedesktop.org/drm/intel/issues/7981
[i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293
[i915#8296]: https://gitlab.freedesktop.org/drm/intel/issues/8296
[i915#8298]: https://gitlab.freedesktop.org/drm/intel/issues/8298
[i915#8299]: https://gitlab.freedesktop.org/drm/intel/issues/8299
[i915#8347]: https://gitlab.freedesktop.org/drm/intel/issues/8347
[i915#8384]: https://gitlab.freedesktop.org/drm/intel/issues/8384
[i915#8397]: https://gitlab.freedesktop.org/drm/intel/issues/8397
Build changes
-------------
* Linux: CI_DRM_13210 -> Patchwork_118672v1
CI-20190529: 20190529
CI_DRM_13210: a66da4c33d8ede541aea9ba6d0d73b556a072d54 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7314: ab70dfcdecf93a17fcaddb774855f726325fa0dd @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_118672v1: a66da4c33d8ede541aea9ba6d0d73b556a072d54 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
1f0a697cb630 drm/i915: sync I915_PMU_MAX_GTS to I915_MAX_GT
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/index.html
[-- Attachment #2: Type: text/html, Size: 9879 bytes --]
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: sync I915_PMU_MAX_GTS to I915_MAX_GT
2023-05-31 22:15 ` Andi Shyti
@ 2023-06-01 17:40 ` Andi Shyti
0 siblings, 0 replies; 15+ messages in thread
From: Andi Shyti @ 2023-06-01 17:40 UTC (permalink / raw)
To: Andi Shyti; +Cc: intel-gfx
Hi Matt,
> > > > --- a/drivers/gpu/drm/i915/i915_pmu.h
> > > > +++ b/drivers/gpu/drm/i915/i915_pmu.h
> > > > @@ -38,7 +38,7 @@ enum {
> > > > __I915_NUM_PMU_SAMPLERS
> > > > };
> > > >
> > > > -#define I915_PMU_MAX_GTS 2
> > > > +#define I915_PMU_MAX_GTS 4
> > >
> > > right! Why not having
> > >
> > > #define I915_PMU_MAX_GTS I915_MAX_GT
> > >
> > > or... why having I915_PMU_MAX_GTS at all?
> > Originally I went the route of s/I915_PMU_MAX_GTS/I915_MAX_GT/g.
> > However, this introduces many changes to where you then move
> > I915_MAX_GT to and #include blocks in fiels that require these values.
> > In the end I decided it was better to keep define and just change the
> > value.
>
> OK, makes sense, then how about
>
> #define I915_PMU_MAX_GTS I915_MAX_GT
>
> i915_pmu.h has visibility on I915_MAX_GT.
ops... it doesn't... sorry!
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Andi
> Andi
>
> > >
> > > Andi
> > >
> > > > /*
> > > > * How many different events we track in the global PMU mask.
> > > > --
> > > > 2.40.0
> > MattA
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: sync I915_PMU_MAX_GTS to I915_MAX_GT
2023-05-31 21:35 [Intel-gfx] [PATCH] drm/i915: sync I915_PMU_MAX_GTS to I915_MAX_GT Matt Atwood
` (2 preceding siblings ...)
2023-06-01 1:46 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2023-06-01 18:22 ` Dixit, Ashutosh
2023-06-01 18:30 ` Dixit, Ashutosh
2023-06-01 18:52 ` Umesh Nerlige Ramappa
2023-06-02 16:19 ` [Intel-gfx] ✓ Fi.CI.IGT: success for " Patchwork
4 siblings, 2 replies; 15+ messages in thread
From: Dixit, Ashutosh @ 2023-06-01 18:22 UTC (permalink / raw)
To: Matt Atwood; +Cc: intel-gfx, Andi Shyti
On Wed, 31 May 2023 14:35:47 -0700, Matt Atwood wrote:
>
Hi Matt,
> Set I915_PMU_MAX_GTS to value in I915_MAX_GT, theres no reason for these
> values to be different.
>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
I don't believe the mailer actually Cc'd us. I just saw this and am Cc'ing
the people who authored/reviewed the previous series now.
> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> ---
> drivers/gpu/drm/i915/i915_pmu.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h
> index 33d80fbaab8b..aa929d8c224a 100644
> --- a/drivers/gpu/drm/i915/i915_pmu.h
> +++ b/drivers/gpu/drm/i915/i915_pmu.h
> @@ -38,7 +38,7 @@ enum {
> __I915_NUM_PMU_SAMPLERS
> };
>
> -#define I915_PMU_MAX_GTS 2
> +#define I915_PMU_MAX_GTS 4
This was a discussed during the previous review and it was decided to keep
the two values (I915_PMU_MAX_GTS and I915_MAX_GT) different. There are
currently no platforms and there will be no i915 supported platforms with
MAX_GT 4. So I prefer to leave the values as they currently are. Unless
Umesh or Tvrtko agrees to this patch.
Thanks.
--
Ashutosh
>
> /*
> * How many different events we track in the global PMU mask.
> --
> 2.40.0
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: sync I915_PMU_MAX_GTS to I915_MAX_GT
2023-06-01 18:22 ` [Intel-gfx] [PATCH] " Dixit, Ashutosh
@ 2023-06-01 18:30 ` Dixit, Ashutosh
2023-06-02 0:23 ` Dixit, Ashutosh
2023-06-01 18:52 ` Umesh Nerlige Ramappa
1 sibling, 1 reply; 15+ messages in thread
From: Dixit, Ashutosh @ 2023-06-01 18:30 UTC (permalink / raw)
To: Matt Atwood; +Cc: intel-gfx, Andi Shyti
On Thu, 01 Jun 2023 11:22:18 -0700, Dixit, Ashutosh wrote:
>
> On Wed, 31 May 2023 14:35:47 -0700, Matt Atwood wrote:
> >
>
> Hi Matt,
>
> > Set I915_PMU_MAX_GTS to value in I915_MAX_GT, theres no reason for these
> > values to be different.
Also, we can't be so sure so as to be able to say "theres no reason for
these values to be different" till we have actually verified it. E.g. there
are various bitfields in the code which might not fit in a u32 if we
increase MAX_GT from 2 to 4. Has this been verified?
If anything, to keep the code from doing unnecessary stuff, IMO I915_MAX_GT
should be reduced to 2 and should be increased to 4 only once/if we have
i915 supported platforms with 4 GT's.
Thanks.
--
Ashutosh
> >
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> > Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
>
> I don't believe the mailer actually Cc'd us. I just saw this and am Cc'ing
> the people who authored/reviewed the previous series now.
>
> > Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_pmu.h | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h
> > index 33d80fbaab8b..aa929d8c224a 100644
> > --- a/drivers/gpu/drm/i915/i915_pmu.h
> > +++ b/drivers/gpu/drm/i915/i915_pmu.h
> > @@ -38,7 +38,7 @@ enum {
> > __I915_NUM_PMU_SAMPLERS
> > };
> >
> > -#define I915_PMU_MAX_GTS 2
> > +#define I915_PMU_MAX_GTS 4
>
> This was a discussed during the previous review and it was decided to keep
> the two values (I915_PMU_MAX_GTS and I915_MAX_GT) different. There are
> currently no platforms and there will be no i915 supported platforms with
> MAX_GT 4. So I prefer to leave the values as they currently are. Unless
> Umesh or Tvrtko agrees to this patch.
>
> Thanks.
> --
> Ashutosh
>
> >
> > /*
> > * How many different events we track in the global PMU mask.
> > --
> > 2.40.0
> >
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: sync I915_PMU_MAX_GTS to I915_MAX_GT
2023-06-01 18:22 ` [Intel-gfx] [PATCH] " Dixit, Ashutosh
2023-06-01 18:30 ` Dixit, Ashutosh
@ 2023-06-01 18:52 ` Umesh Nerlige Ramappa
1 sibling, 0 replies; 15+ messages in thread
From: Umesh Nerlige Ramappa @ 2023-06-01 18:52 UTC (permalink / raw)
To: Dixit, Ashutosh; +Cc: Andi Shyti, intel-gfx
On Thu, Jun 01, 2023 at 11:22:18AM -0700, Dixit, Ashutosh wrote:
>On Wed, 31 May 2023 14:35:47 -0700, Matt Atwood wrote:
>>
>
>Hi Matt,
>
>> Set I915_PMU_MAX_GTS to value in I915_MAX_GT, theres no reason for these
>> values to be different.
>>
>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
>
>I don't believe the mailer actually Cc'd us. I just saw this and am Cc'ing
>the people who authored/reviewed the previous series now.
>
>> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_pmu.h | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h
>> index 33d80fbaab8b..aa929d8c224a 100644
>> --- a/drivers/gpu/drm/i915/i915_pmu.h
>> +++ b/drivers/gpu/drm/i915/i915_pmu.h
>> @@ -38,7 +38,7 @@ enum {
>> __I915_NUM_PMU_SAMPLERS
>> };
>>
>> -#define I915_PMU_MAX_GTS 2
>> +#define I915_PMU_MAX_GTS 4
>
>This was a discussed during the previous review and it was decided to keep
>the two values (I915_PMU_MAX_GTS and I915_MAX_GT) different. There are
>currently no platforms and there will be no i915 supported platforms with
>MAX_GT 4. So I prefer to leave the values as they currently are. Unless
>Umesh or Tvrtko agrees to this patch.
I would leave it as 2 since we specifically changed it to 2 (was 4
earlier) during review of the PMU multi tile support patches.
Thanks,
Umesh
>
>Thanks.
>--
>Ashutosh
>
>>
>> /*
>> * How many different events we track in the global PMU mask.
>> --
>> 2.40.0
>>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: sync I915_PMU_MAX_GTS to I915_MAX_GT
2023-06-01 18:30 ` Dixit, Ashutosh
@ 2023-06-02 0:23 ` Dixit, Ashutosh
2023-06-02 0:40 ` Andi Shyti
0 siblings, 1 reply; 15+ messages in thread
From: Dixit, Ashutosh @ 2023-06-02 0:23 UTC (permalink / raw)
To: Matt Atwood; +Cc: intel-gfx, Andi Shyti
On Thu, 01 Jun 2023 11:30:44 -0700, Dixit, Ashutosh wrote:
>
> On Thu, 01 Jun 2023 11:22:18 -0700, Dixit, Ashutosh wrote:
> >
> > On Wed, 31 May 2023 14:35:47 -0700, Matt Atwood wrote:
> > >
> >
> > Hi Matt,
> >
> > > Set I915_PMU_MAX_GTS to value in I915_MAX_GT, theres no reason for these
> > > values to be different.
>
> Also, we can't be so sure so as to be able to say "theres no reason for
> these values to be different" till we have actually verified it. E.g. there
> are various bitfields in the code which might not fit in a u32 if we
> increase MAX_GT from 2 to 4. Has this been verified?
>
> If anything, to keep the code from doing unnecessary stuff, IMO I915_MAX_GT
> should be reduced to 2 and should be increased to 4 only once/if we have
> i915 supported platforms with 4 GT's.
Matt explained the issue offline to me (it would have helped to explain the
reason for the patch in the commit message). The issue is that in uses of
for_each_gt such as below (there are others too in the PMU code):
for_each_gt(gt, i915, i) {
intel_wakeref_t wakeref;
with_intel_runtime_pm(gt->uncore->rpm, wakeref) {
u64 val = __get_rc6(gt);
store_sample(pmu, i, __I915_SAMPLE_RC6, val);
store_sample(pmu, i, __I915_SAMPLE_RC6_LAST_REPORTED,
val);
pmu->sleep_last[i] = ktime_get_raw();
}
}
static checkers are complaining that for_each_gt can read/write outside the
bounds of PMU arrays. Because absent gt's will be NULL in for_each_gt this
cannot really happen but we still need to keep static checkers happy.
So to resolve this issue we need I915_PMU_MAX_GTS and I915_MAX_GT to have
the same value. So either we need to increase I915_PMU_MAX_GTS to 4 or
reduce I915_MAX_GT to 2.
Regards,
Ashutosh
>
>
> > >
> > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> > > Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> >
> > I don't believe the mailer actually Cc'd us. I just saw this and am Cc'ing
> > the people who authored/reviewed the previous series now.
> >
> > > Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/i915_pmu.h | 2 +-
> > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h
> > > index 33d80fbaab8b..aa929d8c224a 100644
> > > --- a/drivers/gpu/drm/i915/i915_pmu.h
> > > +++ b/drivers/gpu/drm/i915/i915_pmu.h
> > > @@ -38,7 +38,7 @@ enum {
> > > __I915_NUM_PMU_SAMPLERS
> > > };
> > >
> > > -#define I915_PMU_MAX_GTS 2
> > > +#define I915_PMU_MAX_GTS 4
> >
> > This was a discussed during the previous review and it was decided to keep
> > the two values (I915_PMU_MAX_GTS and I915_MAX_GT) different. There are
> > currently no platforms and there will be no i915 supported platforms with
> > MAX_GT 4. So I prefer to leave the values as they currently are. Unless
> > Umesh or Tvrtko agrees to this patch.
> >
> > Thanks.
> > --
> > Ashutosh
> >
> > >
> > > /*
> > > * How many different events we track in the global PMU mask.
> > > --
> > > 2.40.0
> > >
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: sync I915_PMU_MAX_GTS to I915_MAX_GT
2023-06-02 0:23 ` Dixit, Ashutosh
@ 2023-06-02 0:40 ` Andi Shyti
2023-06-02 3:21 ` Dixit, Ashutosh
0 siblings, 1 reply; 15+ messages in thread
From: Andi Shyti @ 2023-06-02 0:40 UTC (permalink / raw)
To: Dixit, Ashutosh; +Cc: intel-gfx
Hi Ashutosh,
On Thu, Jun 01, 2023 at 05:23:24PM -0700, Dixit, Ashutosh wrote:
> On Thu, 01 Jun 2023 11:30:44 -0700, Dixit, Ashutosh wrote:
> >
> > On Thu, 01 Jun 2023 11:22:18 -0700, Dixit, Ashutosh wrote:
> > >
> > > On Wed, 31 May 2023 14:35:47 -0700, Matt Atwood wrote:
> > > >
> > >
> > > Hi Matt,
> > >
> > > > Set I915_PMU_MAX_GTS to value in I915_MAX_GT, theres no reason for these
> > > > values to be different.
> >
> > Also, we can't be so sure so as to be able to say "theres no reason for
> > these values to be different" till we have actually verified it. E.g. there
> > are various bitfields in the code which might not fit in a u32 if we
> > increase MAX_GT from 2 to 4. Has this been verified?
> >
> > If anything, to keep the code from doing unnecessary stuff, IMO I915_MAX_GT
> > should be reduced to 2 and should be increased to 4 only once/if we have
> > i915 supported platforms with 4 GT's.
>
> Matt explained the issue offline to me (it would have helped to explain the
> reason for the patch in the commit message). The issue is that in uses of
> for_each_gt such as below (there are others too in the PMU code):
>
> for_each_gt(gt, i915, i) {
> intel_wakeref_t wakeref;
>
> with_intel_runtime_pm(gt->uncore->rpm, wakeref) {
> u64 val = __get_rc6(gt);
>
> store_sample(pmu, i, __I915_SAMPLE_RC6, val);
> store_sample(pmu, i, __I915_SAMPLE_RC6_LAST_REPORTED,
> val);
> pmu->sleep_last[i] = ktime_get_raw();
> }
> }
>
> static checkers are complaining that for_each_gt can read/write outside the
> bounds of PMU arrays. Because absent gt's will be NULL in for_each_gt this
> cannot really happen but we still need to keep static checkers happy.
>
> So to resolve this issue we need I915_PMU_MAX_GTS and I915_MAX_GT to have
> the same value. So either we need to increase I915_PMU_MAX_GTS to 4 or
> reduce I915_MAX_GT to 2.
the number of GT's is a GPU concept and should remain as such all
over the GPU. If max GT is 4 then it should be 4 everywhere.
The I915_PMU_MAX_GTS define should not exist at all as it is
creating this sort of inconsistencies and everything should refer
to a single I915_MAX_GT. The reason for having I915_PMU_MAX_GTS,
in a first place, is purely practical to avoid over inclusions.
Still I consider it hacky.
On the other had, already I915_MAX_GT is a hardcoded value and
many times there have been discussions about removing it and
fetch it dynamically during the i915 boot. But this requires
quite a good amount of refactoring that no one is willing to do.
If we can't get rid of I915_PMU_MAX_GTS then I strongly believe
it should be aligned with I915_MAX_GT and for this reason I gave
my r-b. The use of for_each_gt() is a clear consequence of this
difference.
Thanks for chiming in,
Andi
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: sync I915_PMU_MAX_GTS to I915_MAX_GT
2023-06-02 0:40 ` Andi Shyti
@ 2023-06-02 3:21 ` Dixit, Ashutosh
2023-06-02 8:51 ` Andi Shyti
0 siblings, 1 reply; 15+ messages in thread
From: Dixit, Ashutosh @ 2023-06-02 3:21 UTC (permalink / raw)
To: Andi Shyti; +Cc: intel-gfx
On Thu, 01 Jun 2023 17:40:18 -0700, Andi Shyti wrote:
>
Hi Andi,
> On Thu, Jun 01, 2023 at 05:23:24PM -0700, Dixit, Ashutosh wrote:
> > On Thu, 01 Jun 2023 11:30:44 -0700, Dixit, Ashutosh wrote:
> > >
> > > On Thu, 01 Jun 2023 11:22:18 -0700, Dixit, Ashutosh wrote:
> > > >
> > > > On Wed, 31 May 2023 14:35:47 -0700, Matt Atwood wrote:
> > > > >
> > > >
> > > > Hi Matt,
> > > >
> > > > > Set I915_PMU_MAX_GTS to value in I915_MAX_GT, theres no reason for these
> > > > > values to be different.
> > >
> > > Also, we can't be so sure so as to be able to say "theres no reason for
> > > these values to be different" till we have actually verified it. E.g. there
> > > are various bitfields in the code which might not fit in a u32 if we
> > > increase MAX_GT from 2 to 4. Has this been verified?
> > >
> > > If anything, to keep the code from doing unnecessary stuff, IMO I915_MAX_GT
> > > should be reduced to 2 and should be increased to 4 only once/if we have
> > > i915 supported platforms with 4 GT's.
> >
> > Matt explained the issue offline to me (it would have helped to explain the
> > reason for the patch in the commit message). The issue is that in uses of
> > for_each_gt such as below (there are others too in the PMU code):
> >
> > for_each_gt(gt, i915, i) {
> > intel_wakeref_t wakeref;
> >
> > with_intel_runtime_pm(gt->uncore->rpm, wakeref) {
> > u64 val = __get_rc6(gt);
> >
> > store_sample(pmu, i, __I915_SAMPLE_RC6, val);
> > store_sample(pmu, i, __I915_SAMPLE_RC6_LAST_REPORTED,
> > val);
> > pmu->sleep_last[i] = ktime_get_raw();
> > }
> > }
> >
> > static checkers are complaining that for_each_gt can read/write outside the
> > bounds of PMU arrays. Because absent gt's will be NULL in for_each_gt this
> > cannot really happen but we still need to keep static checkers happy.
> >
> > So to resolve this issue we need I915_PMU_MAX_GTS and I915_MAX_GT to have
> > the same value. So either we need to increase I915_PMU_MAX_GTS to 4 or
> > reduce I915_MAX_GT to 2.
>
> the number of GT's is a GPU concept and should remain as such all
> over the GPU. If max GT is 4 then it should be 4 everywhere.
>
> The I915_PMU_MAX_GTS define should not exist at all as it is
> creating this sort of inconsistencies and everything should refer
> to a single I915_MAX_GT. The reason for having I915_PMU_MAX_GTS,
> in a first place, is purely practical to avoid over inclusions.
> Still I consider it hacky.
>
> On the other had, already I915_MAX_GT is a hardcoded value and
> many times there have been discussions about removing it and
> fetch it dynamically during the i915 boot. But this requires
> quite a good amount of refactoring that no one is willing to do.
>
> If we can't get rid of I915_PMU_MAX_GTS then I strongly believe
> it should be aligned with I915_MAX_GT and for this reason I gave
> my r-b. The use of for_each_gt() is a clear consequence of this
> difference.
Yes, not disagreeing. At this point I think my preferred solution is
something like:
#define I915_MAX_GT 2
#define I915_PMU_MAX_GTS I915_MAX_GT
Unless someone can explain why I915_MAX_GT cannot be 2. As I see it,
there's no need for I915_MAX_GT to be 4 after xehpsdv disappeared and
support for future platforms is moving to xe.
Thanks.
--
Ashutosh
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: sync I915_PMU_MAX_GTS to I915_MAX_GT
2023-06-02 3:21 ` Dixit, Ashutosh
@ 2023-06-02 8:51 ` Andi Shyti
0 siblings, 0 replies; 15+ messages in thread
From: Andi Shyti @ 2023-06-02 8:51 UTC (permalink / raw)
To: Dixit, Ashutosh; +Cc: intel-gfx
Hi Ashutosh,
> > > > > > Set I915_PMU_MAX_GTS to value in I915_MAX_GT, theres no reason for these
> > > > > > values to be different.
> > > >
> > > > Also, we can't be so sure so as to be able to say "theres no reason for
> > > > these values to be different" till we have actually verified it. E.g. there
> > > > are various bitfields in the code which might not fit in a u32 if we
> > > > increase MAX_GT from 2 to 4. Has this been verified?
> > > >
> > > > If anything, to keep the code from doing unnecessary stuff, IMO I915_MAX_GT
> > > > should be reduced to 2 and should be increased to 4 only once/if we have
> > > > i915 supported platforms with 4 GT's.
> > >
> > > Matt explained the issue offline to me (it would have helped to explain the
> > > reason for the patch in the commit message). The issue is that in uses of
> > > for_each_gt such as below (there are others too in the PMU code):
> > >
> > > for_each_gt(gt, i915, i) {
> > > intel_wakeref_t wakeref;
> > >
> > > with_intel_runtime_pm(gt->uncore->rpm, wakeref) {
> > > u64 val = __get_rc6(gt);
> > >
> > > store_sample(pmu, i, __I915_SAMPLE_RC6, val);
> > > store_sample(pmu, i, __I915_SAMPLE_RC6_LAST_REPORTED,
> > > val);
> > > pmu->sleep_last[i] = ktime_get_raw();
> > > }
> > > }
> > >
> > > static checkers are complaining that for_each_gt can read/write outside the
> > > bounds of PMU arrays. Because absent gt's will be NULL in for_each_gt this
> > > cannot really happen but we still need to keep static checkers happy.
> > >
> > > So to resolve this issue we need I915_PMU_MAX_GTS and I915_MAX_GT to have
> > > the same value. So either we need to increase I915_PMU_MAX_GTS to 4 or
> > > reduce I915_MAX_GT to 2.
> >
> > the number of GT's is a GPU concept and should remain as such all
> > over the GPU. If max GT is 4 then it should be 4 everywhere.
> >
> > The I915_PMU_MAX_GTS define should not exist at all as it is
> > creating this sort of inconsistencies and everything should refer
> > to a single I915_MAX_GT. The reason for having I915_PMU_MAX_GTS,
> > in a first place, is purely practical to avoid over inclusions.
> > Still I consider it hacky.
> >
> > On the other had, already I915_MAX_GT is a hardcoded value and
> > many times there have been discussions about removing it and
> > fetch it dynamically during the i915 boot. But this requires
> > quite a good amount of refactoring that no one is willing to do.
> >
> > If we can't get rid of I915_PMU_MAX_GTS then I strongly believe
> > it should be aligned with I915_MAX_GT and for this reason I gave
> > my r-b. The use of for_each_gt() is a clear consequence of this
> > difference.
>
> Yes, not disagreeing. At this point I think my preferred solution is
> something like:
>
> #define I915_MAX_GT 2
> #define I915_PMU_MAX_GTS I915_MAX_GT
#ifndef I915_MAX_GT
#define I915_MAX_GT 2
#endif
#define I915_PMU_MAX_GTS I915_MAX_GT
Side note: I915_PMU_MAX_GTS in plural is not the best of the
names as we don't really know what the 'S' stands for, is it
G.T.S. or GT's? MAX_GT is already intrinsically plural.
> Unless someone can explain why I915_MAX_GT cannot be 2. As I see it,
> there's no need for I915_MAX_GT to be 4 after xehpsdv disappeared and
> support for future platforms is moving to xe.
Nothing wrong, you can try sending a patch and kick-start a
discussion, let's also see what CI thinks about.
Andi
^ permalink raw reply [flat|nested] 15+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: sync I915_PMU_MAX_GTS to I915_MAX_GT
2023-05-31 21:35 [Intel-gfx] [PATCH] drm/i915: sync I915_PMU_MAX_GTS to I915_MAX_GT Matt Atwood
` (3 preceding siblings ...)
2023-06-01 18:22 ` [Intel-gfx] [PATCH] " Dixit, Ashutosh
@ 2023-06-02 16:19 ` Patchwork
4 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2023-06-02 16:19 UTC (permalink / raw)
To: Matt Atwood; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 16733 bytes --]
== Series Details ==
Series: drm/i915: sync I915_PMU_MAX_GTS to I915_MAX_GT
URL : https://patchwork.freedesktop.org/series/118672/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13210_full -> Patchwork_118672v1_full
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with Patchwork_118672v1_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_118672v1_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (8 -> 7)
------------------------------
Missing (1): shard-rkl0
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_118672v1_full:
### IGT changes ###
#### Warnings ####
* igt@kms_hdmi_inject@inject-audio:
- shard-glk: [SKIP][1] ([fdo#109271]) -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13210/shard-glk3/igt@kms_hdmi_inject@inject-audio.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/shard-glk7/igt@kms_hdmi_inject@inject-audio.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_hdmi_inject@inject-audio:
- {shard-rkl}: [SKIP][3] ([i915#433]) -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13210/shard-rkl-4/igt@kms_hdmi_inject@inject-audio.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/shard-rkl-2/igt@kms_hdmi_inject@inject-audio.html
Known issues
------------
Here are the changes found in Patchwork_118672v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ppgtt@blt-vs-render-ctxn:
- shard-snb: [PASS][5] -> [DMESG-FAIL][6] ([i915#8295])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13210/shard-snb7/igt@gem_ppgtt@blt-vs-render-ctxn.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/shard-snb6/igt@gem_ppgtt@blt-vs-render-ctxn.html
* igt@gen7_exec_parse@oacontrol-tracking:
- shard-apl: NOTRUN -> [SKIP][7] ([fdo#109271]) +12 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/shard-apl4/igt@gen7_exec_parse@oacontrol-tracking.html
* igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#3886])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/shard-apl4/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_flip@2x-flip-vs-blocking-wf-vblank@ab-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][9] -> [FAIL][10] ([i915#2122])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13210/shard-glk2/igt@kms_flip@2x-flip-vs-blocking-wf-vblank@ab-hdmi-a1-hdmi-a2.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/shard-glk3/igt@kms_flip@2x-flip-vs-blocking-wf-vblank@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][11] -> [FAIL][12] ([i915#79])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13210/shard-glk1/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/shard-glk5/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
* igt@kms_flip@2x-plain-flip:
- shard-snb: NOTRUN -> [SKIP][13] ([fdo#109271]) +16 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/shard-snb5/igt@kms_flip@2x-plain-flip.html
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-hdmi-a-1:
- shard-snb: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4579]) +8 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/shard-snb1/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-hdmi-a-1.html
* igt@kms_setmode@basic@pipe-a-vga-1:
- shard-snb: NOTRUN -> [FAIL][15] ([i915#5465]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/shard-snb5/igt@kms_setmode@basic@pipe-a-vga-1.html
#### Possible fixes ####
* igt@drm_fdinfo@most-busy-check-all@rcs0:
- {shard-rkl}: [FAIL][16] ([i915#7742]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13210/shard-rkl-7/igt@drm_fdinfo@most-busy-check-all@rcs0.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/shard-rkl-4/igt@drm_fdinfo@most-busy-check-all@rcs0.html
* igt@gem_ctx_freq@sysfs:
- {shard-dg1}: [FAIL][18] ([i915#6786]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13210/shard-dg1-19/igt@gem_ctx_freq@sysfs.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/shard-dg1-17/igt@gem_ctx_freq@sysfs.html
* igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-apl: [ABORT][20] ([i915#180]) -> [PASS][21] +1 similar issue
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13210/shard-apl6/igt@gem_ctx_isolation@preservation-s3@vcs0.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/shard-apl4/igt@gem_ctx_isolation@preservation-s3@vcs0.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [FAIL][22] ([i915#2846]) -> [PASS][23]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13210/shard-glk2/igt@gem_exec_fair@basic-deadline.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/shard-glk3/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [FAIL][24] ([i915#2842]) -> [PASS][25]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13210/shard-apl3/igt@gem_exec_fair@basic-none-solo@rcs0.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/shard-apl3/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- {shard-dg1}: [DMESG-WARN][26] ([i915#4936] / [i915#5493]) -> [PASS][27]
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13210/shard-dg1-13/igt@gem_lmem_swapping@smem-oom@lmem0.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/shard-dg1-14/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
- {shard-dg1}: [SKIP][28] ([i915#1937] / [i915#4579]) -> [PASS][29]
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13210/shard-dg1-17/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/shard-dg1-19/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
* igt@i915_pm_rc6_residency@rc6-idle@vecs0:
- {shard-dg1}: [FAIL][30] ([i915#3591]) -> [PASS][31]
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13210/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-idle@vecs0.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-idle@vecs0.html
* igt@i915_pm_rpm@modeset-lpsp-stress:
- {shard-dg1}: [SKIP][32] ([i915#1397]) -> [PASS][33]
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13210/shard-dg1-17/igt@i915_pm_rpm@modeset-lpsp-stress.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/shard-dg1-19/igt@i915_pm_rpm@modeset-lpsp-stress.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress:
- {shard-rkl}: [SKIP][34] ([i915#1397]) -> [PASS][35]
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13210/shard-rkl-7/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/shard-rkl-6/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [FAIL][36] ([i915#2346]) -> [PASS][37] +1 similar issue
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13210/shard-glk7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
- shard-apl: [FAIL][38] ([i915#2346]) -> [PASS][39]
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13210/shard-apl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/shard-apl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_rotation_crc@bad-pixel-format:
- {shard-rkl}: [ABORT][40] ([i915#8311]) -> [PASS][41]
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13210/shard-rkl-1/igt@kms_rotation_crc@bad-pixel-format.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/shard-rkl-6/igt@kms_rotation_crc@bad-pixel-format.html
#### Warnings ####
* igt@gem_barrier_race@remote-request@rcs0:
- shard-apl: [ABORT][42] ([i915#7461] / [i915#8211] / [i915#8234]) -> [ABORT][43] ([i915#7461] / [i915#8190])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13210/shard-apl6/igt@gem_barrier_race@remote-request@rcs0.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/shard-apl6/igt@gem_barrier_race@remote-request@rcs0.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4936]: https://gitlab.freedesktop.org/drm/intel/issues/4936
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5465]: https://gitlab.freedesktop.org/drm/intel/issues/5465
[i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6755]: https://gitlab.freedesktop.org/drm/intel/issues/6755
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6786]: https://gitlab.freedesktop.org/drm/intel/issues/6786
[i915#7392]: https://gitlab.freedesktop.org/drm/intel/issues/7392
[i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
[i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011
[i915#8190]: https://gitlab.freedesktop.org/drm/intel/issues/8190
[i915#8211]: https://gitlab.freedesktop.org/drm/intel/issues/8211
[i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
[i915#8234]: https://gitlab.freedesktop.org/drm/intel/issues/8234
[i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247
[i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
[i915#8295]: https://gitlab.freedesktop.org/drm/intel/issues/8295
[i915#8311]: https://gitlab.freedesktop.org/drm/intel/issues/8311
[i915#8411]: https://gitlab.freedesktop.org/drm/intel/issues/8411
[i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
[i915#8555]: https://gitlab.freedesktop.org/drm/intel/issues/8555
Build changes
-------------
* Linux: CI_DRM_13210 -> Patchwork_118672v1
CI-20190529: 20190529
CI_DRM_13210: a66da4c33d8ede541aea9ba6d0d73b556a072d54 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7314: ab70dfcdecf93a17fcaddb774855f726325fa0dd @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_118672v1: a66da4c33d8ede541aea9ba6d0d73b556a072d54 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118672v1/index.html
[-- Attachment #2: Type: text/html, Size: 13706 bytes --]
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2023-06-02 16:19 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-05-31 21:35 [Intel-gfx] [PATCH] drm/i915: sync I915_PMU_MAX_GTS to I915_MAX_GT Matt Atwood
2023-05-31 21:48 ` Andi Shyti
2023-05-31 22:07 ` Matt Atwood
2023-05-31 22:15 ` Andi Shyti
2023-06-01 17:40 ` Andi Shyti
2023-06-01 1:32 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for " Patchwork
2023-06-01 1:46 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-06-01 18:22 ` [Intel-gfx] [PATCH] " Dixit, Ashutosh
2023-06-01 18:30 ` Dixit, Ashutosh
2023-06-02 0:23 ` Dixit, Ashutosh
2023-06-02 0:40 ` Andi Shyti
2023-06-02 3:21 ` Dixit, Ashutosh
2023-06-02 8:51 ` Andi Shyti
2023-06-01 18:52 ` Umesh Nerlige Ramappa
2023-06-02 16:19 ` [Intel-gfx] ✓ Fi.CI.IGT: success for " Patchwork
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