* [Intel-gfx] [PATCH v3] drm/i915/mtl: Add Wa_14019821291
@ 2023-10-25 10:36 Dnyaneshwar Bhadane
2023-10-25 18:10 ` Matt Roper
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Dnyaneshwar Bhadane @ 2023-10-25 10:36 UTC (permalink / raw)
To: intel-gfx
This workaround is primarily implemented by the BIOS. However if the
BIOS applies the workaround it will reserve a small piece of our DSM
(which should be at the top, right below the WOPCM); we just need to
keep that region reserved so that nothing else attempts to re-use it.
v2: Declare regs in intel_gt_regs.h (Matt Roper)
v3: Shift WA implementation before calculation of *base (Matt Roper)
Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 17 +++++++++++++++++
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++
2 files changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index 1a766d8e7cce..192c9a333c0a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -404,6 +404,23 @@ static void icl_get_stolen_reserved(struct drm_i915_private *i915,
MISSING_CASE(reg_val & GEN8_STOLEN_RESERVED_SIZE_MASK);
}
+ /* Wa_14019821291 */
+ if (MEDIA_VER_FULL(i915) == IP_VER(13, 0)) {
+ /*
+ * This workaround is primarily implemented by the BIOS. We
+ * just need to figure out whether the BIOS has applied the
+ * workaround (meaning the programmed address falls within
+ * the DSM) and, if so, reserve that part of the DSM to
+ * prevent accidental reuse. The DSM location should be just
+ * below the WOPCM.
+ */
+ u64 gscpsmi_base = intel_uncore_read64_2x32(uncore,
+ MTL_GSCPSMI_BASEADDR_LSB,
+ MTL_GSCPSMI_BASEADDR_MSB);
+ if (gscpsmi_base >= *base && gscpsmi_base < *base + *size)
+ *size = gscpsmi_base - *base;
+ }
+
if (HAS_LMEMBAR_SMEM_STOLEN(i915))
/* the base is initialized to stolen top so subtract size to get base */
*base -= *size;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index eecd0a87a647..9de41703fae5 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -537,6 +537,9 @@
#define XEHP_SQCM MCR_REG(0x8724)
#define EN_32B_ACCESS REG_BIT(30)
+#define MTL_GSCPSMI_BASEADDR_LSB _MMIO(0x880c)
+#define MTL_GSCPSMI_BASEADDR_MSB _MMIO(0x8810)
+
#define HSW_IDICR _MMIO(0x9008)
#define IDIHASHMSK(x) (((x) & 0x3f) << 16)
--
2.34.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [Intel-gfx] [PATCH v3] drm/i915/mtl: Add Wa_14019821291
2023-10-25 10:36 [Intel-gfx] [PATCH v3] drm/i915/mtl: Add Wa_14019821291 Dnyaneshwar Bhadane
@ 2023-10-25 18:10 ` Matt Roper
2023-10-27 19:59 ` Bhadane, Dnyaneshwar
2023-10-25 19:32 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/mtl: Add Wa_14019821291 (rev3) Patchwork
2023-10-25 19:48 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2 siblings, 1 reply; 5+ messages in thread
From: Matt Roper @ 2023-10-25 18:10 UTC (permalink / raw)
To: Dnyaneshwar Bhadane; +Cc: intel-gfx
On Wed, Oct 25, 2023 at 04:06:46PM +0530, Dnyaneshwar Bhadane wrote:
> This workaround is primarily implemented by the BIOS. However if the
> BIOS applies the workaround it will reserve a small piece of our DSM
> (which should be at the top, right below the WOPCM); we just need to
> keep that region reserved so that nothing else attempts to re-use it.
>
> v2: Declare regs in intel_gt_regs.h (Matt Roper)
>
> v3: Shift WA implementation before calculation of *base (Matt Roper)
>
> Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 17 +++++++++++++++++
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++
> 2 files changed, 20 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> index 1a766d8e7cce..192c9a333c0a 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> @@ -404,6 +404,23 @@ static void icl_get_stolen_reserved(struct drm_i915_private *i915,
> MISSING_CASE(reg_val & GEN8_STOLEN_RESERVED_SIZE_MASK);
> }
>
> + /* Wa_14019821291 */
> + if (MEDIA_VER_FULL(i915) == IP_VER(13, 0)) {
> + /*
> + * This workaround is primarily implemented by the BIOS. We
> + * just need to figure out whether the BIOS has applied the
> + * workaround (meaning the programmed address falls within
> + * the DSM) and, if so, reserve that part of the DSM to
> + * prevent accidental reuse. The DSM location should be just
> + * below the WOPCM.
> + */
> + u64 gscpsmi_base = intel_uncore_read64_2x32(uncore,
> + MTL_GSCPSMI_BASEADDR_LSB,
> + MTL_GSCPSMI_BASEADDR_MSB);
I overlooked it while reviewing the previous revisions, but I think
we're mixing up which regions size/base refer to. Basically the layout
of the overall DSM stolen memory area is:
[[ usable DSM area ][ GSCPSMI WA area ][ WOPCM ]]
^ ^
| |
DSM base DSM end
In i915 we have a resource tracking the DSM as a whole, and then also
another resource tracking the "reserved" subregion of the DSM. Your
patch is trying to incorporate the gscpsmi workaround area into the
reserved subregion:
[ usable DSM area ][[ GSCPSMI WA area ][ WOPCM ]]
^ ^
| |
reserved base reserved end
So regarding the first condition here:
> + if (gscpsmi_base >= *base && gscpsmi_base < *base + *size)
I don't think this is checking the right thing. You want to see whether
the gscpsmi base address falls somewhere within within the DSM as a
whole, whereas the base/size you're comparing against above are the
preliminary bounds for the reserved area. Assuming the gscpsmi address
does fall somewhere within the DSM area, then we can pretty much assume
that the BIOS set things up properly and the GSCPSMI workaround area is
immediately before the WOPCM. I.e., the gscpsmi_base should become the
new start of the reserved region.
So what you really want is a condition like:
if (gscpsmi_base >= i915->dsm.stolen.start &&
gscpsmi_base < i915->dsm.stolen.end)
to see if it falls somewhere within the entire DSM area. If it does,
then everything from gscpsmi_base to the end of the DSM can be
considered to be the reserved area, and we don't even need to look at
the value in GEN6_STOLEN_RESERVED to find the WOPCM size.
So maybe the best thing to do is move this condition to the very top of
the function before we do anything else:
if (gscpsmi_base >= i915->dsm.stolen.start &&
gscpsmi_base < i915->dsm.stolen.end) {
*base = gscpsmi_base;
*size = i915->dsm.stolen.end - gscpsmi_base;
return;
}
Then if the GSCPSMI workaround is not in effect we fall back to reading
the WOPCM size from the register and use that to calculate the reserved
region base.
This is a bit different from how things work in my Xe patch because Xe
isn't tracking the reserved region of the DSM, but rather the usable
region, so the logic is somewhat the inverse of what this i915 function
needs.
Matt
> + *size = gscpsmi_base - *base;
> + }
> +
> if (HAS_LMEMBAR_SMEM_STOLEN(i915))
> /* the base is initialized to stolen top so subtract size to get base */
> *base -= *size;
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index eecd0a87a647..9de41703fae5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -537,6 +537,9 @@
> #define XEHP_SQCM MCR_REG(0x8724)
> #define EN_32B_ACCESS REG_BIT(30)
>
> +#define MTL_GSCPSMI_BASEADDR_LSB _MMIO(0x880c)
> +#define MTL_GSCPSMI_BASEADDR_MSB _MMIO(0x8810)
> +
> #define HSW_IDICR _MMIO(0x9008)
> #define IDIHASHMSK(x) (((x) & 0x3f) << 16)
>
> --
> 2.34.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/mtl: Add Wa_14019821291 (rev3)
2023-10-25 10:36 [Intel-gfx] [PATCH v3] drm/i915/mtl: Add Wa_14019821291 Dnyaneshwar Bhadane
2023-10-25 18:10 ` Matt Roper
@ 2023-10-25 19:32 ` Patchwork
2023-10-25 19:48 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2023-10-25 19:32 UTC (permalink / raw)
To: Dnyaneshwar Bhadane; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/mtl: Add Wa_14019821291 (rev3)
URL : https://patchwork.freedesktop.org/series/125282/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./drivers/gpu/drm/i915/intel_uncore.h:346:1: warning: trying to copy expression type 31
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/mtl: Add Wa_14019821291 (rev3)
2023-10-25 10:36 [Intel-gfx] [PATCH v3] drm/i915/mtl: Add Wa_14019821291 Dnyaneshwar Bhadane
2023-10-25 18:10 ` Matt Roper
2023-10-25 19:32 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/mtl: Add Wa_14019821291 (rev3) Patchwork
@ 2023-10-25 19:48 ` Patchwork
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2023-10-25 19:48 UTC (permalink / raw)
To: Dnyaneshwar Bhadane; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 14072 bytes --]
== Series Details ==
Series: drm/i915/mtl: Add Wa_14019821291 (rev3)
URL : https://patchwork.freedesktop.org/series/125282/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13786 -> Patchwork_125282v3
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_125282v3 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_125282v3, please notify your bug team (lgci.bug.filing@intel.com) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125282v3/index.html
Participating hosts (38 -> 38)
------------------------------
Additional (3): bat-dg2-8 bat-adlp-11 bat-dg1-5
Missing (3): fi-kbl-x1275 bat-dg2-9 fi-snb-2520m
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_125282v3:
### CI changes ###
#### Possible regressions ####
* boot:
- fi-blb-e6850: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13786/fi-blb-e6850/boot.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125282v3/fi-blb-e6850/boot.html
Known issues
------------
Here are the changes found in Patchwork_125282v3 that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- bat-adlp-11: NOTRUN -> [FAIL][3] ([i915#8293])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125282v3/bat-adlp-11/boot.html
#### Possible fixes ####
* boot:
- bat-jsl-1: [FAIL][4] ([i915#8293]) -> [PASS][5]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13786/bat-jsl-1/boot.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125282v3/bat-jsl-1/boot.html
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@basic-hwmon:
- bat-jsl-1: NOTRUN -> [SKIP][6] ([i915#9318])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125282v3/bat-jsl-1/igt@debugfs_test@basic-hwmon.html
* igt@gem_huc_copy@huc-copy:
- bat-jsl-1: NOTRUN -> [SKIP][7] ([i915#2190])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125282v3/bat-jsl-1/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@verify-random:
- bat-jsl-1: NOTRUN -> [SKIP][8] ([i915#4613]) +3 other tests skip
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125282v3/bat-jsl-1/igt@gem_lmem_swapping@verify-random.html
* igt@gem_mmap@basic:
- bat-dg1-5: NOTRUN -> [SKIP][9] ([i915#4083])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125282v3/bat-dg1-5/igt@gem_mmap@basic.html
- bat-dg2-8: NOTRUN -> [SKIP][10] ([i915#4083])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125282v3/bat-dg2-8/igt@gem_mmap@basic.html
* igt@gem_mmap_gtt@basic:
- bat-dg2-8: NOTRUN -> [SKIP][11] ([i915#4077]) +2 other tests skip
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125282v3/bat-dg2-8/igt@gem_mmap_gtt@basic.html
* igt@gem_tiled_fence_blits@basic:
- bat-dg1-5: NOTRUN -> [SKIP][12] ([i915#4077]) +2 other tests skip
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125282v3/bat-dg1-5/igt@gem_tiled_fence_blits@basic.html
* igt@gem_tiled_pread_basic:
- bat-dg1-5: NOTRUN -> [SKIP][13] ([i915#4079]) +1 other test skip
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125282v3/bat-dg1-5/igt@gem_tiled_pread_basic.html
- bat-dg2-8: NOTRUN -> [SKIP][14] ([i915#4079]) +1 other test skip
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125282v3/bat-dg2-8/igt@gem_tiled_pread_basic.html
* igt@i915_pm_rps@basic-api:
- bat-dg1-5: NOTRUN -> [SKIP][15] ([i915#6621])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125282v3/bat-dg1-5/igt@i915_pm_rps@basic-api.html
- bat-dg2-8: NOTRUN -> [SKIP][16] ([i915#6621])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125282v3/bat-dg2-8/igt@i915_pm_rps@basic-api.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [PASS][17] -> [DMESG-FAIL][18] ([i915#5334])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13786/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125282v3/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-dg2-8: NOTRUN -> [SKIP][19] ([i915#6645])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125282v3/bat-dg2-8/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-dg2-8: NOTRUN -> [SKIP][20] ([i915#5190])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125282v3/bat-dg2-8/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_addfb_basic@basic-x-tiled-legacy:
- bat-dg1-5: NOTRUN -> [SKIP][21] ([i915#4212]) +7 other tests skip
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125282v3/bat-dg1-5/igt@kms_addfb_basic@basic-x-tiled-legacy.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg2-8: NOTRUN -> [SKIP][22] ([i915#4215] / [i915#5190])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125282v3/bat-dg2-8/igt@kms_addfb_basic@basic-y-tiled-legacy.html
- bat-dg1-5: NOTRUN -> [SKIP][23] ([i915#4215])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125282v3/bat-dg1-5/igt@kms_addfb_basic@basic-y-tiled-legacy.html
* igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- bat-dg2-8: NOTRUN -> [SKIP][24] ([i915#4212]) +6 other tests skip
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125282v3/bat-dg2-8/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html
* igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-dg2-8: NOTRUN -> [SKIP][25] ([i915#4212] / [i915#5608])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125282v3/bat-dg2-8/igt@kms_addfb_basic@tile-pitch-mismatch.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-dg2-8: NOTRUN -> [SKIP][26] ([i915#4103] / [i915#4213] / [i915#5608]) +1 other test skip
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125282v3/bat-dg2-8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
- bat-jsl-1: NOTRUN -> [SKIP][27] ([i915#4103]) +1 other test skip
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125282v3/bat-jsl-1/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
- bat-dg1-5: NOTRUN -> [SKIP][28] ([i915#4103] / [i915#4213]) +1 other test skip
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125282v3/bat-dg1-5/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_dsc@dsc-basic:
- bat-jsl-1: NOTRUN -> [SKIP][29] ([i915#3555]) +1 other test skip
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125282v3/bat-jsl-1/igt@kms_dsc@dsc-basic.html
- bat-dg1-5: NOTRUN -> [SKIP][30] ([i915#3555] / [i915#3840])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125282v3/bat-dg1-5/igt@kms_dsc@dsc-basic.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-dg2-8: NOTRUN -> [SKIP][31] ([fdo#109285])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125282v3/bat-dg2-8/igt@kms_force_connector_basic@force-load-detect.html
- bat-jsl-1: NOTRUN -> [SKIP][32] ([fdo#109285])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125282v3/bat-jsl-1/igt@kms_force_connector_basic@force-load-detect.html
- bat-dg1-5: NOTRUN -> [SKIP][33] ([fdo#109285])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125282v3/bat-dg1-5/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_force_connector_basic@prune-stale-modes:
- bat-dg2-8: NOTRUN -> [SKIP][34] ([i915#5274])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125282v3/bat-dg2-8/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@kms_hdmi_inject@inject-audio:
- bat-dg1-5: NOTRUN -> [SKIP][35] ([i915#433])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125282v3/bat-dg1-5/igt@kms_hdmi_inject@inject-audio.html
* igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1:
- bat-rplp-1: [PASS][36] -> [ABORT][37] ([i915#8668])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13786/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125282v3/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1.html
* igt@kms_psr@cursor_plane_move:
- bat-dg2-8: NOTRUN -> [SKIP][38] ([i915#1072]) +3 other tests skip
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125282v3/bat-dg2-8/igt@kms_psr@cursor_plane_move.html
* igt@kms_psr@sprite_plane_onoff:
- bat-dg1-5: NOTRUN -> [SKIP][39] ([i915#1072] / [i915#4078]) +3 other tests skip
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125282v3/bat-dg1-5/igt@kms_psr@sprite_plane_onoff.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-dg1-5: NOTRUN -> [SKIP][40] ([i915#3555])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125282v3/bat-dg1-5/igt@kms_setmode@basic-clone-single-crtc.html
- bat-dg2-8: NOTRUN -> [SKIP][41] ([i915#3555] / [i915#4098])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125282v3/bat-dg2-8/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-flip:
- bat-dg2-8: NOTRUN -> [SKIP][42] ([i915#3708])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125282v3/bat-dg2-8/igt@prime_vgem@basic-fence-flip.html
* igt@prime_vgem@basic-fence-mmap:
- bat-dg2-8: NOTRUN -> [SKIP][43] ([i915#3708] / [i915#4077]) +1 other test skip
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125282v3/bat-dg2-8/igt@prime_vgem@basic-fence-mmap.html
* igt@prime_vgem@basic-fence-read:
- bat-dg1-5: NOTRUN -> [SKIP][44] ([i915#3708]) +3 other tests skip
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125282v3/bat-dg1-5/igt@prime_vgem@basic-fence-read.html
* igt@prime_vgem@basic-gtt:
- bat-dg1-5: NOTRUN -> [SKIP][45] ([i915#3708] / [i915#4077]) +1 other test skip
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125282v3/bat-dg1-5/igt@prime_vgem@basic-gtt.html
* igt@prime_vgem@basic-write:
- bat-dg2-8: NOTRUN -> [SKIP][46] ([i915#3291] / [i915#3708]) +2 other tests skip
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125282v3/bat-dg2-8/igt@prime_vgem@basic-write.html
#### Possible fixes ####
* igt@kms_hdmi_inject@inject-audio:
- fi-kbl-guc: [FAIL][47] ([IGT#3]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13786/fi-kbl-guc/igt@kms_hdmi_inject@inject-audio.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125282v3/fi-kbl-guc/igt@kms_hdmi_inject@inject-audio.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#3]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/3
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5608]: https://gitlab.freedesktop.org/drm/intel/issues/5608
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293
[i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
[i915#9318]: https://gitlab.freedesktop.org/drm/intel/issues/9318
Build changes
-------------
* Linux: CI_DRM_13786 -> Patchwork_125282v3
CI-20190529: 20190529
CI_DRM_13786: e8d777a5e7e0ec452142ad0073022733f99c1eb7 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7557: 18fc864d68d382847596594d7eb3488f2c8fb45e @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_125282v3: e8d777a5e7e0ec452142ad0073022733f99c1eb7 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
468b9a983f14 drm/i915/mtl: Add Wa_14019821291
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125282v3/index.html
[-- Attachment #2: Type: text/html, Size: 17319 bytes --]
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Intel-gfx] [PATCH v3] drm/i915/mtl: Add Wa_14019821291
2023-10-25 18:10 ` Matt Roper
@ 2023-10-27 19:59 ` Bhadane, Dnyaneshwar
0 siblings, 0 replies; 5+ messages in thread
From: Bhadane, Dnyaneshwar @ 2023-10-27 19:59 UTC (permalink / raw)
To: Roper, Matthew D; +Cc: intel-gfx
> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@intel.com>
> Sent: Wednesday, October 25, 2023 11:41 PM
> To: Bhadane, Dnyaneshwar <dnyaneshwar.bhadane@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH v3] drm/i915/mtl: Add Wa_14019821291
>
> On Wed, Oct 25, 2023 at 04:06:46PM +0530, Dnyaneshwar Bhadane wrote:
> > This workaround is primarily implemented by the BIOS. However if the
> > BIOS applies the workaround it will reserve a small piece of our DSM
> > (which should be at the top, right below the WOPCM); we just need to
> > keep that region reserved so that nothing else attempts to re-use it.
> >
> > v2: Declare regs in intel_gt_regs.h (Matt Roper)
> >
> > v3: Shift WA implementation before calculation of *base (Matt Roper)
> >
> > Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
> > ---
> > drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 17 +++++++++++++++++
> > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++
> > 2 files changed, 20 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> > b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> > index 1a766d8e7cce..192c9a333c0a 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> > @@ -404,6 +404,23 @@ static void icl_get_stolen_reserved(struct
> drm_i915_private *i915,
> > MISSING_CASE(reg_val &
> GEN8_STOLEN_RESERVED_SIZE_MASK);
> > }
> >
> > + /* Wa_14019821291 */
> > + if (MEDIA_VER_FULL(i915) == IP_VER(13, 0)) {
> > + /*
> > + * This workaround is primarily implemented by the BIOS. We
> > + * just need to figure out whether the BIOS has applied the
> > + * workaround (meaning the programmed address falls within
> > + * the DSM) and, if so, reserve that part of the DSM to
> > + * prevent accidental reuse. The DSM location should be just
> > + * below the WOPCM.
> > + */
> > + u64 gscpsmi_base = intel_uncore_read64_2x32(uncore,
> > +
> MTL_GSCPSMI_BASEADDR_LSB,
> > +
> MTL_GSCPSMI_BASEADDR_MSB);
>
> I overlooked it while reviewing the previous revisions, but I think we're mixing
> up which regions size/base refer to. Basically the layout of the overall DSM
> stolen memory area is:
>
> [[ usable DSM area ][ GSCPSMI WA area ][ WOPCM ]]
> ^ ^
> | |
> DSM base DSM end
>
> In i915 we have a resource tracking the DSM as a whole, and then also
> another resource tracking the "reserved" subregion of the DSM. Your patch is
> trying to incorporate the gscpsmi workaround area into the reserved
> subregion:
>
> [ usable DSM area ][[ GSCPSMI WA area ][ WOPCM ]]
> ^ ^
> | |
> reserved base reserved end
>
> So regarding the first condition here:
>
> > + if (gscpsmi_base >= *base && gscpsmi_base < *base + *size)
>
> I don't think this is checking the right thing. You want to see whether the
> gscpsmi base address falls somewhere within within the DSM as a whole,
> whereas the base/size you're comparing against above are the preliminary
> bounds for the reserved area. Assuming the gscpsmi address does fall
> somewhere within the DSM area, then we can pretty much assume that the
> BIOS set things up properly and the GSCPSMI workaround area is immediately
> before the WOPCM. I.e., the gscpsmi_base should become the new start of
> the reserved region.
>
> So what you really want is a condition like:
>
> if (gscpsmi_base >= i915->dsm.stolen.start &&
> gscpsmi_base < i915->dsm.stolen.end)
>
> to see if it falls somewhere within the entire DSM area. If it does, then
> everything from gscpsmi_base to the end of the DSM can be considered to be
> the reserved area, and we don't even need to look at the value in
> GEN6_STOLEN_RESERVED to find the WOPCM size.
>
> So maybe the best thing to do is move this condition to the very top of the
> function before we do anything else:
>
> if (gscpsmi_base >= i915->dsm.stolen.start &&
> gscpsmi_base < i915->dsm.stolen.end) {
> *base = gscpsmi_base;
> *size = i915->dsm.stolen.end - gscpsmi_base;
> return;
> }
>
> Then if the GSCPSMI workaround is not in effect we fall back to reading the
> WOPCM size from the register and use that to calculate the reserved region
> base.
>
> This is a bit different from how things work in my Xe patch because Xe isn't
> tracking the reserved region of the DSM, but rather the usable region, so the
> logic is somewhat the inverse of what this i915 function needs.
>
>
> Matt
Thank you, Matt, for the wonderful explanation.
I will address these changes in next(V4) revision.
Regards Dnyaneshwar
>
> > + *size = gscpsmi_base - *base;
> > + }
> > +
> > if (HAS_LMEMBAR_SMEM_STOLEN(i915))
> > /* the base is initialized to stolen top so subtract size to get
> base */
> > *base -= *size;
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > index eecd0a87a647..9de41703fae5 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > @@ -537,6 +537,9 @@
> > #define XEHP_SQCM MCR_REG(0x8724)
> > #define EN_32B_ACCESS REG_BIT(30)
> >
> > +#define MTL_GSCPSMI_BASEADDR_LSB _MMIO(0x880c)
> > +#define MTL_GSCPSMI_BASEADDR_MSB _MMIO(0x8810)
> > +
> > #define HSW_IDICR _MMIO(0x9008)
> > #define IDIHASHMSK(x) (((x) & 0x3f) << 16)
> >
> > --
> > 2.34.1
> >
>
> --
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2023-10-27 19:59 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-10-25 10:36 [Intel-gfx] [PATCH v3] drm/i915/mtl: Add Wa_14019821291 Dnyaneshwar Bhadane
2023-10-25 18:10 ` Matt Roper
2023-10-27 19:59 ` Bhadane, Dnyaneshwar
2023-10-25 19:32 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/mtl: Add Wa_14019821291 (rev3) Patchwork
2023-10-25 19:48 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
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