From: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/2] drm/i915: clear GFX_MODE on IVB at init time
Date: Fri, 12 Aug 2011 15:28:32 -0700 [thread overview]
Message-ID: <20110812152832.6c922a17@jbarnes-desktop> (raw)
In-Reply-To: <20110812151809.7fdab276@jbarnes-desktop>
On Fri, 12 Aug 2011 15:18:09 -0700
Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> On Fri, 12 Aug 2011 14:55:32 -0700
> Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
>
> > GFX_MODE controls important behavior like PPGTT, run lists, and TLB
> > invalidate behavior. On the SDV I'm using, the TLB invalidation mode
> > was defaulting to "pipe control only" which meant regular MI_FLUSHes
> > wouldn't actually flush the TLB, leading to all sorts of stale data
> > getting used.
> >
> > So initialize it to 0 at ring buffer init time until we actually use
> > PIPE_CONTROL for TLB invalidation.
>
> Ignore this one, see below for an updated patch that uses bit
> definitions and makes sure the register gets reset at GPU reset time as
> well.
Ignore the last one too. Third time's the charm!
--
Jesse Barnes, Intel Open Source Technology Center
>From 91f24a59e03b338e114ecafe5c589c1f36119c02 Mon Sep 17 00:00:00 2001
From: Jesse Barnes <jbarnes@virtuousgeek.org>
Date: Fri, 12 Aug 2011 15:15:06 -0700
Subject: [PATCH] drm/i915: set GFX_MODE to pre-Ivybridge default value even on Ivybridge
Prior to Ivybridge, the GFX_MODE would default to 0x800, meaning that
MI_FLUSH would flush the TLBs in addition to the rest of the caches
indicated in the MI_FLUSH command. However starting with Ivybridge, the
register defaults to 0x2800 out of reset, meaning that to invalidate the
TLB we need to use PIPE_CONTROL. Since we're not doing that yet, go
back to the old default so things work.
v2: don't forget to actually *clear* the new bit
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.c | 4 ++++
2 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7033e01..26641ad 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -375,6 +375,7 @@
# define MI_FLUSH_ENABLE (1 << 11)
#define GFX_MODE 0x02520
+#define GFX_MODE_GEN7 0x0229c
#define GFX_RUN_LIST_ENABLE (1<<15)
#define GFX_TLB_INVALIDATE_ALWAYS (1<<13)
#define GFX_SURFACE_FAULT_ENABLE (1<<12)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 47b9b27..0b17036 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -290,6 +290,10 @@ static int init_render_ring(struct intel_ring_buffer *ring)
if (IS_GEN6(dev) || IS_GEN7(dev))
mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
I915_WRITE(MI_MODE, mode);
+ if (IS_GEN7(dev))
+ I915_WRITE(GFX_MODE_GEN7, ((GFX_TLB_INVALIDATE_ALWAYS |
+ GFX_REPLAY_MODE) << 16) |
+ GFX_REPLAY_MODE);
}
if (INTEL_INFO(dev)->gen >= 6) {
--
1.7.4.1
next prev parent reply other threads:[~2011-08-12 22:28 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-08-12 21:55 [PATCH 1/2] drm/i915: clear GFX_MODE on IVB at init time Jesse Barnes
2011-08-12 21:55 ` [PATCH 2/2] drm/i915: suspend/resume rps and ring freq state on IVB Jesse Barnes
2011-08-12 22:18 ` [PATCH 1/2] drm/i915: clear GFX_MODE on IVB at init time Jesse Barnes
2011-08-12 22:28 ` Jesse Barnes [this message]
2011-08-12 22:56 ` Chris Wilson
2011-08-15 23:59 ` Kenneth Graunke
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