From: Daniel Vetter <daniel@ffwll.ch>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Only apply the SNB pipe control w/a to gen6
Date: Wed, 8 Aug 2012 09:35:40 +0200 [thread overview]
Message-ID: <20120808073540.GC5490@phenom.ffwll.local> (raw)
In-Reply-To: <1342803748-25695-1-git-send-email-chris@chris-wilson.co.uk>
On Fri, Jul 20, 2012 at 06:02:28PM +0100, Chris Wilson wrote:
> The requirements for the sync flush to be emitted prior to the render
> cache flush is only true for SandyBridge. On IvyBridge and friends we
> can just emit the flushes with an inline CS stall.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Since I've seen Ken ditch these w/a for ivb+ in mesa, I've figured that
this is ok. Some bspec reading seems to agree. Merged to dinq, thanks for
the patch.
-Daniel
--
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48
prev parent reply other threads:[~2012-08-08 7:35 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-07-20 17:02 [PATCH] drm/i915: Only apply the SNB pipe control w/a to gen6 Chris Wilson
2012-07-20 21:00 ` Ben Widawsky
2012-07-25 12:51 ` [PATCH 1/2] drm/i915: flush DC writes cached in l3$ on gen7 Daniel Vetter
2012-07-25 12:51 ` [PATCH 2/2] drm/i915: disable indirect state pointers in render flush Daniel Vetter
2012-07-26 17:33 ` Eric Anholt
2012-07-26 17:47 ` Daniel Vetter
2012-07-26 17:25 ` [PATCH 1/2] drm/i915: flush DC writes cached in l3$ on gen7 Eric Anholt
2012-08-08 7:35 ` Daniel Vetter [this message]
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