From: Eric Anholt <eric@anholt.net>
To: Intel Graphics Development <intel-gfx@lists.freedesktop.org>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Subject: Re: [PATCH 2/2] drm/i915: disable indirect state pointers in render flush
Date: Thu, 26 Jul 2012 10:33:18 -0700 [thread overview]
Message-ID: <87r4rypgv5.fsf@eliezer.anholt.net> (raw)
In-Reply-To: <1343220704-4210-2-git-send-email-daniel.vetter@ffwll.ch>
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Daniel Vetter <daniel.vetter@ffwll.ch> writes:
> Since we don't guarantee that objects stay at the same gtt offset,
> userspace needs to reload all indirect state anyway, even with hw
> contexts. The hw provides a little pipe_control flag to disable at
> least some these indirect state pointers and hence avoid to
> save/restore them at context switch time.
>
> Seems to improve hw context switch throughput as measured by running
> glxgears by about 0.5%, barely above the noise on my ivb gt2 here.
I'd like to see some better testing than picking an fps number out of
glxgears. I'm dubious of there being any measurable effect here. But
then, I haven't even been able to figure out from the specs what exactly
is considered to be "indirect state".
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next prev parent reply other threads:[~2012-07-26 17:33 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-07-20 17:02 [PATCH] drm/i915: Only apply the SNB pipe control w/a to gen6 Chris Wilson
2012-07-20 21:00 ` Ben Widawsky
2012-07-25 12:51 ` [PATCH 1/2] drm/i915: flush DC writes cached in l3$ on gen7 Daniel Vetter
2012-07-25 12:51 ` [PATCH 2/2] drm/i915: disable indirect state pointers in render flush Daniel Vetter
2012-07-26 17:33 ` Eric Anholt [this message]
2012-07-26 17:47 ` Daniel Vetter
2012-07-26 17:25 ` [PATCH 1/2] drm/i915: flush DC writes cached in l3$ on gen7 Eric Anholt
2012-08-08 7:35 ` [PATCH] drm/i915: Only apply the SNB pipe control w/a to gen6 Daniel Vetter
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