* [xf86-video-intel PATCH] intel: Fix Haswell CRW PCI IDs.
@ 2013-03-01 23:40 Kenneth Graunke
2013-03-01 23:52 ` Chris Wilson
0 siblings, 1 reply; 2+ messages in thread
From: Kenneth Graunke @ 2013-03-01 23:40 UTC (permalink / raw)
To: intel-gfx
The second digit was off by one, which meant we accidentally treated
GT(n) as GT(n-1). This also meant no support for GT1 at all.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
---
src/intel_driver.h | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/src/intel_driver.h b/src/intel_driver.h
index c98025b..0dda5b1 100644
--- a/src/intel_driver.h
+++ b/src/intel_driver.h
@@ -219,15 +219,15 @@
#define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A
#define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
#define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A
-#define PCI_CHIP_HASWELL_CRW_D_GT1 0x0D12
-#define PCI_CHIP_HASWELL_CRW_D_GT2 0x0D22
-#define PCI_CHIP_HASWELL_CRW_D_GT2_PLUS 0x0D32
-#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D16
-#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D26
-#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D36
-#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D1A
-#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D2A
-#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A
+#define PCI_CHIP_HASWELL_CRW_D_GT1 0x0D02
+#define PCI_CHIP_HASWELL_CRW_D_GT2 0x0D12
+#define PCI_CHIP_HASWELL_CRW_D_GT2_PLUS 0x0D22
+#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06
+#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16
+#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D26
+#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A
+#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A
+#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D2A
#define PCI_CHIP_VALLEYVIEW_PO 0x0f30
#define PCI_CHIP_VALLEYVIEW_1 0x0f31
--
1.8.1.4
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [xf86-video-intel PATCH] intel: Fix Haswell CRW PCI IDs.
2013-03-01 23:40 [xf86-video-intel PATCH] intel: Fix Haswell CRW PCI IDs Kenneth Graunke
@ 2013-03-01 23:52 ` Chris Wilson
0 siblings, 0 replies; 2+ messages in thread
From: Chris Wilson @ 2013-03-01 23:52 UTC (permalink / raw)
To: Kenneth Graunke; +Cc: intel-gfx
On Fri, Mar 01, 2013 at 03:40:18PM -0800, Kenneth Graunke wrote:
> The second digit was off by one, which meant we accidentally treated
> GT(n) as GT(n-1). This also meant no support for GT1 at all.
Apologies this got delayed in my inbox, I saw all the other patches so
went ahead and fixed up -intel. Thanks,
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
^ permalink raw reply [flat|nested] 2+ messages in thread
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