[RFC-v2 0/9] Add support for mipi dsi cmd mode

[RFC-v2 0/9] Add support for mipi dsi cmd mode

[Vandita Kulkarni]

Fixed the comments on version1 RFC, basically fixing the
challenge on getting access to mipi dsi attributes like
is command mode enabled, and what should be the port for
reading TE and doing a frame update.
Thanks to Jani and Ville for their inputs on this.

Vandita Kulkarni (9):
  drm/i915/dsi: Define command mode registers
  drm/i915/dsi: Configure transcoder operation for command mode.
  drm/i915/dsi: Add vblank calculation for command mode
  drm/i915/dsi: Add cmd mode flags in display mode private flags
  drm/i915/dsi: Add check for periodic command mode
  drm/i915/dsi: Use private flags to indicate TE in cmd mode
  drm/i915/dsi: Configure TE interrupt for cmd mode
  drm/i915/dsi: Add TE handler for dsi cmd mode.
  drm/i915/dsi: Initiate fame request in cmd mode

 drivers/gpu/drm/i915/display/icl_dsi.c        | 134 ++++++++++++++++--
 drivers/gpu/drm/i915/display/intel_display.c  |  10 ++
 .../drm/i915/display/intel_display_types.h    |   6 +
 drivers/gpu/drm/i915/display/intel_dsi.h      |   3 +
 drivers/gpu/drm/i915/i915_irq.c               | 120 +++++++++++++++-
 drivers/gpu/drm/i915/i915_reg.h               |  78 ++++++++--
 6 files changed, 328 insertions(+), 23 deletions(-)

-- 
2.21.0.5.gaeb582a

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[Intel-gfx] [RFC-v2 0/9] Add support for mipi dsi cmd mode

[Vandita Kulkarni]

Fixed the comments on version1 RFC, basically fixing the
challenge on getting access to mipi dsi attributes like
is command mode enabled, and what should be the port for
reading TE and doing a frame update.
Thanks to Jani and Ville for their inputs on this.

Vandita Kulkarni (9):
  drm/i915/dsi: Define command mode registers
  drm/i915/dsi: Configure transcoder operation for command mode.
  drm/i915/dsi: Add vblank calculation for command mode
  drm/i915/dsi: Add cmd mode flags in display mode private flags
  drm/i915/dsi: Add check for periodic command mode
  drm/i915/dsi: Use private flags to indicate TE in cmd mode
  drm/i915/dsi: Configure TE interrupt for cmd mode
  drm/i915/dsi: Add TE handler for dsi cmd mode.
  drm/i915/dsi: Initiate fame request in cmd mode

 drivers/gpu/drm/i915/display/icl_dsi.c        | 134 ++++++++++++++++--
 drivers/gpu/drm/i915/display/intel_display.c  |  10 ++
 .../drm/i915/display/intel_display_types.h    |   6 +
 drivers/gpu/drm/i915/display/intel_dsi.h      |   3 +
 drivers/gpu/drm/i915/i915_irq.c               | 120 +++++++++++++++-
 drivers/gpu/drm/i915/i915_reg.h               |  78 ++++++++--
 6 files changed, 328 insertions(+), 23 deletions(-)

-- 
2.21.0.5.gaeb582a

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[RFC-v2 1/9] drm/i915/dsi: Define command mode registers

[Vandita Kulkarni]

Adding all the register definitions needed
for mipi dsi command mode.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 78 +++++++++++++++++++++++++++++----
 1 file changed, 70 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a607ea520829..2ffcc21670b7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5036,14 +5036,20 @@ enum {
 #define   BLM_PCH_POLARITY			(1 << 29)
 #define BLC_PWM_PCH_CTL2	_MMIO(0xc8254)
 
-#define UTIL_PIN_CTL		_MMIO(0x48400)
-#define   UTIL_PIN_ENABLE	(1 << 31)
-
-#define   UTIL_PIN_PIPE(x)     ((x) << 29)
-#define   UTIL_PIN_PIPE_MASK   (3 << 29)
-#define   UTIL_PIN_MODE_PWM    (1 << 24)
-#define   UTIL_PIN_MODE_MASK   (0xf << 24)
-#define   UTIL_PIN_POLARITY    (1 << 22)
+#define UTIL_PIN_CTL			_MMIO(0x48400)
+#define   UTIL_PIN_ENABLE		(1 << 31)
+#define   UTIL_PIN_PIPE_MASK		(3 << 29)
+#define   UTIL_PIN_PIPE(x)		((x) << 29)
+#define   UTIL_PIN_MODE_MASK		(0xf << 24)
+#define   UTIL_PIN_MODE_DATA		(0 << 24)
+#define   UTIL_PIN_MODE_PWM		(1 << 24)
+#define   UTIL_PIN_MODE_VBLANK		(4 << 24)
+#define   UTIL_PIN_MODE_VSYNC		(5 << 24)
+#define   UTIL_PIN_MODE_EYE_LEVEL	(8 << 24)
+#define   UTIL_PIN_OUTPUT_DATA		(1 << 23)
+#define   UTIL_PIN_POLARITY		(1 << 22)
+#define   UTIL_PIN_DIRECTION_INPUT	(1 << 19)
+#define   UTIL_PIN_INPUT_DATA		(1 << 16)
 
 /* BXT backlight register definition. */
 #define _BXT_BLC_PWM_CTL1			0xC8250
@@ -7500,11 +7506,15 @@ enum {
 #define GEN8_DE_PORT_IMR _MMIO(0x44444)
 #define GEN8_DE_PORT_IIR _MMIO(0x44448)
 #define GEN8_DE_PORT_IER _MMIO(0x4444c)
+#define  DSI1_NON_TE			(1 << 31)
+#define  DSI0_NON_TE			(1 << 30)
 #define  ICL_AUX_CHANNEL_E		(1 << 29)
 #define  CNL_AUX_CHANNEL_F		(1 << 28)
 #define  GEN9_AUX_CHANNEL_D		(1 << 27)
 #define  GEN9_AUX_CHANNEL_C		(1 << 26)
 #define  GEN9_AUX_CHANNEL_B		(1 << 25)
+#define  DSI1_TE			(1 << 24)
+#define  DSI0_TE			(1 << 23)
 #define  BXT_DE_PORT_HP_DDIC		(1 << 5)
 #define  BXT_DE_PORT_HP_DDIB		(1 << 4)
 #define  BXT_DE_PORT_HP_DDIA		(1 << 3)
@@ -10770,6 +10780,57 @@ enum skl_power_gate {
 #define  ICL_ESC_CLK_DIV_SHIFT			0
 #define DSI_MAX_ESC_CLK			20000		/* in KHz */
 
+#define _DSI_CMD_FRMCTL_0		0x6b034
+#define _DSI_CMD_FRMCTL_1		0x6b834
+#define DSI_CMD_FRMCTL(port)		_MMIO_PORT(port,	\
+						   _DSI_CMD_FRMCTL_0,\
+						   _DSI_CMD_FRMCTL_1)
+#define   DSI_FRAME_UPDATE_REQUEST		(1 << 31)
+#define   DSI_PERIODIC_FRAME_UPDATE_ENABLE	(1 << 29)
+#define   DSI_NULL_PACKET_ENABLE		(1 << 28)
+#define   DSI_FRAME_IN_PROGRESS			(1 << 0)
+
+#define _DSI_INTR_MASK_REG_0		0x6b070
+#define _DSI_INTR_MASK_REG_1		0x6b870
+#define DSI_INTR_MASK_REG(port)		_MMIO_PORT(port,	\
+						   _DSI_INTR_MASK_REG_0,\
+						   _DSI_INTR_MASK_REG_1)
+
+#define _DSI_INTR_IDENT_REG_0		0x6b074
+#define _DSI_INTR_IDENT_REG_1		0x6b874
+#define DSI_INTR_IDENT_REG(port)	_MMIO_PORT(port,	\
+						   _DSI_INTR_IDENT_REG_0,\
+						   _DSI_INTR_IDENT_REG_1)
+#define   DSI_TE_EVENT				(1 << 31)
+#define   DSI_RX_DATA_OR_BTA_TERMINATED		(1 << 30)
+#define   DSI_TX_DATA				(1 << 29)
+#define   DSI_ULPS_ENTRY_DONE			(1 << 28)
+#define   DSI_NON_TE_TRIGGER_RECEIVED		(1 << 27)
+#define   DSI_HOST_CHKSUM_ERROR			(1 << 26)
+#define   DSI_HOST_MULTI_ECC_ERROR		(1 << 25)
+#define   DSI_HOST_SINGL_ECC_ERROR		(1 << 24)
+#define   DSI_HOST_CONTENTION_DETECTED		(1 << 23)
+#define   DSI_HOST_FALSE_CONTROL_ERROR		(1 << 22)
+#define   DSI_HOST_TIMEOUT_ERROR		(1 << 21)
+#define   DSI_HOST_LOW_POWER_TX_SYNC_ERROR	(1 << 20)
+#define   DSI_HOST_ESCAPE_MODE_ENTRY_ERROR	(1 << 19)
+#define   DSI_FRAME_UPDATE_DONE			(1 << 16)
+#define   DSI_PROTOCOL_VIOLATION_REPORTED	(1 << 15)
+#define   DSI_INVALID_TX_LENGTH			(1 << 13)
+#define   DSI_INVALID_VC			(1 << 12)
+#define   DSI_INVALID_DATA_TYPE			(1 << 11)
+#define   DSI_PERIPHERAL_CHKSUM_ERROR		(1 << 10)
+#define   DSI_PERIPHERAL_MULTI_ECC_ERROR	(1 << 9)
+#define   DSI_PERIPHERAL_SINGLE_ECC_ERROR	(1 << 8)
+#define   DSI_PERIPHERAL_CONTENTION_DETECTED	(1 << 7)
+#define   DSI_PERIPHERAL_FALSE_CTRL_ERROR	(1 << 6)
+#define   DSI_PERIPHERAL_TIMEOUT_ERROR		(1 << 5)
+#define   DSI_PERIPHERAL_LP_TX_SYNC_ERROR	(1 << 4)
+#define   DSI_PERIPHERAL_ESC_MODE_ENTRY_CMD_ERR	(1 << 3)
+#define   DSI_EOT_SYNC_ERROR			(1 << 2)
+#define   DSI_SOT_SYNC_ERROR			(1 << 1)
+#define   DSI_SOT_ERROR				(1 << 0)
+
 /* Gen4+ Timestamp and Pipe Frame time stamp registers */
 #define GEN4_TIMESTAMP		_MMIO(0x2358)
 #define ILK_TIMESTAMP_HI	_MMIO(0x70070)
@@ -11374,6 +11435,7 @@ enum skl_power_gate {
 #define  CMD_MODE_TE_GATE		(0x1 << 28)
 #define  VIDEO_MODE_SYNC_EVENT		(0x2 << 28)
 #define  VIDEO_MODE_SYNC_PULSE		(0x3 << 28)
+#define  TE_SOURCE_GPIO			(1 << 27)
 #define  LINK_READY			(1 << 20)
 #define  PIX_FMT_MASK			(0x3 << 16)
 #define  PIX_FMT_SHIFT			16
-- 
2.21.0.5.gaeb582a

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[Intel-gfx] [RFC-v2 1/9] drm/i915/dsi: Define command mode registers

[Vandita Kulkarni]

Adding all the register definitions needed
for mipi dsi command mode.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 78 +++++++++++++++++++++++++++++----
 1 file changed, 70 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a607ea520829..2ffcc21670b7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5036,14 +5036,20 @@ enum {
 #define   BLM_PCH_POLARITY			(1 << 29)
 #define BLC_PWM_PCH_CTL2	_MMIO(0xc8254)
 
-#define UTIL_PIN_CTL		_MMIO(0x48400)
-#define   UTIL_PIN_ENABLE	(1 << 31)
-
-#define   UTIL_PIN_PIPE(x)     ((x) << 29)
-#define   UTIL_PIN_PIPE_MASK   (3 << 29)
-#define   UTIL_PIN_MODE_PWM    (1 << 24)
-#define   UTIL_PIN_MODE_MASK   (0xf << 24)
-#define   UTIL_PIN_POLARITY    (1 << 22)
+#define UTIL_PIN_CTL			_MMIO(0x48400)
+#define   UTIL_PIN_ENABLE		(1 << 31)
+#define   UTIL_PIN_PIPE_MASK		(3 << 29)
+#define   UTIL_PIN_PIPE(x)		((x) << 29)
+#define   UTIL_PIN_MODE_MASK		(0xf << 24)
+#define   UTIL_PIN_MODE_DATA		(0 << 24)
+#define   UTIL_PIN_MODE_PWM		(1 << 24)
+#define   UTIL_PIN_MODE_VBLANK		(4 << 24)
+#define   UTIL_PIN_MODE_VSYNC		(5 << 24)
+#define   UTIL_PIN_MODE_EYE_LEVEL	(8 << 24)
+#define   UTIL_PIN_OUTPUT_DATA		(1 << 23)
+#define   UTIL_PIN_POLARITY		(1 << 22)
+#define   UTIL_PIN_DIRECTION_INPUT	(1 << 19)
+#define   UTIL_PIN_INPUT_DATA		(1 << 16)
 
 /* BXT backlight register definition. */
 #define _BXT_BLC_PWM_CTL1			0xC8250
@@ -7500,11 +7506,15 @@ enum {
 #define GEN8_DE_PORT_IMR _MMIO(0x44444)
 #define GEN8_DE_PORT_IIR _MMIO(0x44448)
 #define GEN8_DE_PORT_IER _MMIO(0x4444c)
+#define  DSI1_NON_TE			(1 << 31)
+#define  DSI0_NON_TE			(1 << 30)
 #define  ICL_AUX_CHANNEL_E		(1 << 29)
 #define  CNL_AUX_CHANNEL_F		(1 << 28)
 #define  GEN9_AUX_CHANNEL_D		(1 << 27)
 #define  GEN9_AUX_CHANNEL_C		(1 << 26)
 #define  GEN9_AUX_CHANNEL_B		(1 << 25)
+#define  DSI1_TE			(1 << 24)
+#define  DSI0_TE			(1 << 23)
 #define  BXT_DE_PORT_HP_DDIC		(1 << 5)
 #define  BXT_DE_PORT_HP_DDIB		(1 << 4)
 #define  BXT_DE_PORT_HP_DDIA		(1 << 3)
@@ -10770,6 +10780,57 @@ enum skl_power_gate {
 #define  ICL_ESC_CLK_DIV_SHIFT			0
 #define DSI_MAX_ESC_CLK			20000		/* in KHz */
 
+#define _DSI_CMD_FRMCTL_0		0x6b034
+#define _DSI_CMD_FRMCTL_1		0x6b834
+#define DSI_CMD_FRMCTL(port)		_MMIO_PORT(port,	\
+						   _DSI_CMD_FRMCTL_0,\
+						   _DSI_CMD_FRMCTL_1)
+#define   DSI_FRAME_UPDATE_REQUEST		(1 << 31)
+#define   DSI_PERIODIC_FRAME_UPDATE_ENABLE	(1 << 29)
+#define   DSI_NULL_PACKET_ENABLE		(1 << 28)
+#define   DSI_FRAME_IN_PROGRESS			(1 << 0)
+
+#define _DSI_INTR_MASK_REG_0		0x6b070
+#define _DSI_INTR_MASK_REG_1		0x6b870
+#define DSI_INTR_MASK_REG(port)		_MMIO_PORT(port,	\
+						   _DSI_INTR_MASK_REG_0,\
+						   _DSI_INTR_MASK_REG_1)
+
+#define _DSI_INTR_IDENT_REG_0		0x6b074
+#define _DSI_INTR_IDENT_REG_1		0x6b874
+#define DSI_INTR_IDENT_REG(port)	_MMIO_PORT(port,	\
+						   _DSI_INTR_IDENT_REG_0,\
+						   _DSI_INTR_IDENT_REG_1)
+#define   DSI_TE_EVENT				(1 << 31)
+#define   DSI_RX_DATA_OR_BTA_TERMINATED		(1 << 30)
+#define   DSI_TX_DATA				(1 << 29)
+#define   DSI_ULPS_ENTRY_DONE			(1 << 28)
+#define   DSI_NON_TE_TRIGGER_RECEIVED		(1 << 27)
+#define   DSI_HOST_CHKSUM_ERROR			(1 << 26)
+#define   DSI_HOST_MULTI_ECC_ERROR		(1 << 25)
+#define   DSI_HOST_SINGL_ECC_ERROR		(1 << 24)
+#define   DSI_HOST_CONTENTION_DETECTED		(1 << 23)
+#define   DSI_HOST_FALSE_CONTROL_ERROR		(1 << 22)
+#define   DSI_HOST_TIMEOUT_ERROR		(1 << 21)
+#define   DSI_HOST_LOW_POWER_TX_SYNC_ERROR	(1 << 20)
+#define   DSI_HOST_ESCAPE_MODE_ENTRY_ERROR	(1 << 19)
+#define   DSI_FRAME_UPDATE_DONE			(1 << 16)
+#define   DSI_PROTOCOL_VIOLATION_REPORTED	(1 << 15)
+#define   DSI_INVALID_TX_LENGTH			(1 << 13)
+#define   DSI_INVALID_VC			(1 << 12)
+#define   DSI_INVALID_DATA_TYPE			(1 << 11)
+#define   DSI_PERIPHERAL_CHKSUM_ERROR		(1 << 10)
+#define   DSI_PERIPHERAL_MULTI_ECC_ERROR	(1 << 9)
+#define   DSI_PERIPHERAL_SINGLE_ECC_ERROR	(1 << 8)
+#define   DSI_PERIPHERAL_CONTENTION_DETECTED	(1 << 7)
+#define   DSI_PERIPHERAL_FALSE_CTRL_ERROR	(1 << 6)
+#define   DSI_PERIPHERAL_TIMEOUT_ERROR		(1 << 5)
+#define   DSI_PERIPHERAL_LP_TX_SYNC_ERROR	(1 << 4)
+#define   DSI_PERIPHERAL_ESC_MODE_ENTRY_CMD_ERR	(1 << 3)
+#define   DSI_EOT_SYNC_ERROR			(1 << 2)
+#define   DSI_SOT_SYNC_ERROR			(1 << 1)
+#define   DSI_SOT_ERROR				(1 << 0)
+
 /* Gen4+ Timestamp and Pipe Frame time stamp registers */
 #define GEN4_TIMESTAMP		_MMIO(0x2358)
 #define ILK_TIMESTAMP_HI	_MMIO(0x70070)
@@ -11374,6 +11435,7 @@ enum skl_power_gate {
 #define  CMD_MODE_TE_GATE		(0x1 << 28)
 #define  VIDEO_MODE_SYNC_EVENT		(0x2 << 28)
 #define  VIDEO_MODE_SYNC_PULSE		(0x3 << 28)
+#define  TE_SOURCE_GPIO			(1 << 27)
 #define  LINK_READY			(1 << 20)
 #define  PIX_FMT_MASK			(0x3 << 16)
 #define  PIX_FMT_SHIFT			16
-- 
2.21.0.5.gaeb582a

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[RFC-v2 2/9] drm/i915/dsi: Configure transcoder operation for command mode.

[Vandita Kulkarni]

Configure the transcoder to operate in TE GATE command mode
and  take TE events from GPIO.
Also disable the periodic command mode, that GOP would have
programmed.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 36 ++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 8eb2d7f29c82..5ff2a1ffd3ea 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -704,6 +704,10 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
 				tmp |= VIDEO_MODE_SYNC_PULSE;
 				break;
 			}
+		} else {
+			tmp &= ~OP_MODE_MASK;
+			tmp |= CMD_MODE_TE_GATE;
+			tmp |= TE_SOURCE_GPIO;
 		}
 
 		I915_WRITE(DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
@@ -953,6 +957,26 @@ static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder)
 	}
 }
 
+static void gen11_dsi_config_util_pin(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	u32 tmp;
+
+	/*
+	 * used as TE i/p for DSI0,
+	 * for dual link/DSI1 TE is from slave DSI1
+	 * through GPIO.
+	 */
+	if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B)))
+		return;
+
+	tmp = I915_READ(UTIL_PIN_CTL);
+	tmp |= UTIL_PIN_DIRECTION_INPUT;
+	tmp |= UTIL_PIN_ENABLE;
+	I915_WRITE(UTIL_PIN_CTL, tmp);
+}
+
 static void
 gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
 			      const struct intel_crtc_state *pipe_config)
@@ -974,6 +998,9 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
 	/* setup D-PHY timings */
 	gen11_dsi_setup_dphy_timings(encoder);
 
+	/* Since transcoder is configured to take events from GPIO */
+	gen11_dsi_config_util_pin(encoder);
+
 	/* step 4h: setup DSI protocol timeouts */
 	gen11_dsi_setup_timeouts(encoder);
 
@@ -1104,6 +1131,15 @@ static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
 	enum transcoder dsi_trans;
 	u32 tmp;
 
+	/* disable periodic update mode */
+	if (is_cmd_mode(intel_dsi)) {
+		for_each_dsi_port(port, intel_dsi->ports) {
+			tmp = I915_READ(DSI_CMD_FRMCTL(port));
+			tmp &= ~DSI_PERIODIC_FRAME_UPDATE_ENABLE;
+			I915_WRITE(DSI_CMD_FRMCTL(port), tmp);
+		}
+	}
+
 	/* put dsi link in ULPS */
 	for_each_dsi_port(port, intel_dsi->ports) {
 		dsi_trans = dsi_port_to_transcoder(port);
-- 
2.21.0.5.gaeb582a

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[Intel-gfx] [RFC-v2 2/9] drm/i915/dsi: Configure transcoder operation for command mode.

[Vandita Kulkarni]

Configure the transcoder to operate in TE GATE command mode
and  take TE events from GPIO.
Also disable the periodic command mode, that GOP would have
programmed.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 36 ++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 8eb2d7f29c82..5ff2a1ffd3ea 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -704,6 +704,10 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
 				tmp |= VIDEO_MODE_SYNC_PULSE;
 				break;
 			}
+		} else {
+			tmp &= ~OP_MODE_MASK;
+			tmp |= CMD_MODE_TE_GATE;
+			tmp |= TE_SOURCE_GPIO;
 		}
 
 		I915_WRITE(DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
@@ -953,6 +957,26 @@ static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder)
 	}
 }
 
+static void gen11_dsi_config_util_pin(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	u32 tmp;
+
+	/*
+	 * used as TE i/p for DSI0,
+	 * for dual link/DSI1 TE is from slave DSI1
+	 * through GPIO.
+	 */
+	if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B)))
+		return;
+
+	tmp = I915_READ(UTIL_PIN_CTL);
+	tmp |= UTIL_PIN_DIRECTION_INPUT;
+	tmp |= UTIL_PIN_ENABLE;
+	I915_WRITE(UTIL_PIN_CTL, tmp);
+}
+
 static void
 gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
 			      const struct intel_crtc_state *pipe_config)
@@ -974,6 +998,9 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
 	/* setup D-PHY timings */
 	gen11_dsi_setup_dphy_timings(encoder);
 
+	/* Since transcoder is configured to take events from GPIO */
+	gen11_dsi_config_util_pin(encoder);
+
 	/* step 4h: setup DSI protocol timeouts */
 	gen11_dsi_setup_timeouts(encoder);
 
@@ -1104,6 +1131,15 @@ static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
 	enum transcoder dsi_trans;
 	u32 tmp;
 
+	/* disable periodic update mode */
+	if (is_cmd_mode(intel_dsi)) {
+		for_each_dsi_port(port, intel_dsi->ports) {
+			tmp = I915_READ(DSI_CMD_FRMCTL(port));
+			tmp &= ~DSI_PERIODIC_FRAME_UPDATE_ENABLE;
+			I915_WRITE(DSI_CMD_FRMCTL(port), tmp);
+		}
+	}
+
 	/* put dsi link in ULPS */
 	for_each_dsi_port(port, intel_dsi->ports) {
 		dsi_trans = dsi_port_to_transcoder(port);
-- 
2.21.0.5.gaeb582a

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[RFC-v2 3/9] drm/i915/dsi: Add vblank calculation for command mode

[Vandita Kulkarni]

Transcoder timing calculation differ for command mode.

v2: Use is_vid_mode, and use same I915_WRITE (Jani)

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 39 +++++++++++++++++---------
 1 file changed, 26 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 5ff2a1ffd3ea..488620365f76 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -780,6 +780,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
 	u16 hback_porch;
 	/* vertical timings */
 	u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift;
+	int bpp, line_time_us, byte_clk_period_ns;
 
 	hactive = adjusted_mode->crtc_hdisplay;
 	htotal = adjusted_mode->crtc_htotal;
@@ -817,7 +818,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
 	}
 
 	/* TRANS_HSYNC register to be programmed only for video mode */
-	if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) {
+	if (is_vid_mode(intel_dsi)) {
 		if (intel_dsi->video_mode_format ==
 		    VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE) {
 			/* BSPEC: hsync size should be atleast 16 pixels */
@@ -841,12 +842,20 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
 	}
 
 	/* program TRANS_VTOTAL register */
+	if (is_cmd_mode(intel_dsi)) {
+		bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
+		byte_clk_period_ns = 8 * 1000000 / intel_dsi->pclk;
+		htotal = hactive + 160;
+		line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count);
+		vtotal = vactive + DIV_ROUND_UP(460, line_time_us);
+	}
+
 	for_each_dsi_port(port, intel_dsi->ports) {
 		dsi_trans = dsi_port_to_transcoder(port);
 		/*
-		 * FIXME: Programing this by assuming progressive mode, since
-		 * non-interlaced info from VBT is not saved inside
-		 * struct drm_display_mode.
+		 * FIXME: Programing this by assuming progressive mode,
+		 * since non-interlaced info from VBT is not saved
+		 * inside struct drm_display_mode.
 		 * For interlace mode: program required pixel minus 2
 		 */
 		I915_WRITE(VTOTAL(dsi_trans),
@@ -859,22 +868,26 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
 	if (vsync_start < vactive)
 		DRM_ERROR("vsync_start less than vactive\n");
 
-	/* program TRANS_VSYNC register */
-	for_each_dsi_port(port, intel_dsi->ports) {
-		dsi_trans = dsi_port_to_transcoder(port);
-		I915_WRITE(VSYNC(dsi_trans),
-			   (vsync_start - 1) | ((vsync_end - 1) << 16));
+	/* program TRANS_VSYNC register for video mode only */
+	if (is_vid_mode(intel_dsi)) {
+		for_each_dsi_port(port, intel_dsi->ports) {
+			dsi_trans = dsi_port_to_transcoder(port);
+			I915_WRITE(VSYNC(dsi_trans),
+				   (vsync_start - 1) | ((vsync_end - 1) << 16));
+		}
 	}
 
 	/*
-	 * FIXME: It has to be programmed only for interlaced
+	 * FIXME: It has to be programmed only for video modes and interlaced
 	 * modes. Put the check condition here once interlaced
 	 * info available as described above.
 	 * program TRANS_VSYNCSHIFT register
 	 */
-	for_each_dsi_port(port, intel_dsi->ports) {
-		dsi_trans = dsi_port_to_transcoder(port);
-		I915_WRITE(VSYNCSHIFT(dsi_trans), vsync_shift);
+	if (is_vid_mode(intel_dsi)) {
+		for_each_dsi_port(port, intel_dsi->ports) {
+			dsi_trans = dsi_port_to_transcoder(port);
+			I915_WRITE(VSYNCSHIFT(dsi_trans), vsync_shift);
+		}
 	}
 
 	/* program TRANS_VBLANK register, should be same as vtotal programmed */
-- 
2.21.0.5.gaeb582a

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[Intel-gfx] [RFC-v2 3/9] drm/i915/dsi: Add vblank calculation for command mode

[Vandita Kulkarni]

Transcoder timing calculation differ for command mode.

v2: Use is_vid_mode, and use same I915_WRITE (Jani)

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 39 +++++++++++++++++---------
 1 file changed, 26 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 5ff2a1ffd3ea..488620365f76 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -780,6 +780,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
 	u16 hback_porch;
 	/* vertical timings */
 	u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift;
+	int bpp, line_time_us, byte_clk_period_ns;
 
 	hactive = adjusted_mode->crtc_hdisplay;
 	htotal = adjusted_mode->crtc_htotal;
@@ -817,7 +818,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
 	}
 
 	/* TRANS_HSYNC register to be programmed only for video mode */
-	if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) {
+	if (is_vid_mode(intel_dsi)) {
 		if (intel_dsi->video_mode_format ==
 		    VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE) {
 			/* BSPEC: hsync size should be atleast 16 pixels */
@@ -841,12 +842,20 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
 	}
 
 	/* program TRANS_VTOTAL register */
+	if (is_cmd_mode(intel_dsi)) {
+		bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
+		byte_clk_period_ns = 8 * 1000000 / intel_dsi->pclk;
+		htotal = hactive + 160;
+		line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count);
+		vtotal = vactive + DIV_ROUND_UP(460, line_time_us);
+	}
+
 	for_each_dsi_port(port, intel_dsi->ports) {
 		dsi_trans = dsi_port_to_transcoder(port);
 		/*
-		 * FIXME: Programing this by assuming progressive mode, since
-		 * non-interlaced info from VBT is not saved inside
-		 * struct drm_display_mode.
+		 * FIXME: Programing this by assuming progressive mode,
+		 * since non-interlaced info from VBT is not saved
+		 * inside struct drm_display_mode.
 		 * For interlace mode: program required pixel minus 2
 		 */
 		I915_WRITE(VTOTAL(dsi_trans),
@@ -859,22 +868,26 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
 	if (vsync_start < vactive)
 		DRM_ERROR("vsync_start less than vactive\n");
 
-	/* program TRANS_VSYNC register */
-	for_each_dsi_port(port, intel_dsi->ports) {
-		dsi_trans = dsi_port_to_transcoder(port);
-		I915_WRITE(VSYNC(dsi_trans),
-			   (vsync_start - 1) | ((vsync_end - 1) << 16));
+	/* program TRANS_VSYNC register for video mode only */
+	if (is_vid_mode(intel_dsi)) {
+		for_each_dsi_port(port, intel_dsi->ports) {
+			dsi_trans = dsi_port_to_transcoder(port);
+			I915_WRITE(VSYNC(dsi_trans),
+				   (vsync_start - 1) | ((vsync_end - 1) << 16));
+		}
 	}
 
 	/*
-	 * FIXME: It has to be programmed only for interlaced
+	 * FIXME: It has to be programmed only for video modes and interlaced
 	 * modes. Put the check condition here once interlaced
 	 * info available as described above.
 	 * program TRANS_VSYNCSHIFT register
 	 */
-	for_each_dsi_port(port, intel_dsi->ports) {
-		dsi_trans = dsi_port_to_transcoder(port);
-		I915_WRITE(VSYNCSHIFT(dsi_trans), vsync_shift);
+	if (is_vid_mode(intel_dsi)) {
+		for_each_dsi_port(port, intel_dsi->ports) {
+			dsi_trans = dsi_port_to_transcoder(port);
+			I915_WRITE(VSYNCSHIFT(dsi_trans), vsync_shift);
+		}
 	}
 
 	/* program TRANS_VBLANK register, should be same as vtotal programmed */
-- 
2.21.0.5.gaeb582a

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[RFC-v2 4/9] drm/i915/dsi: Add cmd mode flags in display mode private flags

[Vandita Kulkarni]

Adding TE flags and periodic command mode flags
as part of private flags to indicate what TE interrupts
we would be getting instead of vblanks in case of mipi dsi
command mode.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_types.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index fadd9853f966..f36e8e4e5b55 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -656,6 +656,12 @@ struct intel_crtc_scaler_state {
 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
 /* Flag to use the scanline counter instead of the pixel counter */
 #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2)
+/* Flag to use TE from DSI0 instead of VBI in command mode */
+#define I915_MODE_FLAG_DSI_USE_TE0 (1<<3)
+/* Flag to use TE from DSI1 instead of VBI in command mode */
+#define I915_MODE_FLAG_DSI_USE_TE1 (1<<4)
+/* Flag to indicate mipi dsi periodic command mode where we do not get TE */
+#define I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE (1<<5)
 
 struct intel_pipe_wm {
 	struct intel_wm_level wm[5];
-- 
2.21.0.5.gaeb582a

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[Intel-gfx] [RFC-v2 4/9] drm/i915/dsi: Add cmd mode flags in display mode private flags

[Vandita Kulkarni]

Adding TE flags and periodic command mode flags
as part of private flags to indicate what TE interrupts
we would be getting instead of vblanks in case of mipi dsi
command mode.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_types.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index fadd9853f966..f36e8e4e5b55 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -656,6 +656,12 @@ struct intel_crtc_scaler_state {
 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
 /* Flag to use the scanline counter instead of the pixel counter */
 #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2)
+/* Flag to use TE from DSI0 instead of VBI in command mode */
+#define I915_MODE_FLAG_DSI_USE_TE0 (1<<3)
+/* Flag to use TE from DSI1 instead of VBI in command mode */
+#define I915_MODE_FLAG_DSI_USE_TE1 (1<<4)
+/* Flag to indicate mipi dsi periodic command mode where we do not get TE */
+#define I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE (1<<5)
 
 struct intel_pipe_wm {
 	struct intel_wm_level wm[5];
-- 
2.21.0.5.gaeb582a

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[RFC-v2 5/9] drm/i915/dsi: Add check for periodic command mode

[Vandita Kulkarni]

If the GOP has programmed periodic command mode,
we need to disable that which would need a
deconfigure and configure sequence.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 488620365f76..7aadc4e9ac6f 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1287,6 +1287,21 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder,
 	adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
 }
 
+bool gen11_dsi_is_periodic_cmd_mode(struct drm_i915_private *dev_priv,
+				    struct intel_dsi *intel_dsi)
+{
+	u32 val;
+	enum transcoder dsi_trans;
+
+	if (intel_dsi->ports == BIT(PORT_B))
+		dsi_trans = TRANSCODER_DSI_1;
+	else
+		dsi_trans = TRANSCODER_DSI_0;
+
+	val = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans));
+	return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE);
+}
+
 static void gen11_dsi_get_config(struct intel_encoder *encoder,
 				 struct intel_crtc_state *pipe_config)
 {
@@ -1305,6 +1320,10 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
 	gen11_dsi_get_timings(encoder, pipe_config);
 	pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
 	pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);
+
+	if (gen11_dsi_is_periodic_cmd_mode(dev_priv, intel_dsi))
+		pipe_config->hw.adjusted_mode.private_flags |=
+					I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE;
 }
 
 static int gen11_dsi_compute_config(struct intel_encoder *encoder,
@@ -1335,6 +1354,9 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
 	pipe_config->clock_set = true;
 	pipe_config->port_clock = intel_dsi_bitrate(intel_dsi) / 5;
 
+	/* We would not opereate in peridoc command mode */
+	pipe_config->hw.adjusted_mode.private_flags &=
+					~I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE;
 	return 0;
 }
 
-- 
2.21.0.5.gaeb582a

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[Intel-gfx] [RFC-v2 5/9] drm/i915/dsi: Add check for periodic command mode

[Vandita Kulkarni]

If the GOP has programmed periodic command mode,
we need to disable that which would need a
deconfigure and configure sequence.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 488620365f76..7aadc4e9ac6f 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1287,6 +1287,21 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder,
 	adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
 }
 
+bool gen11_dsi_is_periodic_cmd_mode(struct drm_i915_private *dev_priv,
+				    struct intel_dsi *intel_dsi)
+{
+	u32 val;
+	enum transcoder dsi_trans;
+
+	if (intel_dsi->ports == BIT(PORT_B))
+		dsi_trans = TRANSCODER_DSI_1;
+	else
+		dsi_trans = TRANSCODER_DSI_0;
+
+	val = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans));
+	return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE);
+}
+
 static void gen11_dsi_get_config(struct intel_encoder *encoder,
 				 struct intel_crtc_state *pipe_config)
 {
@@ -1305,6 +1320,10 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
 	gen11_dsi_get_timings(encoder, pipe_config);
 	pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
 	pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);
+
+	if (gen11_dsi_is_periodic_cmd_mode(dev_priv, intel_dsi))
+		pipe_config->hw.adjusted_mode.private_flags |=
+					I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE;
 }
 
 static int gen11_dsi_compute_config(struct intel_encoder *encoder,
@@ -1335,6 +1354,9 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
 	pipe_config->clock_set = true;
 	pipe_config->port_clock = intel_dsi_bitrate(intel_dsi) / 5;
 
+	/* We would not opereate in peridoc command mode */
+	pipe_config->hw.adjusted_mode.private_flags &=
+					~I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE;
 	return 0;
 }
 
-- 
2.21.0.5.gaeb582a

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[RFC-v2 6/9] drm/i915/dsi: Use private flags to indicate TE in cmd mode

[Vandita Kulkarni]

On dsi cmd mode we do not receive vblanks instead
we would get TE and these flags indicate TE is expected on
which port.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 7aadc4e9ac6f..c09e8f5cd247 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1357,6 +1357,21 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
 	/* We would not opereate in peridoc command mode */
 	pipe_config->hw.adjusted_mode.private_flags &=
 					~I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE;
+
+	/*
+	 * In case of TE GATE cmd mode, we
+	 * receive TE from the slave if
+	 * dual link is enabled
+	 */
+	if (is_cmd_mode(intel_dsi)) {
+		if (intel_dsi->ports == BIT(PORT_B))
+			pipe_config->hw.adjusted_mode.private_flags |=
+						I915_MODE_FLAG_DSI_USE_TE1;
+		else
+			pipe_config->hw.adjusted_mode.private_flags |=
+						I915_MODE_FLAG_DSI_USE_TE0;
+	}
+
 	return 0;
 }
 
-- 
2.21.0.5.gaeb582a

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[Intel-gfx] [RFC-v2 6/9] drm/i915/dsi: Use private flags to indicate TE in cmd mode

[Vandita Kulkarni]

On dsi cmd mode we do not receive vblanks instead
we would get TE and these flags indicate TE is expected on
which port.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 7aadc4e9ac6f..c09e8f5cd247 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1357,6 +1357,21 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
 	/* We would not opereate in peridoc command mode */
 	pipe_config->hw.adjusted_mode.private_flags &=
 					~I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE;
+
+	/*
+	 * In case of TE GATE cmd mode, we
+	 * receive TE from the slave if
+	 * dual link is enabled
+	 */
+	if (is_cmd_mode(intel_dsi)) {
+		if (intel_dsi->ports == BIT(PORT_B))
+			pipe_config->hw.adjusted_mode.private_flags |=
+						I915_MODE_FLAG_DSI_USE_TE1;
+		else
+			pipe_config->hw.adjusted_mode.private_flags |=
+						I915_MODE_FLAG_DSI_USE_TE0;
+	}
+
 	return 0;
 }
 
-- 
2.21.0.5.gaeb582a

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[RFC-v2 7/9] drm/i915/dsi: Configure TE interrupt for cmd mode

[Vandita Kulkarni]

We need to configure TE interrupt in two places.
Port interrupt and DSI interrupt mask registers.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 58 +++++++++++++++++++++++++++++++--
 1 file changed, 56 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index dae00f7dd7df..f27afde409bf 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -41,6 +41,7 @@
 #include "display/intel_hotplug.h"
 #include "display/intel_lpe_audio.h"
 #include "display/intel_psr.h"
+#include "display/intel_dsi.h"
 
 #include "gt/intel_gt.h"
 #include "gt/intel_gt_irq.h"
@@ -2571,12 +2572,45 @@ int ilk_enable_vblank(struct drm_crtc *crtc)
 	return 0;
 }
 
+static void gen11_dsi_configure_te(struct drm_i915_private *dev_priv,
+				   struct drm_display_mode *mode, bool enable)
+{
+	enum port port;
+	u32 tmp;
+
+	if (mode->private_flags & I915_MODE_FLAG_DSI_USE_TE1)
+		port = PORT_B;
+	else
+		port = PORT_A;
+
+	tmp =  I915_READ(DSI_INTR_MASK_REG(port));
+	if (enable)
+		tmp &= ~DSI_TE_EVENT;
+	else
+		tmp |= DSI_TE_EVENT;
+
+	I915_WRITE(DSI_INTR_MASK_REG(port), tmp);
+}
+
 int bdw_enable_vblank(struct drm_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
-	enum pipe pipe = to_intel_crtc(crtc)->pipe;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	enum pipe pipe = intel_crtc->pipe;
+	struct drm_vblank_crtc *vblank;
+	struct drm_display_mode *mode;
 	unsigned long irqflags;
 
+	vblank = &crtc->dev->vblank[drm_crtc_index(crtc)];
+	mode = &vblank->hwmode;
+
+	if ((INTEL_GEN(dev_priv) >= 11) &&
+	    (mode->private_flags &
+	     (I915_MODE_FLAG_DSI_USE_TE1 | I915_MODE_FLAG_DSI_USE_TE0))) {
+		gen11_dsi_configure_te(dev_priv, mode, true);
+		return 0;
+	}
+
 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 	bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
@@ -2642,9 +2676,22 @@ void ilk_disable_vblank(struct drm_crtc *crtc)
 void bdw_disable_vblank(struct drm_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
-	enum pipe pipe = to_intel_crtc(crtc)->pipe;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	enum pipe pipe = intel_crtc->pipe;
+	struct drm_vblank_crtc *vblank;
+	struct drm_display_mode *mode;
 	unsigned long irqflags;
 
+	vblank = &crtc->dev->vblank[drm_crtc_index(crtc)];
+	mode = &vblank->hwmode;
+
+	if ((INTEL_GEN(dev_priv) >= 11) &&
+	    (mode->private_flags &
+	     (I915_MODE_FLAG_DSI_USE_TE1 | I915_MODE_FLAG_DSI_USE_TE0))) {
+		gen11_dsi_configure_te(dev_priv, mode, false);
+		return;
+	}
+
 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 	bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
@@ -3350,6 +3397,13 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 		gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
 	}
 
+	if (INTEL_GEN(dev_priv) >= 11) {
+		enum port port;
+
+		if (intel_bios_is_dsi_present(dev_priv, &port))
+			de_port_masked |= DSI0_TE | DSI1_TE;
+	}
+
 	for_each_pipe(dev_priv, pipe) {
 		dev_priv->de_irq_mask[pipe] = ~de_pipe_masked;
 
-- 
2.21.0.5.gaeb582a

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[Intel-gfx] [RFC-v2 7/9] drm/i915/dsi: Configure TE interrupt for cmd mode

[Vandita Kulkarni]

We need to configure TE interrupt in two places.
Port interrupt and DSI interrupt mask registers.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 58 +++++++++++++++++++++++++++++++--
 1 file changed, 56 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index dae00f7dd7df..f27afde409bf 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -41,6 +41,7 @@
 #include "display/intel_hotplug.h"
 #include "display/intel_lpe_audio.h"
 #include "display/intel_psr.h"
+#include "display/intel_dsi.h"
 
 #include "gt/intel_gt.h"
 #include "gt/intel_gt_irq.h"
@@ -2571,12 +2572,45 @@ int ilk_enable_vblank(struct drm_crtc *crtc)
 	return 0;
 }
 
+static void gen11_dsi_configure_te(struct drm_i915_private *dev_priv,
+				   struct drm_display_mode *mode, bool enable)
+{
+	enum port port;
+	u32 tmp;
+
+	if (mode->private_flags & I915_MODE_FLAG_DSI_USE_TE1)
+		port = PORT_B;
+	else
+		port = PORT_A;
+
+	tmp =  I915_READ(DSI_INTR_MASK_REG(port));
+	if (enable)
+		tmp &= ~DSI_TE_EVENT;
+	else
+		tmp |= DSI_TE_EVENT;
+
+	I915_WRITE(DSI_INTR_MASK_REG(port), tmp);
+}
+
 int bdw_enable_vblank(struct drm_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
-	enum pipe pipe = to_intel_crtc(crtc)->pipe;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	enum pipe pipe = intel_crtc->pipe;
+	struct drm_vblank_crtc *vblank;
+	struct drm_display_mode *mode;
 	unsigned long irqflags;
 
+	vblank = &crtc->dev->vblank[drm_crtc_index(crtc)];
+	mode = &vblank->hwmode;
+
+	if ((INTEL_GEN(dev_priv) >= 11) &&
+	    (mode->private_flags &
+	     (I915_MODE_FLAG_DSI_USE_TE1 | I915_MODE_FLAG_DSI_USE_TE0))) {
+		gen11_dsi_configure_te(dev_priv, mode, true);
+		return 0;
+	}
+
 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 	bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
@@ -2642,9 +2676,22 @@ void ilk_disable_vblank(struct drm_crtc *crtc)
 void bdw_disable_vblank(struct drm_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
-	enum pipe pipe = to_intel_crtc(crtc)->pipe;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	enum pipe pipe = intel_crtc->pipe;
+	struct drm_vblank_crtc *vblank;
+	struct drm_display_mode *mode;
 	unsigned long irqflags;
 
+	vblank = &crtc->dev->vblank[drm_crtc_index(crtc)];
+	mode = &vblank->hwmode;
+
+	if ((INTEL_GEN(dev_priv) >= 11) &&
+	    (mode->private_flags &
+	     (I915_MODE_FLAG_DSI_USE_TE1 | I915_MODE_FLAG_DSI_USE_TE0))) {
+		gen11_dsi_configure_te(dev_priv, mode, false);
+		return;
+	}
+
 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 	bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
@@ -3350,6 +3397,13 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 		gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
 	}
 
+	if (INTEL_GEN(dev_priv) >= 11) {
+		enum port port;
+
+		if (intel_bios_is_dsi_present(dev_priv, &port))
+			de_port_masked |= DSI0_TE | DSI1_TE;
+	}
+
 	for_each_pipe(dev_priv, pipe) {
 		dev_priv->de_irq_mask[pipe] = ~de_pipe_masked;
 
-- 
2.21.0.5.gaeb582a

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[RFC-v2 8/9] drm/i915/dsi: Add TE handler for dsi cmd mode.

[Vandita Kulkarni]

In case of dual link, we get the TE on slave.
So clear the TE on slave DSI IIR.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 62 +++++++++++++++++++++++++++++++++
 1 file changed, 62 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f27afde409bf..34a06876a2d7 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2230,6 +2230,62 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
 		DRM_ERROR("Unexpected DE Misc interrupt\n");
 }
 
+void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,
+				    u32 iir_value)
+{
+	enum pipe pipe = INVALID_PIPE;
+	enum transcoder dsi_trans;
+	enum port port;
+	u32 val, tmp;
+
+	/*
+	 * Incase of dual link, TE comes from DSI_1
+	 * this is to check if dual link is enabled
+	 */
+	val = I915_READ(TRANS_DDI_FUNC_CTL2(TRANSCODER_DSI_0));
+	val &= PORT_SYNC_MODE_ENABLE;
+
+	/*
+	 * if dual link is enabled, then read DSI_0
+	 * transcoder registers
+	 */
+	port = ((iir_value & DSI1_TE && val) || (iir_value & DSI0_TE)) ?
+								PORT_A : PORT_B;
+	dsi_trans = (port == PORT_A) ? TRANSCODER_DSI_0 : TRANSCODER_DSI_1;
+
+	/* Check if DSI configured in command mode */
+	val = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans));
+	val = (val & OP_MODE_MASK) >> 28;
+
+	if (val) {
+		DRM_ERROR("DSI trancoder not configured in command mode\n");
+		return;
+	}
+
+	/* Get PIPE for handling VBLANK event */
+	val = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
+	switch (val & TRANS_DDI_EDP_INPUT_MASK) {
+	case TRANS_DDI_EDP_INPUT_A_ON:
+		pipe = PIPE_A;
+		break;
+	case TRANS_DDI_EDP_INPUT_B_ONOFF:
+		pipe = PIPE_B;
+		break;
+	case TRANS_DDI_EDP_INPUT_C_ONOFF:
+		pipe = PIPE_C;
+		break;
+	default:
+		DRM_ERROR("Invalid PIPE\n");
+	}
+
+	/* clear TE in dsi IIR */
+	port = (iir_value & DSI1_TE) ? PORT_B : PORT_A;
+	tmp = I915_READ(DSI_INTR_IDENT_REG(port));
+	I915_WRITE(DSI_INTR_IDENT_REG(port), tmp);
+
+	drm_handle_vblank(&dev_priv->drm, pipe);
+}
+
 static irqreturn_t
 gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 {
@@ -2294,6 +2350,12 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 				found = true;
 			}
 
+			if ((INTEL_GEN(dev_priv) >= 11) &&
+				(iir & (DSI0_TE | DSI1_TE))) {
+				gen11_dsi_te_interrupt_handler(dev_priv, iir);
+				found = true;
+			}
+
 			if (!found)
 				DRM_ERROR("Unexpected DE Port interrupt\n");
 		}
-- 
2.21.0.5.gaeb582a

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[Intel-gfx] [RFC-v2 8/9] drm/i915/dsi: Add TE handler for dsi cmd mode.

[Vandita Kulkarni]

In case of dual link, we get the TE on slave.
So clear the TE on slave DSI IIR.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 62 +++++++++++++++++++++++++++++++++
 1 file changed, 62 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f27afde409bf..34a06876a2d7 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2230,6 +2230,62 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
 		DRM_ERROR("Unexpected DE Misc interrupt\n");
 }
 
+void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,
+				    u32 iir_value)
+{
+	enum pipe pipe = INVALID_PIPE;
+	enum transcoder dsi_trans;
+	enum port port;
+	u32 val, tmp;
+
+	/*
+	 * Incase of dual link, TE comes from DSI_1
+	 * this is to check if dual link is enabled
+	 */
+	val = I915_READ(TRANS_DDI_FUNC_CTL2(TRANSCODER_DSI_0));
+	val &= PORT_SYNC_MODE_ENABLE;
+
+	/*
+	 * if dual link is enabled, then read DSI_0
+	 * transcoder registers
+	 */
+	port = ((iir_value & DSI1_TE && val) || (iir_value & DSI0_TE)) ?
+								PORT_A : PORT_B;
+	dsi_trans = (port == PORT_A) ? TRANSCODER_DSI_0 : TRANSCODER_DSI_1;
+
+	/* Check if DSI configured in command mode */
+	val = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans));
+	val = (val & OP_MODE_MASK) >> 28;
+
+	if (val) {
+		DRM_ERROR("DSI trancoder not configured in command mode\n");
+		return;
+	}
+
+	/* Get PIPE for handling VBLANK event */
+	val = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
+	switch (val & TRANS_DDI_EDP_INPUT_MASK) {
+	case TRANS_DDI_EDP_INPUT_A_ON:
+		pipe = PIPE_A;
+		break;
+	case TRANS_DDI_EDP_INPUT_B_ONOFF:
+		pipe = PIPE_B;
+		break;
+	case TRANS_DDI_EDP_INPUT_C_ONOFF:
+		pipe = PIPE_C;
+		break;
+	default:
+		DRM_ERROR("Invalid PIPE\n");
+	}
+
+	/* clear TE in dsi IIR */
+	port = (iir_value & DSI1_TE) ? PORT_B : PORT_A;
+	tmp = I915_READ(DSI_INTR_IDENT_REG(port));
+	I915_WRITE(DSI_INTR_IDENT_REG(port), tmp);
+
+	drm_handle_vblank(&dev_priv->drm, pipe);
+}
+
 static irqreturn_t
 gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 {
@@ -2294,6 +2350,12 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 				found = true;
 			}
 
+			if ((INTEL_GEN(dev_priv) >= 11) &&
+				(iir & (DSI0_TE | DSI1_TE))) {
+				gen11_dsi_te_interrupt_handler(dev_priv, iir);
+				found = true;
+			}
+
 			if (!found)
 				DRM_ERROR("Unexpected DE Port interrupt\n");
 		}
-- 
2.21.0.5.gaeb582a

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[RFC-v2 9/9] drm/i915/dsi: Initiate fame request in cmd mode

[Vandita Kulkarni]

In TE Gate mode, on every flip we need to set the
frame update request bit. After this  bit is set
transcoder hardware will automatically send the
frame data to the panel when it receives the TE event.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c       | 22 ++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_display.c | 10 +++++++++
 drivers/gpu/drm/i915/display/intel_dsi.h     |  3 +++
 3 files changed, 35 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index c09e8f5cd247..4cd0998b05ed 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -198,6 +198,28 @@ static int dsi_send_pkt_payld(struct intel_dsi_host *host,
 	return 0;
 }
 
+void gen11_dsi_frame_update(struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	u32 tmp, private_flags;
+	enum port port;
+
+	private_flags = crtc_state->hw.adjusted_mode.private_flags;
+
+	/* case 1 also covers dual link */
+	if (private_flags & I915_MODE_FLAG_DSI_USE_TE0)
+		port = PORT_A;
+	else if (private_flags & I915_MODE_FLAG_DSI_USE_TE1)
+		port = PORT_B;
+	else
+		return;
+
+	tmp = I915_READ(DSI_CMD_FRMCTL(port));
+	tmp |= DSI_FRAME_UPDATE_REQUEST;
+	I915_WRITE(DSI_CMD_FRMCTL(port), tmp);
+}
+
 static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 876fc25968bf..066dfddb9aac 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14844,6 +14844,16 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 			intel_color_load_luts(new_crtc_state);
 	}
 
+	/*
+	 * Incase of mipi dsi command mode, we need to set frame update
+	 * for every commit
+	 */
+	if ((INTEL_GEN(dev_priv) >= 11) &&
+	    (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))) {
+		if (new_crtc_state->hw.active)
+			gen11_dsi_frame_update(new_crtc_state);
+	}
+
 	/*
 	 * Now that the vblank has passed, we can go ahead and program the
 	 * optimal watermarks on platforms that need two-step watermark
diff --git a/drivers/gpu/drm/i915/display/intel_dsi.h b/drivers/gpu/drm/i915/display/intel_dsi.h
index b15be5814599..0c5366e23feb 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi.h
+++ b/drivers/gpu/drm/i915/display/intel_dsi.h
@@ -201,6 +201,9 @@ u32 bxt_dsi_get_pclk(struct intel_encoder *encoder,
 		     struct intel_crtc_state *config);
 void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port);
 
+/* icl_dsi.c */
+void gen11_dsi_frame_update(struct intel_crtc_state *crtc_state);
+
 /* intel_dsi_vbt.c */
 bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id);
 void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
-- 
2.21.0.5.gaeb582a

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[Intel-gfx] [RFC-v2 9/9] drm/i915/dsi: Initiate fame request in cmd mode

[Vandita Kulkarni]

In TE Gate mode, on every flip we need to set the
frame update request bit. After this  bit is set
transcoder hardware will automatically send the
frame data to the panel when it receives the TE event.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c       | 22 ++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_display.c | 10 +++++++++
 drivers/gpu/drm/i915/display/intel_dsi.h     |  3 +++
 3 files changed, 35 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index c09e8f5cd247..4cd0998b05ed 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -198,6 +198,28 @@ static int dsi_send_pkt_payld(struct intel_dsi_host *host,
 	return 0;
 }
 
+void gen11_dsi_frame_update(struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	u32 tmp, private_flags;
+	enum port port;
+
+	private_flags = crtc_state->hw.adjusted_mode.private_flags;
+
+	/* case 1 also covers dual link */
+	if (private_flags & I915_MODE_FLAG_DSI_USE_TE0)
+		port = PORT_A;
+	else if (private_flags & I915_MODE_FLAG_DSI_USE_TE1)
+		port = PORT_B;
+	else
+		return;
+
+	tmp = I915_READ(DSI_CMD_FRMCTL(port));
+	tmp |= DSI_FRAME_UPDATE_REQUEST;
+	I915_WRITE(DSI_CMD_FRMCTL(port), tmp);
+}
+
 static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 876fc25968bf..066dfddb9aac 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14844,6 +14844,16 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 			intel_color_load_luts(new_crtc_state);
 	}
 
+	/*
+	 * Incase of mipi dsi command mode, we need to set frame update
+	 * for every commit
+	 */
+	if ((INTEL_GEN(dev_priv) >= 11) &&
+	    (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))) {
+		if (new_crtc_state->hw.active)
+			gen11_dsi_frame_update(new_crtc_state);
+	}
+
 	/*
 	 * Now that the vblank has passed, we can go ahead and program the
 	 * optimal watermarks on platforms that need two-step watermark
diff --git a/drivers/gpu/drm/i915/display/intel_dsi.h b/drivers/gpu/drm/i915/display/intel_dsi.h
index b15be5814599..0c5366e23feb 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi.h
+++ b/drivers/gpu/drm/i915/display/intel_dsi.h
@@ -201,6 +201,9 @@ u32 bxt_dsi_get_pclk(struct intel_encoder *encoder,
 		     struct intel_crtc_state *config);
 void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port);
 
+/* icl_dsi.c */
+void gen11_dsi_frame_update(struct intel_crtc_state *crtc_state);
+
 /* intel_dsi_vbt.c */
 bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id);
 void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
-- 
2.21.0.5.gaeb582a

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✗ Fi.CI.CHECKPATCH: warning for Add support for mipi dsi cmd mode

[Patchwork]

== Series Details ==

Series: Add support for mipi dsi cmd mode
URL   : https://patchwork.freedesktop.org/series/69290/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
8ed082b3989c drm/i915/dsi: Define command mode registers
0b38d9ee6cc7 drm/i915/dsi: Configure transcoder operation for command mode.
8f9408cd0e36 drm/i915/dsi: Add vblank calculation for command mode
-:41: WARNING:LONG_LINE: line over 100 characters
#41: FILE: drivers/gpu/drm/i915/display/icl_dsi.c:849:
+		line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count);

total: 0 errors, 1 warnings, 0 checks, 73 lines checked
c7165f4ca05e drm/i915/dsi: Add cmd mode flags in display mode private flags
-:23: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#23: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:660:
+#define I915_MODE_FLAG_DSI_USE_TE0 (1<<3)
                                      ^

-:25: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#25: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:662:
+#define I915_MODE_FLAG_DSI_USE_TE1 (1<<4)
                                      ^

-:27: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#27: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:664:
+#define I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE (1<<5)
                                                ^

total: 0 errors, 0 warnings, 3 checks, 12 lines checked
0f3617d1c756 drm/i915/dsi: Add check for periodic command mode
d019b5c741be drm/i915/dsi: Use private flags to indicate TE in cmd mode
69add0aa66f3 drm/i915/dsi: Configure TE interrupt for cmd mode
1bce11022cf8 drm/i915/dsi: Add TE handler for dsi cmd mode.
-:83: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#83: FILE: drivers/gpu/drm/i915/i915_irq.c:2354:
+			if ((INTEL_GEN(dev_priv) >= 11) &&
+				(iir & (DSI0_TE | DSI1_TE))) {

total: 0 errors, 0 warnings, 1 checks, 74 lines checked
27a7a9b5a70e drm/i915/dsi: Initiate fame request in cmd mode

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add support for mipi dsi cmd mode

[Patchwork]

== Series Details ==

Series: Add support for mipi dsi cmd mode
URL   : https://patchwork.freedesktop.org/series/69290/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
8ed082b3989c drm/i915/dsi: Define command mode registers
0b38d9ee6cc7 drm/i915/dsi: Configure transcoder operation for command mode.
8f9408cd0e36 drm/i915/dsi: Add vblank calculation for command mode
-:41: WARNING:LONG_LINE: line over 100 characters
#41: FILE: drivers/gpu/drm/i915/display/icl_dsi.c:849:
+		line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count);

total: 0 errors, 1 warnings, 0 checks, 73 lines checked
c7165f4ca05e drm/i915/dsi: Add cmd mode flags in display mode private flags
-:23: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#23: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:660:
+#define I915_MODE_FLAG_DSI_USE_TE0 (1<<3)
                                      ^

-:25: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#25: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:662:
+#define I915_MODE_FLAG_DSI_USE_TE1 (1<<4)
                                      ^

-:27: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#27: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:664:
+#define I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE (1<<5)
                                                ^

total: 0 errors, 0 warnings, 3 checks, 12 lines checked
0f3617d1c756 drm/i915/dsi: Add check for periodic command mode
d019b5c741be drm/i915/dsi: Use private flags to indicate TE in cmd mode
69add0aa66f3 drm/i915/dsi: Configure TE interrupt for cmd mode
1bce11022cf8 drm/i915/dsi: Add TE handler for dsi cmd mode.
-:83: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#83: FILE: drivers/gpu/drm/i915/i915_irq.c:2354:
+			if ((INTEL_GEN(dev_priv) >= 11) &&
+				(iir & (DSI0_TE | DSI1_TE))) {

total: 0 errors, 0 warnings, 1 checks, 74 lines checked
27a7a9b5a70e drm/i915/dsi: Initiate fame request in cmd mode

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✗ Fi.CI.SPARSE: warning for Add support for mipi dsi cmd mode

[Patchwork]

== Series Details ==

Series: Add support for mipi dsi cmd mode
URL   : https://patchwork.freedesktop.org/series/69290/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/dsi: Define command mode registers
Okay!

Commit: drm/i915/dsi: Configure transcoder operation for command mode.
Okay!

Commit: drm/i915/dsi: Add vblank calculation for command mode
Okay!

Commit: drm/i915/dsi: Add cmd mode flags in display mode private flags
Okay!

Commit: drm/i915/dsi: Add check for periodic command mode
-
+drivers/gpu/drm/i915/display/icl_dsi.c:1290:6: warning: symbol 'gen11_dsi_is_periodic_cmd_mode' was not declared. Should it be static?

Commit: drm/i915/dsi: Use private flags to indicate TE in cmd mode
Okay!

Commit: drm/i915/dsi: Configure TE interrupt for cmd mode
Okay!

Commit: drm/i915/dsi: Add TE handler for dsi cmd mode.
-
+drivers/gpu/drm/i915/i915_irq.c:2233:6: warning: symbol 'gen11_dsi_te_interrupt_handler' was not declared. Should it be static?

Commit: drm/i915/dsi: Initiate fame request in cmd mode
Okay!

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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add support for mipi dsi cmd mode

[Patchwork]

== Series Details ==

Series: Add support for mipi dsi cmd mode
URL   : https://patchwork.freedesktop.org/series/69290/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/dsi: Define command mode registers
Okay!

Commit: drm/i915/dsi: Configure transcoder operation for command mode.
Okay!

Commit: drm/i915/dsi: Add vblank calculation for command mode
Okay!

Commit: drm/i915/dsi: Add cmd mode flags in display mode private flags
Okay!

Commit: drm/i915/dsi: Add check for periodic command mode
-
+drivers/gpu/drm/i915/display/icl_dsi.c:1290:6: warning: symbol 'gen11_dsi_is_periodic_cmd_mode' was not declared. Should it be static?

Commit: drm/i915/dsi: Use private flags to indicate TE in cmd mode
Okay!

Commit: drm/i915/dsi: Configure TE interrupt for cmd mode
Okay!

Commit: drm/i915/dsi: Add TE handler for dsi cmd mode.
-
+drivers/gpu/drm/i915/i915_irq.c:2233:6: warning: symbol 'gen11_dsi_te_interrupt_handler' was not declared. Should it be static?

Commit: drm/i915/dsi: Initiate fame request in cmd mode
Okay!

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✓ Fi.CI.BAT: success for Add support for mipi dsi cmd mode

[Patchwork]

== Series Details ==

Series: Add support for mipi dsi cmd mode
URL   : https://patchwork.freedesktop.org/series/69290/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7310 -> Patchwork_15214
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/index.html

Known issues
------------

  Here are the changes found in Patchwork_15214 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@debugfs_test@read_all_entries:
    - fi-icl-u3:          [PASS][1] -> [INCOMPLETE][2] ([fdo#107713])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/fi-icl-u3/igt@debugfs_test@read_all_entries.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/fi-icl-u3/igt@debugfs_test@read_all_entries.html
    - fi-icl-u2:          [PASS][3] -> [INCOMPLETE][4] ([fdo#107713])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/fi-icl-u2/igt@debugfs_test@read_all_entries.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/fi-icl-u2/igt@debugfs_test@read_all_entries.html
    - fi-icl-u4:          [PASS][5] -> [INCOMPLETE][6] ([fdo#107713])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/fi-icl-u4/igt@debugfs_test@read_all_entries.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/fi-icl-u4/igt@debugfs_test@read_all_entries.html
    - fi-icl-y:           [PASS][7] -> [INCOMPLETE][8] ([fdo#107713])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/fi-icl-y/igt@debugfs_test@read_all_entries.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/fi-icl-y/igt@debugfs_test@read_all_entries.html
    - fi-icl-dsi:         [PASS][9] -> [INCOMPLETE][10] ([fdo#107713])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/fi-icl-dsi/igt@debugfs_test@read_all_entries.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/fi-icl-dsi/igt@debugfs_test@read_all_entries.html
    - fi-icl-guc:         [PASS][11] -> [INCOMPLETE][12] ([fdo#107713])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/fi-icl-guc/igt@debugfs_test@read_all_entries.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/fi-icl-guc/igt@debugfs_test@read_all_entries.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [PASS][13] -> [FAIL][14] ([fdo#111045] / [fdo#111096])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096


Participating hosts (51 -> 45)
------------------------------

  Additional (1): fi-bwr-2160 
  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7310 -> Patchwork_15214

  CI-20190529: 20190529
  CI_DRM_7310: f3edc24676599b6c4e6ab713030ae630e864e732 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5271: 05f0400c50af843df301efb5475e9f5e2d16a098 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15214: 27a7a9b5a70e93156c83503a7cae444d06c76659 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

27a7a9b5a70e drm/i915/dsi: Initiate fame request in cmd mode
1bce11022cf8 drm/i915/dsi: Add TE handler for dsi cmd mode.
69add0aa66f3 drm/i915/dsi: Configure TE interrupt for cmd mode
d019b5c741be drm/i915/dsi: Use private flags to indicate TE in cmd mode
0f3617d1c756 drm/i915/dsi: Add check for periodic command mode
c7165f4ca05e drm/i915/dsi: Add cmd mode flags in display mode private flags
8f9408cd0e36 drm/i915/dsi: Add vblank calculation for command mode
0b38d9ee6cc7 drm/i915/dsi: Configure transcoder operation for command mode.
8ed082b3989c drm/i915/dsi: Define command mode registers

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/index.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for Add support for mipi dsi cmd mode

[Patchwork]

== Series Details ==

Series: Add support for mipi dsi cmd mode
URL   : https://patchwork.freedesktop.org/series/69290/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7310 -> Patchwork_15214
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/index.html

Known issues
------------

  Here are the changes found in Patchwork_15214 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@debugfs_test@read_all_entries:
    - fi-icl-u3:          [PASS][1] -> [INCOMPLETE][2] ([fdo#107713])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/fi-icl-u3/igt@debugfs_test@read_all_entries.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/fi-icl-u3/igt@debugfs_test@read_all_entries.html
    - fi-icl-u2:          [PASS][3] -> [INCOMPLETE][4] ([fdo#107713])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/fi-icl-u2/igt@debugfs_test@read_all_entries.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/fi-icl-u2/igt@debugfs_test@read_all_entries.html
    - fi-icl-u4:          [PASS][5] -> [INCOMPLETE][6] ([fdo#107713])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/fi-icl-u4/igt@debugfs_test@read_all_entries.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/fi-icl-u4/igt@debugfs_test@read_all_entries.html
    - fi-icl-y:           [PASS][7] -> [INCOMPLETE][8] ([fdo#107713])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/fi-icl-y/igt@debugfs_test@read_all_entries.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/fi-icl-y/igt@debugfs_test@read_all_entries.html
    - fi-icl-dsi:         [PASS][9] -> [INCOMPLETE][10] ([fdo#107713])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/fi-icl-dsi/igt@debugfs_test@read_all_entries.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/fi-icl-dsi/igt@debugfs_test@read_all_entries.html
    - fi-icl-guc:         [PASS][11] -> [INCOMPLETE][12] ([fdo#107713])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/fi-icl-guc/igt@debugfs_test@read_all_entries.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/fi-icl-guc/igt@debugfs_test@read_all_entries.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [PASS][13] -> [FAIL][14] ([fdo#111045] / [fdo#111096])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096


Participating hosts (51 -> 45)
------------------------------

  Additional (1): fi-bwr-2160 
  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7310 -> Patchwork_15214

  CI-20190529: 20190529
  CI_DRM_7310: f3edc24676599b6c4e6ab713030ae630e864e732 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5271: 05f0400c50af843df301efb5475e9f5e2d16a098 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15214: 27a7a9b5a70e93156c83503a7cae444d06c76659 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

27a7a9b5a70e drm/i915/dsi: Initiate fame request in cmd mode
1bce11022cf8 drm/i915/dsi: Add TE handler for dsi cmd mode.
69add0aa66f3 drm/i915/dsi: Configure TE interrupt for cmd mode
d019b5c741be drm/i915/dsi: Use private flags to indicate TE in cmd mode
0f3617d1c756 drm/i915/dsi: Add check for periodic command mode
c7165f4ca05e drm/i915/dsi: Add cmd mode flags in display mode private flags
8f9408cd0e36 drm/i915/dsi: Add vblank calculation for command mode
0b38d9ee6cc7 drm/i915/dsi: Configure transcoder operation for command mode.
8ed082b3989c drm/i915/dsi: Define command mode registers

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/index.html
_______________________________________________
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✗ Fi.CI.IGT: failure for Add support for mipi dsi cmd mode

[Patchwork]

== Series Details ==

Series: Add support for mipi dsi cmd mode
URL   : https://patchwork.freedesktop.org/series/69290/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_7310_full -> Patchwork_15214_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_15214_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_15214_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_15214_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_busy@extended-modeset-hang-oldfb-render-pipe-b:
    - shard-iclb:         [PASS][1] -> [DMESG-FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-iclb3/igt@kms_busy@extended-modeset-hang-oldfb-render-pipe-b.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-iclb7/igt@kms_busy@extended-modeset-hang-oldfb-render-pipe-b.html
    - shard-tglb:         [PASS][3] -> [DMESG-FAIL][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-tglb2/igt@kms_busy@extended-modeset-hang-oldfb-render-pipe-b.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-tglb9/igt@kms_busy@extended-modeset-hang-oldfb-render-pipe-b.html

  * igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-cpu:
    - shard-tglb:         [PASS][5] -> [INCOMPLETE][6] +15 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-tglb9/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-cpu.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-tglb6/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-cpu.html

  
Known issues
------------

  Here are the changes found in Patchwork_15214_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_persistent_relocs@forked-interruptible-thrash-inactive:
    - shard-hsw:          [PASS][7] -> [FAIL][8] ([fdo#112037])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-hsw2/igt@gem_persistent_relocs@forked-interruptible-thrash-inactive.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-hsw6/igt@gem_persistent_relocs@forked-interruptible-thrash-inactive.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy:
    - shard-snb:          [PASS][9] -> [DMESG-WARN][10] ([fdo#111870])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-snb6/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-snb2/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
    - shard-hsw:          [PASS][11] -> [DMESG-WARN][12] ([fdo#111870])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-hsw2/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-hsw7/igt@gem_userptr_blits@map-fixed-invalidate-busy.html

  * igt@i915_pm_rpm@pm-caching:
    - shard-iclb:         [PASS][13] -> [INCOMPLETE][14] ([fdo#107713] / [fdo#108840])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-iclb7/igt@i915_pm_rpm@pm-caching.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-iclb3/igt@i915_pm_rpm@pm-caching.html

  * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
    - shard-hsw:          [PASS][15] -> [FAIL][16] ([fdo#105767])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-hsw2/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-hsw1/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
    - shard-glk:          [PASS][17] -> [FAIL][18] ([fdo#104873])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-glk2/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-glk1/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html

  * igt@kms_cursor_legacy@pipe-a-torture-move:
    - shard-tglb:         [PASS][19] -> [INCOMPLETE][20] ([fdo#112035 ]) +2 similar issues
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-tglb8/igt@kms_cursor_legacy@pipe-a-torture-move.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-tglb9/igt@kms_cursor_legacy@pipe-a-torture-move.html

  * igt@kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset-interruptible:
    - shard-tglb:         [PASS][21] -> [INCOMPLETE][22] ([fdo#112031]) +1 similar issue
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-tglb6/igt@kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset-interruptible.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-tglb4/igt@kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset-interruptible.html

  * igt@kms_flip_tiling@flip-y-tiled:
    - shard-tglb:         [PASS][23] -> [INCOMPLETE][24] ([fdo#111747] / [fdo#112031]) +1 similar issue
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-tglb3/igt@kms_flip_tiling@flip-y-tiled.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-tglb9/igt@kms_flip_tiling@flip-y-tiled.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-tglb:         [PASS][25] -> [INCOMPLETE][26] ([fdo#111884]) +3 similar issues
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-tglb9/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-wc.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-tglb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move:
    - shard-iclb:         [PASS][27] -> [INCOMPLETE][28] ([fdo#106978] / [fdo#107713]) +5 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-iclb8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-iclb5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - shard-kbl:          [PASS][29] -> [DMESG-WARN][30] ([fdo#108566]) +9 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-kbl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-kbl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
    - shard-apl:          [PASS][31] -> [DMESG-WARN][32] ([fdo#108566]) +2 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-apl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html

  * igt@kms_psr@sprite_mmap_gtt:
    - shard-iclb:         [PASS][33] -> [INCOMPLETE][34] ([fdo#107713]) +24 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-iclb8/igt@kms_psr@sprite_mmap_gtt.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-iclb5/igt@kms_psr@sprite_mmap_gtt.html

  * igt@kms_rotation_crc@cursor-rotation-180:
    - shard-iclb:         [PASS][35] -> [INCOMPLETE][36] ([fdo#107713] / [fdo#110026])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-iclb3/igt@kms_rotation_crc@cursor-rotation-180.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-iclb7/igt@kms_rotation_crc@cursor-rotation-180.html

  * igt@kms_setmode@basic:
    - shard-skl:          [PASS][37] -> [FAIL][38] ([fdo#99912])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-skl1/igt@kms_setmode@basic.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-skl1/igt@kms_setmode@basic.html

  * igt@kms_vblank@pipe-a-wait-forked-busy-hang:
    - shard-hsw:          [PASS][39] -> [INCOMPLETE][40] ([fdo#103540])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-hsw1/igt@kms_vblank@pipe-a-wait-forked-busy-hang.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-hsw1/igt@kms_vblank@pipe-a-wait-forked-busy-hang.html

  * igt@kms_vblank@pipe-c-query-forked-busy-hang:
    - shard-tglb:         [PASS][41] -> [INCOMPLETE][42] ([fdo#111747]) +2 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-tglb6/igt@kms_vblank@pipe-c-query-forked-busy-hang.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-tglb8/igt@kms_vblank@pipe-c-query-forked-busy-hang.html

  
#### Possible fixes ####

  * igt@gem_softpin@noreloc-s3:
    - shard-apl:          [DMESG-WARN][43] ([fdo#108566]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-apl6/igt@gem_softpin@noreloc-s3.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-apl2/igt@gem_softpin@noreloc-s3.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
    - shard-snb:          [DMESG-WARN][45] ([fdo#111870]) -> [PASS][46] +1 similar issue
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-snb5/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-snb7/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html

  * igt@gem_userptr_blits@sync-unmap-after-close:
    - shard-hsw:          [DMESG-WARN][47] ([fdo#111870]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-hsw4/igt@gem_userptr_blits@sync-unmap-after-close.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-hsw2/igt@gem_userptr_blits@sync-unmap-after-close.html

  * igt@gem_workarounds@suspend-resume-fd:
    - shard-kbl:          [DMESG-WARN][49] ([fdo#108566]) -> [PASS][50] +2 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-kbl4/igt@gem_workarounds@suspend-resume-fd.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-kbl3/igt@gem_workarounds@suspend-resume-fd.html

  * igt@i915_pm_rpm@system-suspend:
    - shard-skl:          [INCOMPLETE][51] ([fdo#104108] / [fdo#107807]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-skl7/igt@i915_pm_rpm@system-suspend.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-skl1/igt@i915_pm_rpm@system-suspend.html

  * igt@kms_atomic_interruptible@legacy-dpms:
    - shard-hsw:          [INCOMPLETE][53] ([fdo#103540]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-hsw7/igt@kms_atomic_interruptible@legacy-dpms.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-hsw5/igt@kms_atomic_interruptible@legacy-dpms.html

  * igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding:
    - shard-snb:          [SKIP][55] ([fdo#109271]) -> [PASS][56] +2 similar issues
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-snb2/igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-snb4/igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-snb:          [DMESG-WARN][57] ([fdo#102365]) -> [PASS][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-snb1/igt@kms_flip@flip-vs-suspend-interruptible.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-snb5/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-render:
    - shard-skl:          [FAIL][59] ([fdo#103167]) -> [PASS][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-skl4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-render.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-skl6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
    - shard-skl:          [FAIL][61] ([fdo#108145]) -> [PASS][62] +1 similar issue
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-skl4/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html

  * igt@kms_setmode@basic:
    - shard-apl:          [FAIL][63] ([fdo#99912]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-apl7/igt@kms_setmode@basic.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-apl1/igt@kms_setmode@basic.html

  
#### Warnings ####

  * igt@gem_ctx_isolation@vcs2-dirty-switch:
    - shard-tglb:         [SKIP][65] ([fdo#111912] / [fdo#112080]) -> [SKIP][66] ([fdo#112080])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-tglb2/igt@gem_ctx_isolation@vcs2-dirty-switch.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-tglb9/igt@gem_ctx_isolation@vcs2-dirty-switch.html

  * igt@kms_cursor_crc@pipe-d-cursor-256x256-sliding:
    - shard-tglb:         [FAIL][67] ([fdo#111703]) -> [INCOMPLETE][68] ([fdo#111747])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-tglb4/igt@kms_cursor_crc@pipe-d-cursor-256x256-sliding.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-tglb1/igt@kms_cursor_crc@pipe-d-cursor-256x256-sliding.html

  * igt@kms_flip@flip-vs-blocking-wf-vblank:
    - shard-tglb:         [FAIL][69] ([fdo#111938]) -> [INCOMPLETE][70] ([fdo#112031])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-tglb3/igt@kms_flip@flip-vs-blocking-wf-vblank.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-tglb1/igt@kms_flip@flip-vs-blocking-wf-vblank.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt:
    - shard-tglb:         [FAIL][71] ([fdo#103167]) -> [INCOMPLETE][72] ([fdo#111747] / [fdo#111884])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-tglb1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw:
    - shard-tglb:         [FAIL][73] ([fdo#103167]) -> [INCOMPLETE][74] ([fdo#111884])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html
    - shard-iclb:         [FAIL][75] ([fdo#103167]) -> [INCOMPLETE][76] ([fdo#106978] / [fdo#107713])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html

  
  [fdo#102365]: https://bugs.freedesktop.org/show_bug.cgi?id=102365
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#104873]: https://bugs.freedesktop.org/show_bug.cgi?id=104873
  [fdo#105767]: https://bugs.freedesktop.org/show_bug.cgi?id=105767
  [fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#110026]: https://bugs.freedesktop.org/show_bug.cgi?id=110026
  [fdo#111703]: https://bugs.freedesktop.org/show_bug.cgi?id=111703
  [fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
  [fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
  [fdo#111884]: https://bugs.freedesktop.org/show_bug.cgi?id=111884
  [fdo#111912]: https://bugs.freedesktop.org/show_bug.cgi?id=111912
  [fdo#111938]: https://bugs.freedesktop.org/show_bug.cgi?id=111938
  [fdo#112031]: https://bugs.freedesktop.org/show_bug.cgi?id=112031
  [fdo#112035 ]: https://bugs.freedesktop.org/show_bug.cgi?id=112035 
  [fdo#112037]: https://bugs.freedesktop.org/show_bug.cgi?id=112037
  [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912


Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7310 -> Patchwork_15214

  CI-20190529: 20190529
  CI_DRM_7310: f3edc24676599b6c4e6ab713030ae630e864e732 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5271: 05f0400c50af843df301efb5475e9f5e2d16a098 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15214: 27a7a9b5a70e93156c83503a7cae444d06c76659 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/index.html
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[Intel-gfx] ✗ Fi.CI.IGT: failure for Add support for mipi dsi cmd mode

[Patchwork]

== Series Details ==

Series: Add support for mipi dsi cmd mode
URL   : https://patchwork.freedesktop.org/series/69290/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_7310_full -> Patchwork_15214_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_15214_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_15214_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_15214_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_busy@extended-modeset-hang-oldfb-render-pipe-b:
    - shard-iclb:         [PASS][1] -> [DMESG-FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-iclb3/igt@kms_busy@extended-modeset-hang-oldfb-render-pipe-b.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-iclb7/igt@kms_busy@extended-modeset-hang-oldfb-render-pipe-b.html
    - shard-tglb:         [PASS][3] -> [DMESG-FAIL][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-tglb2/igt@kms_busy@extended-modeset-hang-oldfb-render-pipe-b.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-tglb9/igt@kms_busy@extended-modeset-hang-oldfb-render-pipe-b.html

  * igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-cpu:
    - shard-tglb:         [PASS][5] -> [INCOMPLETE][6] +15 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-tglb9/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-cpu.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-tglb6/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-cpu.html

  
Known issues
------------

  Here are the changes found in Patchwork_15214_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_persistent_relocs@forked-interruptible-thrash-inactive:
    - shard-hsw:          [PASS][7] -> [FAIL][8] ([fdo#112037])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-hsw2/igt@gem_persistent_relocs@forked-interruptible-thrash-inactive.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-hsw6/igt@gem_persistent_relocs@forked-interruptible-thrash-inactive.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy:
    - shard-snb:          [PASS][9] -> [DMESG-WARN][10] ([fdo#111870])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-snb6/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-snb2/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
    - shard-hsw:          [PASS][11] -> [DMESG-WARN][12] ([fdo#111870])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-hsw2/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-hsw7/igt@gem_userptr_blits@map-fixed-invalidate-busy.html

  * igt@i915_pm_rpm@pm-caching:
    - shard-iclb:         [PASS][13] -> [INCOMPLETE][14] ([fdo#107713] / [fdo#108840])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-iclb7/igt@i915_pm_rpm@pm-caching.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-iclb3/igt@i915_pm_rpm@pm-caching.html

  * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
    - shard-hsw:          [PASS][15] -> [FAIL][16] ([fdo#105767])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-hsw2/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-hsw1/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
    - shard-glk:          [PASS][17] -> [FAIL][18] ([fdo#104873])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-glk2/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-glk1/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html

  * igt@kms_cursor_legacy@pipe-a-torture-move:
    - shard-tglb:         [PASS][19] -> [INCOMPLETE][20] ([fdo#112035 ]) +2 similar issues
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-tglb8/igt@kms_cursor_legacy@pipe-a-torture-move.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-tglb9/igt@kms_cursor_legacy@pipe-a-torture-move.html

  * igt@kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset-interruptible:
    - shard-tglb:         [PASS][21] -> [INCOMPLETE][22] ([fdo#112031]) +1 similar issue
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-tglb6/igt@kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset-interruptible.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-tglb4/igt@kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset-interruptible.html

  * igt@kms_flip_tiling@flip-y-tiled:
    - shard-tglb:         [PASS][23] -> [INCOMPLETE][24] ([fdo#111747] / [fdo#112031]) +1 similar issue
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-tglb3/igt@kms_flip_tiling@flip-y-tiled.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-tglb9/igt@kms_flip_tiling@flip-y-tiled.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-tglb:         [PASS][25] -> [INCOMPLETE][26] ([fdo#111884]) +3 similar issues
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-tglb9/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-wc.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-tglb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move:
    - shard-iclb:         [PASS][27] -> [INCOMPLETE][28] ([fdo#106978] / [fdo#107713]) +5 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-iclb8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-iclb5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - shard-kbl:          [PASS][29] -> [DMESG-WARN][30] ([fdo#108566]) +9 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-kbl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-kbl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
    - shard-apl:          [PASS][31] -> [DMESG-WARN][32] ([fdo#108566]) +2 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-apl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html

  * igt@kms_psr@sprite_mmap_gtt:
    - shard-iclb:         [PASS][33] -> [INCOMPLETE][34] ([fdo#107713]) +24 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-iclb8/igt@kms_psr@sprite_mmap_gtt.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-iclb5/igt@kms_psr@sprite_mmap_gtt.html

  * igt@kms_rotation_crc@cursor-rotation-180:
    - shard-iclb:         [PASS][35] -> [INCOMPLETE][36] ([fdo#107713] / [fdo#110026])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-iclb3/igt@kms_rotation_crc@cursor-rotation-180.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-iclb7/igt@kms_rotation_crc@cursor-rotation-180.html

  * igt@kms_setmode@basic:
    - shard-skl:          [PASS][37] -> [FAIL][38] ([fdo#99912])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-skl1/igt@kms_setmode@basic.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-skl1/igt@kms_setmode@basic.html

  * igt@kms_vblank@pipe-a-wait-forked-busy-hang:
    - shard-hsw:          [PASS][39] -> [INCOMPLETE][40] ([fdo#103540])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-hsw1/igt@kms_vblank@pipe-a-wait-forked-busy-hang.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-hsw1/igt@kms_vblank@pipe-a-wait-forked-busy-hang.html

  * igt@kms_vblank@pipe-c-query-forked-busy-hang:
    - shard-tglb:         [PASS][41] -> [INCOMPLETE][42] ([fdo#111747]) +2 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-tglb6/igt@kms_vblank@pipe-c-query-forked-busy-hang.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-tglb8/igt@kms_vblank@pipe-c-query-forked-busy-hang.html

  
#### Possible fixes ####

  * igt@gem_softpin@noreloc-s3:
    - shard-apl:          [DMESG-WARN][43] ([fdo#108566]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-apl6/igt@gem_softpin@noreloc-s3.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-apl2/igt@gem_softpin@noreloc-s3.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
    - shard-snb:          [DMESG-WARN][45] ([fdo#111870]) -> [PASS][46] +1 similar issue
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-snb5/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-snb7/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html

  * igt@gem_userptr_blits@sync-unmap-after-close:
    - shard-hsw:          [DMESG-WARN][47] ([fdo#111870]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-hsw4/igt@gem_userptr_blits@sync-unmap-after-close.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-hsw2/igt@gem_userptr_blits@sync-unmap-after-close.html

  * igt@gem_workarounds@suspend-resume-fd:
    - shard-kbl:          [DMESG-WARN][49] ([fdo#108566]) -> [PASS][50] +2 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-kbl4/igt@gem_workarounds@suspend-resume-fd.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-kbl3/igt@gem_workarounds@suspend-resume-fd.html

  * igt@i915_pm_rpm@system-suspend:
    - shard-skl:          [INCOMPLETE][51] ([fdo#104108] / [fdo#107807]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-skl7/igt@i915_pm_rpm@system-suspend.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-skl1/igt@i915_pm_rpm@system-suspend.html

  * igt@kms_atomic_interruptible@legacy-dpms:
    - shard-hsw:          [INCOMPLETE][53] ([fdo#103540]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-hsw7/igt@kms_atomic_interruptible@legacy-dpms.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-hsw5/igt@kms_atomic_interruptible@legacy-dpms.html

  * igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding:
    - shard-snb:          [SKIP][55] ([fdo#109271]) -> [PASS][56] +2 similar issues
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-snb2/igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-snb4/igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-snb:          [DMESG-WARN][57] ([fdo#102365]) -> [PASS][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-snb1/igt@kms_flip@flip-vs-suspend-interruptible.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-snb5/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-render:
    - shard-skl:          [FAIL][59] ([fdo#103167]) -> [PASS][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-skl4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-render.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-skl6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
    - shard-skl:          [FAIL][61] ([fdo#108145]) -> [PASS][62] +1 similar issue
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-skl4/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html

  * igt@kms_setmode@basic:
    - shard-apl:          [FAIL][63] ([fdo#99912]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-apl7/igt@kms_setmode@basic.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-apl1/igt@kms_setmode@basic.html

  
#### Warnings ####

  * igt@gem_ctx_isolation@vcs2-dirty-switch:
    - shard-tglb:         [SKIP][65] ([fdo#111912] / [fdo#112080]) -> [SKIP][66] ([fdo#112080])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-tglb2/igt@gem_ctx_isolation@vcs2-dirty-switch.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-tglb9/igt@gem_ctx_isolation@vcs2-dirty-switch.html

  * igt@kms_cursor_crc@pipe-d-cursor-256x256-sliding:
    - shard-tglb:         [FAIL][67] ([fdo#111703]) -> [INCOMPLETE][68] ([fdo#111747])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-tglb4/igt@kms_cursor_crc@pipe-d-cursor-256x256-sliding.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-tglb1/igt@kms_cursor_crc@pipe-d-cursor-256x256-sliding.html

  * igt@kms_flip@flip-vs-blocking-wf-vblank:
    - shard-tglb:         [FAIL][69] ([fdo#111938]) -> [INCOMPLETE][70] ([fdo#112031])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-tglb3/igt@kms_flip@flip-vs-blocking-wf-vblank.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-tglb1/igt@kms_flip@flip-vs-blocking-wf-vblank.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt:
    - shard-tglb:         [FAIL][71] ([fdo#103167]) -> [INCOMPLETE][72] ([fdo#111747] / [fdo#111884])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-tglb1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw:
    - shard-tglb:         [FAIL][73] ([fdo#103167]) -> [INCOMPLETE][74] ([fdo#111884])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html
    - shard-iclb:         [FAIL][75] ([fdo#103167]) -> [INCOMPLETE][76] ([fdo#106978] / [fdo#107713])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7310/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html

  
  [fdo#102365]: https://bugs.freedesktop.org/show_bug.cgi?id=102365
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#104873]: https://bugs.freedesktop.org/show_bug.cgi?id=104873
  [fdo#105767]: https://bugs.freedesktop.org/show_bug.cgi?id=105767
  [fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#110026]: https://bugs.freedesktop.org/show_bug.cgi?id=110026
  [fdo#111703]: https://bugs.freedesktop.org/show_bug.cgi?id=111703
  [fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
  [fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
  [fdo#111884]: https://bugs.freedesktop.org/show_bug.cgi?id=111884
  [fdo#111912]: https://bugs.freedesktop.org/show_bug.cgi?id=111912
  [fdo#111938]: https://bugs.freedesktop.org/show_bug.cgi?id=111938
  [fdo#112031]: https://bugs.freedesktop.org/show_bug.cgi?id=112031
  [fdo#112035 ]: https://bugs.freedesktop.org/show_bug.cgi?id=112035 
  [fdo#112037]: https://bugs.freedesktop.org/show_bug.cgi?id=112037
  [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912


Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7310 -> Patchwork_15214

  CI-20190529: 20190529
  CI_DRM_7310: f3edc24676599b6c4e6ab713030ae630e864e732 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5271: 05f0400c50af843df301efb5475e9f5e2d16a098 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15214: 27a7a9b5a70e93156c83503a7cae444d06c76659 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15214/index.html
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Re: [RFC-v2 7/9] drm/i915/dsi: Configure TE interrupt for cmd mode

[Jani Nikula]

On Mon, 11 Nov 2019, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote:
> We need to configure TE interrupt in two places.
> Port interrupt and DSI interrupt mask registers.
>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 58 +++++++++++++++++++++++++++++++--
>  1 file changed, 56 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index dae00f7dd7df..f27afde409bf 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -41,6 +41,7 @@
>  #include "display/intel_hotplug.h"
>  #include "display/intel_lpe_audio.h"
>  #include "display/intel_psr.h"
> +#include "display/intel_dsi.h"
>  
>  #include "gt/intel_gt.h"
>  #include "gt/intel_gt_irq.h"
> @@ -2571,12 +2572,45 @@ int ilk_enable_vblank(struct drm_crtc *crtc)
>  	return 0;
>  }
>  
> +static void gen11_dsi_configure_te(struct drm_i915_private *dev_priv,
> +				   struct drm_display_mode *mode, bool enable)
> +{
> +	enum port port;
> +	u32 tmp;
> +
> +	if (mode->private_flags & I915_MODE_FLAG_DSI_USE_TE1)
> +		port = PORT_B;
> +	else
> +		port = PORT_A;
> +
> +	tmp =  I915_READ(DSI_INTR_MASK_REG(port));
> +	if (enable)
> +		tmp &= ~DSI_TE_EVENT;
> +	else
> +		tmp |= DSI_TE_EVENT;
> +
> +	I915_WRITE(DSI_INTR_MASK_REG(port), tmp);
> +}
> +
>  int bdw_enable_vblank(struct drm_crtc *crtc)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> -	enum pipe pipe = to_intel_crtc(crtc)->pipe;
> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +	enum pipe pipe = intel_crtc->pipe;
> +	struct drm_vblank_crtc *vblank;
> +	struct drm_display_mode *mode;
>  	unsigned long irqflags;
>  
> +	vblank = &crtc->dev->vblank[drm_crtc_index(crtc)];
> +	mode = &vblank->hwmode;
> +
> +	if ((INTEL_GEN(dev_priv) >= 11) &&
> +	    (mode->private_flags &
> +	     (I915_MODE_FLAG_DSI_USE_TE1 | I915_MODE_FLAG_DSI_USE_TE0))) {
> +		gen11_dsi_configure_te(dev_priv, mode, true);
> +		return 0;
> +	}
> +

I'd hide this more inside gen11_dsi_configure_te():

	if (gen11_dsi_configure_te(crtc))
		return 0;

and make that function early return false if neither TE flag is set. It
also doesn't have to check for gen, because you can trust those flags
are only set where it matters.

>  	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
>  	bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
>  	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
> @@ -2642,9 +2676,22 @@ void ilk_disable_vblank(struct drm_crtc *crtc)
>  void bdw_disable_vblank(struct drm_crtc *crtc)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> -	enum pipe pipe = to_intel_crtc(crtc)->pipe;
> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +	enum pipe pipe = intel_crtc->pipe;
> +	struct drm_vblank_crtc *vblank;
> +	struct drm_display_mode *mode;
>  	unsigned long irqflags;
>  
> +	vblank = &crtc->dev->vblank[drm_crtc_index(crtc)];
> +	mode = &vblank->hwmode;
> +
> +	if ((INTEL_GEN(dev_priv) >= 11) &&
> +	    (mode->private_flags &
> +	     (I915_MODE_FLAG_DSI_USE_TE1 | I915_MODE_FLAG_DSI_USE_TE0))) {
> +		gen11_dsi_configure_te(dev_priv, mode, false);
> +		return;
> +	}
> +

Ditto, keep this function clean.

>  	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
>  	bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
>  	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
> @@ -3350,6 +3397,13 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
>  		gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
>  	}
>  
> +	if (INTEL_GEN(dev_priv) >= 11) {
> +		enum port port;
> +
> +		if (intel_bios_is_dsi_present(dev_priv, &port))
> +			de_port_masked |= DSI0_TE | DSI1_TE;
> +	}
> +

Not really happy about this one, but perhaps acceptable for now.

BR,
Jani.

>  	for_each_pipe(dev_priv, pipe) {
>  		dev_priv->de_irq_mask[pipe] = ~de_pipe_masked;

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [RFC-v2 7/9] drm/i915/dsi: Configure TE interrupt for cmd mode

[Jani Nikula]

On Mon, 11 Nov 2019, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote:
> We need to configure TE interrupt in two places.
> Port interrupt and DSI interrupt mask registers.
>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 58 +++++++++++++++++++++++++++++++--
>  1 file changed, 56 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index dae00f7dd7df..f27afde409bf 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -41,6 +41,7 @@
>  #include "display/intel_hotplug.h"
>  #include "display/intel_lpe_audio.h"
>  #include "display/intel_psr.h"
> +#include "display/intel_dsi.h"
>  
>  #include "gt/intel_gt.h"
>  #include "gt/intel_gt_irq.h"
> @@ -2571,12 +2572,45 @@ int ilk_enable_vblank(struct drm_crtc *crtc)
>  	return 0;
>  }
>  
> +static void gen11_dsi_configure_te(struct drm_i915_private *dev_priv,
> +				   struct drm_display_mode *mode, bool enable)
> +{
> +	enum port port;
> +	u32 tmp;
> +
> +	if (mode->private_flags & I915_MODE_FLAG_DSI_USE_TE1)
> +		port = PORT_B;
> +	else
> +		port = PORT_A;
> +
> +	tmp =  I915_READ(DSI_INTR_MASK_REG(port));
> +	if (enable)
> +		tmp &= ~DSI_TE_EVENT;
> +	else
> +		tmp |= DSI_TE_EVENT;
> +
> +	I915_WRITE(DSI_INTR_MASK_REG(port), tmp);
> +}
> +
>  int bdw_enable_vblank(struct drm_crtc *crtc)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> -	enum pipe pipe = to_intel_crtc(crtc)->pipe;
> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +	enum pipe pipe = intel_crtc->pipe;
> +	struct drm_vblank_crtc *vblank;
> +	struct drm_display_mode *mode;
>  	unsigned long irqflags;
>  
> +	vblank = &crtc->dev->vblank[drm_crtc_index(crtc)];
> +	mode = &vblank->hwmode;
> +
> +	if ((INTEL_GEN(dev_priv) >= 11) &&
> +	    (mode->private_flags &
> +	     (I915_MODE_FLAG_DSI_USE_TE1 | I915_MODE_FLAG_DSI_USE_TE0))) {
> +		gen11_dsi_configure_te(dev_priv, mode, true);
> +		return 0;
> +	}
> +

I'd hide this more inside gen11_dsi_configure_te():

	if (gen11_dsi_configure_te(crtc))
		return 0;

and make that function early return false if neither TE flag is set. It
also doesn't have to check for gen, because you can trust those flags
are only set where it matters.

>  	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
>  	bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
>  	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
> @@ -2642,9 +2676,22 @@ void ilk_disable_vblank(struct drm_crtc *crtc)
>  void bdw_disable_vblank(struct drm_crtc *crtc)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> -	enum pipe pipe = to_intel_crtc(crtc)->pipe;
> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +	enum pipe pipe = intel_crtc->pipe;
> +	struct drm_vblank_crtc *vblank;
> +	struct drm_display_mode *mode;
>  	unsigned long irqflags;
>  
> +	vblank = &crtc->dev->vblank[drm_crtc_index(crtc)];
> +	mode = &vblank->hwmode;
> +
> +	if ((INTEL_GEN(dev_priv) >= 11) &&
> +	    (mode->private_flags &
> +	     (I915_MODE_FLAG_DSI_USE_TE1 | I915_MODE_FLAG_DSI_USE_TE0))) {
> +		gen11_dsi_configure_te(dev_priv, mode, false);
> +		return;
> +	}
> +

Ditto, keep this function clean.

>  	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
>  	bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
>  	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
> @@ -3350,6 +3397,13 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
>  		gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
>  	}
>  
> +	if (INTEL_GEN(dev_priv) >= 11) {
> +		enum port port;
> +
> +		if (intel_bios_is_dsi_present(dev_priv, &port))
> +			de_port_masked |= DSI0_TE | DSI1_TE;
> +	}
> +

Not really happy about this one, but perhaps acceptable for now.

BR,
Jani.

>  	for_each_pipe(dev_priv, pipe) {
>  		dev_priv->de_irq_mask[pipe] = ~de_pipe_masked;

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [RFC-v2 8/9] drm/i915/dsi: Add TE handler for dsi cmd mode.

[Jani Nikula]

On Mon, 11 Nov 2019, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote:
> In case of dual link, we get the TE on slave.
> So clear the TE on slave DSI IIR.
>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 62 +++++++++++++++++++++++++++++++++
>  1 file changed, 62 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index f27afde409bf..34a06876a2d7 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2230,6 +2230,62 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
>  		DRM_ERROR("Unexpected DE Misc interrupt\n");
>  }
>  
> +void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,
> +				    u32 iir_value)
> +{
> +	enum pipe pipe = INVALID_PIPE;
> +	enum transcoder dsi_trans;
> +	enum port port;
> +	u32 val, tmp;
> +
> +	/*
> +	 * Incase of dual link, TE comes from DSI_1
> +	 * this is to check if dual link is enabled
> +	 */
> +	val = I915_READ(TRANS_DDI_FUNC_CTL2(TRANSCODER_DSI_0));
> +	val &= PORT_SYNC_MODE_ENABLE;
> +
> +	/*
> +	 * if dual link is enabled, then read DSI_0
> +	 * transcoder registers
> +	 */
> +	port = ((iir_value & DSI1_TE && val) || (iir_value & DSI0_TE)) ?
> +								PORT_A : PORT_B;
> +	dsi_trans = (port == PORT_A) ? TRANSCODER_DSI_0 : TRANSCODER_DSI_1;
> +
> +	/* Check if DSI configured in command mode */
> +	val = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans));
> +	val = (val & OP_MODE_MASK) >> 28;
> +
> +	if (val) {
> +		DRM_ERROR("DSI trancoder not configured in command mode\n");
> +		return;
> +	}
> +
> +	/* Get PIPE for handling VBLANK event */
> +	val = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
> +	switch (val & TRANS_DDI_EDP_INPUT_MASK) {
> +	case TRANS_DDI_EDP_INPUT_A_ON:
> +		pipe = PIPE_A;
> +		break;
> +	case TRANS_DDI_EDP_INPUT_B_ONOFF:
> +		pipe = PIPE_B;
> +		break;
> +	case TRANS_DDI_EDP_INPUT_C_ONOFF:
> +		pipe = PIPE_C;
> +		break;
> +	default:
> +		DRM_ERROR("Invalid PIPE\n");
> +	}
> +
> +	/* clear TE in dsi IIR */
> +	port = (iir_value & DSI1_TE) ? PORT_B : PORT_A;
> +	tmp = I915_READ(DSI_INTR_IDENT_REG(port));
> +	I915_WRITE(DSI_INTR_IDENT_REG(port), tmp);
> +
> +	drm_handle_vblank(&dev_priv->drm, pipe);
> +}
> +
>  static irqreturn_t
>  gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
>  {
> @@ -2294,6 +2350,12 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
>  				found = true;
>  			}
>  
> +			if ((INTEL_GEN(dev_priv) >= 11) &&
> +				(iir & (DSI0_TE | DSI1_TE))) {

Please follow the same style as nearby:

        if (gen11) {
                tmp_mask = iir & (DSI0_TE | DSI1_TE);
                if (tmp_mask) {
                        gen11_dsi_te_interrupt_handler(dev_priv, tmp_mask);
                        found = true;
                }
        }

Even if that's functionally the same, I think it's cleaner to only pass
the relevant masked bits to the handler.


> +				gen11_dsi_te_interrupt_handler(dev_priv, iir);
> +				found = true;
> +			}
> +
>  			if (!found)
>  				DRM_ERROR("Unexpected DE Port interrupt\n");
>  		}

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
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Re: [Intel-gfx] [RFC-v2 8/9] drm/i915/dsi: Add TE handler for dsi cmd mode.

[Jani Nikula]

On Mon, 11 Nov 2019, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote:
> In case of dual link, we get the TE on slave.
> So clear the TE on slave DSI IIR.
>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 62 +++++++++++++++++++++++++++++++++
>  1 file changed, 62 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index f27afde409bf..34a06876a2d7 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2230,6 +2230,62 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
>  		DRM_ERROR("Unexpected DE Misc interrupt\n");
>  }
>  
> +void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,
> +				    u32 iir_value)
> +{
> +	enum pipe pipe = INVALID_PIPE;
> +	enum transcoder dsi_trans;
> +	enum port port;
> +	u32 val, tmp;
> +
> +	/*
> +	 * Incase of dual link, TE comes from DSI_1
> +	 * this is to check if dual link is enabled
> +	 */
> +	val = I915_READ(TRANS_DDI_FUNC_CTL2(TRANSCODER_DSI_0));
> +	val &= PORT_SYNC_MODE_ENABLE;
> +
> +	/*
> +	 * if dual link is enabled, then read DSI_0
> +	 * transcoder registers
> +	 */
> +	port = ((iir_value & DSI1_TE && val) || (iir_value & DSI0_TE)) ?
> +								PORT_A : PORT_B;
> +	dsi_trans = (port == PORT_A) ? TRANSCODER_DSI_0 : TRANSCODER_DSI_1;
> +
> +	/* Check if DSI configured in command mode */
> +	val = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans));
> +	val = (val & OP_MODE_MASK) >> 28;
> +
> +	if (val) {
> +		DRM_ERROR("DSI trancoder not configured in command mode\n");
> +		return;
> +	}
> +
> +	/* Get PIPE for handling VBLANK event */
> +	val = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
> +	switch (val & TRANS_DDI_EDP_INPUT_MASK) {
> +	case TRANS_DDI_EDP_INPUT_A_ON:
> +		pipe = PIPE_A;
> +		break;
> +	case TRANS_DDI_EDP_INPUT_B_ONOFF:
> +		pipe = PIPE_B;
> +		break;
> +	case TRANS_DDI_EDP_INPUT_C_ONOFF:
> +		pipe = PIPE_C;
> +		break;
> +	default:
> +		DRM_ERROR("Invalid PIPE\n");
> +	}
> +
> +	/* clear TE in dsi IIR */
> +	port = (iir_value & DSI1_TE) ? PORT_B : PORT_A;
> +	tmp = I915_READ(DSI_INTR_IDENT_REG(port));
> +	I915_WRITE(DSI_INTR_IDENT_REG(port), tmp);
> +
> +	drm_handle_vblank(&dev_priv->drm, pipe);
> +}
> +
>  static irqreturn_t
>  gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
>  {
> @@ -2294,6 +2350,12 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
>  				found = true;
>  			}
>  
> +			if ((INTEL_GEN(dev_priv) >= 11) &&
> +				(iir & (DSI0_TE | DSI1_TE))) {

Please follow the same style as nearby:

        if (gen11) {
                tmp_mask = iir & (DSI0_TE | DSI1_TE);
                if (tmp_mask) {
                        gen11_dsi_te_interrupt_handler(dev_priv, tmp_mask);
                        found = true;
                }
        }

Even if that's functionally the same, I think it's cleaner to only pass
the relevant masked bits to the handler.


> +				gen11_dsi_te_interrupt_handler(dev_priv, iir);
> +				found = true;
> +			}
> +
>  			if (!found)
>  				DRM_ERROR("Unexpected DE Port interrupt\n");
>  		}

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
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Re: [RFC-v2 2/9] drm/i915/dsi: Configure transcoder operation for command mode.

[Jani Nikula]

On Mon, 11 Nov 2019, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote:
> Configure the transcoder to operate in TE GATE command mode
> and  take TE events from GPIO.
> Also disable the periodic command mode, that GOP would have
> programmed.
>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
>  drivers/gpu/drm/i915/display/icl_dsi.c | 36 ++++++++++++++++++++++++++
>  1 file changed, 36 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 8eb2d7f29c82..5ff2a1ffd3ea 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -704,6 +704,10 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
>  				tmp |= VIDEO_MODE_SYNC_PULSE;
>  				break;
>  			}
> +		} else {
> +			tmp &= ~OP_MODE_MASK;
> +			tmp |= CMD_MODE_TE_GATE;
> +			tmp |= TE_SOURCE_GPIO;

Do we have TE source specified in VBT or somewhere? I can live with this
*for now* but it does freak me out a bit that we might also be using the
utility pin for backlight PWM output. That would conflict magnificently.

Maybe at least add a FIXME comment about that?

>  		}
>  
>  		I915_WRITE(DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
> @@ -953,6 +957,26 @@ static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder)
>  	}
>  }
>  
> +static void gen11_dsi_config_util_pin(struct intel_encoder *encoder)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	u32 tmp;
> +
> +	/*
> +	 * used as TE i/p for DSI0,
> +	 * for dual link/DSI1 TE is from slave DSI1
> +	 * through GPIO.
> +	 */
> +	if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B)))
> +		return;
> +
> +	tmp = I915_READ(UTIL_PIN_CTL);
> +	tmp |= UTIL_PIN_DIRECTION_INPUT;
> +	tmp |= UTIL_PIN_ENABLE;
> +	I915_WRITE(UTIL_PIN_CTL, tmp);

You'll also need to disable the utility pin somewhere, else you'll get
warnings from assert_can_enable_dc6().

> +}
> +
>  static void
>  gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
>  			      const struct intel_crtc_state *pipe_config)
> @@ -974,6 +998,9 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
>  	/* setup D-PHY timings */
>  	gen11_dsi_setup_dphy_timings(encoder);
>  
> +	/* Since transcoder is configured to take events from GPIO */
> +	gen11_dsi_config_util_pin(encoder);
> +
>  	/* step 4h: setup DSI protocol timeouts */
>  	gen11_dsi_setup_timeouts(encoder);
>  
> @@ -1104,6 +1131,15 @@ static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
>  	enum transcoder dsi_trans;
>  	u32 tmp;
>  
> +	/* disable periodic update mode */
> +	if (is_cmd_mode(intel_dsi)) {
> +		for_each_dsi_port(port, intel_dsi->ports) {
> +			tmp = I915_READ(DSI_CMD_FRMCTL(port));
> +			tmp &= ~DSI_PERIODIC_FRAME_UPDATE_ENABLE;
> +			I915_WRITE(DSI_CMD_FRMCTL(port), tmp);
> +		}
> +	}
> +
>  	/* put dsi link in ULPS */
>  	for_each_dsi_port(port, intel_dsi->ports) {
>  		dsi_trans = dsi_port_to_transcoder(port);

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [RFC-v2 2/9] drm/i915/dsi: Configure transcoder operation for command mode.

[Jani Nikula]

On Mon, 11 Nov 2019, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote:
> Configure the transcoder to operate in TE GATE command mode
> and  take TE events from GPIO.
> Also disable the periodic command mode, that GOP would have
> programmed.
>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
>  drivers/gpu/drm/i915/display/icl_dsi.c | 36 ++++++++++++++++++++++++++
>  1 file changed, 36 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 8eb2d7f29c82..5ff2a1ffd3ea 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -704,6 +704,10 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
>  				tmp |= VIDEO_MODE_SYNC_PULSE;
>  				break;
>  			}
> +		} else {
> +			tmp &= ~OP_MODE_MASK;
> +			tmp |= CMD_MODE_TE_GATE;
> +			tmp |= TE_SOURCE_GPIO;

Do we have TE source specified in VBT or somewhere? I can live with this
*for now* but it does freak me out a bit that we might also be using the
utility pin for backlight PWM output. That would conflict magnificently.

Maybe at least add a FIXME comment about that?

>  		}
>  
>  		I915_WRITE(DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
> @@ -953,6 +957,26 @@ static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder)
>  	}
>  }
>  
> +static void gen11_dsi_config_util_pin(struct intel_encoder *encoder)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	u32 tmp;
> +
> +	/*
> +	 * used as TE i/p for DSI0,
> +	 * for dual link/DSI1 TE is from slave DSI1
> +	 * through GPIO.
> +	 */
> +	if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B)))
> +		return;
> +
> +	tmp = I915_READ(UTIL_PIN_CTL);
> +	tmp |= UTIL_PIN_DIRECTION_INPUT;
> +	tmp |= UTIL_PIN_ENABLE;
> +	I915_WRITE(UTIL_PIN_CTL, tmp);

You'll also need to disable the utility pin somewhere, else you'll get
warnings from assert_can_enable_dc6().

> +}
> +
>  static void
>  gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
>  			      const struct intel_crtc_state *pipe_config)
> @@ -974,6 +998,9 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
>  	/* setup D-PHY timings */
>  	gen11_dsi_setup_dphy_timings(encoder);
>  
> +	/* Since transcoder is configured to take events from GPIO */
> +	gen11_dsi_config_util_pin(encoder);
> +
>  	/* step 4h: setup DSI protocol timeouts */
>  	gen11_dsi_setup_timeouts(encoder);
>  
> @@ -1104,6 +1131,15 @@ static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
>  	enum transcoder dsi_trans;
>  	u32 tmp;
>  
> +	/* disable periodic update mode */
> +	if (is_cmd_mode(intel_dsi)) {
> +		for_each_dsi_port(port, intel_dsi->ports) {
> +			tmp = I915_READ(DSI_CMD_FRMCTL(port));
> +			tmp &= ~DSI_PERIODIC_FRAME_UPDATE_ENABLE;
> +			I915_WRITE(DSI_CMD_FRMCTL(port), tmp);
> +		}
> +	}
> +
>  	/* put dsi link in ULPS */
>  	for_each_dsi_port(port, intel_dsi->ports) {
>  		dsi_trans = dsi_port_to_transcoder(port);

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [RFC-v2 1/9] drm/i915/dsi: Define command mode registers

[Jani Nikula]

On Mon, 11 Nov 2019, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote:
> Adding all the register definitions needed
> for mipi dsi command mode.
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>

There may have been a few naming nitpicks I could've had, but meh.

Pushed to dinq, thanks for the patch.

BR,
Jani.


> ---
>  drivers/gpu/drm/i915/i915_reg.h | 78 +++++++++++++++++++++++++++++----
>  1 file changed, 70 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a607ea520829..2ffcc21670b7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5036,14 +5036,20 @@ enum {
>  #define   BLM_PCH_POLARITY			(1 << 29)
>  #define BLC_PWM_PCH_CTL2	_MMIO(0xc8254)
>  
> -#define UTIL_PIN_CTL		_MMIO(0x48400)
> -#define   UTIL_PIN_ENABLE	(1 << 31)
> -
> -#define   UTIL_PIN_PIPE(x)     ((x) << 29)
> -#define   UTIL_PIN_PIPE_MASK   (3 << 29)
> -#define   UTIL_PIN_MODE_PWM    (1 << 24)
> -#define   UTIL_PIN_MODE_MASK   (0xf << 24)
> -#define   UTIL_PIN_POLARITY    (1 << 22)
> +#define UTIL_PIN_CTL			_MMIO(0x48400)
> +#define   UTIL_PIN_ENABLE		(1 << 31)
> +#define   UTIL_PIN_PIPE_MASK		(3 << 29)
> +#define   UTIL_PIN_PIPE(x)		((x) << 29)
> +#define   UTIL_PIN_MODE_MASK		(0xf << 24)
> +#define   UTIL_PIN_MODE_DATA		(0 << 24)
> +#define   UTIL_PIN_MODE_PWM		(1 << 24)
> +#define   UTIL_PIN_MODE_VBLANK		(4 << 24)
> +#define   UTIL_PIN_MODE_VSYNC		(5 << 24)
> +#define   UTIL_PIN_MODE_EYE_LEVEL	(8 << 24)
> +#define   UTIL_PIN_OUTPUT_DATA		(1 << 23)
> +#define   UTIL_PIN_POLARITY		(1 << 22)
> +#define   UTIL_PIN_DIRECTION_INPUT	(1 << 19)
> +#define   UTIL_PIN_INPUT_DATA		(1 << 16)
>  
>  /* BXT backlight register definition. */
>  #define _BXT_BLC_PWM_CTL1			0xC8250
> @@ -7500,11 +7506,15 @@ enum {
>  #define GEN8_DE_PORT_IMR _MMIO(0x44444)
>  #define GEN8_DE_PORT_IIR _MMIO(0x44448)
>  #define GEN8_DE_PORT_IER _MMIO(0x4444c)
> +#define  DSI1_NON_TE			(1 << 31)
> +#define  DSI0_NON_TE			(1 << 30)
>  #define  ICL_AUX_CHANNEL_E		(1 << 29)
>  #define  CNL_AUX_CHANNEL_F		(1 << 28)
>  #define  GEN9_AUX_CHANNEL_D		(1 << 27)
>  #define  GEN9_AUX_CHANNEL_C		(1 << 26)
>  #define  GEN9_AUX_CHANNEL_B		(1 << 25)
> +#define  DSI1_TE			(1 << 24)
> +#define  DSI0_TE			(1 << 23)
>  #define  BXT_DE_PORT_HP_DDIC		(1 << 5)
>  #define  BXT_DE_PORT_HP_DDIB		(1 << 4)
>  #define  BXT_DE_PORT_HP_DDIA		(1 << 3)
> @@ -10770,6 +10780,57 @@ enum skl_power_gate {
>  #define  ICL_ESC_CLK_DIV_SHIFT			0
>  #define DSI_MAX_ESC_CLK			20000		/* in KHz */
>  
> +#define _DSI_CMD_FRMCTL_0		0x6b034
> +#define _DSI_CMD_FRMCTL_1		0x6b834
> +#define DSI_CMD_FRMCTL(port)		_MMIO_PORT(port,	\
> +						   _DSI_CMD_FRMCTL_0,\
> +						   _DSI_CMD_FRMCTL_1)
> +#define   DSI_FRAME_UPDATE_REQUEST		(1 << 31)
> +#define   DSI_PERIODIC_FRAME_UPDATE_ENABLE	(1 << 29)
> +#define   DSI_NULL_PACKET_ENABLE		(1 << 28)
> +#define   DSI_FRAME_IN_PROGRESS			(1 << 0)
> +
> +#define _DSI_INTR_MASK_REG_0		0x6b070
> +#define _DSI_INTR_MASK_REG_1		0x6b870
> +#define DSI_INTR_MASK_REG(port)		_MMIO_PORT(port,	\
> +						   _DSI_INTR_MASK_REG_0,\
> +						   _DSI_INTR_MASK_REG_1)
> +
> +#define _DSI_INTR_IDENT_REG_0		0x6b074
> +#define _DSI_INTR_IDENT_REG_1		0x6b874
> +#define DSI_INTR_IDENT_REG(port)	_MMIO_PORT(port,	\
> +						   _DSI_INTR_IDENT_REG_0,\
> +						   _DSI_INTR_IDENT_REG_1)
> +#define   DSI_TE_EVENT				(1 << 31)
> +#define   DSI_RX_DATA_OR_BTA_TERMINATED		(1 << 30)
> +#define   DSI_TX_DATA				(1 << 29)
> +#define   DSI_ULPS_ENTRY_DONE			(1 << 28)
> +#define   DSI_NON_TE_TRIGGER_RECEIVED		(1 << 27)
> +#define   DSI_HOST_CHKSUM_ERROR			(1 << 26)
> +#define   DSI_HOST_MULTI_ECC_ERROR		(1 << 25)
> +#define   DSI_HOST_SINGL_ECC_ERROR		(1 << 24)
> +#define   DSI_HOST_CONTENTION_DETECTED		(1 << 23)
> +#define   DSI_HOST_FALSE_CONTROL_ERROR		(1 << 22)
> +#define   DSI_HOST_TIMEOUT_ERROR		(1 << 21)
> +#define   DSI_HOST_LOW_POWER_TX_SYNC_ERROR	(1 << 20)
> +#define   DSI_HOST_ESCAPE_MODE_ENTRY_ERROR	(1 << 19)
> +#define   DSI_FRAME_UPDATE_DONE			(1 << 16)
> +#define   DSI_PROTOCOL_VIOLATION_REPORTED	(1 << 15)
> +#define   DSI_INVALID_TX_LENGTH			(1 << 13)
> +#define   DSI_INVALID_VC			(1 << 12)
> +#define   DSI_INVALID_DATA_TYPE			(1 << 11)
> +#define   DSI_PERIPHERAL_CHKSUM_ERROR		(1 << 10)
> +#define   DSI_PERIPHERAL_MULTI_ECC_ERROR	(1 << 9)
> +#define   DSI_PERIPHERAL_SINGLE_ECC_ERROR	(1 << 8)
> +#define   DSI_PERIPHERAL_CONTENTION_DETECTED	(1 << 7)
> +#define   DSI_PERIPHERAL_FALSE_CTRL_ERROR	(1 << 6)
> +#define   DSI_PERIPHERAL_TIMEOUT_ERROR		(1 << 5)
> +#define   DSI_PERIPHERAL_LP_TX_SYNC_ERROR	(1 << 4)
> +#define   DSI_PERIPHERAL_ESC_MODE_ENTRY_CMD_ERR	(1 << 3)
> +#define   DSI_EOT_SYNC_ERROR			(1 << 2)
> +#define   DSI_SOT_SYNC_ERROR			(1 << 1)
> +#define   DSI_SOT_ERROR				(1 << 0)
> +
>  /* Gen4+ Timestamp and Pipe Frame time stamp registers */
>  #define GEN4_TIMESTAMP		_MMIO(0x2358)
>  #define ILK_TIMESTAMP_HI	_MMIO(0x70070)
> @@ -11374,6 +11435,7 @@ enum skl_power_gate {
>  #define  CMD_MODE_TE_GATE		(0x1 << 28)
>  #define  VIDEO_MODE_SYNC_EVENT		(0x2 << 28)
>  #define  VIDEO_MODE_SYNC_PULSE		(0x3 << 28)
> +#define  TE_SOURCE_GPIO			(1 << 27)
>  #define  LINK_READY			(1 << 20)
>  #define  PIX_FMT_MASK			(0x3 << 16)
>  #define  PIX_FMT_SHIFT			16

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
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Re: [Intel-gfx] [RFC-v2 1/9] drm/i915/dsi: Define command mode registers

[Jani Nikula]

On Mon, 11 Nov 2019, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote:
> Adding all the register definitions needed
> for mipi dsi command mode.
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>

There may have been a few naming nitpicks I could've had, but meh.

Pushed to dinq, thanks for the patch.

BR,
Jani.


> ---
>  drivers/gpu/drm/i915/i915_reg.h | 78 +++++++++++++++++++++++++++++----
>  1 file changed, 70 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a607ea520829..2ffcc21670b7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5036,14 +5036,20 @@ enum {
>  #define   BLM_PCH_POLARITY			(1 << 29)
>  #define BLC_PWM_PCH_CTL2	_MMIO(0xc8254)
>  
> -#define UTIL_PIN_CTL		_MMIO(0x48400)
> -#define   UTIL_PIN_ENABLE	(1 << 31)
> -
> -#define   UTIL_PIN_PIPE(x)     ((x) << 29)
> -#define   UTIL_PIN_PIPE_MASK   (3 << 29)
> -#define   UTIL_PIN_MODE_PWM    (1 << 24)
> -#define   UTIL_PIN_MODE_MASK   (0xf << 24)
> -#define   UTIL_PIN_POLARITY    (1 << 22)
> +#define UTIL_PIN_CTL			_MMIO(0x48400)
> +#define   UTIL_PIN_ENABLE		(1 << 31)
> +#define   UTIL_PIN_PIPE_MASK		(3 << 29)
> +#define   UTIL_PIN_PIPE(x)		((x) << 29)
> +#define   UTIL_PIN_MODE_MASK		(0xf << 24)
> +#define   UTIL_PIN_MODE_DATA		(0 << 24)
> +#define   UTIL_PIN_MODE_PWM		(1 << 24)
> +#define   UTIL_PIN_MODE_VBLANK		(4 << 24)
> +#define   UTIL_PIN_MODE_VSYNC		(5 << 24)
> +#define   UTIL_PIN_MODE_EYE_LEVEL	(8 << 24)
> +#define   UTIL_PIN_OUTPUT_DATA		(1 << 23)
> +#define   UTIL_PIN_POLARITY		(1 << 22)
> +#define   UTIL_PIN_DIRECTION_INPUT	(1 << 19)
> +#define   UTIL_PIN_INPUT_DATA		(1 << 16)
>  
>  /* BXT backlight register definition. */
>  #define _BXT_BLC_PWM_CTL1			0xC8250
> @@ -7500,11 +7506,15 @@ enum {
>  #define GEN8_DE_PORT_IMR _MMIO(0x44444)
>  #define GEN8_DE_PORT_IIR _MMIO(0x44448)
>  #define GEN8_DE_PORT_IER _MMIO(0x4444c)
> +#define  DSI1_NON_TE			(1 << 31)
> +#define  DSI0_NON_TE			(1 << 30)
>  #define  ICL_AUX_CHANNEL_E		(1 << 29)
>  #define  CNL_AUX_CHANNEL_F		(1 << 28)
>  #define  GEN9_AUX_CHANNEL_D		(1 << 27)
>  #define  GEN9_AUX_CHANNEL_C		(1 << 26)
>  #define  GEN9_AUX_CHANNEL_B		(1 << 25)
> +#define  DSI1_TE			(1 << 24)
> +#define  DSI0_TE			(1 << 23)
>  #define  BXT_DE_PORT_HP_DDIC		(1 << 5)
>  #define  BXT_DE_PORT_HP_DDIB		(1 << 4)
>  #define  BXT_DE_PORT_HP_DDIA		(1 << 3)
> @@ -10770,6 +10780,57 @@ enum skl_power_gate {
>  #define  ICL_ESC_CLK_DIV_SHIFT			0
>  #define DSI_MAX_ESC_CLK			20000		/* in KHz */
>  
> +#define _DSI_CMD_FRMCTL_0		0x6b034
> +#define _DSI_CMD_FRMCTL_1		0x6b834
> +#define DSI_CMD_FRMCTL(port)		_MMIO_PORT(port,	\
> +						   _DSI_CMD_FRMCTL_0,\
> +						   _DSI_CMD_FRMCTL_1)
> +#define   DSI_FRAME_UPDATE_REQUEST		(1 << 31)
> +#define   DSI_PERIODIC_FRAME_UPDATE_ENABLE	(1 << 29)
> +#define   DSI_NULL_PACKET_ENABLE		(1 << 28)
> +#define   DSI_FRAME_IN_PROGRESS			(1 << 0)
> +
> +#define _DSI_INTR_MASK_REG_0		0x6b070
> +#define _DSI_INTR_MASK_REG_1		0x6b870
> +#define DSI_INTR_MASK_REG(port)		_MMIO_PORT(port,	\
> +						   _DSI_INTR_MASK_REG_0,\
> +						   _DSI_INTR_MASK_REG_1)
> +
> +#define _DSI_INTR_IDENT_REG_0		0x6b074
> +#define _DSI_INTR_IDENT_REG_1		0x6b874
> +#define DSI_INTR_IDENT_REG(port)	_MMIO_PORT(port,	\
> +						   _DSI_INTR_IDENT_REG_0,\
> +						   _DSI_INTR_IDENT_REG_1)
> +#define   DSI_TE_EVENT				(1 << 31)
> +#define   DSI_RX_DATA_OR_BTA_TERMINATED		(1 << 30)
> +#define   DSI_TX_DATA				(1 << 29)
> +#define   DSI_ULPS_ENTRY_DONE			(1 << 28)
> +#define   DSI_NON_TE_TRIGGER_RECEIVED		(1 << 27)
> +#define   DSI_HOST_CHKSUM_ERROR			(1 << 26)
> +#define   DSI_HOST_MULTI_ECC_ERROR		(1 << 25)
> +#define   DSI_HOST_SINGL_ECC_ERROR		(1 << 24)
> +#define   DSI_HOST_CONTENTION_DETECTED		(1 << 23)
> +#define   DSI_HOST_FALSE_CONTROL_ERROR		(1 << 22)
> +#define   DSI_HOST_TIMEOUT_ERROR		(1 << 21)
> +#define   DSI_HOST_LOW_POWER_TX_SYNC_ERROR	(1 << 20)
> +#define   DSI_HOST_ESCAPE_MODE_ENTRY_ERROR	(1 << 19)
> +#define   DSI_FRAME_UPDATE_DONE			(1 << 16)
> +#define   DSI_PROTOCOL_VIOLATION_REPORTED	(1 << 15)
> +#define   DSI_INVALID_TX_LENGTH			(1 << 13)
> +#define   DSI_INVALID_VC			(1 << 12)
> +#define   DSI_INVALID_DATA_TYPE			(1 << 11)
> +#define   DSI_PERIPHERAL_CHKSUM_ERROR		(1 << 10)
> +#define   DSI_PERIPHERAL_MULTI_ECC_ERROR	(1 << 9)
> +#define   DSI_PERIPHERAL_SINGLE_ECC_ERROR	(1 << 8)
> +#define   DSI_PERIPHERAL_CONTENTION_DETECTED	(1 << 7)
> +#define   DSI_PERIPHERAL_FALSE_CTRL_ERROR	(1 << 6)
> +#define   DSI_PERIPHERAL_TIMEOUT_ERROR		(1 << 5)
> +#define   DSI_PERIPHERAL_LP_TX_SYNC_ERROR	(1 << 4)
> +#define   DSI_PERIPHERAL_ESC_MODE_ENTRY_CMD_ERR	(1 << 3)
> +#define   DSI_EOT_SYNC_ERROR			(1 << 2)
> +#define   DSI_SOT_SYNC_ERROR			(1 << 1)
> +#define   DSI_SOT_ERROR				(1 << 0)
> +
>  /* Gen4+ Timestamp and Pipe Frame time stamp registers */
>  #define GEN4_TIMESTAMP		_MMIO(0x2358)
>  #define ILK_TIMESTAMP_HI	_MMIO(0x70070)
> @@ -11374,6 +11435,7 @@ enum skl_power_gate {
>  #define  CMD_MODE_TE_GATE		(0x1 << 28)
>  #define  VIDEO_MODE_SYNC_EVENT		(0x2 << 28)
>  #define  VIDEO_MODE_SYNC_PULSE		(0x3 << 28)
> +#define  TE_SOURCE_GPIO			(1 << 27)
>  #define  LINK_READY			(1 << 20)
>  #define  PIX_FMT_MASK			(0x3 << 16)
>  #define  PIX_FMT_SHIFT			16

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
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Re: [RFC-v2 4/9] drm/i915/dsi: Add cmd mode flags in display mode private flags

[Jani Nikula]

On Mon, 11 Nov 2019, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote:
> Adding TE flags and periodic command mode flags
> as part of private flags to indicate what TE interrupts
> we would be getting instead of vblanks in case of mipi dsi
> command mode.
>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_types.h | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index fadd9853f966..f36e8e4e5b55 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -656,6 +656,12 @@ struct intel_crtc_scaler_state {
>  #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
>  /* Flag to use the scanline counter instead of the pixel counter */
>  #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2)
> +/* Flag to use TE from DSI0 instead of VBI in command mode */
> +#define I915_MODE_FLAG_DSI_USE_TE0 (1<<3)
> +/* Flag to use TE from DSI1 instead of VBI in command mode */
> +#define I915_MODE_FLAG_DSI_USE_TE1 (1<<4)

Might be useful to comment that one or the other is set if the crtc has
a DSI encoder that's operating in command mode, and both are unset
otherwise.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> +/* Flag to indicate mipi dsi periodic command mode where we do not get TE */
> +#define I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE (1<<5)
>  
>  struct intel_pipe_wm {
>  	struct intel_wm_level wm[5];

-- 
Jani Nikula, Intel Open Source Graphics Center
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Re: [Intel-gfx] [RFC-v2 4/9] drm/i915/dsi: Add cmd mode flags in display mode private flags

[Jani Nikula]

On Mon, 11 Nov 2019, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote:
> Adding TE flags and periodic command mode flags
> as part of private flags to indicate what TE interrupts
> we would be getting instead of vblanks in case of mipi dsi
> command mode.
>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_types.h | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index fadd9853f966..f36e8e4e5b55 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -656,6 +656,12 @@ struct intel_crtc_scaler_state {
>  #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
>  /* Flag to use the scanline counter instead of the pixel counter */
>  #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2)
> +/* Flag to use TE from DSI0 instead of VBI in command mode */
> +#define I915_MODE_FLAG_DSI_USE_TE0 (1<<3)
> +/* Flag to use TE from DSI1 instead of VBI in command mode */
> +#define I915_MODE_FLAG_DSI_USE_TE1 (1<<4)

Might be useful to comment that one or the other is set if the crtc has
a DSI encoder that's operating in command mode, and both are unset
otherwise.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> +/* Flag to indicate mipi dsi periodic command mode where we do not get TE */
> +#define I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE (1<<5)
>  
>  struct intel_pipe_wm {
>  	struct intel_wm_level wm[5];

-- 
Jani Nikula, Intel Open Source Graphics Center
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