* [PATCH] drm/i915/selftests: Exercise long preemption chains
@ 2019-11-12 20:50 Chris Wilson
2019-11-12 20:50 ` [Intel-gfx] " Chris Wilson
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Chris Wilson @ 2019-11-12 20:50 UTC (permalink / raw)
To: intel-gfx
Verify that we can execute a long chain of dependent requests from
userspace, each one slightly more important than the last.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 186 +++++++++++++++++++++++++
1 file changed, 186 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index d1ed3c0f851c..0b0316159ae3 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -1915,6 +1915,191 @@ static int live_chain_preempt(void *arg)
goto err_client_lo;
}
+static int create_gang(struct intel_engine_cs *engine,
+ struct i915_request **prev)
+{
+ struct drm_i915_gem_object *obj;
+ struct intel_context *ce;
+ struct i915_request *rq;
+ struct i915_vma *vma;
+ u32 *cs;
+ int err;
+
+ ce = intel_context_create(engine->kernel_context->gem_context, engine);
+ if (IS_ERR(ce))
+ return PTR_ERR(ce);
+
+ obj = i915_gem_object_create_internal(engine->i915, 4096);
+ if (IS_ERR(obj)) {
+ err = PTR_ERR(obj);
+ goto err_ce;
+ }
+
+ vma = i915_vma_instance(obj, ce->vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto err_obj;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err)
+ goto err_obj;
+
+ cs = i915_gem_object_pin_map(obj, I915_MAP_WC);
+ if (IS_ERR(cs))
+ goto err_obj;
+
+ *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
+
+ *cs++ = MI_SEMAPHORE_WAIT |
+ MI_SEMAPHORE_POLL |
+ MI_SEMAPHORE_SAD_EQ_SDD;
+ *cs++ = 0;
+ *cs++ = lower_32_bits(vma->node.start);
+ *cs++ = upper_32_bits(vma->node.start);
+
+ if (*prev) {
+ u64 offset = (*prev)->batch->node.start;
+
+ *cs++ = MI_STORE_DWORD_IMM_GEN4;
+ *cs++ = lower_32_bits(offset);
+ *cs++ = upper_32_bits(offset);
+ *cs++ = 0;
+ }
+
+ *cs++ = MI_BATCH_BUFFER_END;
+ i915_gem_object_flush_map(obj);
+ i915_gem_object_unpin_map(obj);
+
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq))
+ goto err_obj;
+
+ rq->batch = vma;
+ i915_request_get(rq);
+
+ i915_vma_lock(vma);
+ err = i915_request_await_object(rq, vma->obj, false);
+ if (!err)
+ err = i915_vma_move_to_active(vma, rq, 0);
+ if (!err)
+ err = rq->engine->emit_bb_start(rq,
+ vma->node.start,
+ PAGE_SIZE, 0);
+ i915_vma_unlock(vma);
+ i915_request_add(rq);
+ if (err)
+ goto err_rq;
+
+ i915_gem_object_put(obj);
+ intel_context_put(ce);
+
+ rq->client_link.next = &(*prev)->client_link;
+ *prev = rq;
+ return 0;
+
+err_rq:
+ i915_request_put(rq);
+err_obj:
+ i915_gem_object_put(obj);
+err_ce:
+ intel_context_put(ce);
+ return err;
+}
+
+static int live_preempt_gang(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+
+ if (!HAS_LOGICAL_RING_PREEMPTION(gt->i915))
+ return 0;
+
+ /*
+ * Build as long a chain of preempters as we can, with each
+ * request higher priority than the last. Once we give, we release
+ * the last batch which then precolates down the chain, each releasing
+ * the next oldest. The intent is to simply push as hard as we can
+ * with the number of preemptions, trying to exceed narrow HW limits.
+ * At a minimum, we insist that we can sort all the user high
+ * priority levels into execution order.
+ */
+
+ for_each_engine(engine, gt, id) {
+ struct i915_request *rq = NULL;
+ struct igt_live_test t;
+ IGT_TIMEOUT(end_time);
+ int prio = 0;
+ int err = 0;
+ u32 *cs;
+
+ if (!intel_engine_has_preemption(engine))
+ continue;
+
+ if (igt_live_test_begin(&t, gt->i915, __func__, engine->name))
+ return -EIO;
+
+ do {
+ struct i915_sched_attr attr = {
+ .priority = I915_USER_PRIORITY(prio++),
+ };
+
+ err = create_gang(engine, &rq);
+ if (err)
+ break;
+
+ engine->schedule(rq, &attr);
+
+ if (prio <= I915_PRIORITY_MAX)
+ continue;
+
+ if (prio > (INT_MAX >> I915_USER_PRIORITY_SHIFT))
+ break;
+
+ if (__igt_timeout(end_time, NULL))
+ break;
+ } while (1);
+ pr_debug("%s: Preempt chain of %d requests\n",
+ engine->name, prio);
+
+ cs = i915_gem_object_pin_map(rq->batch->obj, I915_MAP_WC);
+ if (!IS_ERR(cs)) {
+ *cs = 0;
+ i915_gem_object_unpin_map(rq->batch->obj);
+ } else {
+ err = PTR_ERR(cs);
+ intel_gt_set_wedged(gt);
+ }
+
+ if (err == 0 && i915_request_wait(rq, 0, HZ) < 0) {
+ struct drm_printer p =
+ drm_info_printer(engine->i915->drm.dev);
+
+ pr_err("Failed to flush chain of %d requests\n", prio);
+ intel_engine_dump(engine, &p,
+ "%s\n", engine->name);
+
+ err = -ETIME;
+ }
+
+ while (rq) {
+ struct i915_request *n =
+ list_next_entry(rq, client_link);
+
+ i915_request_put(rq);
+ rq = n;
+ }
+
+ if (igt_live_test_end(&t))
+ err = -EIO;
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
static int live_preempt_hang(void *arg)
{
struct intel_gt *gt = arg;
@@ -3028,6 +3213,7 @@ int intel_execlists_live_selftests(struct drm_i915_private *i915)
SUBTEST(live_suppress_self_preempt),
SUBTEST(live_suppress_wait_preempt),
SUBTEST(live_chain_preempt),
+ SUBTEST(live_preempt_gang),
SUBTEST(live_preempt_hang),
SUBTEST(live_preempt_timeout),
SUBTEST(live_preempt_smoke),
--
2.24.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/selftests: Exercise long preemption chains
2019-11-12 20:50 [PATCH] drm/i915/selftests: Exercise long preemption chains Chris Wilson
@ 2019-11-12 20:50 ` Chris Wilson
2019-11-12 22:55 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2019-11-12 23:46 ` ✗ Fi.CI.BAT: failure " Patchwork
2 siblings, 0 replies; 6+ messages in thread
From: Chris Wilson @ 2019-11-12 20:50 UTC (permalink / raw)
To: intel-gfx
Verify that we can execute a long chain of dependent requests from
userspace, each one slightly more important than the last.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 186 +++++++++++++++++++++++++
1 file changed, 186 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index d1ed3c0f851c..0b0316159ae3 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -1915,6 +1915,191 @@ static int live_chain_preempt(void *arg)
goto err_client_lo;
}
+static int create_gang(struct intel_engine_cs *engine,
+ struct i915_request **prev)
+{
+ struct drm_i915_gem_object *obj;
+ struct intel_context *ce;
+ struct i915_request *rq;
+ struct i915_vma *vma;
+ u32 *cs;
+ int err;
+
+ ce = intel_context_create(engine->kernel_context->gem_context, engine);
+ if (IS_ERR(ce))
+ return PTR_ERR(ce);
+
+ obj = i915_gem_object_create_internal(engine->i915, 4096);
+ if (IS_ERR(obj)) {
+ err = PTR_ERR(obj);
+ goto err_ce;
+ }
+
+ vma = i915_vma_instance(obj, ce->vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto err_obj;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err)
+ goto err_obj;
+
+ cs = i915_gem_object_pin_map(obj, I915_MAP_WC);
+ if (IS_ERR(cs))
+ goto err_obj;
+
+ *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
+
+ *cs++ = MI_SEMAPHORE_WAIT |
+ MI_SEMAPHORE_POLL |
+ MI_SEMAPHORE_SAD_EQ_SDD;
+ *cs++ = 0;
+ *cs++ = lower_32_bits(vma->node.start);
+ *cs++ = upper_32_bits(vma->node.start);
+
+ if (*prev) {
+ u64 offset = (*prev)->batch->node.start;
+
+ *cs++ = MI_STORE_DWORD_IMM_GEN4;
+ *cs++ = lower_32_bits(offset);
+ *cs++ = upper_32_bits(offset);
+ *cs++ = 0;
+ }
+
+ *cs++ = MI_BATCH_BUFFER_END;
+ i915_gem_object_flush_map(obj);
+ i915_gem_object_unpin_map(obj);
+
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq))
+ goto err_obj;
+
+ rq->batch = vma;
+ i915_request_get(rq);
+
+ i915_vma_lock(vma);
+ err = i915_request_await_object(rq, vma->obj, false);
+ if (!err)
+ err = i915_vma_move_to_active(vma, rq, 0);
+ if (!err)
+ err = rq->engine->emit_bb_start(rq,
+ vma->node.start,
+ PAGE_SIZE, 0);
+ i915_vma_unlock(vma);
+ i915_request_add(rq);
+ if (err)
+ goto err_rq;
+
+ i915_gem_object_put(obj);
+ intel_context_put(ce);
+
+ rq->client_link.next = &(*prev)->client_link;
+ *prev = rq;
+ return 0;
+
+err_rq:
+ i915_request_put(rq);
+err_obj:
+ i915_gem_object_put(obj);
+err_ce:
+ intel_context_put(ce);
+ return err;
+}
+
+static int live_preempt_gang(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+
+ if (!HAS_LOGICAL_RING_PREEMPTION(gt->i915))
+ return 0;
+
+ /*
+ * Build as long a chain of preempters as we can, with each
+ * request higher priority than the last. Once we give, we release
+ * the last batch which then precolates down the chain, each releasing
+ * the next oldest. The intent is to simply push as hard as we can
+ * with the number of preemptions, trying to exceed narrow HW limits.
+ * At a minimum, we insist that we can sort all the user high
+ * priority levels into execution order.
+ */
+
+ for_each_engine(engine, gt, id) {
+ struct i915_request *rq = NULL;
+ struct igt_live_test t;
+ IGT_TIMEOUT(end_time);
+ int prio = 0;
+ int err = 0;
+ u32 *cs;
+
+ if (!intel_engine_has_preemption(engine))
+ continue;
+
+ if (igt_live_test_begin(&t, gt->i915, __func__, engine->name))
+ return -EIO;
+
+ do {
+ struct i915_sched_attr attr = {
+ .priority = I915_USER_PRIORITY(prio++),
+ };
+
+ err = create_gang(engine, &rq);
+ if (err)
+ break;
+
+ engine->schedule(rq, &attr);
+
+ if (prio <= I915_PRIORITY_MAX)
+ continue;
+
+ if (prio > (INT_MAX >> I915_USER_PRIORITY_SHIFT))
+ break;
+
+ if (__igt_timeout(end_time, NULL))
+ break;
+ } while (1);
+ pr_debug("%s: Preempt chain of %d requests\n",
+ engine->name, prio);
+
+ cs = i915_gem_object_pin_map(rq->batch->obj, I915_MAP_WC);
+ if (!IS_ERR(cs)) {
+ *cs = 0;
+ i915_gem_object_unpin_map(rq->batch->obj);
+ } else {
+ err = PTR_ERR(cs);
+ intel_gt_set_wedged(gt);
+ }
+
+ if (err == 0 && i915_request_wait(rq, 0, HZ) < 0) {
+ struct drm_printer p =
+ drm_info_printer(engine->i915->drm.dev);
+
+ pr_err("Failed to flush chain of %d requests\n", prio);
+ intel_engine_dump(engine, &p,
+ "%s\n", engine->name);
+
+ err = -ETIME;
+ }
+
+ while (rq) {
+ struct i915_request *n =
+ list_next_entry(rq, client_link);
+
+ i915_request_put(rq);
+ rq = n;
+ }
+
+ if (igt_live_test_end(&t))
+ err = -EIO;
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
static int live_preempt_hang(void *arg)
{
struct intel_gt *gt = arg;
@@ -3028,6 +3213,7 @@ int intel_execlists_live_selftests(struct drm_i915_private *i915)
SUBTEST(live_suppress_self_preempt),
SUBTEST(live_suppress_wait_preempt),
SUBTEST(live_chain_preempt),
+ SUBTEST(live_preempt_gang),
SUBTEST(live_preempt_hang),
SUBTEST(live_preempt_timeout),
SUBTEST(live_preempt_smoke),
--
2.24.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Exercise long preemption chains
2019-11-12 20:50 [PATCH] drm/i915/selftests: Exercise long preemption chains Chris Wilson
2019-11-12 20:50 ` [Intel-gfx] " Chris Wilson
@ 2019-11-12 22:55 ` Patchwork
2019-11-12 22:55 ` [Intel-gfx] " Patchwork
2019-11-12 23:46 ` ✗ Fi.CI.BAT: failure " Patchwork
2 siblings, 1 reply; 6+ messages in thread
From: Patchwork @ 2019-11-12 22:55 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/selftests: Exercise long preemption chains
URL : https://patchwork.freedesktop.org/series/69375/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a2d073857c00 drm/i915/selftests: Exercise long preemption chains
-:134: WARNING:LINE_SPACING: Missing a blank line after declarations
#134: FILE: drivers/gpu/drm/i915/gt/selftest_lrc.c:2032:
+ struct igt_live_test t;
+ IGT_TIMEOUT(end_time);
total: 0 errors, 1 warnings, 0 checks, 198 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Exercise long preemption chains
2019-11-12 22:55 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
@ 2019-11-12 22:55 ` Patchwork
0 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2019-11-12 22:55 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/selftests: Exercise long preemption chains
URL : https://patchwork.freedesktop.org/series/69375/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a2d073857c00 drm/i915/selftests: Exercise long preemption chains
-:134: WARNING:LINE_SPACING: Missing a blank line after declarations
#134: FILE: drivers/gpu/drm/i915/gt/selftest_lrc.c:2032:
+ struct igt_live_test t;
+ IGT_TIMEOUT(end_time);
total: 0 errors, 1 warnings, 0 checks, 198 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915/selftests: Exercise long preemption chains
2019-11-12 20:50 [PATCH] drm/i915/selftests: Exercise long preemption chains Chris Wilson
2019-11-12 20:50 ` [Intel-gfx] " Chris Wilson
2019-11-12 22:55 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
@ 2019-11-12 23:46 ` Patchwork
2019-11-12 23:46 ` [Intel-gfx] " Patchwork
2 siblings, 1 reply; 6+ messages in thread
From: Patchwork @ 2019-11-12 23:46 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/selftests: Exercise long preemption chains
URL : https://patchwork.freedesktop.org/series/69375/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7323 -> Patchwork_15243
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_15243 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15243, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15243/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_15243:
### IGT changes ###
#### Possible regressions ####
* igt@i915_pm_rpm@module-reload:
- fi-skl-lmem: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15243/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html
Known issues
------------
Here are the changes found in Patchwork_15243 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_setmode@basic-clone-single-crtc:
- fi-skl-6770hq: [PASS][3] -> [WARN][4] ([fdo#112252])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/fi-skl-6770hq/igt@kms_setmode@basic-clone-single-crtc.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15243/fi-skl-6770hq/igt@kms_setmode@basic-clone-single-crtc.html
#### Possible fixes ####
* igt@gem_mmap_gtt@basic-copy:
- fi-glk-dsi: [INCOMPLETE][5] ([fdo#103359] / [k.org#198133]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/fi-glk-dsi/igt@gem_mmap_gtt@basic-copy.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15243/fi-glk-dsi/igt@gem_mmap_gtt@basic-copy.html
* igt@kms_flip@basic-flip-vs-wf_vblank:
- fi-skl-6770hq: [DMESG-WARN][7] ([fdo#105541]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/fi-skl-6770hq/igt@kms_flip@basic-flip-vs-wf_vblank.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15243/fi-skl-6770hq/igt@kms_flip@basic-flip-vs-wf_vblank.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#105541]: https://bugs.freedesktop.org/show_bug.cgi?id=105541
[fdo#109964]: https://bugs.freedesktop.org/show_bug.cgi?id=109964
[fdo#110343]: https://bugs.freedesktop.org/show_bug.cgi?id=110343
[fdo#112252]: https://bugs.freedesktop.org/show_bug.cgi?id=112252
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (51 -> 44)
------------------------------
Missing (7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-bsw-kefka fi-byt-clapper
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7323 -> Patchwork_15243
CI-20190529: 20190529
CI_DRM_7323: aac244f23bf1eaf986c5df9e529863b34e52bee8 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5273: 602003c3d751c72fc309a0e64d4193f6da720f6b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15243: a2d073857c00c20fa37e78ffdfa7bd6f491f51b3 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
a2d073857c00 drm/i915/selftests: Exercise long preemption chains
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15243/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests: Exercise long preemption chains
2019-11-12 23:46 ` ✗ Fi.CI.BAT: failure " Patchwork
@ 2019-11-12 23:46 ` Patchwork
0 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2019-11-12 23:46 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/selftests: Exercise long preemption chains
URL : https://patchwork.freedesktop.org/series/69375/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7323 -> Patchwork_15243
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_15243 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15243, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15243/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_15243:
### IGT changes ###
#### Possible regressions ####
* igt@i915_pm_rpm@module-reload:
- fi-skl-lmem: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15243/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html
Known issues
------------
Here are the changes found in Patchwork_15243 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_setmode@basic-clone-single-crtc:
- fi-skl-6770hq: [PASS][3] -> [WARN][4] ([fdo#112252])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/fi-skl-6770hq/igt@kms_setmode@basic-clone-single-crtc.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15243/fi-skl-6770hq/igt@kms_setmode@basic-clone-single-crtc.html
#### Possible fixes ####
* igt@gem_mmap_gtt@basic-copy:
- fi-glk-dsi: [INCOMPLETE][5] ([fdo#103359] / [k.org#198133]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/fi-glk-dsi/igt@gem_mmap_gtt@basic-copy.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15243/fi-glk-dsi/igt@gem_mmap_gtt@basic-copy.html
* igt@kms_flip@basic-flip-vs-wf_vblank:
- fi-skl-6770hq: [DMESG-WARN][7] ([fdo#105541]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/fi-skl-6770hq/igt@kms_flip@basic-flip-vs-wf_vblank.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15243/fi-skl-6770hq/igt@kms_flip@basic-flip-vs-wf_vblank.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#105541]: https://bugs.freedesktop.org/show_bug.cgi?id=105541
[fdo#109964]: https://bugs.freedesktop.org/show_bug.cgi?id=109964
[fdo#110343]: https://bugs.freedesktop.org/show_bug.cgi?id=110343
[fdo#112252]: https://bugs.freedesktop.org/show_bug.cgi?id=112252
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (51 -> 44)
------------------------------
Missing (7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-bsw-kefka fi-byt-clapper
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7323 -> Patchwork_15243
CI-20190529: 20190529
CI_DRM_7323: aac244f23bf1eaf986c5df9e529863b34e52bee8 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5273: 602003c3d751c72fc309a0e64d4193f6da720f6b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15243: a2d073857c00c20fa37e78ffdfa7bd6f491f51b3 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
a2d073857c00 drm/i915/selftests: Exercise long preemption chains
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15243/index.html
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Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2019-11-12 23:46 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-11-12 20:50 [PATCH] drm/i915/selftests: Exercise long preemption chains Chris Wilson
2019-11-12 20:50 ` [Intel-gfx] " Chris Wilson
2019-11-12 22:55 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2019-11-12 22:55 ` [Intel-gfx] " Patchwork
2019-11-12 23:46 ` ✗ Fi.CI.BAT: failure " Patchwork
2019-11-12 23:46 ` [Intel-gfx] " Patchwork
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