[PATCH 1/4] drm/i915/gt: Set unused mocs entry to follow PTE on tgl as on all others

[PATCH 1/4] drm/i915/gt: Set unused mocs entry to follow PTE on tgl as on all others

[Chris Wilson]

Be consistent in our mocs setup on Tigerlake and set the unused control
value to follow the PTE entry as we previously have done. The unused
values are beyond the defines of the ABI, the consistency simplifies our
checking.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 6e881c735b20..d2b445d6c258 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -489,7 +489,7 @@ static void intel_mocs_init_global(struct intel_gt *gt)
 	for (; index < table.n_entries; index++)
 		intel_uncore_write(uncore,
 				   GEN12_GLOBAL_MOCS(index),
-				   table.table[0].control_value);
+				   table.table[I915_MOCS_PTE].control_value);
 }
 
 void intel_mocs_init(struct intel_gt *gt)
-- 
2.24.0

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[Intel-gfx] [PATCH 1/4] drm/i915/gt: Set unused mocs entry to follow PTE on tgl as on all others

[Chris Wilson]

Be consistent in our mocs setup on Tigerlake and set the unused control
value to follow the PTE entry as we previously have done. The unused
values are beyond the defines of the ABI, the consistency simplifies our
checking.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 6e881c735b20..d2b445d6c258 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -489,7 +489,7 @@ static void intel_mocs_init_global(struct intel_gt *gt)
 	for (; index < table.n_entries; index++)
 		intel_uncore_write(uncore,
 				   GEN12_GLOBAL_MOCS(index),
-				   table.table[0].control_value);
+				   table.table[I915_MOCS_PTE].control_value);
 }
 
 void intel_mocs_init(struct intel_gt *gt)
-- 
2.24.0

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[PATCH 2/4] drm/i915/gt: Tidy up debug-warns for the mocs control table

[Chris Wilson]

As we always run new platforms through CI, we only need the debug code
compiled in during CI runs.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gt/intel_mocs.c | 30 ++++++++++------------------
 1 file changed, 11 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index d2b445d6c258..e6f3f36a3988 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -291,44 +291,42 @@ static const struct drm_i915_mocs_entry icelake_mocs_table[] = {
 static bool get_mocs_settings(const struct drm_i915_private *i915,
 			      struct drm_i915_mocs_table *table)
 {
-	bool result = false;
-
 	if (INTEL_GEN(i915) >= 12) {
 		table->size  = ARRAY_SIZE(tigerlake_mocs_table);
 		table->table = tigerlake_mocs_table;
 		table->n_entries = GEN11_NUM_MOCS_ENTRIES;
-		result = true;
 	} else if (IS_GEN(i915, 11)) {
 		table->size  = ARRAY_SIZE(icelake_mocs_table);
 		table->table = icelake_mocs_table;
 		table->n_entries = GEN11_NUM_MOCS_ENTRIES;
-		result = true;
 	} else if (IS_GEN9_BC(i915) || IS_CANNONLAKE(i915)) {
 		table->size  = ARRAY_SIZE(skylake_mocs_table);
 		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
 		table->table = skylake_mocs_table;
-		result = true;
 	} else if (IS_GEN9_LP(i915)) {
 		table->size  = ARRAY_SIZE(broxton_mocs_table);
 		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
 		table->table = broxton_mocs_table;
-		result = true;
 	} else {
 		WARN_ONCE(INTEL_GEN(i915) >= 9,
 			  "Platform that should have a MOCS table does not.\n");
+		return false;
 	}
 
+	if (GEM_DEBUG_WARN_ON(table->size > table->n_entries))
+		return false;
+
 	/* WaDisableSkipCaching:skl,bxt,kbl,glk */
 	if (IS_GEN(i915, 9)) {
 		int i;
 
 		for (i = 0; i < table->size; i++)
-			if (WARN_ON(table->table[i].l3cc_value &
-				    (L3_ESC(1) | L3_SCC(0x7))))
+			if (GEM_DEBUG_WARN_ON(table->table[i].l3cc_value &
+					      (L3_ESC(1) | L3_SCC(0x7))))
 				return false;
 	}
 
-	return result;
+	return true;
 }
 
 static i915_reg_t mocs_register(const struct intel_engine_cs *engine, int index)
@@ -397,9 +395,7 @@ static u16 get_entry_l3cc(const struct drm_i915_mocs_table *table,
 	return table->table[I915_MOCS_PTE].l3cc_value;
 }
 
-static inline u32 l3cc_combine(const struct drm_i915_mocs_table *table,
-			       u16 low,
-			       u16 high)
+static inline u32 l3cc_combine(u16 low, u16 high)
 {
 	return low | (u32)high << 16;
 }
@@ -417,7 +413,7 @@ static void init_l3cc_table(struct intel_engine_cs *engine,
 
 		intel_uncore_write(uncore,
 				   GEN9_LNCFCMOCS(i),
-				   l3cc_combine(table, low, high));
+				   l3cc_combine(low, high));
 	}
 
 	/* Odd table size - 1 left over */
@@ -426,7 +422,7 @@ static void init_l3cc_table(struct intel_engine_cs *engine,
 
 		intel_uncore_write(uncore,
 				   GEN9_LNCFCMOCS(i),
-				   l3cc_combine(table, low, unused_value));
+				   l3cc_combine(low, unused_value));
 		i++;
 	}
 
@@ -434,8 +430,7 @@ static void init_l3cc_table(struct intel_engine_cs *engine,
 	for (; i < table->n_entries / 2; i++)
 		intel_uncore_write(uncore,
 				   GEN9_LNCFCMOCS(i),
-				   l3cc_combine(table, unused_value,
-						unused_value));
+				   l3cc_combine(unused_value, unused_value));
 }
 
 void intel_mocs_init_engine(struct intel_engine_cs *engine)
@@ -473,9 +468,6 @@ static void intel_mocs_init_global(struct intel_gt *gt)
 	if (!get_mocs_settings(gt->i915, &table))
 		return;
 
-	if (GEM_DEBUG_WARN_ON(table.size > table.n_entries))
-		return;
-
 	for (index = 0; index < table.size; index++)
 		intel_uncore_write(uncore,
 				   GEN12_GLOBAL_MOCS(index),
-- 
2.24.0

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[Intel-gfx] [PATCH 2/4] drm/i915/gt: Tidy up debug-warns for the mocs control table

[Chris Wilson]

As we always run new platforms through CI, we only need the debug code
compiled in during CI runs.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gt/intel_mocs.c | 30 ++++++++++------------------
 1 file changed, 11 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index d2b445d6c258..e6f3f36a3988 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -291,44 +291,42 @@ static const struct drm_i915_mocs_entry icelake_mocs_table[] = {
 static bool get_mocs_settings(const struct drm_i915_private *i915,
 			      struct drm_i915_mocs_table *table)
 {
-	bool result = false;
-
 	if (INTEL_GEN(i915) >= 12) {
 		table->size  = ARRAY_SIZE(tigerlake_mocs_table);
 		table->table = tigerlake_mocs_table;
 		table->n_entries = GEN11_NUM_MOCS_ENTRIES;
-		result = true;
 	} else if (IS_GEN(i915, 11)) {
 		table->size  = ARRAY_SIZE(icelake_mocs_table);
 		table->table = icelake_mocs_table;
 		table->n_entries = GEN11_NUM_MOCS_ENTRIES;
-		result = true;
 	} else if (IS_GEN9_BC(i915) || IS_CANNONLAKE(i915)) {
 		table->size  = ARRAY_SIZE(skylake_mocs_table);
 		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
 		table->table = skylake_mocs_table;
-		result = true;
 	} else if (IS_GEN9_LP(i915)) {
 		table->size  = ARRAY_SIZE(broxton_mocs_table);
 		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
 		table->table = broxton_mocs_table;
-		result = true;
 	} else {
 		WARN_ONCE(INTEL_GEN(i915) >= 9,
 			  "Platform that should have a MOCS table does not.\n");
+		return false;
 	}
 
+	if (GEM_DEBUG_WARN_ON(table->size > table->n_entries))
+		return false;
+
 	/* WaDisableSkipCaching:skl,bxt,kbl,glk */
 	if (IS_GEN(i915, 9)) {
 		int i;
 
 		for (i = 0; i < table->size; i++)
-			if (WARN_ON(table->table[i].l3cc_value &
-				    (L3_ESC(1) | L3_SCC(0x7))))
+			if (GEM_DEBUG_WARN_ON(table->table[i].l3cc_value &
+					      (L3_ESC(1) | L3_SCC(0x7))))
 				return false;
 	}
 
-	return result;
+	return true;
 }
 
 static i915_reg_t mocs_register(const struct intel_engine_cs *engine, int index)
@@ -397,9 +395,7 @@ static u16 get_entry_l3cc(const struct drm_i915_mocs_table *table,
 	return table->table[I915_MOCS_PTE].l3cc_value;
 }
 
-static inline u32 l3cc_combine(const struct drm_i915_mocs_table *table,
-			       u16 low,
-			       u16 high)
+static inline u32 l3cc_combine(u16 low, u16 high)
 {
 	return low | (u32)high << 16;
 }
@@ -417,7 +413,7 @@ static void init_l3cc_table(struct intel_engine_cs *engine,
 
 		intel_uncore_write(uncore,
 				   GEN9_LNCFCMOCS(i),
-				   l3cc_combine(table, low, high));
+				   l3cc_combine(low, high));
 	}
 
 	/* Odd table size - 1 left over */
@@ -426,7 +422,7 @@ static void init_l3cc_table(struct intel_engine_cs *engine,
 
 		intel_uncore_write(uncore,
 				   GEN9_LNCFCMOCS(i),
-				   l3cc_combine(table, low, unused_value));
+				   l3cc_combine(low, unused_value));
 		i++;
 	}
 
@@ -434,8 +430,7 @@ static void init_l3cc_table(struct intel_engine_cs *engine,
 	for (; i < table->n_entries / 2; i++)
 		intel_uncore_write(uncore,
 				   GEN9_LNCFCMOCS(i),
-				   l3cc_combine(table, unused_value,
-						unused_value));
+				   l3cc_combine(unused_value, unused_value));
 }
 
 void intel_mocs_init_engine(struct intel_engine_cs *engine)
@@ -473,9 +468,6 @@ static void intel_mocs_init_global(struct intel_gt *gt)
 	if (!get_mocs_settings(gt->i915, &table))
 		return;
 
-	if (GEM_DEBUG_WARN_ON(table.size > table.n_entries))
-		return;
-
 	for (index = 0; index < table.size; index++)
 		intel_uncore_write(uncore,
 				   GEN12_GLOBAL_MOCS(index),
-- 
2.24.0

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[PATCH 3/4] drm/i915/gt: Refactor mocs loops into single control macro

[Chris Wilson]

We repeatedly (and more so in future) use the same looping construct
over the mocs definition table to setup the register state. Refactor the
loop construct into a reusable macro.

add/remove: 2/1 grow/shrink: 1/2 up/down: 113/-330 (-217)
Function                                     old     new   delta
intel_mocs_init_engine.cold                    -      71     +71
offset                                         -      28     +28
__func__                                   17273   17287     +14
intel_mocs_init                              143     113     -30
mocs_register.isra                            91       -     -91
intel_mocs_init_engine                       503     294    -209

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gt/intel_mocs.c | 133 +++++++++++----------------
 drivers/gpu/drm/i915/i915_reg.h      |  19 ++--
 2 files changed, 64 insertions(+), 88 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index e6f3f36a3988..47d16a242183 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -329,27 +329,6 @@ static bool get_mocs_settings(const struct drm_i915_private *i915,
 	return true;
 }
 
-static i915_reg_t mocs_register(const struct intel_engine_cs *engine, int index)
-{
-	switch (engine->id) {
-	case RCS0:
-		return GEN9_GFX_MOCS(index);
-	case VCS0:
-		return GEN9_MFX0_MOCS(index);
-	case BCS0:
-		return GEN9_BLT_MOCS(index);
-	case VECS0:
-		return GEN9_VEBOX_MOCS(index);
-	case VCS1:
-		return GEN9_MFX1_MOCS(index);
-	case VCS2:
-		return GEN11_MFX2_MOCS(index);
-	default:
-		MISSING_CASE(engine->id);
-		return INVALID_MMIO_REG;
-	}
-}
-
 /*
  * Get control_value from MOCS entry taking into account when it's not used:
  * I915_MOCS_PTE's value is returned in this case.
@@ -357,29 +336,47 @@ static i915_reg_t mocs_register(const struct intel_engine_cs *engine, int index)
 static u32 get_entry_control(const struct drm_i915_mocs_table *table,
 			     unsigned int index)
 {
-	if (table->table[index].used)
+	if (index < table->size && table->table[index].used)
 		return table->table[index].control_value;
 
 	return table->table[I915_MOCS_PTE].control_value;
 }
 
-static void init_mocs_table(struct intel_engine_cs *engine,
-			    const struct drm_i915_mocs_table *table)
+#define for_each_mocs(mocs, t, i) \
+	for (i = 0; \
+	     i < (t)->n_entries ? (mocs = get_entry_control((t), i)), 1 : 0;\
+	     i++)
+
+static void __init_mocs_table(struct intel_uncore *uncore,
+			      const struct drm_i915_mocs_table *table,
+			      u32 addr)
 {
-	struct intel_uncore *uncore = engine->uncore;
-	u32 unused_value = table->table[I915_MOCS_PTE].control_value;
 	unsigned int i;
+	u32 mocs;
 
-	for (i = 0; i < table->size; i++)
-		intel_uncore_write_fw(uncore,
-				      mocs_register(engine, i),
-				      get_entry_control(table, i));
+	for_each_mocs(mocs, table, i)
+		intel_uncore_write_fw(uncore, _MMIO(addr + i * 4), mocs);
+}
+
+static u32 mocs_offset(const struct intel_engine_cs *engine)
+{
+	static const u32 offset[] = {
+		[RCS0]  =  __GEN9_RCS0_MOCS0,
+		[VCS0]  =  __GEN9_VCS0_MOCS0,
+		[VCS1]  =  __GEN9_VCS1_MOCS0,
+		[VECS0] =  __GEN9_VECS0_MOCS0,
+		[BCS0]  =  __GEN9_BCS0_MOCS0,
+		[VCS2]  = __GEN11_VCS2_MOCS0,
+	};
+
+	GEM_BUG_ON(engine->id >= ARRAY_SIZE(offset));
+	return offset[engine->id];
+}
 
-	/* All remaining entries are unused */
-	for (; i < table->n_entries; i++)
-		intel_uncore_write_fw(uncore,
-				      mocs_register(engine, i),
-				      unused_value);
+static void init_mocs_table(struct intel_engine_cs *engine,
+			    const struct drm_i915_mocs_table *table)
+{
+	__init_mocs_table(engine->uncore, table, mocs_offset(engine));
 }
 
 /*
@@ -389,7 +386,7 @@ static void init_mocs_table(struct intel_engine_cs *engine,
 static u16 get_entry_l3cc(const struct drm_i915_mocs_table *table,
 			  unsigned int index)
 {
-	if (table->table[index].used)
+	if (index < table->size && table->table[index].used)
 		return table->table[index].l3cc_value;
 
 	return table->table[I915_MOCS_PTE].l3cc_value;
@@ -400,37 +397,23 @@ static inline u32 l3cc_combine(u16 low, u16 high)
 	return low | (u32)high << 16;
 }
 
+#define for_each_l3cc(l3cc, t, i) \
+	for (i = 0; \
+	     i < ((t)->n_entries + 1) / 2 ? \
+	     (l3cc = l3cc_combine(get_entry_l3cc((t), 2 * i), \
+				  get_entry_l3cc((t), 2 * i + 1))), 1 : \
+	     0; \
+	     i++)
+
 static void init_l3cc_table(struct intel_engine_cs *engine,
 			    const struct drm_i915_mocs_table *table)
 {
 	struct intel_uncore *uncore = engine->uncore;
-	u16 unused_value = table->table[I915_MOCS_PTE].l3cc_value;
 	unsigned int i;
+	u32 l3cc;
 
-	for (i = 0; i < table->size / 2; i++) {
-		u16 low = get_entry_l3cc(table, 2 * i);
-		u16 high = get_entry_l3cc(table, 2 * i + 1);
-
-		intel_uncore_write(uncore,
-				   GEN9_LNCFCMOCS(i),
-				   l3cc_combine(low, high));
-	}
-
-	/* Odd table size - 1 left over */
-	if (table->size & 1) {
-		u16 low = get_entry_l3cc(table, 2 * i);
-
-		intel_uncore_write(uncore,
-				   GEN9_LNCFCMOCS(i),
-				   l3cc_combine(low, unused_value));
-		i++;
-	}
-
-	/* All remaining entries are also unused */
-	for (; i < table->n_entries / 2; i++)
-		intel_uncore_write(uncore,
-				   GEN9_LNCFCMOCS(i),
-				   l3cc_combine(unused_value, unused_value));
+	for_each_l3cc(l3cc, table, i)
+		intel_uncore_write_fw(uncore, GEN9_LNCFCMOCS(i), l3cc);
 }
 
 void intel_mocs_init_engine(struct intel_engine_cs *engine)
@@ -451,11 +434,14 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
 		init_l3cc_table(engine, &table);
 }
 
-static void intel_mocs_init_global(struct intel_gt *gt)
+static u32 global_mocs_offset(void)
+{
+	return i915_mmio_reg_offset(GEN12_GLOBAL_MOCS(0));
+}
+
+static void init_global_mocs(struct intel_gt *gt)
 {
-	struct intel_uncore *uncore = gt->uncore;
 	struct drm_i915_mocs_table table;
-	unsigned int index;
 
 	/*
 	 * LLC and eDRAM control values are not applicable to dgfx
@@ -463,29 +449,14 @@ static void intel_mocs_init_global(struct intel_gt *gt)
 	if (IS_DGFX(gt->i915))
 		return;
 
-	GEM_BUG_ON(!HAS_GLOBAL_MOCS_REGISTERS(gt->i915));
-
 	if (!get_mocs_settings(gt->i915, &table))
 		return;
 
-	for (index = 0; index < table.size; index++)
-		intel_uncore_write(uncore,
-				   GEN12_GLOBAL_MOCS(index),
-				   table.table[index].control_value);
-
-	/*
-	 * Ok, now set the unused entries to the invalid entry (index 0). These
-	 * entries are officially undefined and no contract for the contents and
-	 * settings is given for these entries.
-	 */
-	for (; index < table.n_entries; index++)
-		intel_uncore_write(uncore,
-				   GEN12_GLOBAL_MOCS(index),
-				   table.table[I915_MOCS_PTE].control_value);
+	__init_mocs_table(gt->uncore, &table, global_mocs_offset());
 }
 
 void intel_mocs_init(struct intel_gt *gt)
 {
 	if (HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
-		intel_mocs_init_global(gt);
+		init_global_mocs(gt);
 }
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2ffcc21670b7..0960ea0b5a66 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11688,13 +11688,18 @@ enum skl_power_gate {
 /* MOCS (Memory Object Control State) registers */
 #define GEN9_LNCFCMOCS(i)	_MMIO(0xb020 + (i) * 4)	/* L3 Cache Control */
 
-#define GEN9_GFX_MOCS(i)	_MMIO(0xc800 + (i) * 4)	/* Graphics MOCS registers */
-#define GEN9_MFX0_MOCS(i)	_MMIO(0xc900 + (i) * 4)	/* Media 0 MOCS registers */
-#define GEN9_MFX1_MOCS(i)	_MMIO(0xca00 + (i) * 4)	/* Media 1 MOCS registers */
-#define GEN9_VEBOX_MOCS(i)	_MMIO(0xcb00 + (i) * 4)	/* Video MOCS registers */
-#define GEN9_BLT_MOCS(i)	_MMIO(0xcc00 + (i) * 4)	/* Blitter MOCS registers */
-/* Media decoder 2 MOCS registers */
-#define GEN11_MFX2_MOCS(i)	_MMIO(0x10000 + (i) * 4)
+#define __GEN9_RCS0_MOCS0	0xc800
+#define GEN9_GFX_MOCS(i)	_MMIO(__GEN9_RCS0_MOCS0 + (i) * 4)
+#define __GEN9_VCS0_MOCS0	0xc900
+#define GEN9_MFX0_MOCS(i)	_MMIO(__GEN9_VCS0_MOCS0 + (i) * 4)
+#define __GEN9_VCS1_MOCS0	0xca00
+#define GEN9_MFX1_MOCS(i)	_MMIO(__GEN9_VCS1_MOCS0 + (i) * 4)
+#define __GEN9_VECS0_MOCS0	0xcb00
+#define GEN9_VEBOX_MOCS(i)	_MMIO(__GEN9_VECS0_MOCS0 + (i) * 4)
+#define __GEN9_BCS0_MOCS0	0xcc00
+#define GEN9_BLT_MOCS(i)	_MMIO(__GEN9_BCS0_MOCS0 + (i) * 4)
+#define __GEN11_VCS2_MOCS0	0x10000
+#define GEN11_MFX2_MOCS(i)	_MMIO(__GEN11_VCS2_MOCS0 + (i) * 4)
 
 #define GEN10_SCRATCH_LNCF2		_MMIO(0xb0a0)
 #define   PMFLUSHDONE_LNICRSDROP	(1 << 20)
-- 
2.24.0

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[Intel-gfx] [PATCH 3/4] drm/i915/gt: Refactor mocs loops into single control macro

[Chris Wilson]

We repeatedly (and more so in future) use the same looping construct
over the mocs definition table to setup the register state. Refactor the
loop construct into a reusable macro.

add/remove: 2/1 grow/shrink: 1/2 up/down: 113/-330 (-217)
Function                                     old     new   delta
intel_mocs_init_engine.cold                    -      71     +71
offset                                         -      28     +28
__func__                                   17273   17287     +14
intel_mocs_init                              143     113     -30
mocs_register.isra                            91       -     -91
intel_mocs_init_engine                       503     294    -209

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gt/intel_mocs.c | 133 +++++++++++----------------
 drivers/gpu/drm/i915/i915_reg.h      |  19 ++--
 2 files changed, 64 insertions(+), 88 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index e6f3f36a3988..47d16a242183 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -329,27 +329,6 @@ static bool get_mocs_settings(const struct drm_i915_private *i915,
 	return true;
 }
 
-static i915_reg_t mocs_register(const struct intel_engine_cs *engine, int index)
-{
-	switch (engine->id) {
-	case RCS0:
-		return GEN9_GFX_MOCS(index);
-	case VCS0:
-		return GEN9_MFX0_MOCS(index);
-	case BCS0:
-		return GEN9_BLT_MOCS(index);
-	case VECS0:
-		return GEN9_VEBOX_MOCS(index);
-	case VCS1:
-		return GEN9_MFX1_MOCS(index);
-	case VCS2:
-		return GEN11_MFX2_MOCS(index);
-	default:
-		MISSING_CASE(engine->id);
-		return INVALID_MMIO_REG;
-	}
-}
-
 /*
  * Get control_value from MOCS entry taking into account when it's not used:
  * I915_MOCS_PTE's value is returned in this case.
@@ -357,29 +336,47 @@ static i915_reg_t mocs_register(const struct intel_engine_cs *engine, int index)
 static u32 get_entry_control(const struct drm_i915_mocs_table *table,
 			     unsigned int index)
 {
-	if (table->table[index].used)
+	if (index < table->size && table->table[index].used)
 		return table->table[index].control_value;
 
 	return table->table[I915_MOCS_PTE].control_value;
 }
 
-static void init_mocs_table(struct intel_engine_cs *engine,
-			    const struct drm_i915_mocs_table *table)
+#define for_each_mocs(mocs, t, i) \
+	for (i = 0; \
+	     i < (t)->n_entries ? (mocs = get_entry_control((t), i)), 1 : 0;\
+	     i++)
+
+static void __init_mocs_table(struct intel_uncore *uncore,
+			      const struct drm_i915_mocs_table *table,
+			      u32 addr)
 {
-	struct intel_uncore *uncore = engine->uncore;
-	u32 unused_value = table->table[I915_MOCS_PTE].control_value;
 	unsigned int i;
+	u32 mocs;
 
-	for (i = 0; i < table->size; i++)
-		intel_uncore_write_fw(uncore,
-				      mocs_register(engine, i),
-				      get_entry_control(table, i));
+	for_each_mocs(mocs, table, i)
+		intel_uncore_write_fw(uncore, _MMIO(addr + i * 4), mocs);
+}
+
+static u32 mocs_offset(const struct intel_engine_cs *engine)
+{
+	static const u32 offset[] = {
+		[RCS0]  =  __GEN9_RCS0_MOCS0,
+		[VCS0]  =  __GEN9_VCS0_MOCS0,
+		[VCS1]  =  __GEN9_VCS1_MOCS0,
+		[VECS0] =  __GEN9_VECS0_MOCS0,
+		[BCS0]  =  __GEN9_BCS0_MOCS0,
+		[VCS2]  = __GEN11_VCS2_MOCS0,
+	};
+
+	GEM_BUG_ON(engine->id >= ARRAY_SIZE(offset));
+	return offset[engine->id];
+}
 
-	/* All remaining entries are unused */
-	for (; i < table->n_entries; i++)
-		intel_uncore_write_fw(uncore,
-				      mocs_register(engine, i),
-				      unused_value);
+static void init_mocs_table(struct intel_engine_cs *engine,
+			    const struct drm_i915_mocs_table *table)
+{
+	__init_mocs_table(engine->uncore, table, mocs_offset(engine));
 }
 
 /*
@@ -389,7 +386,7 @@ static void init_mocs_table(struct intel_engine_cs *engine,
 static u16 get_entry_l3cc(const struct drm_i915_mocs_table *table,
 			  unsigned int index)
 {
-	if (table->table[index].used)
+	if (index < table->size && table->table[index].used)
 		return table->table[index].l3cc_value;
 
 	return table->table[I915_MOCS_PTE].l3cc_value;
@@ -400,37 +397,23 @@ static inline u32 l3cc_combine(u16 low, u16 high)
 	return low | (u32)high << 16;
 }
 
+#define for_each_l3cc(l3cc, t, i) \
+	for (i = 0; \
+	     i < ((t)->n_entries + 1) / 2 ? \
+	     (l3cc = l3cc_combine(get_entry_l3cc((t), 2 * i), \
+				  get_entry_l3cc((t), 2 * i + 1))), 1 : \
+	     0; \
+	     i++)
+
 static void init_l3cc_table(struct intel_engine_cs *engine,
 			    const struct drm_i915_mocs_table *table)
 {
 	struct intel_uncore *uncore = engine->uncore;
-	u16 unused_value = table->table[I915_MOCS_PTE].l3cc_value;
 	unsigned int i;
+	u32 l3cc;
 
-	for (i = 0; i < table->size / 2; i++) {
-		u16 low = get_entry_l3cc(table, 2 * i);
-		u16 high = get_entry_l3cc(table, 2 * i + 1);
-
-		intel_uncore_write(uncore,
-				   GEN9_LNCFCMOCS(i),
-				   l3cc_combine(low, high));
-	}
-
-	/* Odd table size - 1 left over */
-	if (table->size & 1) {
-		u16 low = get_entry_l3cc(table, 2 * i);
-
-		intel_uncore_write(uncore,
-				   GEN9_LNCFCMOCS(i),
-				   l3cc_combine(low, unused_value));
-		i++;
-	}
-
-	/* All remaining entries are also unused */
-	for (; i < table->n_entries / 2; i++)
-		intel_uncore_write(uncore,
-				   GEN9_LNCFCMOCS(i),
-				   l3cc_combine(unused_value, unused_value));
+	for_each_l3cc(l3cc, table, i)
+		intel_uncore_write_fw(uncore, GEN9_LNCFCMOCS(i), l3cc);
 }
 
 void intel_mocs_init_engine(struct intel_engine_cs *engine)
@@ -451,11 +434,14 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
 		init_l3cc_table(engine, &table);
 }
 
-static void intel_mocs_init_global(struct intel_gt *gt)
+static u32 global_mocs_offset(void)
+{
+	return i915_mmio_reg_offset(GEN12_GLOBAL_MOCS(0));
+}
+
+static void init_global_mocs(struct intel_gt *gt)
 {
-	struct intel_uncore *uncore = gt->uncore;
 	struct drm_i915_mocs_table table;
-	unsigned int index;
 
 	/*
 	 * LLC and eDRAM control values are not applicable to dgfx
@@ -463,29 +449,14 @@ static void intel_mocs_init_global(struct intel_gt *gt)
 	if (IS_DGFX(gt->i915))
 		return;
 
-	GEM_BUG_ON(!HAS_GLOBAL_MOCS_REGISTERS(gt->i915));
-
 	if (!get_mocs_settings(gt->i915, &table))
 		return;
 
-	for (index = 0; index < table.size; index++)
-		intel_uncore_write(uncore,
-				   GEN12_GLOBAL_MOCS(index),
-				   table.table[index].control_value);
-
-	/*
-	 * Ok, now set the unused entries to the invalid entry (index 0). These
-	 * entries are officially undefined and no contract for the contents and
-	 * settings is given for these entries.
-	 */
-	for (; index < table.n_entries; index++)
-		intel_uncore_write(uncore,
-				   GEN12_GLOBAL_MOCS(index),
-				   table.table[I915_MOCS_PTE].control_value);
+	__init_mocs_table(gt->uncore, &table, global_mocs_offset());
 }
 
 void intel_mocs_init(struct intel_gt *gt)
 {
 	if (HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
-		intel_mocs_init_global(gt);
+		init_global_mocs(gt);
 }
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2ffcc21670b7..0960ea0b5a66 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11688,13 +11688,18 @@ enum skl_power_gate {
 /* MOCS (Memory Object Control State) registers */
 #define GEN9_LNCFCMOCS(i)	_MMIO(0xb020 + (i) * 4)	/* L3 Cache Control */
 
-#define GEN9_GFX_MOCS(i)	_MMIO(0xc800 + (i) * 4)	/* Graphics MOCS registers */
-#define GEN9_MFX0_MOCS(i)	_MMIO(0xc900 + (i) * 4)	/* Media 0 MOCS registers */
-#define GEN9_MFX1_MOCS(i)	_MMIO(0xca00 + (i) * 4)	/* Media 1 MOCS registers */
-#define GEN9_VEBOX_MOCS(i)	_MMIO(0xcb00 + (i) * 4)	/* Video MOCS registers */
-#define GEN9_BLT_MOCS(i)	_MMIO(0xcc00 + (i) * 4)	/* Blitter MOCS registers */
-/* Media decoder 2 MOCS registers */
-#define GEN11_MFX2_MOCS(i)	_MMIO(0x10000 + (i) * 4)
+#define __GEN9_RCS0_MOCS0	0xc800
+#define GEN9_GFX_MOCS(i)	_MMIO(__GEN9_RCS0_MOCS0 + (i) * 4)
+#define __GEN9_VCS0_MOCS0	0xc900
+#define GEN9_MFX0_MOCS(i)	_MMIO(__GEN9_VCS0_MOCS0 + (i) * 4)
+#define __GEN9_VCS1_MOCS0	0xca00
+#define GEN9_MFX1_MOCS(i)	_MMIO(__GEN9_VCS1_MOCS0 + (i) * 4)
+#define __GEN9_VECS0_MOCS0	0xcb00
+#define GEN9_VEBOX_MOCS(i)	_MMIO(__GEN9_VECS0_MOCS0 + (i) * 4)
+#define __GEN9_BCS0_MOCS0	0xcc00
+#define GEN9_BLT_MOCS(i)	_MMIO(__GEN9_BCS0_MOCS0 + (i) * 4)
+#define __GEN11_VCS2_MOCS0	0x10000
+#define GEN11_MFX2_MOCS(i)	_MMIO(__GEN11_VCS2_MOCS0 + (i) * 4)
 
 #define GEN10_SCRATCH_LNCF2		_MMIO(0xb0a0)
 #define   PMFLUSHDONE_LNICRSDROP	(1 << 20)
-- 
2.24.0

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[PATCH 4/4] drm/i915/selftests: Add coverage of mocs registers

[Chris Wilson]

Probe the mocs registers for new contexts and across GPU resets. Similar
to intel_workarounds, we have tables of what register values we expect
to see, so verify that user contexts are affected by them. In the
future, we should add tests similar to intel_sseu to cover dynamic
reconfigurations.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_mocs.c          |   4 +
 drivers/gpu/drm/i915/gt/selftest_mocs.c       | 419 ++++++++++++++++++
 .../drm/i915/selftests/i915_live_selftests.h  |   1 +
 3 files changed, 424 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/gt/selftest_mocs.c

diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 47d16a242183..7f292aacaa81 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -460,3 +460,7 @@ void intel_mocs_init(struct intel_gt *gt)
 	if (HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
 		init_global_mocs(gt);
 }
+
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftest_mocs.c"
+#endif
diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c
new file mode 100644
index 000000000000..a34d4fb52fa1
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c
@@ -0,0 +1,419 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "gt/intel_engine_pm.h"
+#include "i915_selftest.h"
+
+#include "gem/selftests/mock_context.h"
+#include "selftests/igt_reset.h"
+#include "selftests/igt_spinner.h"
+
+struct live_mocs {
+	struct drm_i915_mocs_table table;
+	struct i915_vma *scratch;
+	void *vaddr;
+};
+
+static int request_add_sync(struct i915_request *rq, int err)
+{
+	i915_request_get(rq);
+	i915_request_add(rq);
+	if (i915_request_wait(rq, 0, HZ / 5) < 0)
+		err = -ETIME;
+	i915_request_put(rq);
+
+	return err;
+}
+
+static int request_add_spin(struct i915_request *rq, struct igt_spinner *spin)
+{
+	int err = 0;
+
+	i915_request_get(rq);
+	i915_request_add(rq);
+	if (spin && !igt_wait_for_spinner(spin, rq))
+		err = -ETIME;
+	i915_request_put(rq);
+
+	return err;
+}
+
+static struct i915_vma *create_scratch(struct intel_gt *gt)
+{
+	struct drm_i915_gem_object *obj;
+	struct i915_vma *vma;
+	int err;
+
+	obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE);
+	if (IS_ERR(obj))
+		return ERR_CAST(obj);
+
+	i915_gem_object_set_cache_coherency(obj, I915_CACHING_CACHED);
+
+	vma = i915_vma_instance(obj, &gt->ggtt->vm, NULL);
+	if (IS_ERR(vma)) {
+		i915_gem_object_put(obj);
+		return vma;
+	}
+
+	err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL);
+	if (err) {
+		i915_gem_object_put(obj);
+		return ERR_PTR(err);
+	}
+
+	return vma;
+}
+
+static int live_mocs_init(struct live_mocs *arg, struct intel_gt *gt)
+{
+	int err;
+
+	if (!get_mocs_settings(gt->i915, &arg->table))
+		return -EINVAL;
+
+	arg->scratch = create_scratch(gt);
+	if (IS_ERR(arg->scratch))
+		return PTR_ERR(arg->scratch);
+
+	arg->vaddr = i915_gem_object_pin_map(arg->scratch->obj, I915_MAP_WB);
+	if (IS_ERR(arg->vaddr)) {
+		err = PTR_ERR(arg->vaddr);
+		goto err_scratch;
+	}
+
+	return 0;
+
+err_scratch:
+	i915_vma_unpin_and_release(&arg->scratch, 0);
+	return err;
+}
+
+static void live_mocs_fini(struct live_mocs *arg)
+{
+	i915_vma_unpin_and_release(&arg->scratch, I915_VMA_RELEASE_MAP);
+}
+
+static int read_regs(struct i915_request *rq,
+		     u32 addr, unsigned int count,
+		     uint32_t *offset)
+{
+	unsigned int i;
+	u32 *cs;
+
+	GEM_BUG_ON(!IS_ALIGNED(*offset, sizeof(u32)));
+
+	cs = intel_ring_begin(rq, 4 * count);
+	if (IS_ERR(cs))
+		return PTR_ERR(cs);
+
+	for (i = 0; i < count; i++) {
+		*cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
+		*cs++ = addr;
+		*cs++ = *offset;
+		*cs++ = 0;
+
+		addr += sizeof(u32);
+		*offset += sizeof(u32);
+	}
+
+	intel_ring_advance(rq, cs);
+
+	return 0;
+}
+
+static int read_mocs_table(struct i915_request *rq,
+			   const struct drm_i915_mocs_table *table,
+			   uint32_t *offset)
+{
+	u32 addr;
+
+	if (HAS_GLOBAL_MOCS_REGISTERS(rq->i915))
+		addr = global_mocs_offset();
+	else
+		addr = mocs_offset(rq->engine);
+
+	return read_regs(rq, addr, table->n_entries, offset);
+}
+
+static int read_l3cc_table(struct i915_request *rq,
+			   const struct drm_i915_mocs_table *table,
+			   uint32_t *offset)
+{
+	u32 addr = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0));
+
+	return read_regs(rq, addr, (table->n_entries + 1) / 2, offset);
+}
+
+static int check_mocs_table(struct intel_engine_cs *engine,
+			    const struct drm_i915_mocs_table *table,
+			    uint32_t **vaddr)
+{
+	unsigned int i;
+	u32 expect;
+
+	for_each_mocs(expect, table, i) {
+		if (**vaddr != expect) {
+			pr_err("%s: Invalid MOCS[%d] entry, found %08x, expected %08x\n",
+			       engine->name, i, **vaddr, expect);
+			return -EINVAL;
+		}
+		++*vaddr;
+	}
+
+	return 0;
+}
+
+static bool mcr_range(struct drm_i915_private *i915, u32 offset)
+{
+	/*
+	 * Registers in this range are affected by the MCR selector
+	 * which only controls CPU initiated MMIO. Routing does not
+	 * work for CS access so we cannot verify them on this path.
+	 */
+	return INTEL_GEN(i915) >= 8 && offset >= 0xb000 && offset <= 0xb4ff;
+}
+
+static int check_l3cc_table(struct intel_engine_cs *engine,
+			    const struct drm_i915_mocs_table *table,
+			    uint32_t **vaddr)
+{
+	/* Can we read the MCR range 0xb00 directly? See intel_workarounds! */
+	u32 reg = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0));
+	unsigned int i;
+	u32 expect;
+
+	for_each_l3cc(expect, table, i) {
+		if (!mcr_range(engine->i915, reg) && **vaddr != expect) {
+			pr_err("%s: Invalid L3CC[%d] entry, found %08x, expected %08x\n",
+			       engine->name, i, **vaddr, expect);
+			return -EINVAL;
+		}
+		++*vaddr;
+		reg += 4;
+	}
+
+	return 0;
+}
+
+static int check_mocs_engine(struct live_mocs *arg,
+			     struct intel_context *ce)
+{
+	struct i915_vma *vma = arg->scratch;
+	struct i915_request *rq;
+	u32 offset;
+	u32 *vaddr;
+	int err;
+
+	memset32(arg->vaddr, STACK_MAGIC, PAGE_SIZE / sizeof(u32));
+
+	rq = intel_context_create_request(ce);
+	if (IS_ERR(rq))
+		return PTR_ERR(rq);
+
+	i915_vma_lock(vma);
+	err = i915_request_await_object(rq, vma->obj, true);
+	if (!err)
+		err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
+	i915_vma_unlock(vma);
+
+	/* Read the mocs tables back using SRM */
+	offset = i915_ggtt_offset(vma);
+	if (!err)
+		err = read_mocs_table(rq, &arg->table, &offset);
+	if (!err && ce->engine->class == RENDER_CLASS)
+		err = read_l3cc_table(rq, &arg->table, &offset);
+	offset -= i915_ggtt_offset(vma);
+	GEM_BUG_ON(offset > PAGE_SIZE);
+
+	err = request_add_sync(rq, err);
+	if (err)
+		return err;
+
+	/* Compare the results against the expected tables */
+	vaddr = arg->vaddr;
+	if (!err)
+		err = check_mocs_table(ce->engine, &arg->table, &vaddr);
+	if (!err && ce->engine->class == RENDER_CLASS)
+		err = check_l3cc_table(ce->engine, &arg->table, &vaddr);
+	if (err)
+		return err;
+
+	GEM_BUG_ON(arg->vaddr + offset != vaddr);
+	return 0;
+}
+
+static int live_mocs_kernel(void *arg)
+{
+	struct intel_gt *gt = arg;
+	struct intel_engine_cs *engine;
+	enum intel_engine_id id;
+	struct live_mocs mocs;
+	int err;
+
+	/* Basic check the system is configured with the expected mocs table */
+
+	err = live_mocs_init(&mocs, gt);
+	if (err)
+		return err;
+
+	for_each_engine(engine, gt, id) {
+		err = check_mocs_engine(&mocs, engine->kernel_context);
+		if (err)
+			break;
+	}
+
+	live_mocs_fini(&mocs);
+	return err;
+}
+
+static int live_mocs_clean(void *arg)
+{
+	struct intel_gt *gt = arg;
+	struct intel_engine_cs *engine;
+	enum intel_engine_id id;
+	struct live_mocs mocs;
+	int err;
+
+	/* Every new context should see the same mocs table */
+
+	err = live_mocs_init(&mocs, gt);
+	if (err)
+		return err;
+
+	for_each_engine(engine, gt, id) {
+		struct intel_context *ce;
+
+		ce = intel_context_create(engine->kernel_context->gem_context,
+					  engine);
+		if (IS_ERR(ce)) {
+			err = PTR_ERR(ce);
+			break;
+		}
+
+		err = check_mocs_engine(&mocs, ce);
+		intel_context_put(ce);
+		if (err)
+			break;
+	}
+
+	live_mocs_fini(&mocs);
+	return err;
+}
+
+static int active_engine_reset(struct intel_context *ce,
+			       const char *reason)
+{
+	struct igt_spinner spin;
+	struct i915_request *rq;
+	int err;
+
+	err = igt_spinner_init(&spin, ce->engine->gt);
+	if (err)
+		return err;
+
+	rq = igt_spinner_create_request(&spin, ce, MI_NOOP);
+	if (IS_ERR(rq)) {
+		igt_spinner_fini(&spin);
+		return PTR_ERR(rq);
+	}
+
+	err = request_add_spin(rq, &spin);
+	if (err == 0)
+		err = intel_engine_reset(ce->engine, reason);
+
+	igt_spinner_end(&spin);
+	igt_spinner_fini(&spin);
+
+	return err;
+}
+
+static int __live_mocs_reset(struct live_mocs *mocs,
+			     struct intel_context *ce)
+{
+	int err;
+
+	err = intel_engine_reset(ce->engine, "mocs");
+	if (err)
+		return err;
+
+	err = check_mocs_engine(mocs, ce);
+	if (err)
+		return err;
+
+	err = active_engine_reset(ce, "mocs");
+	if (err)
+		return err;
+
+	err = check_mocs_engine(mocs, ce);
+	if (err)
+		return err;
+
+	intel_gt_reset(ce->engine->gt, ce->engine->mask, "mocs");
+
+	err = check_mocs_engine(mocs, ce);
+	if (err)
+		return err;
+
+	return 0;
+}
+
+static int live_mocs_reset(void *arg)
+{
+	struct intel_gt *gt = arg;
+	struct intel_engine_cs *engine;
+	enum intel_engine_id id;
+	struct live_mocs mocs;
+	int err = 0;
+
+	/* Check the mocs setup is retained over per-engine and global resets */
+
+	if (!intel_has_reset_engine(gt))
+		return 0;
+
+	err = live_mocs_init(&mocs, gt);
+	if (err)
+		return err;
+
+	igt_global_reset_lock(gt);
+	for_each_engine(engine, gt, id) {
+		struct intel_context *ce;
+
+		ce = intel_context_create(engine->kernel_context->gem_context,
+					  engine);
+		if (IS_ERR(ce)) {
+			err = PTR_ERR(ce);
+			break;
+		}
+
+		intel_engine_pm_get(engine);
+		err = __live_mocs_reset(&mocs, ce);
+		intel_engine_pm_put(engine);
+
+		intel_context_put(ce);
+		if (err)
+			break;
+	}
+	igt_global_reset_unlock(gt);
+
+	live_mocs_fini(&mocs);
+	return err;
+}
+
+int intel_mocs_live_selftests(struct drm_i915_private *i915)
+{
+	static const struct i915_subtest tests[] = {
+		SUBTEST(live_mocs_kernel),
+		SUBTEST(live_mocs_clean),
+		SUBTEST(live_mocs_reset),
+	};
+	struct drm_i915_mocs_table table;
+
+	if (!get_mocs_settings(i915, &table))
+		return 0;
+
+	return intel_gt_live_subtests(tests, &i915->gt);
+}
diff --git a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
index 4b3cac73e291..11b40bc58e6d 100644
--- a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
@@ -16,6 +16,7 @@ selftest(gt_engines, intel_engine_live_selftests)
 selftest(gt_timelines, intel_timeline_live_selftests)
 selftest(gt_contexts, intel_context_live_selftests)
 selftest(gt_lrc, intel_lrc_live_selftests)
+selftest(gt_mocs, intel_mocs_live_selftests)
 selftest(gt_pm, intel_gt_pm_live_selftests)
 selftest(gt_heartbeat, intel_heartbeat_live_selftests)
 selftest(requests, i915_request_live_selftests)
-- 
2.24.0

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[Intel-gfx] [PATCH 4/4] drm/i915/selftests: Add coverage of mocs registers

[Chris Wilson]

Probe the mocs registers for new contexts and across GPU resets. Similar
to intel_workarounds, we have tables of what register values we expect
to see, so verify that user contexts are affected by them. In the
future, we should add tests similar to intel_sseu to cover dynamic
reconfigurations.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_mocs.c          |   4 +
 drivers/gpu/drm/i915/gt/selftest_mocs.c       | 419 ++++++++++++++++++
 .../drm/i915/selftests/i915_live_selftests.h  |   1 +
 3 files changed, 424 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/gt/selftest_mocs.c

diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 47d16a242183..7f292aacaa81 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -460,3 +460,7 @@ void intel_mocs_init(struct intel_gt *gt)
 	if (HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
 		init_global_mocs(gt);
 }
+
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftest_mocs.c"
+#endif
diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c
new file mode 100644
index 000000000000..a34d4fb52fa1
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c
@@ -0,0 +1,419 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "gt/intel_engine_pm.h"
+#include "i915_selftest.h"
+
+#include "gem/selftests/mock_context.h"
+#include "selftests/igt_reset.h"
+#include "selftests/igt_spinner.h"
+
+struct live_mocs {
+	struct drm_i915_mocs_table table;
+	struct i915_vma *scratch;
+	void *vaddr;
+};
+
+static int request_add_sync(struct i915_request *rq, int err)
+{
+	i915_request_get(rq);
+	i915_request_add(rq);
+	if (i915_request_wait(rq, 0, HZ / 5) < 0)
+		err = -ETIME;
+	i915_request_put(rq);
+
+	return err;
+}
+
+static int request_add_spin(struct i915_request *rq, struct igt_spinner *spin)
+{
+	int err = 0;
+
+	i915_request_get(rq);
+	i915_request_add(rq);
+	if (spin && !igt_wait_for_spinner(spin, rq))
+		err = -ETIME;
+	i915_request_put(rq);
+
+	return err;
+}
+
+static struct i915_vma *create_scratch(struct intel_gt *gt)
+{
+	struct drm_i915_gem_object *obj;
+	struct i915_vma *vma;
+	int err;
+
+	obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE);
+	if (IS_ERR(obj))
+		return ERR_CAST(obj);
+
+	i915_gem_object_set_cache_coherency(obj, I915_CACHING_CACHED);
+
+	vma = i915_vma_instance(obj, &gt->ggtt->vm, NULL);
+	if (IS_ERR(vma)) {
+		i915_gem_object_put(obj);
+		return vma;
+	}
+
+	err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL);
+	if (err) {
+		i915_gem_object_put(obj);
+		return ERR_PTR(err);
+	}
+
+	return vma;
+}
+
+static int live_mocs_init(struct live_mocs *arg, struct intel_gt *gt)
+{
+	int err;
+
+	if (!get_mocs_settings(gt->i915, &arg->table))
+		return -EINVAL;
+
+	arg->scratch = create_scratch(gt);
+	if (IS_ERR(arg->scratch))
+		return PTR_ERR(arg->scratch);
+
+	arg->vaddr = i915_gem_object_pin_map(arg->scratch->obj, I915_MAP_WB);
+	if (IS_ERR(arg->vaddr)) {
+		err = PTR_ERR(arg->vaddr);
+		goto err_scratch;
+	}
+
+	return 0;
+
+err_scratch:
+	i915_vma_unpin_and_release(&arg->scratch, 0);
+	return err;
+}
+
+static void live_mocs_fini(struct live_mocs *arg)
+{
+	i915_vma_unpin_and_release(&arg->scratch, I915_VMA_RELEASE_MAP);
+}
+
+static int read_regs(struct i915_request *rq,
+		     u32 addr, unsigned int count,
+		     uint32_t *offset)
+{
+	unsigned int i;
+	u32 *cs;
+
+	GEM_BUG_ON(!IS_ALIGNED(*offset, sizeof(u32)));
+
+	cs = intel_ring_begin(rq, 4 * count);
+	if (IS_ERR(cs))
+		return PTR_ERR(cs);
+
+	for (i = 0; i < count; i++) {
+		*cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
+		*cs++ = addr;
+		*cs++ = *offset;
+		*cs++ = 0;
+
+		addr += sizeof(u32);
+		*offset += sizeof(u32);
+	}
+
+	intel_ring_advance(rq, cs);
+
+	return 0;
+}
+
+static int read_mocs_table(struct i915_request *rq,
+			   const struct drm_i915_mocs_table *table,
+			   uint32_t *offset)
+{
+	u32 addr;
+
+	if (HAS_GLOBAL_MOCS_REGISTERS(rq->i915))
+		addr = global_mocs_offset();
+	else
+		addr = mocs_offset(rq->engine);
+
+	return read_regs(rq, addr, table->n_entries, offset);
+}
+
+static int read_l3cc_table(struct i915_request *rq,
+			   const struct drm_i915_mocs_table *table,
+			   uint32_t *offset)
+{
+	u32 addr = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0));
+
+	return read_regs(rq, addr, (table->n_entries + 1) / 2, offset);
+}
+
+static int check_mocs_table(struct intel_engine_cs *engine,
+			    const struct drm_i915_mocs_table *table,
+			    uint32_t **vaddr)
+{
+	unsigned int i;
+	u32 expect;
+
+	for_each_mocs(expect, table, i) {
+		if (**vaddr != expect) {
+			pr_err("%s: Invalid MOCS[%d] entry, found %08x, expected %08x\n",
+			       engine->name, i, **vaddr, expect);
+			return -EINVAL;
+		}
+		++*vaddr;
+	}
+
+	return 0;
+}
+
+static bool mcr_range(struct drm_i915_private *i915, u32 offset)
+{
+	/*
+	 * Registers in this range are affected by the MCR selector
+	 * which only controls CPU initiated MMIO. Routing does not
+	 * work for CS access so we cannot verify them on this path.
+	 */
+	return INTEL_GEN(i915) >= 8 && offset >= 0xb000 && offset <= 0xb4ff;
+}
+
+static int check_l3cc_table(struct intel_engine_cs *engine,
+			    const struct drm_i915_mocs_table *table,
+			    uint32_t **vaddr)
+{
+	/* Can we read the MCR range 0xb00 directly? See intel_workarounds! */
+	u32 reg = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0));
+	unsigned int i;
+	u32 expect;
+
+	for_each_l3cc(expect, table, i) {
+		if (!mcr_range(engine->i915, reg) && **vaddr != expect) {
+			pr_err("%s: Invalid L3CC[%d] entry, found %08x, expected %08x\n",
+			       engine->name, i, **vaddr, expect);
+			return -EINVAL;
+		}
+		++*vaddr;
+		reg += 4;
+	}
+
+	return 0;
+}
+
+static int check_mocs_engine(struct live_mocs *arg,
+			     struct intel_context *ce)
+{
+	struct i915_vma *vma = arg->scratch;
+	struct i915_request *rq;
+	u32 offset;
+	u32 *vaddr;
+	int err;
+
+	memset32(arg->vaddr, STACK_MAGIC, PAGE_SIZE / sizeof(u32));
+
+	rq = intel_context_create_request(ce);
+	if (IS_ERR(rq))
+		return PTR_ERR(rq);
+
+	i915_vma_lock(vma);
+	err = i915_request_await_object(rq, vma->obj, true);
+	if (!err)
+		err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
+	i915_vma_unlock(vma);
+
+	/* Read the mocs tables back using SRM */
+	offset = i915_ggtt_offset(vma);
+	if (!err)
+		err = read_mocs_table(rq, &arg->table, &offset);
+	if (!err && ce->engine->class == RENDER_CLASS)
+		err = read_l3cc_table(rq, &arg->table, &offset);
+	offset -= i915_ggtt_offset(vma);
+	GEM_BUG_ON(offset > PAGE_SIZE);
+
+	err = request_add_sync(rq, err);
+	if (err)
+		return err;
+
+	/* Compare the results against the expected tables */
+	vaddr = arg->vaddr;
+	if (!err)
+		err = check_mocs_table(ce->engine, &arg->table, &vaddr);
+	if (!err && ce->engine->class == RENDER_CLASS)
+		err = check_l3cc_table(ce->engine, &arg->table, &vaddr);
+	if (err)
+		return err;
+
+	GEM_BUG_ON(arg->vaddr + offset != vaddr);
+	return 0;
+}
+
+static int live_mocs_kernel(void *arg)
+{
+	struct intel_gt *gt = arg;
+	struct intel_engine_cs *engine;
+	enum intel_engine_id id;
+	struct live_mocs mocs;
+	int err;
+
+	/* Basic check the system is configured with the expected mocs table */
+
+	err = live_mocs_init(&mocs, gt);
+	if (err)
+		return err;
+
+	for_each_engine(engine, gt, id) {
+		err = check_mocs_engine(&mocs, engine->kernel_context);
+		if (err)
+			break;
+	}
+
+	live_mocs_fini(&mocs);
+	return err;
+}
+
+static int live_mocs_clean(void *arg)
+{
+	struct intel_gt *gt = arg;
+	struct intel_engine_cs *engine;
+	enum intel_engine_id id;
+	struct live_mocs mocs;
+	int err;
+
+	/* Every new context should see the same mocs table */
+
+	err = live_mocs_init(&mocs, gt);
+	if (err)
+		return err;
+
+	for_each_engine(engine, gt, id) {
+		struct intel_context *ce;
+
+		ce = intel_context_create(engine->kernel_context->gem_context,
+					  engine);
+		if (IS_ERR(ce)) {
+			err = PTR_ERR(ce);
+			break;
+		}
+
+		err = check_mocs_engine(&mocs, ce);
+		intel_context_put(ce);
+		if (err)
+			break;
+	}
+
+	live_mocs_fini(&mocs);
+	return err;
+}
+
+static int active_engine_reset(struct intel_context *ce,
+			       const char *reason)
+{
+	struct igt_spinner spin;
+	struct i915_request *rq;
+	int err;
+
+	err = igt_spinner_init(&spin, ce->engine->gt);
+	if (err)
+		return err;
+
+	rq = igt_spinner_create_request(&spin, ce, MI_NOOP);
+	if (IS_ERR(rq)) {
+		igt_spinner_fini(&spin);
+		return PTR_ERR(rq);
+	}
+
+	err = request_add_spin(rq, &spin);
+	if (err == 0)
+		err = intel_engine_reset(ce->engine, reason);
+
+	igt_spinner_end(&spin);
+	igt_spinner_fini(&spin);
+
+	return err;
+}
+
+static int __live_mocs_reset(struct live_mocs *mocs,
+			     struct intel_context *ce)
+{
+	int err;
+
+	err = intel_engine_reset(ce->engine, "mocs");
+	if (err)
+		return err;
+
+	err = check_mocs_engine(mocs, ce);
+	if (err)
+		return err;
+
+	err = active_engine_reset(ce, "mocs");
+	if (err)
+		return err;
+
+	err = check_mocs_engine(mocs, ce);
+	if (err)
+		return err;
+
+	intel_gt_reset(ce->engine->gt, ce->engine->mask, "mocs");
+
+	err = check_mocs_engine(mocs, ce);
+	if (err)
+		return err;
+
+	return 0;
+}
+
+static int live_mocs_reset(void *arg)
+{
+	struct intel_gt *gt = arg;
+	struct intel_engine_cs *engine;
+	enum intel_engine_id id;
+	struct live_mocs mocs;
+	int err = 0;
+
+	/* Check the mocs setup is retained over per-engine and global resets */
+
+	if (!intel_has_reset_engine(gt))
+		return 0;
+
+	err = live_mocs_init(&mocs, gt);
+	if (err)
+		return err;
+
+	igt_global_reset_lock(gt);
+	for_each_engine(engine, gt, id) {
+		struct intel_context *ce;
+
+		ce = intel_context_create(engine->kernel_context->gem_context,
+					  engine);
+		if (IS_ERR(ce)) {
+			err = PTR_ERR(ce);
+			break;
+		}
+
+		intel_engine_pm_get(engine);
+		err = __live_mocs_reset(&mocs, ce);
+		intel_engine_pm_put(engine);
+
+		intel_context_put(ce);
+		if (err)
+			break;
+	}
+	igt_global_reset_unlock(gt);
+
+	live_mocs_fini(&mocs);
+	return err;
+}
+
+int intel_mocs_live_selftests(struct drm_i915_private *i915)
+{
+	static const struct i915_subtest tests[] = {
+		SUBTEST(live_mocs_kernel),
+		SUBTEST(live_mocs_clean),
+		SUBTEST(live_mocs_reset),
+	};
+	struct drm_i915_mocs_table table;
+
+	if (!get_mocs_settings(i915, &table))
+		return 0;
+
+	return intel_gt_live_subtests(tests, &i915->gt);
+}
diff --git a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
index 4b3cac73e291..11b40bc58e6d 100644
--- a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
@@ -16,6 +16,7 @@ selftest(gt_engines, intel_engine_live_selftests)
 selftest(gt_timelines, intel_timeline_live_selftests)
 selftest(gt_contexts, intel_context_live_selftests)
 selftest(gt_lrc, intel_lrc_live_selftests)
+selftest(gt_mocs, intel_mocs_live_selftests)
 selftest(gt_pm, intel_gt_pm_live_selftests)
 selftest(gt_heartbeat, intel_heartbeat_live_selftests)
 selftest(requests, i915_request_live_selftests)
-- 
2.24.0

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✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915/gt: Set unused mocs entry to follow PTE on tgl as on all others

[Patchwork]

== Series Details ==

Series: series starting with [1/4] drm/i915/gt: Set unused mocs entry to follow PTE on tgl as on all others
URL   : https://patchwork.freedesktop.org/series/69382/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
3876af3a2069 drm/i915/gt: Set unused mocs entry to follow PTE on tgl as on all others
32b7d4b60407 drm/i915/gt: Tidy up debug-warns for the mocs control table
726603472df5 drm/i915/gt: Refactor mocs loops into single control macro
-:66: CHECK:MACRO_ARG_REUSE: Macro argument reuse 't' - possible side-effects?
#66: FILE: drivers/gpu/drm/i915/gt/intel_mocs.c:345:
+#define for_each_mocs(mocs, t, i) \
+	for (i = 0; \
+	     i < (t)->n_entries ? (mocs = get_entry_control((t), i)), 1 : 0;\
+	     i++)

-:66: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i' - possible side-effects?
#66: FILE: drivers/gpu/drm/i915/gt/intel_mocs.c:345:
+#define for_each_mocs(mocs, t, i) \
+	for (i = 0; \
+	     i < (t)->n_entries ? (mocs = get_entry_control((t), i)), 1 : 0;\
+	     i++)

-:128: CHECK:MACRO_ARG_REUSE: Macro argument reuse 't' - possible side-effects?
#128: FILE: drivers/gpu/drm/i915/gt/intel_mocs.c:400:
+#define for_each_l3cc(l3cc, t, i) \
+	for (i = 0; \
+	     i < ((t)->n_entries + 1) / 2 ? \
+	     (l3cc = l3cc_combine(get_entry_l3cc((t), 2 * i), \
+				  get_entry_l3cc((t), 2 * i + 1))), 1 : \
+	     0; \
+	     i++)

-:128: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i' - possible side-effects?
#128: FILE: drivers/gpu/drm/i915/gt/intel_mocs.c:400:
+#define for_each_l3cc(l3cc, t, i) \
+	for (i = 0; \
+	     i < ((t)->n_entries + 1) / 2 ? \
+	     (l3cc = l3cc_combine(get_entry_l3cc((t), 2 * i), \
+				  get_entry_l3cc((t), 2 * i + 1))), 1 : \
+	     0; \
+	     i++)

total: 0 errors, 0 warnings, 4 checks, 217 lines checked
eb1c77834cff drm/i915/selftests: Add coverage of mocs registers
-:30: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#30: 
new file mode 100644

-:35: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#35: FILE: drivers/gpu/drm/i915/gt/selftest_mocs.c:1:
+/*

-:36: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead
#36: FILE: drivers/gpu/drm/i915/gt/selftest_mocs.c:2:
+ * SPDX-License-Identifier: MIT

total: 0 errors, 3 warnings, 0 checks, 433 lines checked

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915/gt: Set unused mocs entry to follow PTE on tgl as on all others

[Patchwork]

== Series Details ==

Series: series starting with [1/4] drm/i915/gt: Set unused mocs entry to follow PTE on tgl as on all others
URL   : https://patchwork.freedesktop.org/series/69382/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
3876af3a2069 drm/i915/gt: Set unused mocs entry to follow PTE on tgl as on all others
32b7d4b60407 drm/i915/gt: Tidy up debug-warns for the mocs control table
726603472df5 drm/i915/gt: Refactor mocs loops into single control macro
-:66: CHECK:MACRO_ARG_REUSE: Macro argument reuse 't' - possible side-effects?
#66: FILE: drivers/gpu/drm/i915/gt/intel_mocs.c:345:
+#define for_each_mocs(mocs, t, i) \
+	for (i = 0; \
+	     i < (t)->n_entries ? (mocs = get_entry_control((t), i)), 1 : 0;\
+	     i++)

-:66: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i' - possible side-effects?
#66: FILE: drivers/gpu/drm/i915/gt/intel_mocs.c:345:
+#define for_each_mocs(mocs, t, i) \
+	for (i = 0; \
+	     i < (t)->n_entries ? (mocs = get_entry_control((t), i)), 1 : 0;\
+	     i++)

-:128: CHECK:MACRO_ARG_REUSE: Macro argument reuse 't' - possible side-effects?
#128: FILE: drivers/gpu/drm/i915/gt/intel_mocs.c:400:
+#define for_each_l3cc(l3cc, t, i) \
+	for (i = 0; \
+	     i < ((t)->n_entries + 1) / 2 ? \
+	     (l3cc = l3cc_combine(get_entry_l3cc((t), 2 * i), \
+				  get_entry_l3cc((t), 2 * i + 1))), 1 : \
+	     0; \
+	     i++)

-:128: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i' - possible side-effects?
#128: FILE: drivers/gpu/drm/i915/gt/intel_mocs.c:400:
+#define for_each_l3cc(l3cc, t, i) \
+	for (i = 0; \
+	     i < ((t)->n_entries + 1) / 2 ? \
+	     (l3cc = l3cc_combine(get_entry_l3cc((t), 2 * i), \
+				  get_entry_l3cc((t), 2 * i + 1))), 1 : \
+	     0; \
+	     i++)

total: 0 errors, 0 warnings, 4 checks, 217 lines checked
eb1c77834cff drm/i915/selftests: Add coverage of mocs registers
-:30: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#30: 
new file mode 100644

-:35: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#35: FILE: drivers/gpu/drm/i915/gt/selftest_mocs.c:1:
+/*

-:36: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead
#36: FILE: drivers/gpu/drm/i915/gt/selftest_mocs.c:2:
+ * SPDX-License-Identifier: MIT

total: 0 errors, 3 warnings, 0 checks, 433 lines checked

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915/gt: Set unused mocs entry to follow PTE on tgl as on all others

[Patchwork]

== Series Details ==

Series: series starting with [1/4] drm/i915/gt: Set unused mocs entry to follow PTE on tgl as on all others
URL   : https://patchwork.freedesktop.org/series/69382/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7323 -> Patchwork_15244
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/index.html

New tests
---------

  New tests have been introduced between CI_DRM_7323 and Patchwork_15244:

### New IGT tests (1) ###

  * igt@i915_selftest@live_gt_mocs:
    - Statuses : 42 pass(s)
    - Exec time: [0.43, 2.95] s

  

Known issues
------------

  Here are the changes found in Patchwork_15244 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live_blt:
    - fi-bsw-n3050:       [PASS][1] -> [DMESG-FAIL][2] ([fdo#112176])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/fi-bsw-n3050/igt@i915_selftest@live_blt.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/fi-bsw-n3050/igt@i915_selftest@live_blt.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - fi-skl-6770hq:      [PASS][3] -> [WARN][4] ([fdo#112252])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/fi-skl-6770hq/igt@kms_setmode@basic-clone-single-crtc.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/fi-skl-6770hq/igt@kms_setmode@basic-clone-single-crtc.html

  
#### Possible fixes ####

  * igt@gem_mmap_gtt@basic-copy:
    - fi-glk-dsi:         [INCOMPLETE][5] ([fdo#103359] / [k.org#198133]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/fi-glk-dsi/igt@gem_mmap_gtt@basic-copy.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/fi-glk-dsi/igt@gem_mmap_gtt@basic-copy.html

  * igt@kms_flip@basic-flip-vs-wf_vblank:
    - fi-skl-6770hq:      [DMESG-WARN][7] ([fdo#105541]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/fi-skl-6770hq/igt@kms_flip@basic-flip-vs-wf_vblank.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/fi-skl-6770hq/igt@kms_flip@basic-flip-vs-wf_vblank.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
  [fdo#105541]: https://bugs.freedesktop.org/show_bug.cgi?id=105541
  [fdo#109964]: https://bugs.freedesktop.org/show_bug.cgi?id=109964
  [fdo#110343]: https://bugs.freedesktop.org/show_bug.cgi?id=110343
  [fdo#112176]: https://bugs.freedesktop.org/show_bug.cgi?id=112176
  [fdo#112252]: https://bugs.freedesktop.org/show_bug.cgi?id=112252
  [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133


Participating hosts (51 -> 46)
------------------------------

  Missing    (5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7323 -> Patchwork_15244

  CI-20190529: 20190529
  CI_DRM_7323: aac244f23bf1eaf986c5df9e529863b34e52bee8 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5273: 602003c3d751c72fc309a0e64d4193f6da720f6b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15244: eb1c77834cff62bf68581e3a84d88231eab4c5a4 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

eb1c77834cff drm/i915/selftests: Add coverage of mocs registers
726603472df5 drm/i915/gt: Refactor mocs loops into single control macro
32b7d4b60407 drm/i915/gt: Tidy up debug-warns for the mocs control table
3876af3a2069 drm/i915/gt: Set unused mocs entry to follow PTE on tgl as on all others

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915/gt: Set unused mocs entry to follow PTE on tgl as on all others

[Patchwork]

== Series Details ==

Series: series starting with [1/4] drm/i915/gt: Set unused mocs entry to follow PTE on tgl as on all others
URL   : https://patchwork.freedesktop.org/series/69382/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7323 -> Patchwork_15244
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/index.html

New tests
---------

  New tests have been introduced between CI_DRM_7323 and Patchwork_15244:

### New IGT tests (1) ###

  * igt@i915_selftest@live_gt_mocs:
    - Statuses : 42 pass(s)
    - Exec time: [0.43, 2.95] s

  

Known issues
------------

  Here are the changes found in Patchwork_15244 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live_blt:
    - fi-bsw-n3050:       [PASS][1] -> [DMESG-FAIL][2] ([fdo#112176])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/fi-bsw-n3050/igt@i915_selftest@live_blt.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/fi-bsw-n3050/igt@i915_selftest@live_blt.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - fi-skl-6770hq:      [PASS][3] -> [WARN][4] ([fdo#112252])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/fi-skl-6770hq/igt@kms_setmode@basic-clone-single-crtc.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/fi-skl-6770hq/igt@kms_setmode@basic-clone-single-crtc.html

  
#### Possible fixes ####

  * igt@gem_mmap_gtt@basic-copy:
    - fi-glk-dsi:         [INCOMPLETE][5] ([fdo#103359] / [k.org#198133]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/fi-glk-dsi/igt@gem_mmap_gtt@basic-copy.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/fi-glk-dsi/igt@gem_mmap_gtt@basic-copy.html

  * igt@kms_flip@basic-flip-vs-wf_vblank:
    - fi-skl-6770hq:      [DMESG-WARN][7] ([fdo#105541]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/fi-skl-6770hq/igt@kms_flip@basic-flip-vs-wf_vblank.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/fi-skl-6770hq/igt@kms_flip@basic-flip-vs-wf_vblank.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
  [fdo#105541]: https://bugs.freedesktop.org/show_bug.cgi?id=105541
  [fdo#109964]: https://bugs.freedesktop.org/show_bug.cgi?id=109964
  [fdo#110343]: https://bugs.freedesktop.org/show_bug.cgi?id=110343
  [fdo#112176]: https://bugs.freedesktop.org/show_bug.cgi?id=112176
  [fdo#112252]: https://bugs.freedesktop.org/show_bug.cgi?id=112252
  [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133


Participating hosts (51 -> 46)
------------------------------

  Missing    (5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7323 -> Patchwork_15244

  CI-20190529: 20190529
  CI_DRM_7323: aac244f23bf1eaf986c5df9e529863b34e52bee8 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5273: 602003c3d751c72fc309a0e64d4193f6da720f6b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15244: eb1c77834cff62bf68581e3a84d88231eab4c5a4 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

eb1c77834cff drm/i915/selftests: Add coverage of mocs registers
726603472df5 drm/i915/gt: Refactor mocs loops into single control macro
32b7d4b60407 drm/i915/gt: Tidy up debug-warns for the mocs control table
3876af3a2069 drm/i915/gt: Set unused mocs entry to follow PTE on tgl as on all others

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.IGT: success for series starting with [1/4] drm/i915/gt: Set unused mocs entry to follow PTE on tgl as on all others

[Patchwork]

== Series Details ==

Series: series starting with [1/4] drm/i915/gt: Set unused mocs entry to follow PTE on tgl as on all others
URL   : https://patchwork.freedesktop.org/series/69382/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7323_full -> Patchwork_15244_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

New tests
---------

  New tests have been introduced between CI_DRM_7323_full and Patchwork_15244_full:

### New IGT tests (1) ###

  * igt@i915_selftest@live_gt_mocs:
    - Statuses : 8 pass(s)
    - Exec time: [0.29, 4.11] s

  

Known issues
------------

  Here are the changes found in Patchwork_15244_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_isolation@vcs1-dirty-create:
    - shard-iclb:         [PASS][1] -> [SKIP][2] ([fdo#109276] / [fdo#112080]) +3 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb2/igt@gem_ctx_isolation@vcs1-dirty-create.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-iclb6/igt@gem_ctx_isolation@vcs1-dirty-create.html

  * igt@gem_ctx_shared@exec-single-timeline-bsd:
    - shard-iclb:         [PASS][3] -> [SKIP][4] ([fdo#110841])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb5/igt@gem_ctx_shared@exec-single-timeline-bsd.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-iclb1/igt@gem_ctx_shared@exec-single-timeline-bsd.html

  * igt@gem_exec_balancer@smoke:
    - shard-iclb:         [PASS][5] -> [SKIP][6] ([fdo#110854])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb1/igt@gem_exec_balancer@smoke.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-iclb7/igt@gem_exec_balancer@smoke.html

  * igt@gem_exec_parallel@vcs1-fds:
    - shard-iclb:         [PASS][7] -> [SKIP][8] ([fdo#112080]) +19 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb1/igt@gem_exec_parallel@vcs1-fds.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-iclb3/igt@gem_exec_parallel@vcs1-fds.html

  * igt@gem_exec_schedule@in-order-bsd:
    - shard-iclb:         [PASS][9] -> [SKIP][10] ([fdo#112146]) +5 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb7/igt@gem_exec_schedule@in-order-bsd.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-iclb4/igt@gem_exec_schedule@in-order-bsd.html

  * igt@gem_persistent_relocs@forked-thrashing:
    - shard-iclb:         [PASS][11] -> [INCOMPLETE][12] ([fdo#107713] / [fdo#109100] / [fdo#112068 ])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb7/igt@gem_persistent_relocs@forked-thrashing.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-iclb4/igt@gem_persistent_relocs@forked-thrashing.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy:
    - shard-hsw:          [PASS][13] -> [DMESG-WARN][14] ([fdo#110789] / [fdo#111870])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-hsw4/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-hsw4/igt@gem_userptr_blits@map-fixed-invalidate-busy.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
    - shard-hsw:          [PASS][15] -> [DMESG-WARN][16] ([fdo#111870])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-hsw4/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-hsw7/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html

  * igt@i915_pm_rc6_residency@rc6-accuracy:
    - shard-snb:          [PASS][17] -> [SKIP][18] ([fdo#109271])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-snb7/igt@i915_pm_rc6_residency@rc6-accuracy.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-snb6/igt@i915_pm_rc6_residency@rc6-accuracy.html

  * igt@i915_pm_rpm@system-suspend:
    - shard-tglb:         [PASS][19] -> [INCOMPLETE][20] ([fdo#111747] / [fdo#111850])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb9/igt@i915_pm_rpm@system-suspend.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-tglb8/igt@i915_pm_rpm@system-suspend.html

  * igt@kms_color@pipe-b-ctm-red-to-blue:
    - shard-skl:          [PASS][21] -> [DMESG-WARN][22] ([fdo#106107])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-skl3/igt@kms_color@pipe-b-ctm-red-to-blue.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-skl3/igt@kms_color@pipe-b-ctm-red-to-blue.html

  * igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen:
    - shard-skl:          [PASS][23] -> [FAIL][24] ([fdo#103232])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-skl5/igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-skl3/igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html

  * igt@kms_cursor_legacy@flip-vs-cursor-toggle:
    - shard-skl:          [PASS][25] -> [FAIL][26] ([fdo#102670] / [fdo#106081])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-skl8/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-kbl:          [PASS][27] -> [FAIL][28] ([fdo#105363])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-kbl3/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-kbl6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-apl:          [PASS][29] -> [DMESG-WARN][30] ([fdo#108566]) +1 similar issue
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt:
    - shard-tglb:         [PASS][31] -> [FAIL][32] ([fdo#103167]) +1 similar issue
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt:
    - shard-iclb:         [PASS][33] -> [FAIL][34] ([fdo#103167]) +6 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt:
    - shard-skl:          [PASS][35] -> [FAIL][36] ([fdo#103167])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-skl5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-skl3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
    - shard-kbl:          [PASS][37] -> [DMESG-WARN][38] ([fdo#108566]) +2 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-kbl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-kbl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
    - shard-skl:          [PASS][39] -> [FAIL][40] ([fdo#108145])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html

  * igt@kms_psr2_su@frontbuffer:
    - shard-iclb:         [PASS][41] -> [SKIP][42] ([fdo#109642] / [fdo#111068])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-iclb6/igt@kms_psr2_su@frontbuffer.html

  * igt@kms_psr@psr2_cursor_render:
    - shard-iclb:         [PASS][43] -> [SKIP][44] ([fdo#109441]) +1 similar issue
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-iclb6/igt@kms_psr@psr2_cursor_render.html

  * igt@kms_psr@psr2_suspend:
    - shard-tglb:         [PASS][45] -> [DMESG-WARN][46] ([fdo#111600])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb8/igt@kms_psr@psr2_suspend.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-tglb2/igt@kms_psr@psr2_suspend.html

  * igt@kms_psr@suspend:
    - shard-tglb:         [PASS][47] -> [INCOMPLETE][48] ([fdo#111832] / [fdo#111850]) +1 similar issue
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb5/igt@kms_psr@suspend.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-tglb7/igt@kms_psr@suspend.html

  * igt@kms_setmode@basic:
    - shard-kbl:          [PASS][49] -> [FAIL][50] ([fdo#99912])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-kbl6/igt@kms_setmode@basic.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-kbl4/igt@kms_setmode@basic.html

  * igt@prime_vgem@fence-wait-bsd2:
    - shard-iclb:         [PASS][51] -> [SKIP][52] ([fdo#109276]) +25 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb4/igt@prime_vgem@fence-wait-bsd2.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-iclb3/igt@prime_vgem@fence-wait-bsd2.html

  
#### Possible fixes ####

  * igt@gem_ctx_exec@basic-invalid-context-vcs1:
    - shard-iclb:         [SKIP][53] ([fdo#112080]) -> [PASS][54] +19 similar issues
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb8/igt@gem_ctx_exec@basic-invalid-context-vcs1.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-iclb2/igt@gem_ctx_exec@basic-invalid-context-vcs1.html

  * igt@gem_ctx_isolation@bcs0-s3:
    - shard-apl:          [DMESG-WARN][55] ([fdo#108566]) -> [PASS][56] +4 similar issues
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-apl4/igt@gem_ctx_isolation@bcs0-s3.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-apl1/igt@gem_ctx_isolation@bcs0-s3.html

  * igt@gem_ctx_persistence@vcs1-mixed-process:
    - shard-iclb:         [SKIP][57] ([fdo#109276] / [fdo#112080]) -> [PASS][58] +4 similar issues
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb7/igt@gem_ctx_persistence@vcs1-mixed-process.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-iclb4/igt@gem_ctx_persistence@vcs1-mixed-process.html

  * igt@gem_eio@suspend:
    - shard-tglb:         [INCOMPLETE][59] ([fdo#111850]) -> [PASS][60] +1 similar issue
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb3/igt@gem_eio@suspend.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-tglb9/igt@gem_eio@suspend.html

  * igt@gem_exec_parallel@basic:
    - shard-tglb:         [INCOMPLETE][61] ([fdo#111887]) -> [PASS][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb7/igt@gem_exec_parallel@basic.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-tglb8/igt@gem_exec_parallel@basic.html

  * igt@gem_exec_schedule@preempt-other-chain-bsd:
    - shard-iclb:         [SKIP][63] ([fdo#112146]) -> [PASS][64] +8 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb1/igt@gem_exec_schedule@preempt-other-chain-bsd.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-iclb7/igt@gem_exec_schedule@preempt-other-chain-bsd.html

  * igt@gem_exec_suspend@basic-s0:
    - shard-tglb:         [INCOMPLETE][65] ([fdo#111832]) -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb3/igt@gem_exec_suspend@basic-s0.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-tglb3/igt@gem_exec_suspend@basic-s0.html

  * igt@gem_exec_suspend@basic-s3:
    - shard-kbl:          [DMESG-WARN][67] ([fdo#108566]) -> [PASS][68] +3 similar issues
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-kbl7/igt@gem_exec_suspend@basic-s3.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-kbl7/igt@gem_exec_suspend@basic-s3.html

  * igt@gem_sync@basic-each:
    - shard-tglb:         [INCOMPLETE][69] ([fdo#111647] / [fdo#111998]) -> [PASS][70]
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb6/igt@gem_sync@basic-each.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-tglb2/igt@gem_sync@basic-each.html

  * igt@gem_sync@basic-store-all:
    - shard-tglb:         [INCOMPLETE][71] ([fdo#111647]) -> [PASS][72]
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb6/igt@gem_sync@basic-store-all.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-tglb5/igt@gem_sync@basic-store-all.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-snb:          [DMESG-WARN][73] ([fdo#111870]) -> [PASS][74] +1 similar issue
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-snb5/igt@gem_userptr_blits@dmabuf-sync.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-snb1/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gem_userptr_blits@dmabuf-unsync:
    - shard-hsw:          [DMESG-WARN][75] ([fdo#111870]) -> [PASS][76] +1 similar issue
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-hsw6/igt@gem_userptr_blits@dmabuf-unsync.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-hsw7/igt@gem_userptr_blits@dmabuf-unsync.html

  * igt@i915_pm_rpm@system-suspend-execbuf:
    - shard-tglb:         [INCOMPLETE][77] ([fdo#111832] / [fdo#111850]) -> [PASS][78] +4 similar issues
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb7/igt@i915_pm_rpm@system-suspend-execbuf.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-tglb8/igt@i915_pm_rpm@system-suspend-execbuf.html

  * igt@i915_selftest@live_execlists:
    - shard-glk:          [INCOMPLETE][79] ([fdo#103359] / [k.org#198133]) -> [PASS][80]
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-glk5/igt@i915_selftest@live_execlists.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-glk5/igt@i915_selftest@live_execlists.html

  * igt@i915_selftest@live_hangcheck:
    - shard-snb:          [INCOMPLETE][81] ([fdo#105411]) -> [PASS][82]
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-snb5/igt@i915_selftest@live_hangcheck.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-snb1/igt@i915_selftest@live_hangcheck.html

  * igt@kms_color@pipe-b-ctm-0-5:
    - shard-skl:          [DMESG-WARN][83] ([fdo#106107]) -> [PASS][84]
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-skl9/igt@kms_color@pipe-b-ctm-0-5.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-skl5/igt@kms_color@pipe-b-ctm-0-5.html

  * igt@kms_flip@2x-flip-vs-expired-vblank:
    - shard-glk:          [FAIL][85] ([fdo#105363]) -> [PASS][86]
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-tglb:         [INCOMPLETE][87] ([fdo#111832] / [fdo#111850] / [fdo#112031]) -> [PASS][88]
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb7/igt@kms_flip@flip-vs-suspend-interruptible.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-tglb9/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack:
    - shard-tglb:         [FAIL][89] ([fdo#103167]) -> [PASS][90] +5 similar issues
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-tglb8/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt:
    - shard-iclb:         [FAIL][91] ([fdo#103167]) -> [PASS][92] +6 similar issues
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [FAIL][93] ([fdo#108145] / [fdo#110403]) -> [PASS][94]
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_psr2_su@page_flip:
    - shard-iclb:         [SKIP][95] ([fdo#109642] / [fdo#111068]) -> [PASS][96]
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb8/igt@kms_psr2_su@page_flip.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-iclb2/igt@kms_psr2_su@page_flip.html

  * igt@kms_psr@psr2_no_drrs:
    - shard-iclb:         [SKIP][97] ([fdo#109441]) -> [PASS][98] +1 similar issue
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb8/igt@kms_psr@psr2_no_drrs.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-iclb2/igt@kms_psr@psr2_no_drrs.html

  * igt@kms_psr@suspend:
    - shard-skl:          [INCOMPLETE][99] ([fdo#108972]) -> [PASS][100]
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-skl9/igt@kms_psr@suspend.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-skl6/igt@kms_psr@suspend.html

  * igt@kms_vblank@pipe-b-wait-busy-hang:
    - shard-snb:          [SKIP][101] ([fdo#109271]) -> [PASS][102] +4 similar issues
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-snb6/igt@kms_vblank@pipe-b-wait-busy-hang.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-snb7/igt@kms_vblank@pipe-b-wait-busy-hang.html

  * igt@prime_busy@hang-bsd2:
    - shard-iclb:         [SKIP][103] ([fdo#109276]) -> [PASS][104] +17 similar issues
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb6/igt@prime_busy@hang-bsd2.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-iclb1/igt@prime_busy@hang-bsd2.html

  
#### Warnings ####

  * igt@gem_ctx_isolation@vcs2-reset:
    - shard-tglb:         [SKIP][105] ([fdo#111912] / [fdo#112080]) -> [SKIP][106] ([fdo#112080])
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb7/igt@gem_ctx_isolation@vcs2-reset.html
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-tglb9/igt@gem_ctx_isolation@vcs2-reset.html

  * igt@gem_eio@kms:
    - shard-snb:          [INCOMPLETE][107] ([fdo#105411]) -> [DMESG-WARN][108] ([fdo#111780 ] / [fdo#111781])
   [107]: https://

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/4] drm/i915/gt: Set unused mocs entry to follow PTE on tgl as on all others

[Patchwork]

== Series Details ==

Series: series starting with [1/4] drm/i915/gt: Set unused mocs entry to follow PTE on tgl as on all others
URL   : https://patchwork.freedesktop.org/series/69382/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7323_full -> Patchwork_15244_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

New tests
---------

  New tests have been introduced between CI_DRM_7323_full and Patchwork_15244_full:

### New IGT tests (1) ###

  * igt@i915_selftest@live_gt_mocs:
    - Statuses : 8 pass(s)
    - Exec time: [0.29, 4.11] s

  

Known issues
------------

  Here are the changes found in Patchwork_15244_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_isolation@vcs1-dirty-create:
    - shard-iclb:         [PASS][1] -> [SKIP][2] ([fdo#109276] / [fdo#112080]) +3 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb2/igt@gem_ctx_isolation@vcs1-dirty-create.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-iclb6/igt@gem_ctx_isolation@vcs1-dirty-create.html

  * igt@gem_ctx_shared@exec-single-timeline-bsd:
    - shard-iclb:         [PASS][3] -> [SKIP][4] ([fdo#110841])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb5/igt@gem_ctx_shared@exec-single-timeline-bsd.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-iclb1/igt@gem_ctx_shared@exec-single-timeline-bsd.html

  * igt@gem_exec_balancer@smoke:
    - shard-iclb:         [PASS][5] -> [SKIP][6] ([fdo#110854])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb1/igt@gem_exec_balancer@smoke.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-iclb7/igt@gem_exec_balancer@smoke.html

  * igt@gem_exec_parallel@vcs1-fds:
    - shard-iclb:         [PASS][7] -> [SKIP][8] ([fdo#112080]) +19 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb1/igt@gem_exec_parallel@vcs1-fds.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-iclb3/igt@gem_exec_parallel@vcs1-fds.html

  * igt@gem_exec_schedule@in-order-bsd:
    - shard-iclb:         [PASS][9] -> [SKIP][10] ([fdo#112146]) +5 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb7/igt@gem_exec_schedule@in-order-bsd.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-iclb4/igt@gem_exec_schedule@in-order-bsd.html

  * igt@gem_persistent_relocs@forked-thrashing:
    - shard-iclb:         [PASS][11] -> [INCOMPLETE][12] ([fdo#107713] / [fdo#109100] / [fdo#112068 ])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb7/igt@gem_persistent_relocs@forked-thrashing.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-iclb4/igt@gem_persistent_relocs@forked-thrashing.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy:
    - shard-hsw:          [PASS][13] -> [DMESG-WARN][14] ([fdo#110789] / [fdo#111870])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-hsw4/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-hsw4/igt@gem_userptr_blits@map-fixed-invalidate-busy.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
    - shard-hsw:          [PASS][15] -> [DMESG-WARN][16] ([fdo#111870])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-hsw4/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-hsw7/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html

  * igt@i915_pm_rc6_residency@rc6-accuracy:
    - shard-snb:          [PASS][17] -> [SKIP][18] ([fdo#109271])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-snb7/igt@i915_pm_rc6_residency@rc6-accuracy.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-snb6/igt@i915_pm_rc6_residency@rc6-accuracy.html

  * igt@i915_pm_rpm@system-suspend:
    - shard-tglb:         [PASS][19] -> [INCOMPLETE][20] ([fdo#111747] / [fdo#111850])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb9/igt@i915_pm_rpm@system-suspend.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-tglb8/igt@i915_pm_rpm@system-suspend.html

  * igt@kms_color@pipe-b-ctm-red-to-blue:
    - shard-skl:          [PASS][21] -> [DMESG-WARN][22] ([fdo#106107])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-skl3/igt@kms_color@pipe-b-ctm-red-to-blue.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-skl3/igt@kms_color@pipe-b-ctm-red-to-blue.html

  * igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen:
    - shard-skl:          [PASS][23] -> [FAIL][24] ([fdo#103232])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-skl5/igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-skl3/igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html

  * igt@kms_cursor_legacy@flip-vs-cursor-toggle:
    - shard-skl:          [PASS][25] -> [FAIL][26] ([fdo#102670] / [fdo#106081])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-skl8/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-kbl:          [PASS][27] -> [FAIL][28] ([fdo#105363])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-kbl3/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-kbl6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-apl:          [PASS][29] -> [DMESG-WARN][30] ([fdo#108566]) +1 similar issue
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt:
    - shard-tglb:         [PASS][31] -> [FAIL][32] ([fdo#103167]) +1 similar issue
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt:
    - shard-iclb:         [PASS][33] -> [FAIL][34] ([fdo#103167]) +6 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt:
    - shard-skl:          [PASS][35] -> [FAIL][36] ([fdo#103167])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-skl5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-skl3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
    - shard-kbl:          [PASS][37] -> [DMESG-WARN][38] ([fdo#108566]) +2 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-kbl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-kbl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
    - shard-skl:          [PASS][39] -> [FAIL][40] ([fdo#108145])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html

  * igt@kms_psr2_su@frontbuffer:
    - shard-iclb:         [PASS][41] -> [SKIP][42] ([fdo#109642] / [fdo#111068])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-iclb6/igt@kms_psr2_su@frontbuffer.html

  * igt@kms_psr@psr2_cursor_render:
    - shard-iclb:         [PASS][43] -> [SKIP][44] ([fdo#109441]) +1 similar issue
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-iclb6/igt@kms_psr@psr2_cursor_render.html

  * igt@kms_psr@psr2_suspend:
    - shard-tglb:         [PASS][45] -> [DMESG-WARN][46] ([fdo#111600])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb8/igt@kms_psr@psr2_suspend.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-tglb2/igt@kms_psr@psr2_suspend.html

  * igt@kms_psr@suspend:
    - shard-tglb:         [PASS][47] -> [INCOMPLETE][48] ([fdo#111832] / [fdo#111850]) +1 similar issue
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb5/igt@kms_psr@suspend.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-tglb7/igt@kms_psr@suspend.html

  * igt@kms_setmode@basic:
    - shard-kbl:          [PASS][49] -> [FAIL][50] ([fdo#99912])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-kbl6/igt@kms_setmode@basic.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-kbl4/igt@kms_setmode@basic.html

  * igt@prime_vgem@fence-wait-bsd2:
    - shard-iclb:         [PASS][51] -> [SKIP][52] ([fdo#109276]) +25 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb4/igt@prime_vgem@fence-wait-bsd2.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-iclb3/igt@prime_vgem@fence-wait-bsd2.html

  
#### Possible fixes ####

  * igt@gem_ctx_exec@basic-invalid-context-vcs1:
    - shard-iclb:         [SKIP][53] ([fdo#112080]) -> [PASS][54] +19 similar issues
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb8/igt@gem_ctx_exec@basic-invalid-context-vcs1.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-iclb2/igt@gem_ctx_exec@basic-invalid-context-vcs1.html

  * igt@gem_ctx_isolation@bcs0-s3:
    - shard-apl:          [DMESG-WARN][55] ([fdo#108566]) -> [PASS][56] +4 similar issues
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-apl4/igt@gem_ctx_isolation@bcs0-s3.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-apl1/igt@gem_ctx_isolation@bcs0-s3.html

  * igt@gem_ctx_persistence@vcs1-mixed-process:
    - shard-iclb:         [SKIP][57] ([fdo#109276] / [fdo#112080]) -> [PASS][58] +4 similar issues
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb7/igt@gem_ctx_persistence@vcs1-mixed-process.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-iclb4/igt@gem_ctx_persistence@vcs1-mixed-process.html

  * igt@gem_eio@suspend:
    - shard-tglb:         [INCOMPLETE][59] ([fdo#111850]) -> [PASS][60] +1 similar issue
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb3/igt@gem_eio@suspend.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-tglb9/igt@gem_eio@suspend.html

  * igt@gem_exec_parallel@basic:
    - shard-tglb:         [INCOMPLETE][61] ([fdo#111887]) -> [PASS][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb7/igt@gem_exec_parallel@basic.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-tglb8/igt@gem_exec_parallel@basic.html

  * igt@gem_exec_schedule@preempt-other-chain-bsd:
    - shard-iclb:         [SKIP][63] ([fdo#112146]) -> [PASS][64] +8 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb1/igt@gem_exec_schedule@preempt-other-chain-bsd.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-iclb7/igt@gem_exec_schedule@preempt-other-chain-bsd.html

  * igt@gem_exec_suspend@basic-s0:
    - shard-tglb:         [INCOMPLETE][65] ([fdo#111832]) -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb3/igt@gem_exec_suspend@basic-s0.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-tglb3/igt@gem_exec_suspend@basic-s0.html

  * igt@gem_exec_suspend@basic-s3:
    - shard-kbl:          [DMESG-WARN][67] ([fdo#108566]) -> [PASS][68] +3 similar issues
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-kbl7/igt@gem_exec_suspend@basic-s3.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-kbl7/igt@gem_exec_suspend@basic-s3.html

  * igt@gem_sync@basic-each:
    - shard-tglb:         [INCOMPLETE][69] ([fdo#111647] / [fdo#111998]) -> [PASS][70]
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb6/igt@gem_sync@basic-each.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-tglb2/igt@gem_sync@basic-each.html

  * igt@gem_sync@basic-store-all:
    - shard-tglb:         [INCOMPLETE][71] ([fdo#111647]) -> [PASS][72]
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb6/igt@gem_sync@basic-store-all.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-tglb5/igt@gem_sync@basic-store-all.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-snb:          [DMESG-WARN][73] ([fdo#111870]) -> [PASS][74] +1 similar issue
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-snb5/igt@gem_userptr_blits@dmabuf-sync.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-snb1/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gem_userptr_blits@dmabuf-unsync:
    - shard-hsw:          [DMESG-WARN][75] ([fdo#111870]) -> [PASS][76] +1 similar issue
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-hsw6/igt@gem_userptr_blits@dmabuf-unsync.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-hsw7/igt@gem_userptr_blits@dmabuf-unsync.html

  * igt@i915_pm_rpm@system-suspend-execbuf:
    - shard-tglb:         [INCOMPLETE][77] ([fdo#111832] / [fdo#111850]) -> [PASS][78] +4 similar issues
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb7/igt@i915_pm_rpm@system-suspend-execbuf.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-tglb8/igt@i915_pm_rpm@system-suspend-execbuf.html

  * igt@i915_selftest@live_execlists:
    - shard-glk:          [INCOMPLETE][79] ([fdo#103359] / [k.org#198133]) -> [PASS][80]
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-glk5/igt@i915_selftest@live_execlists.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-glk5/igt@i915_selftest@live_execlists.html

  * igt@i915_selftest@live_hangcheck:
    - shard-snb:          [INCOMPLETE][81] ([fdo#105411]) -> [PASS][82]
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-snb5/igt@i915_selftest@live_hangcheck.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-snb1/igt@i915_selftest@live_hangcheck.html

  * igt@kms_color@pipe-b-ctm-0-5:
    - shard-skl:          [DMESG-WARN][83] ([fdo#106107]) -> [PASS][84]
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-skl9/igt@kms_color@pipe-b-ctm-0-5.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-skl5/igt@kms_color@pipe-b-ctm-0-5.html

  * igt@kms_flip@2x-flip-vs-expired-vblank:
    - shard-glk:          [FAIL][85] ([fdo#105363]) -> [PASS][86]
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-tglb:         [INCOMPLETE][87] ([fdo#111832] / [fdo#111850] / [fdo#112031]) -> [PASS][88]
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb7/igt@kms_flip@flip-vs-suspend-interruptible.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-tglb9/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack:
    - shard-tglb:         [FAIL][89] ([fdo#103167]) -> [PASS][90] +5 similar issues
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-tglb8/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt:
    - shard-iclb:         [FAIL][91] ([fdo#103167]) -> [PASS][92] +6 similar issues
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [FAIL][93] ([fdo#108145] / [fdo#110403]) -> [PASS][94]
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_psr2_su@page_flip:
    - shard-iclb:         [SKIP][95] ([fdo#109642] / [fdo#111068]) -> [PASS][96]
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb8/igt@kms_psr2_su@page_flip.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-iclb2/igt@kms_psr2_su@page_flip.html

  * igt@kms_psr@psr2_no_drrs:
    - shard-iclb:         [SKIP][97] ([fdo#109441]) -> [PASS][98] +1 similar issue
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb8/igt@kms_psr@psr2_no_drrs.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-iclb2/igt@kms_psr@psr2_no_drrs.html

  * igt@kms_psr@suspend:
    - shard-skl:          [INCOMPLETE][99] ([fdo#108972]) -> [PASS][100]
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-skl9/igt@kms_psr@suspend.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-skl6/igt@kms_psr@suspend.html

  * igt@kms_vblank@pipe-b-wait-busy-hang:
    - shard-snb:          [SKIP][101] ([fdo#109271]) -> [PASS][102] +4 similar issues
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-snb6/igt@kms_vblank@pipe-b-wait-busy-hang.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-snb7/igt@kms_vblank@pipe-b-wait-busy-hang.html

  * igt@prime_busy@hang-bsd2:
    - shard-iclb:         [SKIP][103] ([fdo#109276]) -> [PASS][104] +17 similar issues
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-iclb6/igt@prime_busy@hang-bsd2.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-iclb1/igt@prime_busy@hang-bsd2.html

  
#### Warnings ####

  * igt@gem_ctx_isolation@vcs2-reset:
    - shard-tglb:         [SKIP][105] ([fdo#111912] / [fdo#112080]) -> [SKIP][106] ([fdo#112080])
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7323/shard-tglb7/igt@gem_ctx_isolation@vcs2-reset.html
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/shard-tglb9/igt@gem_ctx_isolation@vcs2-reset.html

  * igt@gem_eio@kms:
    - shard-snb:          [INCOMPLETE][107] ([fdo#105411]) -> [DMESG-WARN][108] ([fdo#111780 ] / [fdo#111781])
   [107]: https://

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15244/index.html
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Re: [PATCH 1/4] drm/i915/gt: Set unused mocs entry to follow PTE on tgl as on all others

[Mika Kuoppala]

Chris Wilson <chris@chris-wilson.co.uk> writes:

> Be consistent in our mocs setup on Tigerlake and set the unused control
> value to follow the PTE entry as we previously have done. The unused
> values are beyond the defines of the ABI, the consistency simplifies our
> checking.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index 6e881c735b20..d2b445d6c258 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -489,7 +489,7 @@ static void intel_mocs_init_global(struct intel_gt *gt)
>  	for (; index < table.n_entries; index++)
>  		intel_uncore_write(uncore,
>  				   GEN12_GLOBAL_MOCS(index),
> -				   table.table[0].control_value);
> +				   table.table[I915_MOCS_PTE].control_value);
>  }
>  
>  void intel_mocs_init(struct intel_gt *gt)
> -- 
> 2.24.0
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Re: [Intel-gfx] [PATCH 1/4] drm/i915/gt: Set unused mocs entry to follow PTE on tgl as on all others

[Mika Kuoppala]

Chris Wilson <chris@chris-wilson.co.uk> writes:

> Be consistent in our mocs setup on Tigerlake and set the unused control
> value to follow the PTE entry as we previously have done. The unused
> values are beyond the defines of the ABI, the consistency simplifies our
> checking.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index 6e881c735b20..d2b445d6c258 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -489,7 +489,7 @@ static void intel_mocs_init_global(struct intel_gt *gt)
>  	for (; index < table.n_entries; index++)
>  		intel_uncore_write(uncore,
>  				   GEN12_GLOBAL_MOCS(index),
> -				   table.table[0].control_value);
> +				   table.table[I915_MOCS_PTE].control_value);
>  }
>  
>  void intel_mocs_init(struct intel_gt *gt)
> -- 
> 2.24.0
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Re: [PATCH 1/4] drm/i915/gt: Set unused mocs entry to follow PTE on tgl as on all others

[Mika Kuoppala]

Chris Wilson <chris@chris-wilson.co.uk> writes:

> Be consistent in our mocs setup on Tigerlake and set the unused control
> value to follow the PTE entry as we previously have done. The unused
> values are beyond the defines of the ABI, the consistency simplifies our
> checking.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index 6e881c735b20..d2b445d6c258 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -489,7 +489,7 @@ static void intel_mocs_init_global(struct intel_gt *gt)
>  	for (; index < table.n_entries; index++)
>  		intel_uncore_write(uncore,
>  				   GEN12_GLOBAL_MOCS(index),
> -				   table.table[0].control_value);
> +				   table.table[I915_MOCS_PTE].control_value);
>  }
>  
>  void intel_mocs_init(struct intel_gt *gt)
> -- 
> 2.24.0
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Re: [Intel-gfx] [PATCH 1/4] drm/i915/gt: Set unused mocs entry to follow PTE on tgl as on all others

[Mika Kuoppala]

Chris Wilson <chris@chris-wilson.co.uk> writes:

> Be consistent in our mocs setup on Tigerlake and set the unused control
> value to follow the PTE entry as we previously have done. The unused
> values are beyond the defines of the ABI, the consistency simplifies our
> checking.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index 6e881c735b20..d2b445d6c258 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -489,7 +489,7 @@ static void intel_mocs_init_global(struct intel_gt *gt)
>  	for (; index < table.n_entries; index++)
>  		intel_uncore_write(uncore,
>  				   GEN12_GLOBAL_MOCS(index),
> -				   table.table[0].control_value);
> +				   table.table[I915_MOCS_PTE].control_value);
>  }
>  
>  void intel_mocs_init(struct intel_gt *gt)
> -- 
> 2.24.0
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Re: [PATCH 2/4] drm/i915/gt: Tidy up debug-warns for the mocs control table

[Mika Kuoppala]

Chris Wilson <chris@chris-wilson.co.uk> writes:

> As we always run new platforms through CI, we only need the debug code
> compiled in during CI runs.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/gt/intel_mocs.c | 30 ++++++++++------------------
>  1 file changed, 11 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index d2b445d6c258..e6f3f36a3988 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -291,44 +291,42 @@ static const struct drm_i915_mocs_entry icelake_mocs_table[] = {
>  static bool get_mocs_settings(const struct drm_i915_private *i915,
>  			      struct drm_i915_mocs_table *table)
>  {
> -	bool result = false;
> -
>  	if (INTEL_GEN(i915) >= 12) {
>  		table->size  = ARRAY_SIZE(tigerlake_mocs_table);
>  		table->table = tigerlake_mocs_table;
>  		table->n_entries = GEN11_NUM_MOCS_ENTRIES;
> -		result = true;
>  	} else if (IS_GEN(i915, 11)) {
>  		table->size  = ARRAY_SIZE(icelake_mocs_table);
>  		table->table = icelake_mocs_table;
>  		table->n_entries = GEN11_NUM_MOCS_ENTRIES;
> -		result = true;
>  	} else if (IS_GEN9_BC(i915) || IS_CANNONLAKE(i915)) {
>  		table->size  = ARRAY_SIZE(skylake_mocs_table);
>  		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
>  		table->table = skylake_mocs_table;
> -		result = true;
>  	} else if (IS_GEN9_LP(i915)) {
>  		table->size  = ARRAY_SIZE(broxton_mocs_table);
>  		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
>  		table->table = broxton_mocs_table;
> -		result = true;
>  	} else {
>  		WARN_ONCE(INTEL_GEN(i915) >= 9,
>  			  "Platform that should have a MOCS table does not.\n");
> +		return false;
>  	}
>  
> +	if (GEM_DEBUG_WARN_ON(table->size > table->n_entries))
> +		return false;
> +
>  	/* WaDisableSkipCaching:skl,bxt,kbl,glk */
>  	if (IS_GEN(i915, 9)) {
>  		int i;
>  
>  		for (i = 0; i < table->size; i++)
> -			if (WARN_ON(table->table[i].l3cc_value &
> -				    (L3_ESC(1) | L3_SCC(0x7))))
> +			if (GEM_DEBUG_WARN_ON(table->table[i].l3cc_value &
> +					      (L3_ESC(1) | L3_SCC(0x7))))
>  				return false;
>  	}
>  
> -	return result;
> +	return true;
>  }
>  
>  static i915_reg_t mocs_register(const struct intel_engine_cs *engine, int index)
> @@ -397,9 +395,7 @@ static u16 get_entry_l3cc(const struct drm_i915_mocs_table *table,
>  	return table->table[I915_MOCS_PTE].l3cc_value;
>  }
>  
> -static inline u32 l3cc_combine(const struct drm_i915_mocs_table *table,
> -			       u16 low,
> -			       u16 high)
> +static inline u32 l3cc_combine(u16 low, u16 high)
>  {
>  	return low | (u32)high << 16;
>  }
> @@ -417,7 +413,7 @@ static void init_l3cc_table(struct intel_engine_cs *engine,
>  
>  		intel_uncore_write(uncore,
>  				   GEN9_LNCFCMOCS(i),
> -				   l3cc_combine(table, low, high));
> +				   l3cc_combine(low, high));
>  	}
>  
>  	/* Odd table size - 1 left over */
> @@ -426,7 +422,7 @@ static void init_l3cc_table(struct intel_engine_cs *engine,
>  
>  		intel_uncore_write(uncore,
>  				   GEN9_LNCFCMOCS(i),
> -				   l3cc_combine(table, low, unused_value));
> +				   l3cc_combine(low, unused_value));
>  		i++;
>  	}
>  
> @@ -434,8 +430,7 @@ static void init_l3cc_table(struct intel_engine_cs *engine,
>  	for (; i < table->n_entries / 2; i++)
>  		intel_uncore_write(uncore,
>  				   GEN9_LNCFCMOCS(i),
> -				   l3cc_combine(table, unused_value,
> -						unused_value));
> +				   l3cc_combine(unused_value, unused_value));
>  }
>  
>  void intel_mocs_init_engine(struct intel_engine_cs *engine)
> @@ -473,9 +468,6 @@ static void intel_mocs_init_global(struct intel_gt *gt)
>  	if (!get_mocs_settings(gt->i915, &table))
>  		return;
>  
> -	if (GEM_DEBUG_WARN_ON(table.size > table.n_entries))
> -		return;
> -
>  	for (index = 0; index < table.size; index++)
>  		intel_uncore_write(uncore,
>  				   GEN12_GLOBAL_MOCS(index),
> -- 
> 2.24.0
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Re: [Intel-gfx] [PATCH 2/4] drm/i915/gt: Tidy up debug-warns for the mocs control table

[Mika Kuoppala]

Chris Wilson <chris@chris-wilson.co.uk> writes:

> As we always run new platforms through CI, we only need the debug code
> compiled in during CI runs.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/gt/intel_mocs.c | 30 ++++++++++------------------
>  1 file changed, 11 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index d2b445d6c258..e6f3f36a3988 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -291,44 +291,42 @@ static const struct drm_i915_mocs_entry icelake_mocs_table[] = {
>  static bool get_mocs_settings(const struct drm_i915_private *i915,
>  			      struct drm_i915_mocs_table *table)
>  {
> -	bool result = false;
> -
>  	if (INTEL_GEN(i915) >= 12) {
>  		table->size  = ARRAY_SIZE(tigerlake_mocs_table);
>  		table->table = tigerlake_mocs_table;
>  		table->n_entries = GEN11_NUM_MOCS_ENTRIES;
> -		result = true;
>  	} else if (IS_GEN(i915, 11)) {
>  		table->size  = ARRAY_SIZE(icelake_mocs_table);
>  		table->table = icelake_mocs_table;
>  		table->n_entries = GEN11_NUM_MOCS_ENTRIES;
> -		result = true;
>  	} else if (IS_GEN9_BC(i915) || IS_CANNONLAKE(i915)) {
>  		table->size  = ARRAY_SIZE(skylake_mocs_table);
>  		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
>  		table->table = skylake_mocs_table;
> -		result = true;
>  	} else if (IS_GEN9_LP(i915)) {
>  		table->size  = ARRAY_SIZE(broxton_mocs_table);
>  		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
>  		table->table = broxton_mocs_table;
> -		result = true;
>  	} else {
>  		WARN_ONCE(INTEL_GEN(i915) >= 9,
>  			  "Platform that should have a MOCS table does not.\n");
> +		return false;
>  	}
>  
> +	if (GEM_DEBUG_WARN_ON(table->size > table->n_entries))
> +		return false;
> +
>  	/* WaDisableSkipCaching:skl,bxt,kbl,glk */
>  	if (IS_GEN(i915, 9)) {
>  		int i;
>  
>  		for (i = 0; i < table->size; i++)
> -			if (WARN_ON(table->table[i].l3cc_value &
> -				    (L3_ESC(1) | L3_SCC(0x7))))
> +			if (GEM_DEBUG_WARN_ON(table->table[i].l3cc_value &
> +					      (L3_ESC(1) | L3_SCC(0x7))))
>  				return false;
>  	}
>  
> -	return result;
> +	return true;
>  }
>  
>  static i915_reg_t mocs_register(const struct intel_engine_cs *engine, int index)
> @@ -397,9 +395,7 @@ static u16 get_entry_l3cc(const struct drm_i915_mocs_table *table,
>  	return table->table[I915_MOCS_PTE].l3cc_value;
>  }
>  
> -static inline u32 l3cc_combine(const struct drm_i915_mocs_table *table,
> -			       u16 low,
> -			       u16 high)
> +static inline u32 l3cc_combine(u16 low, u16 high)
>  {
>  	return low | (u32)high << 16;
>  }
> @@ -417,7 +413,7 @@ static void init_l3cc_table(struct intel_engine_cs *engine,
>  
>  		intel_uncore_write(uncore,
>  				   GEN9_LNCFCMOCS(i),
> -				   l3cc_combine(table, low, high));
> +				   l3cc_combine(low, high));
>  	}
>  
>  	/* Odd table size - 1 left over */
> @@ -426,7 +422,7 @@ static void init_l3cc_table(struct intel_engine_cs *engine,
>  
>  		intel_uncore_write(uncore,
>  				   GEN9_LNCFCMOCS(i),
> -				   l3cc_combine(table, low, unused_value));
> +				   l3cc_combine(low, unused_value));
>  		i++;
>  	}
>  
> @@ -434,8 +430,7 @@ static void init_l3cc_table(struct intel_engine_cs *engine,
>  	for (; i < table->n_entries / 2; i++)
>  		intel_uncore_write(uncore,
>  				   GEN9_LNCFCMOCS(i),
> -				   l3cc_combine(table, unused_value,
> -						unused_value));
> +				   l3cc_combine(unused_value, unused_value));
>  }
>  
>  void intel_mocs_init_engine(struct intel_engine_cs *engine)
> @@ -473,9 +468,6 @@ static void intel_mocs_init_global(struct intel_gt *gt)
>  	if (!get_mocs_settings(gt->i915, &table))
>  		return;
>  
> -	if (GEM_DEBUG_WARN_ON(table.size > table.n_entries))
> -		return;
> -
>  	for (index = 0; index < table.size; index++)
>  		intel_uncore_write(uncore,
>  				   GEN12_GLOBAL_MOCS(index),
> -- 
> 2.24.0
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Re: [PATCH 3/4] drm/i915/gt: Refactor mocs loops into single control macro

[Mika Kuoppala]

Chris Wilson <chris@chris-wilson.co.uk> writes:

> We repeatedly (and more so in future) use the same looping construct
> over the mocs definition table to setup the register state. Refactor the
> loop construct into a reusable macro.
>
> add/remove: 2/1 grow/shrink: 1/2 up/down: 113/-330 (-217)
> Function                                     old     new   delta
> intel_mocs_init_engine.cold                    -      71     +71
> offset                                         -      28     +28
> __func__                                   17273   17287     +14
> intel_mocs_init                              143     113     -30
> mocs_register.isra                            91       -     -91
> intel_mocs_init_engine                       503     294    -209

Effective diet.

>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

Could not spot anything off at this round and even pretty
defines this time.

Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/gt/intel_mocs.c | 133 +++++++++++----------------
>  drivers/gpu/drm/i915/i915_reg.h      |  19 ++--
>  2 files changed, 64 insertions(+), 88 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index e6f3f36a3988..47d16a242183 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -329,27 +329,6 @@ static bool get_mocs_settings(const struct drm_i915_private *i915,
>  	return true;
>  }
>  
> -static i915_reg_t mocs_register(const struct intel_engine_cs *engine, int index)
> -{
> -	switch (engine->id) {
> -	case RCS0:
> -		return GEN9_GFX_MOCS(index);
> -	case VCS0:
> -		return GEN9_MFX0_MOCS(index);
> -	case BCS0:
> -		return GEN9_BLT_MOCS(index);
> -	case VECS0:
> -		return GEN9_VEBOX_MOCS(index);
> -	case VCS1:
> -		return GEN9_MFX1_MOCS(index);
> -	case VCS2:
> -		return GEN11_MFX2_MOCS(index);
> -	default:
> -		MISSING_CASE(engine->id);
> -		return INVALID_MMIO_REG;
> -	}
> -}
> -
>  /*
>   * Get control_value from MOCS entry taking into account when it's not used:
>   * I915_MOCS_PTE's value is returned in this case.
> @@ -357,29 +336,47 @@ static i915_reg_t mocs_register(const struct intel_engine_cs *engine, int index)
>  static u32 get_entry_control(const struct drm_i915_mocs_table *table,
>  			     unsigned int index)
>  {
> -	if (table->table[index].used)
> +	if (index < table->size && table->table[index].used)
>  		return table->table[index].control_value;
>  
>  	return table->table[I915_MOCS_PTE].control_value;
>  }
>  
> -static void init_mocs_table(struct intel_engine_cs *engine,
> -			    const struct drm_i915_mocs_table *table)
> +#define for_each_mocs(mocs, t, i) \
> +	for (i = 0; \
> +	     i < (t)->n_entries ? (mocs = get_entry_control((t), i)), 1 : 0;\
> +	     i++)
> +
> +static void __init_mocs_table(struct intel_uncore *uncore,
> +			      const struct drm_i915_mocs_table *table,
> +			      u32 addr)
>  {
> -	struct intel_uncore *uncore = engine->uncore;
> -	u32 unused_value = table->table[I915_MOCS_PTE].control_value;
>  	unsigned int i;
> +	u32 mocs;
>  
> -	for (i = 0; i < table->size; i++)
> -		intel_uncore_write_fw(uncore,
> -				      mocs_register(engine, i),
> -				      get_entry_control(table, i));
> +	for_each_mocs(mocs, table, i)
> +		intel_uncore_write_fw(uncore, _MMIO(addr + i * 4), mocs);
> +}
> +
> +static u32 mocs_offset(const struct intel_engine_cs *engine)
> +{
> +	static const u32 offset[] = {
> +		[RCS0]  =  __GEN9_RCS0_MOCS0,
> +		[VCS0]  =  __GEN9_VCS0_MOCS0,
> +		[VCS1]  =  __GEN9_VCS1_MOCS0,
> +		[VECS0] =  __GEN9_VECS0_MOCS0,
> +		[BCS0]  =  __GEN9_BCS0_MOCS0,
> +		[VCS2]  = __GEN11_VCS2_MOCS0,
> +	};
> +
> +	GEM_BUG_ON(engine->id >= ARRAY_SIZE(offset));
> +	return offset[engine->id];
> +}
>  
> -	/* All remaining entries are unused */
> -	for (; i < table->n_entries; i++)
> -		intel_uncore_write_fw(uncore,
> -				      mocs_register(engine, i),
> -				      unused_value);
> +static void init_mocs_table(struct intel_engine_cs *engine,
> +			    const struct drm_i915_mocs_table *table)
> +{
> +	__init_mocs_table(engine->uncore, table, mocs_offset(engine));
>  }
>  
>  /*
> @@ -389,7 +386,7 @@ static void init_mocs_table(struct intel_engine_cs *engine,
>  static u16 get_entry_l3cc(const struct drm_i915_mocs_table *table,
>  			  unsigned int index)
>  {
> -	if (table->table[index].used)
> +	if (index < table->size && table->table[index].used)
>  		return table->table[index].l3cc_value;
>  
>  	return table->table[I915_MOCS_PTE].l3cc_value;
> @@ -400,37 +397,23 @@ static inline u32 l3cc_combine(u16 low, u16 high)
>  	return low | (u32)high << 16;
>  }
>  
> +#define for_each_l3cc(l3cc, t, i) \
> +	for (i = 0; \
> +	     i < ((t)->n_entries + 1) / 2 ? \
> +	     (l3cc = l3cc_combine(get_entry_l3cc((t), 2 * i), \
> +				  get_entry_l3cc((t), 2 * i + 1))), 1 : \
> +	     0; \
> +	     i++)
> +
>  static void init_l3cc_table(struct intel_engine_cs *engine,
>  			    const struct drm_i915_mocs_table *table)
>  {
>  	struct intel_uncore *uncore = engine->uncore;
> -	u16 unused_value = table->table[I915_MOCS_PTE].l3cc_value;
>  	unsigned int i;
> +	u32 l3cc;
>  
> -	for (i = 0; i < table->size / 2; i++) {
> -		u16 low = get_entry_l3cc(table, 2 * i);
> -		u16 high = get_entry_l3cc(table, 2 * i + 1);
> -
> -		intel_uncore_write(uncore,
> -				   GEN9_LNCFCMOCS(i),
> -				   l3cc_combine(low, high));
> -	}
> -
> -	/* Odd table size - 1 left over */
> -	if (table->size & 1) {
> -		u16 low = get_entry_l3cc(table, 2 * i);
> -
> -		intel_uncore_write(uncore,
> -				   GEN9_LNCFCMOCS(i),
> -				   l3cc_combine(low, unused_value));
> -		i++;
> -	}
> -
> -	/* All remaining entries are also unused */
> -	for (; i < table->n_entries / 2; i++)
> -		intel_uncore_write(uncore,
> -				   GEN9_LNCFCMOCS(i),
> -				   l3cc_combine(unused_value, unused_value));
> +	for_each_l3cc(l3cc, table, i)
> +		intel_uncore_write_fw(uncore, GEN9_LNCFCMOCS(i), l3cc);
>  }
>  
>  void intel_mocs_init_engine(struct intel_engine_cs *engine)
> @@ -451,11 +434,14 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
>  		init_l3cc_table(engine, &table);
>  }
>  
> -static void intel_mocs_init_global(struct intel_gt *gt)
> +static u32 global_mocs_offset(void)
> +{
> +	return i915_mmio_reg_offset(GEN12_GLOBAL_MOCS(0));
> +}
> +
> +static void init_global_mocs(struct intel_gt *gt)
>  {
> -	struct intel_uncore *uncore = gt->uncore;
>  	struct drm_i915_mocs_table table;
> -	unsigned int index;
>  
>  	/*
>  	 * LLC and eDRAM control values are not applicable to dgfx
> @@ -463,29 +449,14 @@ static void intel_mocs_init_global(struct intel_gt *gt)
>  	if (IS_DGFX(gt->i915))
>  		return;
>  
> -	GEM_BUG_ON(!HAS_GLOBAL_MOCS_REGISTERS(gt->i915));
> -
>  	if (!get_mocs_settings(gt->i915, &table))
>  		return;
>  
> -	for (index = 0; index < table.size; index++)
> -		intel_uncore_write(uncore,
> -				   GEN12_GLOBAL_MOCS(index),
> -				   table.table[index].control_value);
> -
> -	/*
> -	 * Ok, now set the unused entries to the invalid entry (index 0). These
> -	 * entries are officially undefined and no contract for the contents and
> -	 * settings is given for these entries.
> -	 */
> -	for (; index < table.n_entries; index++)
> -		intel_uncore_write(uncore,
> -				   GEN12_GLOBAL_MOCS(index),
> -				   table.table[I915_MOCS_PTE].control_value);
> +	__init_mocs_table(gt->uncore, &table, global_mocs_offset());
>  }
>  
>  void intel_mocs_init(struct intel_gt *gt)
>  {
>  	if (HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
> -		intel_mocs_init_global(gt);
> +		init_global_mocs(gt);
>  }
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2ffcc21670b7..0960ea0b5a66 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -11688,13 +11688,18 @@ enum skl_power_gate {
>  /* MOCS (Memory Object Control State) registers */
>  #define GEN9_LNCFCMOCS(i)	_MMIO(0xb020 + (i) * 4)	/* L3 Cache Control */
>  
> -#define GEN9_GFX_MOCS(i)	_MMIO(0xc800 + (i) * 4)	/* Graphics MOCS registers */
> -#define GEN9_MFX0_MOCS(i)	_MMIO(0xc900 + (i) * 4)	/* Media 0 MOCS registers */
> -#define GEN9_MFX1_MOCS(i)	_MMIO(0xca00 + (i) * 4)	/* Media 1 MOCS registers */
> -#define GEN9_VEBOX_MOCS(i)	_MMIO(0xcb00 + (i) * 4)	/* Video MOCS registers */
> -#define GEN9_BLT_MOCS(i)	_MMIO(0xcc00 + (i) * 4)	/* Blitter MOCS registers */
> -/* Media decoder 2 MOCS registers */
> -#define GEN11_MFX2_MOCS(i)	_MMIO(0x10000 + (i) * 4)
> +#define __GEN9_RCS0_MOCS0	0xc800
> +#define GEN9_GFX_MOCS(i)	_MMIO(__GEN9_RCS0_MOCS0 + (i) * 4)
> +#define __GEN9_VCS0_MOCS0	0xc900
> +#define GEN9_MFX0_MOCS(i)	_MMIO(__GEN9_VCS0_MOCS0 + (i) * 4)
> +#define __GEN9_VCS1_MOCS0	0xca00
> +#define GEN9_MFX1_MOCS(i)	_MMIO(__GEN9_VCS1_MOCS0 + (i) * 4)
> +#define __GEN9_VECS0_MOCS0	0xcb00
> +#define GEN9_VEBOX_MOCS(i)	_MMIO(__GEN9_VECS0_MOCS0 + (i) * 4)
> +#define __GEN9_BCS0_MOCS0	0xcc00
> +#define GEN9_BLT_MOCS(i)	_MMIO(__GEN9_BCS0_MOCS0 + (i) * 4)
> +#define __GEN11_VCS2_MOCS0	0x10000
> +#define GEN11_MFX2_MOCS(i)	_MMIO(__GEN11_VCS2_MOCS0 + (i) * 4)
>  
>  #define GEN10_SCRATCH_LNCF2		_MMIO(0xb0a0)
>  #define   PMFLUSHDONE_LNICRSDROP	(1 << 20)
> -- 
> 2.24.0
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Re: [Intel-gfx] [PATCH 3/4] drm/i915/gt: Refactor mocs loops into single control macro

[Mika Kuoppala]

Chris Wilson <chris@chris-wilson.co.uk> writes:

> We repeatedly (and more so in future) use the same looping construct
> over the mocs definition table to setup the register state. Refactor the
> loop construct into a reusable macro.
>
> add/remove: 2/1 grow/shrink: 1/2 up/down: 113/-330 (-217)
> Function                                     old     new   delta
> intel_mocs_init_engine.cold                    -      71     +71
> offset                                         -      28     +28
> __func__                                   17273   17287     +14
> intel_mocs_init                              143     113     -30
> mocs_register.isra                            91       -     -91
> intel_mocs_init_engine                       503     294    -209

Effective diet.

>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

Could not spot anything off at this round and even pretty
defines this time.

Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/gt/intel_mocs.c | 133 +++++++++++----------------
>  drivers/gpu/drm/i915/i915_reg.h      |  19 ++--
>  2 files changed, 64 insertions(+), 88 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index e6f3f36a3988..47d16a242183 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -329,27 +329,6 @@ static bool get_mocs_settings(const struct drm_i915_private *i915,
>  	return true;
>  }
>  
> -static i915_reg_t mocs_register(const struct intel_engine_cs *engine, int index)
> -{
> -	switch (engine->id) {
> -	case RCS0:
> -		return GEN9_GFX_MOCS(index);
> -	case VCS0:
> -		return GEN9_MFX0_MOCS(index);
> -	case BCS0:
> -		return GEN9_BLT_MOCS(index);
> -	case VECS0:
> -		return GEN9_VEBOX_MOCS(index);
> -	case VCS1:
> -		return GEN9_MFX1_MOCS(index);
> -	case VCS2:
> -		return GEN11_MFX2_MOCS(index);
> -	default:
> -		MISSING_CASE(engine->id);
> -		return INVALID_MMIO_REG;
> -	}
> -}
> -
>  /*
>   * Get control_value from MOCS entry taking into account when it's not used:
>   * I915_MOCS_PTE's value is returned in this case.
> @@ -357,29 +336,47 @@ static i915_reg_t mocs_register(const struct intel_engine_cs *engine, int index)
>  static u32 get_entry_control(const struct drm_i915_mocs_table *table,
>  			     unsigned int index)
>  {
> -	if (table->table[index].used)
> +	if (index < table->size && table->table[index].used)
>  		return table->table[index].control_value;
>  
>  	return table->table[I915_MOCS_PTE].control_value;
>  }
>  
> -static void init_mocs_table(struct intel_engine_cs *engine,
> -			    const struct drm_i915_mocs_table *table)
> +#define for_each_mocs(mocs, t, i) \
> +	for (i = 0; \
> +	     i < (t)->n_entries ? (mocs = get_entry_control((t), i)), 1 : 0;\
> +	     i++)
> +
> +static void __init_mocs_table(struct intel_uncore *uncore,
> +			      const struct drm_i915_mocs_table *table,
> +			      u32 addr)
>  {
> -	struct intel_uncore *uncore = engine->uncore;
> -	u32 unused_value = table->table[I915_MOCS_PTE].control_value;
>  	unsigned int i;
> +	u32 mocs;
>  
> -	for (i = 0; i < table->size; i++)
> -		intel_uncore_write_fw(uncore,
> -				      mocs_register(engine, i),
> -				      get_entry_control(table, i));
> +	for_each_mocs(mocs, table, i)
> +		intel_uncore_write_fw(uncore, _MMIO(addr + i * 4), mocs);
> +}
> +
> +static u32 mocs_offset(const struct intel_engine_cs *engine)
> +{
> +	static const u32 offset[] = {
> +		[RCS0]  =  __GEN9_RCS0_MOCS0,
> +		[VCS0]  =  __GEN9_VCS0_MOCS0,
> +		[VCS1]  =  __GEN9_VCS1_MOCS0,
> +		[VECS0] =  __GEN9_VECS0_MOCS0,
> +		[BCS0]  =  __GEN9_BCS0_MOCS0,
> +		[VCS2]  = __GEN11_VCS2_MOCS0,
> +	};
> +
> +	GEM_BUG_ON(engine->id >= ARRAY_SIZE(offset));
> +	return offset[engine->id];
> +}
>  
> -	/* All remaining entries are unused */
> -	for (; i < table->n_entries; i++)
> -		intel_uncore_write_fw(uncore,
> -				      mocs_register(engine, i),
> -				      unused_value);
> +static void init_mocs_table(struct intel_engine_cs *engine,
> +			    const struct drm_i915_mocs_table *table)
> +{
> +	__init_mocs_table(engine->uncore, table, mocs_offset(engine));
>  }
>  
>  /*
> @@ -389,7 +386,7 @@ static void init_mocs_table(struct intel_engine_cs *engine,
>  static u16 get_entry_l3cc(const struct drm_i915_mocs_table *table,
>  			  unsigned int index)
>  {
> -	if (table->table[index].used)
> +	if (index < table->size && table->table[index].used)
>  		return table->table[index].l3cc_value;
>  
>  	return table->table[I915_MOCS_PTE].l3cc_value;
> @@ -400,37 +397,23 @@ static inline u32 l3cc_combine(u16 low, u16 high)
>  	return low | (u32)high << 16;
>  }
>  
> +#define for_each_l3cc(l3cc, t, i) \
> +	for (i = 0; \
> +	     i < ((t)->n_entries + 1) / 2 ? \
> +	     (l3cc = l3cc_combine(get_entry_l3cc((t), 2 * i), \
> +				  get_entry_l3cc((t), 2 * i + 1))), 1 : \
> +	     0; \
> +	     i++)
> +
>  static void init_l3cc_table(struct intel_engine_cs *engine,
>  			    const struct drm_i915_mocs_table *table)
>  {
>  	struct intel_uncore *uncore = engine->uncore;
> -	u16 unused_value = table->table[I915_MOCS_PTE].l3cc_value;
>  	unsigned int i;
> +	u32 l3cc;
>  
> -	for (i = 0; i < table->size / 2; i++) {
> -		u16 low = get_entry_l3cc(table, 2 * i);
> -		u16 high = get_entry_l3cc(table, 2 * i + 1);
> -
> -		intel_uncore_write(uncore,
> -				   GEN9_LNCFCMOCS(i),
> -				   l3cc_combine(low, high));
> -	}
> -
> -	/* Odd table size - 1 left over */
> -	if (table->size & 1) {
> -		u16 low = get_entry_l3cc(table, 2 * i);
> -
> -		intel_uncore_write(uncore,
> -				   GEN9_LNCFCMOCS(i),
> -				   l3cc_combine(low, unused_value));
> -		i++;
> -	}
> -
> -	/* All remaining entries are also unused */
> -	for (; i < table->n_entries / 2; i++)
> -		intel_uncore_write(uncore,
> -				   GEN9_LNCFCMOCS(i),
> -				   l3cc_combine(unused_value, unused_value));
> +	for_each_l3cc(l3cc, table, i)
> +		intel_uncore_write_fw(uncore, GEN9_LNCFCMOCS(i), l3cc);
>  }
>  
>  void intel_mocs_init_engine(struct intel_engine_cs *engine)
> @@ -451,11 +434,14 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
>  		init_l3cc_table(engine, &table);
>  }
>  
> -static void intel_mocs_init_global(struct intel_gt *gt)
> +static u32 global_mocs_offset(void)
> +{
> +	return i915_mmio_reg_offset(GEN12_GLOBAL_MOCS(0));
> +}
> +
> +static void init_global_mocs(struct intel_gt *gt)
>  {
> -	struct intel_uncore *uncore = gt->uncore;
>  	struct drm_i915_mocs_table table;
> -	unsigned int index;
>  
>  	/*
>  	 * LLC and eDRAM control values are not applicable to dgfx
> @@ -463,29 +449,14 @@ static void intel_mocs_init_global(struct intel_gt *gt)
>  	if (IS_DGFX(gt->i915))
>  		return;
>  
> -	GEM_BUG_ON(!HAS_GLOBAL_MOCS_REGISTERS(gt->i915));
> -
>  	if (!get_mocs_settings(gt->i915, &table))
>  		return;
>  
> -	for (index = 0; index < table.size; index++)
> -		intel_uncore_write(uncore,
> -				   GEN12_GLOBAL_MOCS(index),
> -				   table.table[index].control_value);
> -
> -	/*
> -	 * Ok, now set the unused entries to the invalid entry (index 0). These
> -	 * entries are officially undefined and no contract for the contents and
> -	 * settings is given for these entries.
> -	 */
> -	for (; index < table.n_entries; index++)
> -		intel_uncore_write(uncore,
> -				   GEN12_GLOBAL_MOCS(index),
> -				   table.table[I915_MOCS_PTE].control_value);
> +	__init_mocs_table(gt->uncore, &table, global_mocs_offset());
>  }
>  
>  void intel_mocs_init(struct intel_gt *gt)
>  {
>  	if (HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
> -		intel_mocs_init_global(gt);
> +		init_global_mocs(gt);
>  }
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2ffcc21670b7..0960ea0b5a66 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -11688,13 +11688,18 @@ enum skl_power_gate {
>  /* MOCS (Memory Object Control State) registers */
>  #define GEN9_LNCFCMOCS(i)	_MMIO(0xb020 + (i) * 4)	/* L3 Cache Control */
>  
> -#define GEN9_GFX_MOCS(i)	_MMIO(0xc800 + (i) * 4)	/* Graphics MOCS registers */
> -#define GEN9_MFX0_MOCS(i)	_MMIO(0xc900 + (i) * 4)	/* Media 0 MOCS registers */
> -#define GEN9_MFX1_MOCS(i)	_MMIO(0xca00 + (i) * 4)	/* Media 1 MOCS registers */
> -#define GEN9_VEBOX_MOCS(i)	_MMIO(0xcb00 + (i) * 4)	/* Video MOCS registers */
> -#define GEN9_BLT_MOCS(i)	_MMIO(0xcc00 + (i) * 4)	/* Blitter MOCS registers */
> -/* Media decoder 2 MOCS registers */
> -#define GEN11_MFX2_MOCS(i)	_MMIO(0x10000 + (i) * 4)
> +#define __GEN9_RCS0_MOCS0	0xc800
> +#define GEN9_GFX_MOCS(i)	_MMIO(__GEN9_RCS0_MOCS0 + (i) * 4)
> +#define __GEN9_VCS0_MOCS0	0xc900
> +#define GEN9_MFX0_MOCS(i)	_MMIO(__GEN9_VCS0_MOCS0 + (i) * 4)
> +#define __GEN9_VCS1_MOCS0	0xca00
> +#define GEN9_MFX1_MOCS(i)	_MMIO(__GEN9_VCS1_MOCS0 + (i) * 4)
> +#define __GEN9_VECS0_MOCS0	0xcb00
> +#define GEN9_VEBOX_MOCS(i)	_MMIO(__GEN9_VECS0_MOCS0 + (i) * 4)
> +#define __GEN9_BCS0_MOCS0	0xcc00
> +#define GEN9_BLT_MOCS(i)	_MMIO(__GEN9_BCS0_MOCS0 + (i) * 4)
> +#define __GEN11_VCS2_MOCS0	0x10000
> +#define GEN11_MFX2_MOCS(i)	_MMIO(__GEN11_VCS2_MOCS0 + (i) * 4)
>  
>  #define GEN10_SCRATCH_LNCF2		_MMIO(0xb0a0)
>  #define   PMFLUSHDONE_LNICRSDROP	(1 << 20)
> -- 
> 2.24.0
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[PATCH 4/4] drm/i915/selftests: Add coverage of mocs registers

[Chris Wilson]

Probe the mocs registers for new contexts and across GPU resets. Similar
to intel_workarounds, we have tables of what register values we expect
to see, so verify that user contexts are affected by them. In the
future, we should add tests similar to intel_sseu to cover dynamic
reconfigurations.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_mocs.c          |   4 +
 drivers/gpu/drm/i915/gt/selftest_mocs.c       | 405 ++++++++++++++++++
 .../drm/i915/selftests/i915_live_selftests.h  |   1 +
 3 files changed, 410 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/gt/selftest_mocs.c

diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 445ec025bda0..06dba7ff294e 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -448,3 +448,7 @@ void intel_mocs_init(struct intel_gt *gt)
 	if (HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
 		init_global_mocs(gt);
 }
+
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftest_mocs.c"
+#endif
diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c
new file mode 100644
index 000000000000..f4dfb36f450d
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c
@@ -0,0 +1,405 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "gt/intel_engine_pm.h"
+#include "i915_selftest.h"
+
+#include "gem/selftests/mock_context.h"
+#include "selftests/igt_reset.h"
+#include "selftests/igt_spinner.h"
+
+struct live_mocs {
+	struct drm_i915_mocs_table table;
+	struct i915_vma *scratch;
+	void *vaddr;
+};
+
+static int request_add_sync(struct i915_request *rq, int err)
+{
+	i915_request_get(rq);
+	i915_request_add(rq);
+	if (i915_request_wait(rq, 0, HZ / 5) < 0)
+		err = -ETIME;
+	i915_request_put(rq);
+
+	return err;
+}
+
+static int request_add_spin(struct i915_request *rq, struct igt_spinner *spin)
+{
+	int err = 0;
+
+	i915_request_get(rq);
+	i915_request_add(rq);
+	if (spin && !igt_wait_for_spinner(spin, rq))
+		err = -ETIME;
+	i915_request_put(rq);
+
+	return err;
+}
+
+static struct i915_vma *create_scratch(struct intel_gt *gt)
+{
+	struct drm_i915_gem_object *obj;
+	struct i915_vma *vma;
+	int err;
+
+	obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE);
+	if (IS_ERR(obj))
+		return ERR_CAST(obj);
+
+	i915_gem_object_set_cache_coherency(obj, I915_CACHING_CACHED);
+
+	vma = i915_vma_instance(obj, &gt->ggtt->vm, NULL);
+	if (IS_ERR(vma)) {
+		i915_gem_object_put(obj);
+		return vma;
+	}
+
+	err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL);
+	if (err) {
+		i915_gem_object_put(obj);
+		return ERR_PTR(err);
+	}
+
+	return vma;
+}
+
+static int live_mocs_init(struct live_mocs *arg, struct intel_gt *gt)
+{
+	int err;
+
+	if (!get_mocs_settings(gt->i915, &arg->table))
+		return -EINVAL;
+
+	arg->scratch = create_scratch(gt);
+	if (IS_ERR(arg->scratch))
+		return PTR_ERR(arg->scratch);
+
+	arg->vaddr = i915_gem_object_pin_map(arg->scratch->obj, I915_MAP_WB);
+	if (IS_ERR(arg->vaddr)) {
+		err = PTR_ERR(arg->vaddr);
+		goto err_scratch;
+	}
+
+	return 0;
+
+err_scratch:
+	i915_vma_unpin_and_release(&arg->scratch, 0);
+	return err;
+}
+
+static void live_mocs_fini(struct live_mocs *arg)
+{
+	i915_vma_unpin_and_release(&arg->scratch, I915_VMA_RELEASE_MAP);
+}
+
+static int read_mocs_table(struct i915_request *rq,
+			   const struct drm_i915_mocs_table *table,
+			   uint32_t *offset)
+{
+	unsigned int i;
+	u32 addr;
+	u32 *cs;
+
+	GEM_BUG_ON(!IS_ALIGNED(*offset, sizeof(u32)));
+
+	if (HAS_GLOBAL_MOCS_REGISTERS(rq->i915))
+		addr = 0x4000;
+	else
+		addr = mocs_register(rq->engine);
+
+	cs = intel_ring_begin(rq, 4 * table->n_entries);
+	if (IS_ERR(cs))
+		return PTR_ERR(cs);
+
+	for (i = 0; i < table->n_entries; i++) {
+		*cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
+		*cs++ = addr;
+		*cs++ = *offset;
+		*cs++ = 0;
+
+		addr += sizeof(u32);
+		*offset += sizeof(u32);
+	}
+
+	intel_ring_advance(rq, cs);
+
+	return 0;
+}
+
+static int read_l3cc_table(struct i915_request *rq,
+			   const struct drm_i915_mocs_table *table,
+			   uint32_t *offset)
+{
+	u32 addr = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0));
+	unsigned int i;
+	u32 *cs;
+
+	GEM_BUG_ON(!IS_ALIGNED(*offset, sizeof(u32)));
+
+	cs = intel_ring_begin(rq, (table->n_entries + 1) / 2 * 4);
+	if (IS_ERR(cs))
+		return PTR_ERR(cs);
+
+	/* Can we read the MCR range 0xb00 directly? See intel_workarounds! */
+	for (i = 0; i < (table->n_entries + 1) / 2; i++) {
+		*cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
+		*cs++ = addr;
+		*cs++ = *offset;
+		*cs++ = 0;
+
+		addr += sizeof(u32);
+		*offset += sizeof(u32);
+	}
+
+	intel_ring_advance(rq, cs);
+
+	return 0;
+}
+
+static int check_mocs_table(struct intel_engine_cs *engine,
+			    const struct drm_i915_mocs_table *table,
+			    uint32_t **vaddr)
+{
+	unsigned int i;
+	u32 expect;
+
+	for_each_mocs(expect, table, i) {
+		if (**vaddr != expect) {
+			pr_err("%s: Invalid MOCS[%d] entry, found %08x, expected %08x\n",
+			       engine->name, i, **vaddr, expect);
+			return -EINVAL;
+		}
+		++*vaddr;
+	}
+
+	return 0;
+}
+
+static int check_l3cc_table(struct intel_engine_cs *engine,
+			    const struct drm_i915_mocs_table *table,
+			    uint32_t **vaddr)
+{
+	unsigned int i;
+	u32 expect;
+
+	for_each_l3cc(expect, table, i) {
+		if (**vaddr != expect) {
+			pr_err("%s: Invalid L3CC[%d] entry, found %08x, expected %08x\n",
+			       engine->name, i, **vaddr, expect);
+			return -EINVAL;
+		}
+		++*vaddr;
+	}
+
+	return 0;
+}
+
+static int check_mocs_engine(struct live_mocs *arg,
+			     struct intel_context *ce)
+{
+	struct i915_vma *vma = arg->scratch;
+	struct i915_request *rq;
+	u32 offset;
+	u32 *vaddr;
+	int err;
+
+	memset32(arg->vaddr, STACK_MAGIC, PAGE_SIZE / sizeof(u32));
+
+	rq = intel_context_create_request(ce);
+	if (IS_ERR(rq))
+		return PTR_ERR(rq);
+
+	i915_vma_lock(vma);
+	err = i915_request_await_object(rq, vma->obj, true);
+	if (!err)
+		err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
+	i915_vma_unlock(vma);
+
+	offset = i915_ggtt_offset(vma);
+	if (!err)
+		err = read_mocs_table(rq, &arg->table, &offset);
+	if (!err && ce->engine->class == RENDER_CLASS)
+		err = read_l3cc_table(rq, &arg->table, &offset);
+	offset -= i915_ggtt_offset(vma);
+	GEM_BUG_ON(offset > PAGE_SIZE);
+
+	err = request_add_sync(rq, err);
+	if (err)
+		return err;
+
+	vaddr = arg->vaddr;
+	if (!err)
+		err = check_mocs_table(ce->engine, &arg->table, &vaddr);
+	if (!err && ce->engine->class == RENDER_CLASS)
+		err = check_l3cc_table(ce->engine, &arg->table, &vaddr);
+	if (err)
+		return err;
+
+	GEM_BUG_ON(arg->vaddr + offset != vaddr);
+	return 0;
+}
+
+static int live_mocs_kernel(void *arg)
+{
+	struct intel_gt *gt = arg;
+	struct intel_engine_cs *engine;
+	enum intel_engine_id id;
+	struct live_mocs mocs;
+	int err;
+
+	err = live_mocs_init(&mocs, gt);
+	if (err)
+		return err;
+
+	for_each_engine(engine, gt, id) {
+		err = check_mocs_engine(&mocs, engine->kernel_context);
+		if (err)
+			break;
+	}
+
+	live_mocs_fini(&mocs);
+	return err;
+}
+
+static int live_mocs_clean(void *arg)
+{
+	struct intel_gt *gt = arg;
+	struct intel_engine_cs *engine;
+	enum intel_engine_id id;
+	struct live_mocs mocs;
+	int err;
+
+	err = live_mocs_init(&mocs, gt);
+	if (err)
+		return err;
+
+	for_each_engine(engine, gt, id) {
+		struct intel_context *ce;
+
+		ce = intel_context_create(engine->kernel_context->gem_context,
+					  engine);
+		if (IS_ERR(ce)) {
+			err = PTR_ERR(ce);
+			break;
+		}
+
+		err = check_mocs_engine(&mocs, ce);
+		intel_context_put(ce);
+		if (err)
+			break;
+	}
+
+	live_mocs_fini(&mocs);
+	return err;
+}
+
+static int active_engine_reset(struct intel_context *ce,
+			       const char *reason)
+{
+	struct igt_spinner spin;
+	struct i915_request *rq;
+	int err;
+
+	err = igt_spinner_init(&spin, ce->engine->gt);
+	if (err)
+		return err;
+
+	rq = igt_spinner_create_request(&spin, ce, MI_NOOP);
+	if (IS_ERR(rq)) {
+		igt_spinner_fini(&spin);
+		return PTR_ERR(rq);
+	}
+
+	err = request_add_spin(rq, &spin);
+	if (err == 0)
+		err = intel_engine_reset(ce->engine, reason);
+
+	igt_spinner_end(&spin);
+	igt_spinner_fini(&spin);
+
+	return err;
+}
+
+static int __live_mocs_reset(struct live_mocs *mocs,
+			     struct intel_context *ce)
+{
+	int err;
+
+	err = intel_engine_reset(ce->engine, "mocs");
+	if (err)
+		return err;
+
+	err = check_mocs_engine(mocs, ce);
+	if (err)
+		return err;
+
+	err = active_engine_reset(ce, "mocs");
+	if (err)
+		return err;
+
+	err = check_mocs_engine(mocs, ce);
+	if (err)
+		return err;
+
+	return 0;
+}
+
+static int live_mocs_reset(void *arg)
+{
+	struct intel_gt *gt = arg;
+	struct intel_engine_cs *engine;
+	enum intel_engine_id id;
+	struct live_mocs mocs;
+	int err = 0;
+
+	if (!intel_has_reset_engine(gt))
+		return 0;
+
+	err = live_mocs_init(&mocs, gt);
+	if (err)
+		return err;
+
+	igt_global_reset_lock(gt);
+	for_each_engine(engine, gt, id) {
+		struct intel_context *ce;
+
+		ce = intel_context_create(engine->kernel_context->gem_context,
+					  engine);
+		if (IS_ERR(ce)) {
+			err = PTR_ERR(ce);
+			break;
+		}
+
+		intel_engine_pm_get(engine);
+		err = __live_mocs_reset(&mocs, ce);
+		intel_engine_pm_put(engine);
+
+		intel_context_put(ce);
+		if (err)
+			break;
+	}
+	igt_global_reset_unlock(gt);
+
+	live_mocs_fini(&mocs);
+	return err;
+}
+
+int intel_mocs_live_selftests(struct drm_i915_private *i915)
+{
+	static const struct i915_subtest tests[] = {
+		SUBTEST(live_mocs_kernel),
+		SUBTEST(live_mocs_clean),
+		SUBTEST(live_mocs_reset),
+	};
+	struct drm_i915_mocs_table table;
+
+	if (!get_mocs_settings(i915, &table))
+		return 0;
+
+	return intel_gt_live_subtests(tests, &i915->gt);
+}
diff --git a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
index 00a063730bc3..c23d06bca09e 100644
--- a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
@@ -16,6 +16,7 @@ selftest(gt_engines, intel_engine_live_selftests)
 selftest(gt_timelines, intel_timeline_live_selftests)
 selftest(gt_contexts, intel_context_live_selftests)
 selftest(gt_lrc, intel_lrc_live_selftests)
+selftest(gt_mocs, intel_mocs_live_selftests)
 selftest(gt_pm, intel_gt_pm_live_selftests)
 selftest(gt_heartbeat, intel_heartbeat_live_selftests)
 selftest(requests, i915_request_live_selftests)
-- 
2.24.0.rc0

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