* [Intel-gfx] [PATCH 1/2] drm/i915/selftest: Analyse timestamp behaviour across context switches
@ 2020-02-19 11:20 Chris Wilson
2020-02-19 11:20 ` [Intel-gfx] [PATCH 2/2] drm/i915/selftests: Mark GPR checking more hostile Chris Wilson
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: Chris Wilson @ 2020-02-19 11:20 UTC (permalink / raw)
To: intel-gfx
Check that the CTX_TIMESTAMP is monotonic across context save/restore
and upon preemption.
References: https://gitlab.freedesktop.org/drm/intel/issues/1233
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 229 +++++++++++++++++++++++++
1 file changed, 229 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index a9c9cfb2def8..52eb1a8a1a9a 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -3985,6 +3985,36 @@ static void hexdump(const void *buf, size_t len)
}
}
+static int emit_semaphore_signal(struct intel_context *ce, void *slot)
+{
+ const u32 offset =
+ i915_ggtt_offset(ce->engine->status_page.vma) +
+ offset_in_page(slot);
+ struct i915_request *rq;
+ u32 *cs;
+
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ cs = intel_ring_begin(rq, 4);
+ if (IS_ERR(cs)) {
+ i915_request_add(rq);
+ return PTR_ERR(cs);
+ }
+
+ *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
+ *cs++ = offset;
+ *cs++ = 0;
+ *cs++ = 1;
+
+ intel_ring_advance(rq, cs);
+
+ rq->sched.attr.priority = I915_PRIORITY_BARRIER;
+ i915_request_add(rq);
+ return 0;
+}
+
static int live_lrc_layout(void *arg)
{
struct intel_gt *gt = arg;
@@ -4455,6 +4485,204 @@ static int live_gpr_clear(void *arg)
return err;
}
+static struct i915_request *
+create_timestamp(struct intel_context *ce, void *slot, int idx)
+{
+ const u32 offset =
+ i915_ggtt_offset(ce->engine->status_page.vma) +
+ offset_in_page(slot);
+ struct i915_request *rq;
+ u32 *cs;
+ int err;
+
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq))
+ return rq;
+
+ cs = intel_ring_begin(rq, 10);
+ if (IS_ERR(cs)) {
+ err = PTR_ERR(cs);
+ goto err;
+ }
+
+ *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
+ *cs++ = MI_NOOP;
+
+ *cs++ = MI_SEMAPHORE_WAIT |
+ MI_SEMAPHORE_GLOBAL_GTT |
+ MI_SEMAPHORE_POLL |
+ MI_SEMAPHORE_SAD_NEQ_SDD;
+ *cs++ = 0;
+ *cs++ = offset;
+ *cs++ = 0;
+
+ *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
+ *cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(rq->engine->mmio_base));
+ *cs++ = offset + idx * sizeof(u32);
+ *cs++ = 0;
+
+ intel_ring_advance(rq, cs);
+
+ rq->sched.attr.priority = I915_PRIORITY_MASK;
+ err = 0;
+err:
+ i915_request_get(rq);
+ i915_request_add(rq);
+ if (err) {
+ i915_request_put(rq);
+ return ERR_PTR(err);
+ }
+
+ return rq;
+}
+
+struct lrc_timestamp {
+ struct intel_engine_cs *engine;
+ struct intel_context *ce[2];
+ u32 poison;
+};
+
+static bool timestamp_advanced(u32 start, u32 end)
+{
+ return (s32)(end - start) > 0;
+}
+
+static int __lrc_timestamp(const struct lrc_timestamp *arg, bool preempt)
+{
+ u32 *slot = memset32(arg->engine->status_page.addr + 1000, 0, 4);
+ struct i915_request *rq;
+ u32 timestamp;
+ int err = 0;
+
+ arg->ce[0]->lrc_reg_state[CTX_TIMESTAMP] = arg->poison;
+ rq = create_timestamp(arg->ce[0], slot, 1);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ err = wait_for_submit(rq->engine, rq, HZ / 2);
+ if (err)
+ goto err;
+
+ if (preempt) {
+ arg->ce[1]->lrc_reg_state[CTX_TIMESTAMP] = 0xdeadbeef;
+ err = emit_semaphore_signal(arg->ce[1], slot);
+ if (err)
+ goto err;
+ } else {
+ slot[0] = 1;
+ wmb();
+ }
+
+ if (i915_request_wait(rq, 0, HZ / 2) < 0) {
+ err = -ETIME;
+ goto err;
+ }
+
+ /* and wait for switch to kernel */
+ if (igt_flush_test(arg->engine->i915)) {
+ err = -EIO;
+ goto err;
+ }
+
+ rmb();
+
+ if (!timestamp_advanced(arg->poison, slot[1])) {
+ pr_err("%s(%s): invalid timestamp on restore, context:%x, request:%x\n",
+ arg->engine->name, preempt ? "preempt" : "simple",
+ arg->poison, slot[1]);
+ err = -EINVAL;
+ }
+
+ timestamp = READ_ONCE(arg->ce[0]->lrc_reg_state[CTX_TIMESTAMP]);
+ if (!timestamp_advanced(slot[1], timestamp)) {
+ pr_err("%s(%s): invalid timestamp on save, request:%x, context:%x\n",
+ arg->engine->name, preempt ? "preempt" : "simple",
+ slot[1], timestamp);
+ err = -EINVAL;
+ }
+
+err:
+ memset32(slot, -1, 4);
+ i915_request_put(rq);
+ return err;
+}
+
+static int live_lrc_timestamp(void *arg)
+{
+ struct intel_gt *gt = arg;
+ enum intel_engine_id id;
+ struct lrc_timestamp data;
+ const u32 poison[] = {
+ 0,
+ S32_MAX,
+ (u32)S32_MAX + 1,
+ U32_MAX,
+ };
+
+ /*
+ * We want to verify that the timestamp is saved and restore across
+ * context switches and is monotonic.
+ *
+ * So we do this with a little bit of LRC poisoning to check various
+ * boundary conditions, and see what happens if we preempt the context
+ * with a second request (carrying more poison into the timestamp).
+ */
+
+ for_each_engine(data.engine, gt, id) {
+ unsigned long heartbeat;
+ int i, err = 0;
+
+ engine_heartbeat_disable(data.engine, &heartbeat);
+
+ for (i = 0; i < ARRAY_SIZE(data.ce); i++) {
+ struct intel_context *tmp;
+
+ tmp = intel_context_create(data.engine);
+ if (IS_ERR(tmp)) {
+ err = PTR_ERR(tmp);
+ goto err;
+ }
+
+ err = intel_context_pin(tmp);
+ if (err) {
+ intel_context_put(tmp);
+ goto err;
+ }
+
+ data.ce[i] = tmp;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(poison); i++) {
+ data.poison = poison[i];
+
+ err = __lrc_timestamp(&data, false);
+ if (err)
+ break;
+
+ err = __lrc_timestamp(&data, true);
+ if (err)
+ break;
+ }
+
+err:
+ engine_heartbeat_enable(data.engine, heartbeat);
+ for (i = 0; i < ARRAY_SIZE(data.ce); i++) {
+ if (!data.ce[i])
+ break;
+
+ intel_context_unpin(data.ce[i]);
+ intel_context_put(data.ce[i]);
+ }
+
+ if (igt_flush_test(gt->i915))
+ err = -EIO;
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
static int __live_pphwsp_runtime(struct intel_engine_cs *engine)
{
struct intel_context *ce;
@@ -4552,6 +4780,7 @@ int intel_lrc_live_selftests(struct drm_i915_private *i915)
SUBTEST(live_lrc_fixed),
SUBTEST(live_lrc_state),
SUBTEST(live_gpr_clear),
+ SUBTEST(live_lrc_timestamp),
SUBTEST(live_pphwsp_runtime),
};
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/i915/selftests: Mark GPR checking more hostile
2020-02-19 11:20 [Intel-gfx] [PATCH 1/2] drm/i915/selftest: Analyse timestamp behaviour across context switches Chris Wilson
@ 2020-02-19 11:20 ` Chris Wilson
2020-02-19 12:34 ` [Intel-gfx] [PATCH v2] " Chris Wilson
2020-02-19 11:59 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/selftest: Analyse timestamp behaviour across context switches Patchwork
` (2 subsequent siblings)
3 siblings, 1 reply; 6+ messages in thread
From: Chris Wilson @ 2020-02-19 11:20 UTC (permalink / raw)
To: intel-gfx
Currently, we check that a new context has a clear set of general
purpose registers. Add a little bit of hostility by preempting our new
context and re-poisoning the GPR to ensure that there is no context
leakage from preemption.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 125 ++++++++++++++++++-------
1 file changed, 93 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 52eb1a8a1a9a..4eba2b3ec81d 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -4344,13 +4344,13 @@ static int live_lrc_state(void *arg)
return err;
}
-static int gpr_make_dirty(struct intel_engine_cs *engine)
+static int gpr_make_dirty(struct intel_context *ce)
{
struct i915_request *rq;
u32 *cs;
int n;
- rq = intel_engine_create_kernel_request(engine);
+ rq = intel_context_create_request(ce);
if (IS_ERR(rq))
return PTR_ERR(rq);
@@ -4362,53 +4362,54 @@ static int gpr_make_dirty(struct intel_engine_cs *engine)
*cs++ = MI_LOAD_REGISTER_IMM(NUM_GPR_DW);
for (n = 0; n < NUM_GPR_DW; n++) {
- *cs++ = CS_GPR(engine, n);
+ *cs++ = CS_GPR(ce->engine, n);
*cs++ = STACK_MAGIC;
}
*cs++ = MI_NOOP;
intel_ring_advance(rq, cs);
+
+ rq->sched.attr.priority = I915_PRIORITY_BARRIER;
i915_request_add(rq);
return 0;
}
-static int __live_gpr_clear(struct intel_engine_cs *engine,
- struct i915_vma *scratch)
+static struct i915_request *
+__gpr_read(struct intel_context *ce, struct i915_vma *scratch, u32 *slot)
{
- struct intel_context *ce;
+ const u32 offset =
+ i915_ggtt_offset(ce->engine->status_page.vma) +
+ offset_in_page(slot);
struct i915_request *rq;
u32 *cs;
int err;
int n;
- if (INTEL_GEN(engine->i915) < 9 && engine->class != RENDER_CLASS)
- return 0; /* GPR only on rcs0 for gen8 */
-
- err = gpr_make_dirty(engine);
- if (err)
- return err;
-
- ce = intel_context_create(engine);
- if (IS_ERR(ce))
- return PTR_ERR(ce);
-
rq = intel_context_create_request(ce);
- if (IS_ERR(rq)) {
- err = PTR_ERR(rq);
- goto err_put;
- }
+ if (IS_ERR(rq))
+ return rq;
- cs = intel_ring_begin(rq, 4 * NUM_GPR_DW);
+ cs = intel_ring_begin(rq, 6 + 4 * NUM_GPR_DW);
if (IS_ERR(cs)) {
- err = PTR_ERR(cs);
i915_request_add(rq);
- goto err_put;
+ return ERR_CAST(cs);
}
+ *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
+ *cs++ = MI_NOOP;
+
+ *cs++ = MI_SEMAPHORE_WAIT |
+ MI_SEMAPHORE_GLOBAL_GTT |
+ MI_SEMAPHORE_POLL |
+ MI_SEMAPHORE_SAD_NEQ_SDD;
+ *cs++ = 0;
+ *cs++ = offset;
+ *cs++ = 0;
+
for (n = 0; n < NUM_GPR_DW; n++) {
*cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
- *cs++ = CS_GPR(engine, n);
+ *cs++ = CS_GPR(ce->engine, n);
*cs++ = i915_ggtt_offset(scratch) + n * sizeof(u32);
*cs++ = 0;
}
@@ -4421,8 +4422,54 @@ static int __live_gpr_clear(struct intel_engine_cs *engine,
i915_request_get(rq);
i915_request_add(rq);
+ if (err) {
+ i915_request_put(rq);
+ rq = ERR_PTR(err);
+ }
+
+ return rq;
+}
+
+static int __live_lrc_gpr(struct intel_engine_cs *engine,
+ struct i915_vma *scratch,
+ bool preempt)
+{
+ u32 *slot = memset32(engine->status_page.addr + 1000, 0, 4);
+ struct intel_context *ce;
+ struct i915_request *rq;
+ u32 *cs;
+ int err;
+ int n;
+
+ if (INTEL_GEN(engine->i915) < 9 && engine->class != RENDER_CLASS)
+ return 0; /* GPR only on rcs0 for gen8 */
+
+ err = gpr_make_dirty(engine->kernel_context);
if (err)
- goto err_rq;
+ return err;
+
+ ce = intel_context_create(engine);
+ if (IS_ERR(ce))
+ return PTR_ERR(ce);
+
+ rq = __gpr_read(ce, scratch, slot);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto err_put;
+ }
+
+ if (preempt) {
+ err = gpr_make_dirty(engine->kernel_context);
+ if (err)
+ goto err_rq;
+
+ err = emit_semaphore_signal(engine->kernel_context, slot);
+ if (err)
+ goto err_rq;
+ } else {
+ slot[0] = 1;
+ wmb();
+ }
if (i915_request_wait(rq, 0, HZ / 5) < 0) {
err = -ETIME;
@@ -4449,13 +4496,15 @@ static int __live_gpr_clear(struct intel_engine_cs *engine,
i915_gem_object_unpin_map(scratch->obj);
err_rq:
+ memset32(&slot[0], -1, 4);
+ wmb();
i915_request_put(rq);
err_put:
intel_context_put(ce);
return err;
}
-static int live_gpr_clear(void *arg)
+static int live_lrc_gpr(void *arg)
{
struct intel_gt *gt = arg;
struct intel_engine_cs *engine;
@@ -4473,14 +4522,26 @@ static int live_gpr_clear(void *arg)
return PTR_ERR(scratch);
for_each_engine(engine, gt, id) {
- err = __live_gpr_clear(engine, scratch);
+ unsigned long heartbeat;
+
+ engine_heartbeat_disable(engine, &heartbeat);
+
+ err = __live_lrc_gpr(engine, scratch, false);
+ if (err)
+ goto err;
+
+ err = __live_lrc_gpr(engine, scratch, true);
+ if (err)
+ goto err;
+
+err:
+ engine_heartbeat_enable(engine, heartbeat);
+ if (igt_flush_test(gt->i915))
+ err = -EIO;
if (err)
break;
}
- if (igt_flush_test(gt->i915))
- err = -EIO;
-
i915_vma_unpin_and_release(&scratch, 0);
return err;
}
@@ -4779,7 +4840,7 @@ int intel_lrc_live_selftests(struct drm_i915_private *i915)
SUBTEST(live_lrc_layout),
SUBTEST(live_lrc_fixed),
SUBTEST(live_lrc_state),
- SUBTEST(live_gpr_clear),
+ SUBTEST(live_lrc_gpr),
SUBTEST(live_lrc_timestamp),
SUBTEST(live_pphwsp_runtime),
};
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/selftest: Analyse timestamp behaviour across context switches
2020-02-19 11:20 [Intel-gfx] [PATCH 1/2] drm/i915/selftest: Analyse timestamp behaviour across context switches Chris Wilson
2020-02-19 11:20 ` [Intel-gfx] [PATCH 2/2] drm/i915/selftests: Mark GPR checking more hostile Chris Wilson
@ 2020-02-19 11:59 ` Patchwork
2020-02-19 12:22 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-02-19 15:55 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/2] drm/i915/selftest: Analyse timestamp behaviour across context switches (rev2) Patchwork
3 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2020-02-19 11:59 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/selftest: Analyse timestamp behaviour across context switches
URL : https://patchwork.freedesktop.org/series/73637/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e360e7c59c3d drm/i915/selftest: Analyse timestamp behaviour across context switches
-:143: WARNING:MEMORY_BARRIER: memory barrier without comment
#143: FILE: drivers/gpu/drm/i915/gt/selftest_lrc.c:4573:
+ wmb();
-:157: WARNING:MEMORY_BARRIER: memory barrier without comment
#157: FILE: drivers/gpu/drm/i915/gt/selftest_lrc.c:4587:
+ rmb();
total: 0 errors, 2 warnings, 0 checks, 247 lines checked
e95291057367 drm/i915/selftests: Mark GPR checking more hostile
-:162: WARNING:MEMORY_BARRIER: memory barrier without comment
#162: FILE: drivers/gpu/drm/i915/gt/selftest_lrc.c:4471:
+ wmb();
-:172: WARNING:MEMORY_BARRIER: memory barrier without comment
#172: FILE: drivers/gpu/drm/i915/gt/selftest_lrc.c:4500:
+ wmb();
total: 0 errors, 2 warnings, 0 checks, 201 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/selftest: Analyse timestamp behaviour across context switches
2020-02-19 11:20 [Intel-gfx] [PATCH 1/2] drm/i915/selftest: Analyse timestamp behaviour across context switches Chris Wilson
2020-02-19 11:20 ` [Intel-gfx] [PATCH 2/2] drm/i915/selftests: Mark GPR checking more hostile Chris Wilson
2020-02-19 11:59 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/selftest: Analyse timestamp behaviour across context switches Patchwork
@ 2020-02-19 12:22 ` Patchwork
2020-02-19 15:55 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/2] drm/i915/selftest: Analyse timestamp behaviour across context switches (rev2) Patchwork
3 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2020-02-19 12:22 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/selftest: Analyse timestamp behaviour across context switches
URL : https://patchwork.freedesktop.org/series/73637/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7963 -> Patchwork_16619
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16619/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_16619:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live_gt_lrc:
- {fi-tgl-u}: [INCOMPLETE][1] ([i915#1233]) -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7963/fi-tgl-u/igt@i915_selftest@live_gt_lrc.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16619/fi-tgl-u/igt@i915_selftest@live_gt_lrc.html
- {fi-tgl-dsi}: [INCOMPLETE][3] ([i915#1233]) -> [DMESG-FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7963/fi-tgl-dsi/igt@i915_selftest@live_gt_lrc.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16619/fi-tgl-dsi/igt@i915_selftest@live_gt_lrc.html
Known issues
------------
Here are the changes found in Patchwork_16619 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-guc: [PASS][5] -> [DMESG-FAIL][6] ([i915#623])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7963/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16619/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html
* igt@i915_selftest@live_gtt:
- fi-cfl-guc: [PASS][7] -> [TIMEOUT][8] ([fdo#112271])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7963/fi-cfl-guc/igt@i915_selftest@live_gtt.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16619/fi-cfl-guc/igt@i915_selftest@live_gtt.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u3: [PASS][9] -> [DMESG-WARN][10] ([i915#585]) +37 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7963/fi-icl-u3/igt@kms_frontbuffer_tracking@basic.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16619/fi-icl-u3/igt@kms_frontbuffer_tracking@basic.html
#### Possible fixes ####
* igt@gem_close_race@basic-threads:
- fi-byt-j1900: [INCOMPLETE][11] ([i915#45]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7963/fi-byt-j1900/igt@gem_close_race@basic-threads.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16619/fi-byt-j1900/igt@gem_close_race@basic-threads.html
- fi-byt-n2820: [INCOMPLETE][13] ([i915#45]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7963/fi-byt-n2820/igt@gem_close_race@basic-threads.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16619/fi-byt-n2820/igt@gem_close_race@basic-threads.html
* igt@gem_exec_parallel@contexts:
- {fi-ehl-1}: [INCOMPLETE][15] ([i915#937]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7963/fi-ehl-1/igt@gem_exec_parallel@contexts.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16619/fi-ehl-1/igt@gem_exec_parallel@contexts.html
* igt@i915_selftest@live_active:
- fi-icl-dsi: [DMESG-FAIL][17] ([i915#765]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7963/fi-icl-dsi/igt@i915_selftest@live_active.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16619/fi-icl-dsi/igt@i915_selftest@live_active.html
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-8700k: [INCOMPLETE][19] ([i915#424]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7963/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16619/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html
- fi-cml-s: [DMESG-FAIL][21] ([i915#877]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7963/fi-cml-s/igt@i915_selftest@live_gem_contexts.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16619/fi-cml-s/igt@i915_selftest@live_gem_contexts.html
* igt@i915_selftest@live_gt_heartbeat:
- fi-kbl-7500u: [DMESG-FAIL][23] ([fdo#112406]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7963/fi-kbl-7500u/igt@i915_selftest@live_gt_heartbeat.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16619/fi-kbl-7500u/igt@i915_selftest@live_gt_heartbeat.html
* igt@kms_flip@basic-flip-vs-wf_vblank:
- fi-bsw-n3050: [FAIL][25] ([i915#34]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7963/fi-bsw-n3050/igt@kms_flip@basic-flip-vs-wf_vblank.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16619/fi-bsw-n3050/igt@kms_flip@basic-flip-vs-wf_vblank.html
#### Warnings ####
* igt@amdgpu/amd_prime@amd-to-i915:
- fi-icl-u3: [SKIP][27] ([fdo#109315]) -> [SKIP][28] ([fdo#109315] / [i915#585])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7963/fi-icl-u3/igt@amdgpu/amd_prime@amd-to-i915.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16619/fi-icl-u3/igt@amdgpu/amd_prime@amd-to-i915.html
* igt@i915_pm_rpm@basic-rte:
- fi-kbl-guc: [FAIL][29] ([i915#579]) -> [SKIP][30] ([fdo#109271])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7963/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16619/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html
* igt@kms_chamelium@dp-hpd-fast:
- fi-icl-u3: [SKIP][31] ([fdo#109284] / [fdo#111827]) -> [SKIP][32] ([fdo#109284] / [fdo#111827] / [i915#585])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7963/fi-icl-u3/igt@kms_chamelium@dp-hpd-fast.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16619/fi-icl-u3/igt@kms_chamelium@dp-hpd-fast.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-icl-u3: [SKIP][33] ([fdo#109285]) -> [SKIP][34] ([fdo#109285] / [i915#585])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7963/fi-icl-u3/igt@kms_force_connector_basic@force-load-detect.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16619/fi-icl-u3/igt@kms_force_connector_basic@force-load-detect.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271
[fdo#112406]: https://bugs.freedesktop.org/show_bug.cgi?id=112406
[i915#1233]: https://gitlab.freedesktop.org/drm/intel/issues/1233
[i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
[i915#424]: https://gitlab.freedesktop.org/drm/intel/issues/424
[i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45
[i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579
[i915#585]: https://gitlab.freedesktop.org/drm/intel/issues/585
[i915#623]: https://gitlab.freedesktop.org/drm/intel/issues/623
[i915#765]: https://gitlab.freedesktop.org/drm/intel/issues/765
[i915#877]: https://gitlab.freedesktop.org/drm/intel/issues/877
[i915#937]: https://gitlab.freedesktop.org/drm/intel/issues/937
Participating hosts (50 -> 45)
------------------------------
Missing (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7963 -> Patchwork_16619
CI-20190529: 20190529
CI_DRM_7963: e0d737598eb749378a5dc4ed3dfafc6f79d512cb @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5448: 116020b1f83c1b3994c76882df7f77b6731d78ba @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16619: e9529105736741b37acc174ea5ae7247e26757bb @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
e95291057367 drm/i915/selftests: Mark GPR checking more hostile
e360e7c59c3d drm/i915/selftest: Analyse timestamp behaviour across context switches
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16619/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Intel-gfx] [PATCH v2] drm/i915/selftests: Mark GPR checking more hostile
2020-02-19 11:20 ` [Intel-gfx] [PATCH 2/2] drm/i915/selftests: Mark GPR checking more hostile Chris Wilson
@ 2020-02-19 12:34 ` Chris Wilson
0 siblings, 0 replies; 6+ messages in thread
From: Chris Wilson @ 2020-02-19 12:34 UTC (permalink / raw)
To: intel-gfx
Currently, we check that a new context has a clear set of general
purpose registers. Add a little bit of hostility by preempting our new
context and re-poisoning the GPR to ensure that there is no context
leakage from preemption.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 127 +++++++++++++++++++------
1 file changed, 96 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 52eb1a8a1a9a..49b93cda04ca 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -4344,13 +4344,13 @@ static int live_lrc_state(void *arg)
return err;
}
-static int gpr_make_dirty(struct intel_engine_cs *engine)
+static int gpr_make_dirty(struct intel_context *ce)
{
struct i915_request *rq;
u32 *cs;
int n;
- rq = intel_engine_create_kernel_request(engine);
+ rq = intel_context_create_request(ce);
if (IS_ERR(rq))
return PTR_ERR(rq);
@@ -4362,53 +4362,54 @@ static int gpr_make_dirty(struct intel_engine_cs *engine)
*cs++ = MI_LOAD_REGISTER_IMM(NUM_GPR_DW);
for (n = 0; n < NUM_GPR_DW; n++) {
- *cs++ = CS_GPR(engine, n);
+ *cs++ = CS_GPR(ce->engine, n);
*cs++ = STACK_MAGIC;
}
*cs++ = MI_NOOP;
intel_ring_advance(rq, cs);
+
+ rq->sched.attr.priority = I915_PRIORITY_BARRIER;
i915_request_add(rq);
return 0;
}
-static int __live_gpr_clear(struct intel_engine_cs *engine,
- struct i915_vma *scratch)
+static struct i915_request *
+__gpr_read(struct intel_context *ce, struct i915_vma *scratch, u32 *slot)
{
- struct intel_context *ce;
+ const u32 offset =
+ i915_ggtt_offset(ce->engine->status_page.vma) +
+ offset_in_page(slot);
struct i915_request *rq;
u32 *cs;
int err;
int n;
- if (INTEL_GEN(engine->i915) < 9 && engine->class != RENDER_CLASS)
- return 0; /* GPR only on rcs0 for gen8 */
-
- err = gpr_make_dirty(engine);
- if (err)
- return err;
-
- ce = intel_context_create(engine);
- if (IS_ERR(ce))
- return PTR_ERR(ce);
-
rq = intel_context_create_request(ce);
- if (IS_ERR(rq)) {
- err = PTR_ERR(rq);
- goto err_put;
- }
+ if (IS_ERR(rq))
+ return rq;
- cs = intel_ring_begin(rq, 4 * NUM_GPR_DW);
+ cs = intel_ring_begin(rq, 6 + 4 * NUM_GPR_DW);
if (IS_ERR(cs)) {
- err = PTR_ERR(cs);
i915_request_add(rq);
- goto err_put;
+ return ERR_CAST(cs);
}
+ *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
+ *cs++ = MI_NOOP;
+
+ *cs++ = MI_SEMAPHORE_WAIT |
+ MI_SEMAPHORE_GLOBAL_GTT |
+ MI_SEMAPHORE_POLL |
+ MI_SEMAPHORE_SAD_NEQ_SDD;
+ *cs++ = 0;
+ *cs++ = offset;
+ *cs++ = 0;
+
for (n = 0; n < NUM_GPR_DW; n++) {
*cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
- *cs++ = CS_GPR(engine, n);
+ *cs++ = CS_GPR(ce->engine, n);
*cs++ = i915_ggtt_offset(scratch) + n * sizeof(u32);
*cs++ = 0;
}
@@ -4421,9 +4422,59 @@ static int __live_gpr_clear(struct intel_engine_cs *engine,
i915_request_get(rq);
i915_request_add(rq);
+ if (err) {
+ i915_request_put(rq);
+ rq = ERR_PTR(err);
+ }
+
+ return rq;
+}
+
+static int __live_lrc_gpr(struct intel_engine_cs *engine,
+ struct i915_vma *scratch,
+ bool preempt)
+{
+ u32 *slot = memset32(engine->status_page.addr + 1000, 0, 4);
+ struct intel_context *ce;
+ struct i915_request *rq;
+ u32 *cs;
+ int err;
+ int n;
+
+ if (INTEL_GEN(engine->i915) < 9 && engine->class != RENDER_CLASS)
+ return 0; /* GPR only on rcs0 for gen8 */
+
+ err = gpr_make_dirty(engine->kernel_context);
+ if (err)
+ return err;
+
+ ce = intel_context_create(engine);
+ if (IS_ERR(ce))
+ return PTR_ERR(ce);
+
+ rq = __gpr_read(ce, scratch, slot);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto err_put;
+ }
+
+ err = wait_for_submit(engine, rq, HZ / 2);
if (err)
goto err_rq;
+ if (preempt) {
+ err = gpr_make_dirty(engine->kernel_context);
+ if (err)
+ goto err_rq;
+
+ err = emit_semaphore_signal(engine->kernel_context, slot);
+ if (err)
+ goto err_rq;
+ } else {
+ slot[0] = 1;
+ wmb();
+ }
+
if (i915_request_wait(rq, 0, HZ / 5) < 0) {
err = -ETIME;
goto err_rq;
@@ -4449,13 +4500,15 @@ static int __live_gpr_clear(struct intel_engine_cs *engine,
i915_gem_object_unpin_map(scratch->obj);
err_rq:
+ memset32(&slot[0], -1, 4);
+ wmb();
i915_request_put(rq);
err_put:
intel_context_put(ce);
return err;
}
-static int live_gpr_clear(void *arg)
+static int live_lrc_gpr(void *arg)
{
struct intel_gt *gt = arg;
struct intel_engine_cs *engine;
@@ -4473,14 +4526,26 @@ static int live_gpr_clear(void *arg)
return PTR_ERR(scratch);
for_each_engine(engine, gt, id) {
- err = __live_gpr_clear(engine, scratch);
+ unsigned long heartbeat;
+
+ engine_heartbeat_disable(engine, &heartbeat);
+
+ err = __live_lrc_gpr(engine, scratch, false);
+ if (err)
+ goto err;
+
+ err = __live_lrc_gpr(engine, scratch, true);
+ if (err)
+ goto err;
+
+err:
+ engine_heartbeat_enable(engine, heartbeat);
+ if (igt_flush_test(gt->i915))
+ err = -EIO;
if (err)
break;
}
- if (igt_flush_test(gt->i915))
- err = -EIO;
-
i915_vma_unpin_and_release(&scratch, 0);
return err;
}
@@ -4779,7 +4844,7 @@ int intel_lrc_live_selftests(struct drm_i915_private *i915)
SUBTEST(live_lrc_layout),
SUBTEST(live_lrc_fixed),
SUBTEST(live_lrc_state),
- SUBTEST(live_gpr_clear),
+ SUBTEST(live_lrc_gpr),
SUBTEST(live_lrc_timestamp),
SUBTEST(live_pphwsp_runtime),
};
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/2] drm/i915/selftest: Analyse timestamp behaviour across context switches (rev2)
2020-02-19 11:20 [Intel-gfx] [PATCH 1/2] drm/i915/selftest: Analyse timestamp behaviour across context switches Chris Wilson
` (2 preceding siblings ...)
2020-02-19 12:22 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-02-19 15:55 ` Patchwork
3 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2020-02-19 15:55 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/selftest: Analyse timestamp behaviour across context switches (rev2)
URL : https://patchwork.freedesktop.org/series/73637/
State : failure
== Summary ==
Applying: drm/i915/selftest: Analyse timestamp behaviour across context switches
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/gt/selftest_lrc.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/gt/selftest_lrc.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/gt/selftest_lrc.c
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch' to see the failed patch
Patch failed at 0001 drm/i915/selftest: Analyse timestamp behaviour across context switches
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-02-19 15:55 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-02-19 11:20 [Intel-gfx] [PATCH 1/2] drm/i915/selftest: Analyse timestamp behaviour across context switches Chris Wilson
2020-02-19 11:20 ` [Intel-gfx] [PATCH 2/2] drm/i915/selftests: Mark GPR checking more hostile Chris Wilson
2020-02-19 12:34 ` [Intel-gfx] [PATCH v2] " Chris Wilson
2020-02-19 11:59 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/selftest: Analyse timestamp behaviour across context switches Patchwork
2020-02-19 12:22 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-02-19 15:55 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/2] drm/i915/selftest: Analyse timestamp behaviour across context switches (rev2) Patchwork
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