* [Intel-gfx] [PATCH] drm/i915/tgl: add Wa_1409085225, Wa_14010229206
@ 2020-02-19 19:05 Matt Atwood
2020-02-19 22:38 ` Matt Roper
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Matt Atwood @ 2020-02-19 19:05 UTC (permalink / raw)
To: intel-gfx
Disable Push Constant buffer addition, which can cause FIFO
underruns.
Fix a minor white space issue while we're here.
v2: typos, add additional Wa reference
Bspec: 52890
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +++++++++
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 887e0dc701f7..0681e64be741 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -580,6 +580,7 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
{
+ struct drm_i915_private *i915 = engine->i915;
u32 val;
/* Wa_1409142259:tgl */
@@ -590,6 +591,7 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
val = intel_uncore_read(engine->uncore, FF_MODE2);
val &= ~FF_MODE2_TDS_TIMER_MASK;
val |= FF_MODE2_TDS_TIMER_128;
+
/*
* FIXME: FF_MODE2 register is not readable till TGL B0. We can
* enable verification of WA from the later steppings, which enables
@@ -598,6 +600,13 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 :
FF_MODE2_TDS_TIMER_MASK);
+
+ /*
+ * Wa_1409085225:tgl
+ * Wa_14010229206:tgl
+ * Push Constant Buffer can cause FIFO underruns on tgl
+ */
+ WA_SET_BIT_MASKED(GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
}
static void
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b09c1d6dc0aa..70cbe576fdfa 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9153,6 +9153,9 @@ enum {
#define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
#define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)
+#define GEN9_ROW_CHICKEN4 _MMIO(0xe48c)
+#define GEN12_DISABLE_TDL_PUSH (1 << 9)
+
#define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
--
2.21.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/tgl: add Wa_1409085225, Wa_14010229206
2020-02-19 19:05 [Intel-gfx] [PATCH] drm/i915/tgl: add Wa_1409085225, Wa_14010229206 Matt Atwood
@ 2020-02-19 22:38 ` Matt Roper
2020-02-20 0:12 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for " Patchwork
2020-02-22 2:12 ` [Intel-gfx] [PATCH] " kbuild test robot
2 siblings, 0 replies; 5+ messages in thread
From: Matt Roper @ 2020-02-19 22:38 UTC (permalink / raw)
To: Matt Atwood; +Cc: intel-gfx
On Wed, Feb 19, 2020 at 02:05:29PM -0500, Matt Atwood wrote:
> Disable Push Constant buffer addition, which can cause FIFO
> underruns.
>
> Fix a minor white space issue while we're here.
>
> v2: typos, add additional Wa reference
>
> Bspec: 52890
> Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +++++++++
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> 2 files changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 887e0dc701f7..0681e64be741 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -580,6 +580,7 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
> static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
According to bspec page 46255, this register isn't part of the TGL
context image, so ctx_workarounds_init isn't the right place to handle
this. The next question is whether this is a general GT workaround or a
specific engine workaround...in this case, 0xE48C falls in one of the
render engine forcewake ranges (0xE000-0xE8FF -- see bspec page 52078)
so rcs_engine_wa_init() is where we'd actually want to take care of
this. That will ensure that the workaround gets re-applied when we
reset the render engine without doing a full GPU reset.
> {
> + struct drm_i915_private *i915 = engine->i915;
> u32 val;
>
> /* Wa_1409142259:tgl */
> @@ -590,6 +591,7 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> val = intel_uncore_read(engine->uncore, FF_MODE2);
> val &= ~FF_MODE2_TDS_TIMER_MASK;
> val |= FF_MODE2_TDS_TIMER_128;
> +
> /*
> * FIXME: FF_MODE2 register is not readable till TGL B0. We can
> * enable verification of WA from the later steppings, which enables
> @@ -598,6 +600,13 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
> IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 :
> FF_MODE2_TDS_TIMER_MASK);
> +
> + /*
> + * Wa_1409085225:tgl
> + * Wa_14010229206:tgl
> + * Push Constant Buffer can cause FIFO underruns on tgl
The description in the bspec says that it can cause an overflow rather
than an underrun.
Actually, I'm not sure whether it's worth even mentioning this here
since the things that's overflowing isn't something that our kernel
driver has any direct interaction with. I.e., this FIFO is completely
different than the display FIFO that underruns when we have watermark
issues.
> + */
> + WA_SET_BIT_MASKED(GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
> }
>
> static void
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b09c1d6dc0aa..70cbe576fdfa 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9153,6 +9153,9 @@ enum {
> #define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
> #define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)
>
> +#define GEN9_ROW_CHICKEN4 _MMIO(0xe48c)
> +#define GEN12_DISABLE_TDL_PUSH (1 << 9)
Even though many of the registers in this area of the file use the old
form, the preferred style for new registers is to use REG_BIT(9). See
the comments at the top of the file for details.
Matt
> +
> #define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
> #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
>
> --
> 2.21.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/tgl: add Wa_1409085225, Wa_14010229206
2020-02-19 19:05 [Intel-gfx] [PATCH] drm/i915/tgl: add Wa_1409085225, Wa_14010229206 Matt Atwood
2020-02-19 22:38 ` Matt Roper
@ 2020-02-20 0:12 ` Patchwork
2020-02-22 2:12 ` [Intel-gfx] [PATCH] " kbuild test robot
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2020-02-20 0:12 UTC (permalink / raw)
To: Matt Atwood; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/tgl: add Wa_1409085225, Wa_14010229206
URL : https://patchwork.freedesktop.org/series/73679/
State : failure
== Summary ==
CALL scripts/checksyscalls.sh
CALL scripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
CC [M] drivers/gpu/drm/i915/gt/intel_workarounds.o
drivers/gpu/drm/i915/gt/intel_workarounds.c: In function ‘tgl_ctx_workarounds_init’:
drivers/gpu/drm/i915/gt/intel_workarounds.c:583:27: error: unused variable ‘i915’ [-Werror=unused-variable]
struct drm_i915_private *i915 = engine->i915;
^~~~
cc1: all warnings being treated as errors
scripts/Makefile.build:267: recipe for target 'drivers/gpu/drm/i915/gt/intel_workarounds.o' failed
make[4]: *** [drivers/gpu/drm/i915/gt/intel_workarounds.o] Error 1
scripts/Makefile.build:505: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:505: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:505: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1681: recipe for target 'drivers' failed
make: *** [drivers] Error 2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/tgl: add Wa_1409085225, Wa_14010229206
2020-02-19 19:05 [Intel-gfx] [PATCH] drm/i915/tgl: add Wa_1409085225, Wa_14010229206 Matt Atwood
2020-02-19 22:38 ` Matt Roper
2020-02-20 0:12 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for " Patchwork
@ 2020-02-22 2:12 ` kbuild test robot
2 siblings, 0 replies; 5+ messages in thread
From: kbuild test robot @ 2020-02-22 2:12 UTC (permalink / raw)
To: Matt Atwood; +Cc: intel-gfx, kbuild-all
[-- Attachment #1: Type: text/plain, Size: 10520 bytes --]
Hi Matt,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip v5.6-rc2 next-20200221]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url: https://github.com/0day-ci/linux/commits/Matt-Atwood/drm-i915-tgl-add-Wa_1409085225-Wa_14010229206/20200222-030001
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-c002-20200221 (attached as .config)
compiler: gcc-7 (Debian 7.5.0-5) 7.5.0
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
drivers/gpu/drm/i915/gt/intel_workarounds.c: In function 'tgl_ctx_workarounds_init':
>> drivers/gpu/drm/i915/gt/intel_workarounds.c:583:27: error: unused variable 'i915' [-Werror=unused-variable]
struct drm_i915_private *i915 = engine->i915;
^~~~
Cyclomatic Complexity 5 include/linux/compiler.h:__read_once_size
Cyclomatic Complexity 1 arch/x86/include/asm/bitops.h:constant_test_bit
Cyclomatic Complexity 1 arch/x86/include/asm/bitops.h:variable_test_bit
Cyclomatic Complexity 1 arch/x86/include/asm/bitops.h:ffs
Cyclomatic Complexity 1 arch/x86/include/asm/bitops.h:fls
Cyclomatic Complexity 1 arch/x86/include/asm/bitops.h:fls64
Cyclomatic Complexity 1 include/linux/log2.h:__ilog2_u64
Cyclomatic Complexity 3 include/linux/log2.h:is_power_of_2
Cyclomatic Complexity 1 arch/x86/include/asm/atomic.h:arch_atomic_read
Cyclomatic Complexity 1 arch/x86/include/asm/atomic.h:arch_atomic_dec
Cyclomatic Complexity 1 arch/x86/include/asm/atomic.h:arch_atomic_fetch_add
Cyclomatic Complexity 1 arch/x86/include/asm/atomic.h:arch_atomic_fetch_sub
Cyclomatic Complexity 2 arch/x86/include/asm/atomic.h:arch_atomic_try_cmpxchg
Cyclomatic Complexity 1 include/linux/err.h:ERR_PTR
Cyclomatic Complexity 1 include/linux/err.h:PTR_ERR
Cyclomatic Complexity 1 include/linux/err.h:ERR_CAST
Cyclomatic Complexity 1 include/linux/spinlock.h:spinlock_check
Cyclomatic Complexity 1 include/linux/spinlock.h:spin_unlock_irqrestore
Cyclomatic Complexity 4 include/linux/rcupdate.h:rcu_read_lock
Cyclomatic Complexity 1 arch/x86/include/asm/io.h:readl
Cyclomatic Complexity 1 arch/x86/include/asm/io.h:writel
Cyclomatic Complexity 1 include/linux/slab.h:kmalloc_type
Cyclomatic Complexity 28 include/linux/slab.h:kmalloc_index
Cyclomatic Complexity 1 include/linux/slab.h:kmalloc_large
Cyclomatic Complexity 4 include/linux/slab.h:kmalloc
Cyclomatic Complexity 1 include/linux/kobject.h:kobject_name
Cyclomatic Complexity 2 include/linux/device.h:dev_name
Cyclomatic Complexity 1 drivers/gpu/drm/i915/i915_reg.h:i915_mmio_reg_offset
Cyclomatic Complexity 1 drivers/gpu/drm/i915/i915_request.h:dma_fence_is_i915
Cyclomatic Complexity 1 drivers/gpu/drm/i915/intel_uncore.h:__raw_uncore_read32
Cyclomatic Complexity 1 drivers/gpu/drm/i915/intel_uncore.h:__raw_uncore_write32
Cyclomatic Complexity 1 drivers/gpu/drm/i915/intel_uncore.h:intel_uncore_read
Cyclomatic Complexity 1 drivers/gpu/drm/i915/intel_uncore.h:intel_uncore_write
Cyclomatic Complexity 2 drivers/gpu/drm/i915/intel_uncore.h:intel_uncore_rmw_fw
Cyclomatic Complexity 1 drivers/gpu/drm/i915/i915_drv.h:__platform_mask_index
Cyclomatic Complexity 1 drivers/gpu/drm/i915/i915_drv.h:__platform_mask_bit
Cyclomatic Complexity 2 drivers/gpu/drm/i915/i915_drv.h:IS_PLATFORM
Cyclomatic Complexity 1 drivers/gpu/drm/i915/gt/intel_workarounds.c:wa_init_start
Cyclomatic Complexity 3 drivers/gpu/drm/i915/gt/intel_workarounds.c:is_nonpriv_flags_valid
Cyclomatic Complexity 3 drivers/gpu/drm/i915/gt/intel_workarounds.c:mcr_range
Cyclomatic Complexity 2 drivers/gpu/drm/i915/gt/selftest_workarounds.c:get_whitelist_reg
Cyclomatic Complexity 2 drivers/gpu/drm/i915/gt/selftest_workarounds.c:reg_write
Cyclomatic Complexity 5 drivers/gpu/drm/i915/gt/selftest_workarounds.c:wo_register
Cyclomatic Complexity 2 drivers/gpu/drm/i915/gt/selftest_workarounds.c:ro_register
Cyclomatic Complexity 3 drivers/gpu/drm/i915/gt/selftest_workarounds.c:whitelist_writable_count
Cyclomatic Complexity 4 drivers/gpu/drm/i915/gt/selftest_workarounds.c:find_reg
Cyclomatic Complexity 1 drivers/gpu/drm/i915/gt/selftest_workarounds.c:pardon_reg
Cyclomatic Complexity 1 drivers/gpu/drm/i915/gt/selftest_workarounds.c:writeonly_reg
Cyclomatic Complexity 1 include/linux/err.h:IS_ERR
Cyclomatic Complexity 3 include/linux/err.h:IS_ERR_OR_NULL
Cyclomatic Complexity 1 drivers/gpu/drm/i915/gem/i915_gem_object.h:i915_gem_object_has_pages
Cyclomatic Complexity 1 drivers/gpu/drm/i915/gt/intel_ring.h:intel_ring_advance
Cyclomatic Complexity 2 drivers/gpu/drm/i915/i915_request.h:to_request
Cyclomatic Complexity 1 drivers/gpu/drm/i915/gem/i915_gem_context.h:i915_gem_engines_iter_init
Cyclomatic Complexity 2 drivers/gpu/drm/i915/gt/intel_workarounds.c:wa_verify
Cyclomatic Complexity 2 drivers/gpu/drm/i915/gt/intel_workarounds.c:wa_list_verify
Cyclomatic Complexity 68 include/asm-generic/getorder.h:get_order
Cyclomatic Complexity 4 include/linux/slab.h:kmalloc_array
Cyclomatic Complexity 11 drivers/gpu/drm/i915/gt/intel_workarounds.c:_wa_add
Cyclomatic Complexity 1 drivers/gpu/drm/i915/gt/intel_workarounds.c:wa_add
Cyclomatic Complexity 1 drivers/gpu/drm/i915/gt/intel_workarounds.c:wa_write_masked_or
Cyclomatic Complexity 1 drivers/gpu/drm/i915/gt/intel_workarounds.c:wa_write
Cyclomatic Complexity 3 drivers/gpu/drm/i915/gt/intel_workarounds.c:xcs_engine_wa_init
Cyclomatic Complexity 1 drivers/gpu/drm/i915/gt/intel_workarounds.c:wa_write_or
Cyclomatic Complexity 5 drivers/gpu/drm/i915/gt/intel_workarounds.c:tgl_gt_workarounds_init
Cyclomatic Complexity 3 drivers/gpu/drm/i915/gt/intel_workarounds.c:gen9_gt_workarounds_init
Cyclomatic Complexity 1 drivers/gpu/drm/i915/gt/intel_workarounds.c:cfl_gt_workarounds_init
Cyclomatic Complexity 1 drivers/gpu/drm/i915/gt/intel_workarounds.c:glk_gt_workarounds_init
Cyclomatic Complexity 3 drivers/gpu/drm/i915/gt/intel_workarounds.c:kbl_gt_workarounds_init
Cyclomatic Complexity 1 drivers/gpu/drm/i915/gt/intel_workarounds.c:bxt_gt_workarounds_init
Cyclomatic Complexity 3 drivers/gpu/drm/i915/gt/intel_workarounds.c:skl_gt_workarounds_init
Cyclomatic Complexity 5 drivers/gpu/drm/i915/gt/intel_workarounds.c:whitelist_reg_ext
Cyclomatic Complexity 1 drivers/gpu/drm/i915/gt/intel_workarounds.c:whitelist_reg
Cyclomatic Complexity 2 drivers/gpu/drm/i915/gt/intel_workarounds.c:tgl_whitelist_build
Cyclomatic Complexity 2 drivers/gpu/drm/i915/gt/intel_workarounds.c:cnl_whitelist_build
Cyclomatic Complexity 1 drivers/gpu/drm/i915/gt/intel_workarounds.c:gen9_whitelist_build
Cyclomatic Complexity 2 drivers/gpu/drm/i915/gt/intel_workarounds.c:bxt_whitelist_build
Cyclomatic Complexity 2 drivers/gpu/drm/i915/gt/intel_workarounds.c:glk_whitelist_build
Cyclomatic Complexity 2 drivers/gpu/drm/i915/gt/intel_workarounds.c:kbl_whitelist_build
Cyclomatic Complexity 2 drivers/gpu/drm/i915/gt/intel_workarounds.c:skl_whitelist_build
Cyclomatic Complexity 3 drivers/gpu/drm/i915/gt/intel_workarounds.c:icl_whitelist_build
Cyclomatic Complexity 2 drivers/gpu/drm/i915/gt/intel_workarounds.c:cfl_whitelist_build
Cyclomatic Complexity 5 drivers/gpu/drm/i915/gt/intel_workarounds.c:wa_masked_en
Cyclomatic Complexity 3 drivers/gpu/drm/i915/gt/intel_workarounds.c:tgl_ctx_workarounds_init
Cyclomatic Complexity 11 drivers/gpu/drm/i915/gt/intel_workarounds.c:icl_ctx_workarounds_init
Cyclomatic Complexity 3 drivers/gpu/drm/i915/gt/intel_workarounds.c:wa_masked_dis
Cyclomatic Complexity 5 drivers/gpu/drm/i915/gt/intel_workarounds.c:cnl_ctx_workarounds_init
Cyclomatic Complexity 7 drivers/gpu/drm/i915/gt/intel_workarounds.c:gen9_ctx_workarounds_init
Cyclomatic Complexity 1 drivers/gpu/drm/i915/gt/intel_workarounds.c:cfl_ctx_workarounds_init
Cyclomatic Complexity 1 drivers/gpu/drm/i915/gt/intel_workarounds.c:glk_ctx_workarounds_init
Cyclomatic Complexity 3 drivers/gpu/drm/i915/gt/intel_workarounds.c:kbl_ctx_workarounds_init
Cyclomatic Complexity 1 drivers/gpu/drm/i915/gt/intel_workarounds.c:bxt_ctx_workarounds_init
Cyclomatic Complexity 1 drivers/gpu/drm/i915/gt/intel_workarounds.c:gen8_ctx_workarounds_init
Cyclomatic Complexity 1 drivers/gpu/drm/i915/gt/intel_workarounds.c:chv_ctx_workarounds_init
Cyclomatic Complexity 3 drivers/gpu/drm/i915/gt/intel_workarounds.c:bdw_ctx_workarounds_init
Cyclomatic Complexity 10 drivers/gpu/drm/i915/gt/intel_workarounds.c:skl_tune_iz_hashing
Cyclomatic Complexity 1 drivers/gpu/drm/i915/gt/intel_workarounds.c:skl_ctx_workarounds_init
Cyclomatic Complexity 4 drivers/gpu/drm/i915/gt/intel_workarounds.c:wa_init_finish
vim +/i915 +583 drivers/gpu/drm/i915/gt/intel_workarounds.c
579
580 static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
581 struct i915_wa_list *wal)
582 {
> 583 struct drm_i915_private *i915 = engine->i915;
584 u32 val;
585
586 /* Wa_1409142259:tgl */
587 WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
588 GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
589
590 /* Wa_1604555607:tgl */
591 val = intel_uncore_read(engine->uncore, FF_MODE2);
592 val &= ~FF_MODE2_TDS_TIMER_MASK;
593 val |= FF_MODE2_TDS_TIMER_128;
594
595 /*
596 * FIXME: FF_MODE2 register is not readable till TGL B0. We can
597 * enable verification of WA from the later steppings, which enables
598 * the read of FF_MODE2.
599 */
600 wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
601 IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 :
602 FF_MODE2_TDS_TIMER_MASK);
603
604 /*
605 * Wa_1409085225:tgl
606 * Wa_14010229206:tgl
607 * Push Constant Buffer can cause FIFO underruns on tgl
608 */
609 WA_SET_BIT_MASKED(GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
610 }
611
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 30157 bytes --]
[-- Attachment #3: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/tgl: Add Wa_1409085225, Wa_14010229206
2020-02-20 17:19 [Intel-gfx] [PATCH 1/2] drm/i915: Extend Wa_1606931601 for all steppings Matt Atwood
@ 2020-02-20 17:25 ` Matt Atwood
0 siblings, 0 replies; 5+ messages in thread
From: Matt Atwood @ 2020-02-20 17:25 UTC (permalink / raw)
To: intel-gfx
Disable Push Constant buffer addition for TGL.
v2: typos, add additional Wa reference
v3: use REG_BIT macro, move to rcs_engine_wa_init, clean up commit
message.
Bspec: 52890
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 7cc8a7fc53c7..5db9a9fa9ca5 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1334,6 +1334,11 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
wa_masked_en(wal,
GEN7_ROW_CHICKEN2,
GEN12_DISABLE_EARLY_READ);
+ /*
+ * Wa_1409085225:tgl
+ * Wa_14010229206:tgl
+ */
+ WA_SET_BIT_MASKED(GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
}
if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b09c1d6dc0aa..4d6342a2883e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9153,6 +9153,9 @@ enum {
#define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
#define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)
+#define GEN9_ROW_CHICKEN4 _MMIO(0xe48c)
+#define GEN12_DISABLE_TDL_PUSH REG_BIT(9)
+
#define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
--
2.21.1
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^ permalink raw reply related [flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-02-22 2:12 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-02-19 19:05 [Intel-gfx] [PATCH] drm/i915/tgl: add Wa_1409085225, Wa_14010229206 Matt Atwood
2020-02-19 22:38 ` Matt Roper
2020-02-20 0:12 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for " Patchwork
2020-02-22 2:12 ` [Intel-gfx] [PATCH] " kbuild test robot
2020-02-20 17:19 [Intel-gfx] [PATCH 1/2] drm/i915: Extend Wa_1606931601 for all steppings Matt Atwood
2020-02-20 17:25 ` [Intel-gfx] [PATCH] drm/i915/tgl: Add Wa_1409085225, Wa_14010229206 Matt Atwood
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