* [Intel-gfx] [PATCH v4] drm/i915/tgl: Add definitions for VRR registers and bits
@ 2020-03-19 1:59 Aditya Swarup
2020-03-19 3:12 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/tgl: Add definitions for VRR registers and bits (rev3) Patchwork
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: Aditya Swarup @ 2020-03-19 1:59 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Add definitions for registers grouped under Transcoder VRR function
with necessary bitfields.
Bspec: 49268
v2: Use REG_GENMASK, correct tabs/space indentation and move the
definitions near the transcoder section.(Jani)
v3: Remove unnecessary prefix from bit/mask definitions.(Manasi)
v4: Use 'trans' in macro for better readability.(Manasi)
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 90 +++++++++++++++++++++++++++++++++
1 file changed, 90 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9c53fe918be6..e154a3a73cf4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4324,6 +4324,96 @@ enum {
#define EXITLINE_MASK REG_GENMASK(12, 0)
#define EXITLINE_SHIFT 0
+/* VRR registers */
+#define _TRANS_VRR_CTL_A 0x60420
+#define _TRANS_VRR_CTL_B 0x61420
+#define _TRANS_VRR_CTL_C 0x62420
+#define _TRANS_VRR_CTL_D 0x63420
+#define TRANS_VRR_CTL(trans) _MMIO_TRANS2(trans, _TRANS_VRR_CTL_A)
+#define VRR_CTL_VRR_ENABLE REG_BIT(31)
+#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
+#define VRR_CTL_FLIP_LINE_EN REG_BIT(29)
+#define VRR_CTL_LINE_COUNT_MASK REG_GENMASK(10, 3)
+#define VRR_CTL_SW_FULLLINE_COUNT REG_BIT(0)
+
+#define _TRANS_VRR_VMAX_A 0x60424
+#define _TRANS_VRR_VMAX_B 0x61424
+#define _TRANS_VRR_VMAX_C 0x62424
+#define _TRANS_VRR_VMAX_D 0x63424
+#define TRANS_VRR_VMAX(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VMAX_A)
+#define VRR_VMAX_MASK REG_GENMASK(19, 0)
+
+#define _TRANS_VRR_VMIN_A 0x60434
+#define _TRANS_VRR_VMIN_B 0x61434
+#define _TRANS_VRR_VMIN_C 0x62434
+#define _TRANS_VRR_VMIN_D 0x63434
+#define TRANS_VRR_VMIN(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VMIN_A)
+#define VRR_VMIN_MASK REG_GENMASK(15, 0)
+
+#define _TRANS_VRR_VMAXSHIFT_A 0x60428
+#define _TRANS_VRR_VMAXSHIFT_B 0x61428
+#define _TRANS_VRR_VMAXSHIFT_C 0x62428
+#define _TRANS_VRR_VMAXSHIFT_D 0x63428
+#define TRANS_VRR_VMAXSHIFT(trans) _MMIO_TRANS2(trans, \
+ _TRANS_VRR_VMAXSHIFT_A)
+#define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16)
+#define VRR_VMAXSHIFT_DEC REG_BIT(16)
+#define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0)
+
+#define _TRANS_VRR_STATUS_A 0x6042C
+#define _TRANS_VRR_STATUS_B 0x6142C
+#define _TRANS_VRR_STATUS_C 0x6242C
+#define _TRANS_VRR_STATUS_D 0x6342C
+#define TRANS_VRR_STATUS(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS_A)
+#define VRR_STATUS_VMAX_REACHED REG_BIT(31)
+#define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30)
+#define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29)
+#define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28)
+#define VRR_STATUS_VRR_EN_LIVE REG_BIT(27)
+#define VRR_STATUS_FLIPS_SERVICED REG_BIT(26)
+#define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20)
+#define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0)
+#define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1)
+#define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2)
+#define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3)
+#define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4)
+#define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5)
+#define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6)
+
+#define _TRANS_VRR_VTOTAL_PREV_A 0x60480
+#define _TRANS_VRR_VTOTAL_PREV_B 0x61480
+#define _TRANS_VRR_VTOTAL_PREV_C 0x62480
+#define _TRANS_VRR_VTOTAL_PREV_D 0x63480
+#define TRANS_VRR_VTOTAL_PREV(trans) _MMIO_TRANS2(trans, \
+ _TRANS_VRR_VTOTAL_PREV_A)
+#define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31)
+#define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30)
+#define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29)
+#define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0)
+
+#define _TRANS_VRR_FLIPLINE_A 0x60438
+#define _TRANS_VRR_FLIPLINE_B 0x61438
+#define _TRANS_VRR_FLIPLINE_C 0x62438
+#define _TRANS_VRR_FLIPLINE_D 0x63438
+#define TRANS_VRR_FLIPLINE(trans) _MMIO_TRANS2(trans, \
+ _TRANS_VRR_FLIPLINE_A)
+#define VRR_FLIPLINE_MASK REG_GENMASK(19, 0)
+
+#define _TRANS_VRR_STATUS2_A 0x6043C
+#define _TRANS_VRR_STATUS2_B 0x6143C
+#define _TRANS_VRR_STATUS2_C 0x6243C
+#define _TRANS_VRR_STATUS2_D 0x6343C
+#define TRANS_VRR_STATUS2(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS2_A)
+#define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0)
+
+#define _TRANS_PUSH_A 0x60A70
+#define _TRANS_PUSH_B 0x61A70
+#define _TRANS_PUSH_C 0x62A70
+#define _TRANS_PUSH_D 0x63A70
+#define TRANS_PUSH(trans) _MMIO_TRANS2(trans, _TRANS_PUSH_A)
+#define TRANS_PUSH_EN REG_BIT(31)
+#define TRANS_PUSH_SEND REG_BIT(30)
+
/*
* HSW+ eDP PSR registers
*
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/tgl: Add definitions for VRR registers and bits (rev3)
2020-03-19 1:59 [Intel-gfx] [PATCH v4] drm/i915/tgl: Add definitions for VRR registers and bits Aditya Swarup
@ 2020-03-19 3:12 ` Patchwork
2020-03-19 3:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2020-03-19 3:12 UTC (permalink / raw)
To: Aditya Swarup; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/tgl: Add definitions for VRR registers and bits (rev3)
URL : https://patchwork.freedesktop.org/series/74410/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0a8a0885ae09 drm/i915/tgl: Add definitions for VRR registers and bits
-:24: WARNING:BAD_SIGN_OFF: Duplicate signature
#24:
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
total: 0 errors, 1 warnings, 0 checks, 96 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Add definitions for VRR registers and bits (rev3)
2020-03-19 1:59 [Intel-gfx] [PATCH v4] drm/i915/tgl: Add definitions for VRR registers and bits Aditya Swarup
2020-03-19 3:12 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/tgl: Add definitions for VRR registers and bits (rev3) Patchwork
@ 2020-03-19 3:36 ` Patchwork
2020-03-19 5:48 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-03-27 23:56 ` [Intel-gfx] [PATCH v4] drm/i915/tgl: Add definitions for VRR registers and bits Manasi Navare
3 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2020-03-19 3:36 UTC (permalink / raw)
To: Aditya Swarup; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/tgl: Add definitions for VRR registers and bits (rev3)
URL : https://patchwork.freedesktop.org/series/74410/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8156 -> Patchwork_17019
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/index.html
Known issues
------------
Here are the changes found in Patchwork_17019 that come from known issues:
### IGT changes ###
#### Possible fixes ####
* igt@i915_selftest@live@execlists:
- fi-apl-guc: [INCOMPLETE][1] ([fdo#103927] / [i915#1430] / [i915#656]) -> [PASS][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8156/fi-apl-guc/igt@i915_selftest@live@execlists.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/fi-apl-guc/igt@i915_selftest@live@execlists.html
- fi-bsw-kefka: [DMESG-FAIL][3] ([i915#1314]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8156/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][5] ([fdo#111407]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8156/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[i915#1314]: https://gitlab.freedesktop.org/drm/intel/issues/1314
[i915#1430]: https://gitlab.freedesktop.org/drm/intel/issues/1430
[i915#656]: https://gitlab.freedesktop.org/drm/intel/issues/656
Participating hosts (44 -> 40)
------------------------------
Missing (4): fi-bsw-cyan fi-byt-clapper fi-gdg-551 fi-snb-2520m
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8156 -> Patchwork_17019
CI-20190529: 20190529
CI_DRM_8156: ecef6724d06ce8e5adac2c4e77ab18f605b09a9a @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5522: bd2b01af69c9720d54e68a8702a23e4ff3637746 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17019: 0a8a0885ae0998b020295f4f865cb5d113138ae8 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
0a8a0885ae09 drm/i915/tgl: Add definitions for VRR registers and bits
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/tgl: Add definitions for VRR registers and bits (rev3)
2020-03-19 1:59 [Intel-gfx] [PATCH v4] drm/i915/tgl: Add definitions for VRR registers and bits Aditya Swarup
2020-03-19 3:12 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/tgl: Add definitions for VRR registers and bits (rev3) Patchwork
2020-03-19 3:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-03-19 5:48 ` Patchwork
2020-03-27 23:56 ` [Intel-gfx] [PATCH v4] drm/i915/tgl: Add definitions for VRR registers and bits Manasi Navare
3 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2020-03-19 5:48 UTC (permalink / raw)
To: Aditya Swarup; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/tgl: Add definitions for VRR registers and bits (rev3)
URL : https://patchwork.freedesktop.org/series/74410/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8156_full -> Patchwork_17019_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_17019_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_busy@busy-vcs1:
- shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#112080]) +15 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8156/shard-iclb4/igt@gem_busy@busy-vcs1.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/shard-iclb7/igt@gem_busy@busy-vcs1.html
* igt@gem_ctx_isolation@rcs0-s3:
- shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +3 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8156/shard-kbl3/igt@gem_ctx_isolation@rcs0-s3.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/shard-kbl1/igt@gem_ctx_isolation@rcs0-s3.html
* igt@gem_ctx_persistence@close-replace-race:
- shard-tglb: [PASS][5] -> [INCOMPLETE][6] ([i915#1402])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8156/shard-tglb3/igt@gem_ctx_persistence@close-replace-race.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/shard-tglb8/igt@gem_ctx_persistence@close-replace-race.html
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#110841])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8156/shard-iclb7/igt@gem_ctx_shared@exec-single-timeline-bsd.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/shard-iclb4/igt@gem_ctx_shared@exec-single-timeline-bsd.html
* igt@gem_exec_schedule@implicit-read-write-bsd1:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109276] / [i915#677]) +2 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8156/shard-iclb1/igt@gem_exec_schedule@implicit-read-write-bsd1.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/shard-iclb8/igt@gem_exec_schedule@implicit-read-write-bsd1.html
* igt@gem_exec_schedule@pi-common-bsd:
- shard-iclb: [PASS][11] -> [SKIP][12] ([i915#677]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8156/shard-iclb7/igt@gem_exec_schedule@pi-common-bsd.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/shard-iclb1/igt@gem_exec_schedule@pi-common-bsd.html
* igt@gem_exec_schedule@reorder-wide-bsd:
- shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#112146]) +6 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8156/shard-iclb8/igt@gem_exec_schedule@reorder-wide-bsd.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/shard-iclb2/igt@gem_exec_schedule@reorder-wide-bsd.html
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +3 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8156/shard-apl6/igt@gem_workarounds@suspend-resume-context.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/shard-apl4/igt@gem_workarounds@suspend-resume-context.html
* igt@i915_pm_rpm@system-suspend-modeset:
- shard-kbl: [PASS][17] -> [INCOMPLETE][18] ([i915#151] / [i915#155])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8156/shard-kbl7/igt@i915_pm_rpm@system-suspend-modeset.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/shard-kbl6/igt@i915_pm_rpm@system-suspend-modeset.html
* igt@kms_color@pipe-a-ctm-0-5:
- shard-skl: [PASS][19] -> [FAIL][20] ([i915#182])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8156/shard-skl3/igt@kms_color@pipe-a-ctm-0-5.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/shard-skl9/igt@kms_color@pipe-a-ctm-0-5.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-skl: [PASS][21] -> [INCOMPLETE][22] ([i915#300])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8156/shard-skl8/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/shard-skl2/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-glk: [PASS][23] -> [FAIL][24] ([i915#79])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8156/shard-glk1/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@plain-flip-fb-recreate:
- shard-kbl: [PASS][25] -> [FAIL][26] ([i915#34])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8156/shard-kbl3/igt@kms_flip@plain-flip-fb-recreate.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/shard-kbl1/igt@kms_flip@plain-flip-fb-recreate.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [PASS][27] -> [FAIL][28] ([i915#1188])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8156/shard-skl10/igt@kms_hdr@bpc-switch.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/shard-skl7/igt@kms_hdr@bpc-switch.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [PASS][29] -> [FAIL][30] ([fdo#108145]) +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8156/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [PASS][31] -> [SKIP][32] ([fdo#109642] / [fdo#111068])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8156/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/shard-iclb6/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [PASS][33] -> [SKIP][34] ([fdo#109441])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8156/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/shard-iclb6/igt@kms_psr@psr2_cursor_render.html
* igt@kms_setmode@basic:
- shard-skl: [PASS][35] -> [FAIL][36] ([i915#31])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8156/shard-skl8/igt@kms_setmode@basic.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/shard-skl2/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend:
- shard-skl: [PASS][37] -> [INCOMPLETE][38] ([i915#69])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8156/shard-skl6/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/shard-skl5/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html
* igt@prime_busy@hang-bsd2:
- shard-iclb: [PASS][39] -> [SKIP][40] ([fdo#109276]) +21 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8156/shard-iclb4/igt@prime_busy@hang-bsd2.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/shard-iclb7/igt@prime_busy@hang-bsd2.html
#### Possible fixes ####
* igt@gem_ctx_persistence@close-replace-race:
- shard-apl: [INCOMPLETE][41] ([fdo#103927] / [i915#1402]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8156/shard-apl2/igt@gem_ctx_persistence@close-replace-race.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/shard-apl3/igt@gem_ctx_persistence@close-replace-race.html
* igt@gem_exec_schedule@implicit-both-bsd:
- shard-iclb: [SKIP][43] ([i915#677]) -> [PASS][44] +3 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8156/shard-iclb2/igt@gem_exec_schedule@implicit-both-bsd.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/shard-iclb6/igt@gem_exec_schedule@implicit-both-bsd.html
* igt@gem_exec_schedule@implicit-both-bsd1:
- shard-iclb: [SKIP][45] ([fdo#109276] / [i915#677]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8156/shard-iclb8/igt@gem_exec_schedule@implicit-both-bsd1.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/shard-iclb2/igt@gem_exec_schedule@implicit-both-bsd1.html
* igt@gem_exec_schedule@in-order-bsd:
- shard-iclb: [SKIP][47] ([fdo#112146]) -> [PASS][48] +7 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8156/shard-iclb4/igt@gem_exec_schedule@in-order-bsd.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/shard-iclb7/igt@gem_exec_schedule@in-order-bsd.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-apl: [FAIL][49] ([i915#644]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8156/shard-apl3/igt@gem_ppgtt@flink-and-close-vma-leak.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/shard-apl4/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@i915_pm_rps@reset:
- shard-iclb: [FAIL][51] ([i915#413]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8156/shard-iclb4/igt@i915_pm_rps@reset.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/shard-iclb7/igt@i915_pm_rps@reset.html
* igt@i915_selftest@live@execlists:
- shard-glk: [INCOMPLETE][53] ([i915#58] / [i915#656] / [k.org#198133]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8156/shard-glk8/igt@i915_selftest@live@execlists.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/shard-glk5/igt@i915_selftest@live@execlists.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-glk: [FAIL][55] ([i915#72]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8156/shard-glk7/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/shard-glk6/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: [FAIL][57] ([IGT#5]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8156/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@flip-vs-suspend:
- shard-skl: [INCOMPLETE][59] ([i915#221]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8156/shard-skl8/igt@kms_flip@flip-vs-suspend.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/shard-skl4/igt@kms_flip@flip-vs-suspend.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible:
- shard-skl: [FAIL][61] ([i915#34]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8156/shard-skl3/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/shard-skl6/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-apl: [DMESG-WARN][63] ([i915#180]) -> [PASS][64] +1 similar issue
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8156/shard-apl1/igt@kms_hdr@bpc-switch-suspend.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/shard-apl2/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [FAIL][65] ([fdo#108145]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8156/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [FAIL][67] ([fdo#108145] / [i915#265]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8156/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [SKIP][69] ([fdo#109441]) -> [PASS][70] +1 similar issue
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8156/shard-iclb8/igt@kms_psr@psr2_sprite_plane_move.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_psr@suspend:
- shard-skl: [INCOMPLETE][71] ([i915#198]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8156/shard-skl1/igt@kms_psr@suspend.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/shard-skl3/igt@kms_psr@suspend.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: [DMESG-WARN][73] ([i915#180]) -> [PASS][74] +3 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8156/shard-kbl2/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/shard-kbl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@perf_pmu@busy-accuracy-98-vcs1:
- shard-iclb: [SKIP][75] ([fdo#112080]) -> [PASS][76] +11 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8156/shard-iclb7/igt@perf_pmu@busy-accuracy-98-vcs1.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/shard-iclb1/igt@perf_pmu@busy-accuracy-98-vcs1.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [SKIP][77] ([fdo#109276]) -> [PASS][78] +20 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8156/shard-iclb7/igt@prime_vgem@fence-wait-bsd2.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/shard-iclb1/igt@prime_vgem@fence-wait-bsd2.html
#### Warnings ####
* igt@i915_pm_rpm@modeset-lpsp-stress:
- shard-snb: [INCOMPLETE][79] ([i915#82]) -> [SKIP][80] ([fdo#109271])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8156/shard-snb2/igt@i915_pm_rpm@modeset-lpsp-stress.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/shard-snb2/igt@i915_pm_rpm@modeset-lpsp-stress.html
* igt@runner@aborted:
- shard-apl: [FAIL][81] ([i915#1402]) -> [FAIL][82] ([fdo#103927])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8156/shard-apl2/igt@runner@aborted.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/shard-apl7/igt@runner@aborted.html
[IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1402]: https://gitlab.freedesktop.org/drm/intel/issues/1402
[i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151
[i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#182]: https://gitlab.freedesktop.org/drm/intel/issues/182
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#221]: https://gitlab.freedesktop.org/drm/intel/issues/221
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#300]: https://gitlab.freedesktop.org/drm/intel/issues/300
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
[i915#413]: https://gitlab.freedesktop.org/drm/intel/issues/413
[i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58
[i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
[i915#656]: https://gitlab.freedesktop.org/drm/intel/issues/656
[i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
[i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
[i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8156 -> Patchwork_17019
CI-20190529: 20190529
CI_DRM_8156: ecef6724d06ce8e5adac2c4e77ab18f605b09a9a @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5522: bd2b01af69c9720d54e68a8702a23e4ff3637746 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17019: 0a8a0885ae0998b020295f4f865cb5d113138ae8 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17019/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH v4] drm/i915/tgl: Add definitions for VRR registers and bits
2020-03-19 1:59 [Intel-gfx] [PATCH v4] drm/i915/tgl: Add definitions for VRR registers and bits Aditya Swarup
` (2 preceding siblings ...)
2020-03-19 5:48 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2020-03-27 23:56 ` Manasi Navare
3 siblings, 0 replies; 6+ messages in thread
From: Manasi Navare @ 2020-03-27 23:56 UTC (permalink / raw)
To: Aditya Swarup; +Cc: Jani Nikula, intel-gfx
Thanks for the patch, puhed to dinq
Manasi
On Wed, Mar 18, 2020 at 06:59:41PM -0700, Aditya Swarup wrote:
> Add definitions for registers grouped under Transcoder VRR function
> with necessary bitfields.
>
> Bspec: 49268
>
> v2: Use REG_GENMASK, correct tabs/space indentation and move the
> definitions near the transcoder section.(Jani)
>
> v3: Remove unnecessary prefix from bit/mask definitions.(Manasi)
>
> v4: Use 'trans' in macro for better readability.(Manasi)
>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 90 +++++++++++++++++++++++++++++++++
> 1 file changed, 90 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9c53fe918be6..e154a3a73cf4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4324,6 +4324,96 @@ enum {
> #define EXITLINE_MASK REG_GENMASK(12, 0)
> #define EXITLINE_SHIFT 0
>
> +/* VRR registers */
> +#define _TRANS_VRR_CTL_A 0x60420
> +#define _TRANS_VRR_CTL_B 0x61420
> +#define _TRANS_VRR_CTL_C 0x62420
> +#define _TRANS_VRR_CTL_D 0x63420
> +#define TRANS_VRR_CTL(trans) _MMIO_TRANS2(trans, _TRANS_VRR_CTL_A)
> +#define VRR_CTL_VRR_ENABLE REG_BIT(31)
> +#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
> +#define VRR_CTL_FLIP_LINE_EN REG_BIT(29)
> +#define VRR_CTL_LINE_COUNT_MASK REG_GENMASK(10, 3)
> +#define VRR_CTL_SW_FULLLINE_COUNT REG_BIT(0)
> +
> +#define _TRANS_VRR_VMAX_A 0x60424
> +#define _TRANS_VRR_VMAX_B 0x61424
> +#define _TRANS_VRR_VMAX_C 0x62424
> +#define _TRANS_VRR_VMAX_D 0x63424
> +#define TRANS_VRR_VMAX(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VMAX_A)
> +#define VRR_VMAX_MASK REG_GENMASK(19, 0)
> +
> +#define _TRANS_VRR_VMIN_A 0x60434
> +#define _TRANS_VRR_VMIN_B 0x61434
> +#define _TRANS_VRR_VMIN_C 0x62434
> +#define _TRANS_VRR_VMIN_D 0x63434
> +#define TRANS_VRR_VMIN(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VMIN_A)
> +#define VRR_VMIN_MASK REG_GENMASK(15, 0)
> +
> +#define _TRANS_VRR_VMAXSHIFT_A 0x60428
> +#define _TRANS_VRR_VMAXSHIFT_B 0x61428
> +#define _TRANS_VRR_VMAXSHIFT_C 0x62428
> +#define _TRANS_VRR_VMAXSHIFT_D 0x63428
> +#define TRANS_VRR_VMAXSHIFT(trans) _MMIO_TRANS2(trans, \
> + _TRANS_VRR_VMAXSHIFT_A)
> +#define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16)
> +#define VRR_VMAXSHIFT_DEC REG_BIT(16)
> +#define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0)
> +
> +#define _TRANS_VRR_STATUS_A 0x6042C
> +#define _TRANS_VRR_STATUS_B 0x6142C
> +#define _TRANS_VRR_STATUS_C 0x6242C
> +#define _TRANS_VRR_STATUS_D 0x6342C
> +#define TRANS_VRR_STATUS(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS_A)
> +#define VRR_STATUS_VMAX_REACHED REG_BIT(31)
> +#define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30)
> +#define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29)
> +#define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28)
> +#define VRR_STATUS_VRR_EN_LIVE REG_BIT(27)
> +#define VRR_STATUS_FLIPS_SERVICED REG_BIT(26)
> +#define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20)
> +#define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0)
> +#define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1)
> +#define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2)
> +#define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3)
> +#define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4)
> +#define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5)
> +#define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6)
> +
> +#define _TRANS_VRR_VTOTAL_PREV_A 0x60480
> +#define _TRANS_VRR_VTOTAL_PREV_B 0x61480
> +#define _TRANS_VRR_VTOTAL_PREV_C 0x62480
> +#define _TRANS_VRR_VTOTAL_PREV_D 0x63480
> +#define TRANS_VRR_VTOTAL_PREV(trans) _MMIO_TRANS2(trans, \
> + _TRANS_VRR_VTOTAL_PREV_A)
> +#define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31)
> +#define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30)
> +#define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29)
> +#define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0)
> +
> +#define _TRANS_VRR_FLIPLINE_A 0x60438
> +#define _TRANS_VRR_FLIPLINE_B 0x61438
> +#define _TRANS_VRR_FLIPLINE_C 0x62438
> +#define _TRANS_VRR_FLIPLINE_D 0x63438
> +#define TRANS_VRR_FLIPLINE(trans) _MMIO_TRANS2(trans, \
> + _TRANS_VRR_FLIPLINE_A)
> +#define VRR_FLIPLINE_MASK REG_GENMASK(19, 0)
> +
> +#define _TRANS_VRR_STATUS2_A 0x6043C
> +#define _TRANS_VRR_STATUS2_B 0x6143C
> +#define _TRANS_VRR_STATUS2_C 0x6243C
> +#define _TRANS_VRR_STATUS2_D 0x6343C
> +#define TRANS_VRR_STATUS2(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS2_A)
> +#define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0)
> +
> +#define _TRANS_PUSH_A 0x60A70
> +#define _TRANS_PUSH_B 0x61A70
> +#define _TRANS_PUSH_C 0x62A70
> +#define _TRANS_PUSH_D 0x63A70
> +#define TRANS_PUSH(trans) _MMIO_TRANS2(trans, _TRANS_PUSH_A)
> +#define TRANS_PUSH_EN REG_BIT(31)
> +#define TRANS_PUSH_SEND REG_BIT(30)
> +
> /*
> * HSW+ eDP PSR registers
> *
> --
> 2.25.0
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Intel-gfx] [PATCH v4] drm/i915/tgl: Add definitions for VRR registers and bits
@ 2020-03-19 1:57 Aditya Swarup
0 siblings, 0 replies; 6+ messages in thread
From: Aditya Swarup @ 2020-03-19 1:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Add definitions for registers grouped under Transcoder VRR function
with necessary bitfields.
Bspec: 49268
v2: Use REG_GENMASK, correct tabs/space indentation and move the
definitions near the transcoder section.(Jani)
v3: Remove unnecessary prefix from bit/mask definitions.(Manasi)
v4: Use 'trans' in macro for better readability.(Manasi)
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 90 +++++++++++++++++++++++++++++++++
1 file changed, 90 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9c53fe918be6..b785142d4930 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4324,6 +4324,96 @@ enum {
#define EXITLINE_MASK REG_GENMASK(12, 0)
#define EXITLINE_SHIFT 0
+/* VRR registers */
+#define _TRANS_VRR_CTL_A 0x60420
+#define _TRANS_VRR_CTL_B 0x61420
+#define _TRANS_VRR_CTL_C 0x62420
+#define _TRANS_VRR_CTL_D 0x63420
+#define TRANS_VRR_CTL(tran) _MMIO_TRANS2(tran, _TRANS_VRR_CTL_A)
+#define VRR_CTL_VRR_ENABLE REG_BIT(31)
+#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
+#define VRR_CTL_FLIP_LINE_EN REG_BIT(29)
+#define VRR_CTL_LINE_COUNT_MASK REG_GENMASK(10, 3)
+#define VRR_CTL_SW_FULLLINE_COUNT REG_BIT(0)
+
+#define _TRANS_VRR_VMAX_A 0x60424
+#define _TRANS_VRR_VMAX_B 0x61424
+#define _TRANS_VRR_VMAX_C 0x62424
+#define _TRANS_VRR_VMAX_D 0x63424
+#define TRANS_VRR_VMAX(tran) _MMIO_TRANS2(tran, _TRANS_VRR_VMAX_A)
+#define VRR_VMAX_MASK REG_GENMASK(19, 0)
+
+#define _TRANS_VRR_VMIN_A 0x60434
+#define _TRANS_VRR_VMIN_B 0x61434
+#define _TRANS_VRR_VMIN_C 0x62434
+#define _TRANS_VRR_VMIN_D 0x63434
+#define TRANS_VRR_VMIN(tran) _MMIO_TRANS2(tran, _TRANS_VRR_VMIN_A)
+#define VRR_VMIN_MASK REG_GENMASK(15, 0)
+
+#define _TRANS_VRR_VMAXSHIFT_A 0x60428
+#define _TRANS_VRR_VMAXSHIFT_B 0x61428
+#define _TRANS_VRR_VMAXSHIFT_C 0x62428
+#define _TRANS_VRR_VMAXSHIFT_D 0x63428
+#define TRANS_VRR_VMAXSHIFT(tran) _MMIO_TRANS2(tran, \
+ _TRANS_VRR_VMAXSHIFT_A)
+#define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16)
+#define VRR_VMAXSHIFT_DEC REG_BIT(16)
+#define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0)
+
+#define _TRANS_VRR_STATUS_A 0x6042C
+#define _TRANS_VRR_STATUS_B 0x6142C
+#define _TRANS_VRR_STATUS_C 0x6242C
+#define _TRANS_VRR_STATUS_D 0x6342C
+#define TRANS_VRR_STATUS(tran) _MMIO_TRANS2(tran, _TRANS_VRR_STATUS_A)
+#define VRR_STATUS_VMAX_REACHED REG_BIT(31)
+#define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30)
+#define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29)
+#define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28)
+#define VRR_STATUS_VRR_EN_LIVE REG_BIT(27)
+#define VRR_STATUS_FLIPS_SERVICED REG_BIT(26)
+#define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20)
+#define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0)
+#define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1)
+#define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2)
+#define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3)
+#define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4)
+#define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5)
+#define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6)
+
+#define _TRANS_VRR_VTOTAL_PREV_A 0x60480
+#define _TRANS_VRR_VTOTAL_PREV_B 0x61480
+#define _TRANS_VRR_VTOTAL_PREV_C 0x62480
+#define _TRANS_VRR_VTOTAL_PREV_D 0x63480
+#define TRANS_VRR_VTOTAL_PREV(tran) _MMIO_TRANS2(tran, \
+ _TRANS_VRR_VTOTAL_PREV_A)
+#define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31)
+#define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30)
+#define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29)
+#define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0)
+
+#define _TRANS_VRR_FLIPLINE_A 0x60438
+#define _TRANS_VRR_FLIPLINE_B 0x61438
+#define _TRANS_VRR_FLIPLINE_C 0x62438
+#define _TRANS_VRR_FLIPLINE_D 0x63438
+#define TRANS_VRR_FLIPLINE(tran) _MMIO_TRANS2(tran, \
+ _TRANS_VRR_FLIPLINE_A)
+#define VRR_FLIPLINE_MASK REG_GENMASK(19, 0)
+
+#define _TRANS_VRR_STATUS2_A 0x6043C
+#define _TRANS_VRR_STATUS2_B 0x6143C
+#define _TRANS_VRR_STATUS2_C 0x6243C
+#define _TRANS_VRR_STATUS2_D 0x6343C
+#define TRANS_VRR_STATUS2(tran) _MMIO_TRANS2(tran, _TRANS_VRR_STATUS2_A)
+#define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0)
+
+#define _TRANS_PUSH_A 0x60A70
+#define _TRANS_PUSH_B 0x61A70
+#define _TRANS_PUSH_C 0x62A70
+#define _TRANS_PUSH_D 0x63A70
+#define TRANS_PUSH(tran) _MMIO_TRANS2(tran, _TRANS_PUSH_A)
+#define TRANS_PUSH_EN REG_BIT(31)
+#define TRANS_PUSH_SEND REG_BIT(30)
+
/*
* HSW+ eDP PSR registers
*
--
2.25.0
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^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-03-27 23:54 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2020-03-19 1:59 [Intel-gfx] [PATCH v4] drm/i915/tgl: Add definitions for VRR registers and bits Aditya Swarup
2020-03-19 3:12 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/tgl: Add definitions for VRR registers and bits (rev3) Patchwork
2020-03-19 3:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-03-19 5:48 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-03-27 23:56 ` [Intel-gfx] [PATCH v4] drm/i915/tgl: Add definitions for VRR registers and bits Manasi Navare
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2020-03-19 1:57 Aditya Swarup
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