* [Intel-gfx] [PATCH v2 0/3] i915 lpsp support for lpsp igt
@ 2020-03-23 7:13 Anshuman Gupta
2020-03-23 7:13 ` [Intel-gfx] [PATCH v2 1/3] drm/i915: Power well id for ICL PG3 Anshuman Gupta
` (5 more replies)
0 siblings, 6 replies; 10+ messages in thread
From: Anshuman Gupta @ 2020-03-23 7:13 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ankit.k.nautiyal, martin.peres
This series adds i915_lpsp_info connector debugfs.
Test-with: 20200323063248.5261-2-anshuman.gupta@intel.com
Anshuman Gupta (3):
drm/i915: Power well id for ICL PG3
drm/i915: Add i915_lpsp_info debugfs
drm/i915: Add connector dbgfs for all connectors
.../gpu/drm/i915/display/intel_connector.c | 3 +
.../drm/i915/display/intel_display_debugfs.c | 102 ++++++++++++++++++
.../drm/i915/display/intel_display_power.c | 6 +-
.../drm/i915/display/intel_display_power.h | 2 +-
drivers/gpu/drm/i915/display/intel_dp.c | 3 -
drivers/gpu/drm/i915/display/intel_hdmi.c | 3 -
6 files changed, 109 insertions(+), 10 deletions(-)
--
2.25.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] [PATCH v2 1/3] drm/i915: Power well id for ICL PG3
2020-03-23 7:13 [Intel-gfx] [PATCH v2 0/3] i915 lpsp support for lpsp igt Anshuman Gupta
@ 2020-03-23 7:13 ` Anshuman Gupta
2020-03-23 7:13 ` [Intel-gfx] [PATCH v2 2/3] drm/i915: Add i915_lpsp_info debugfs Anshuman Gupta
` (4 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Anshuman Gupta @ 2020-03-23 7:13 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ankit.k.nautiyal, martin.peres
Gen11 onwards PG3 is contains functions for pipe B,
external displays, and VGA. It make sense to add
a power well id with name ICL_DISP_PW_3 rather then
TGL_DISP_PW_3, Also PG3 power well id requires to
know if lpsp is enabled.
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 6 +++---
drivers/gpu/drm/i915/display/intel_display_power.h | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 246e406bb385..15af5177c260 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -943,7 +943,7 @@ static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
/* Power wells at this level and above must be disabled for DC5 entry */
if (INTEL_GEN(dev_priv) >= 12)
- high_pg = TGL_DISP_PW_3;
+ high_pg = ICL_DISP_PW_3;
else
high_pg = SKL_DISP_PW_2;
@@ -3564,7 +3564,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.name = "power well 3",
.domains = ICL_PW_3_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
+ .id = ICL_DISP_PW_3,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_PW_3,
@@ -3942,7 +3942,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.name = "power well 3",
.domains = TGL_PW_3_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = TGL_DISP_PW_3,
+ .id = ICL_DISP_PW_3,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_PW_3,
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index da64a5edae7a..56cbae6327b7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -100,7 +100,7 @@ enum i915_power_well_id {
SKL_DISP_PW_MISC_IO,
SKL_DISP_PW_1,
SKL_DISP_PW_2,
- TGL_DISP_PW_3,
+ ICL_DISP_PW_3,
SKL_DISP_DC_OFF,
};
--
2.25.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] [PATCH v2 2/3] drm/i915: Add i915_lpsp_info debugfs
2020-03-23 7:13 [Intel-gfx] [PATCH v2 0/3] i915 lpsp support for lpsp igt Anshuman Gupta
2020-03-23 7:13 ` [Intel-gfx] [PATCH v2 1/3] drm/i915: Power well id for ICL PG3 Anshuman Gupta
@ 2020-03-23 7:13 ` Anshuman Gupta
2020-03-23 7:13 ` [Intel-gfx] [PATCH v2 3/3] drm/i915: Add connector dbgfs for all connectors Anshuman Gupta
` (3 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Anshuman Gupta @ 2020-03-23 7:13 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ankit.k.nautiyal, martin.peres
New i915_pm_lpsp igt solution approach relies on connector specific
debugfs attribute i915_lpsp_info, it exposes whether an output is
capable of driving lpsp and exposes lpsp enablement info.
v2:
- CI fixup.
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
.../drm/i915/display/intel_display_debugfs.c | 102 ++++++++++++++++++
1 file changed, 102 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 424f4e52f783..3105f4a80764 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -9,6 +9,7 @@
#include "i915_debugfs.h"
#include "intel_csr.h"
#include "intel_display_debugfs.h"
+#include "intel_display_power.h"
#include "intel_display_types.h"
#include "intel_dp.h"
#include "intel_fbc.h"
@@ -611,6 +612,93 @@ static void intel_hdcp_info(struct seq_file *m,
seq_puts(m, "\n");
}
+static bool intel_have_embedded_panel(struct drm_connector *connector)
+{
+ return connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
+ connector->connector_type == DRM_MODE_CONNECTOR_eDP;
+}
+
+static bool intel_have_gen9_lpsp_panel(struct drm_connector *connector)
+{
+ return intel_have_embedded_panel(connector) ||
+ connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort;
+}
+
+static int
+intel_lpsp_power_well_enabled(struct drm_i915_private *dev_priv,
+ enum i915_power_well_id power_well_id)
+{
+ struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_well *power_well = NULL;
+ bool is_enabled;
+
+ mutex_lock(&power_domains->lock);
+
+ for_each_power_well(dev_priv, power_well)
+ if (power_well->desc->id == power_well_id)
+ break;
+
+ if (drm_WARN_ON(&dev_priv->drm, !power_well)) {
+ mutex_unlock(&power_domains->lock);
+ /* Assume that BIOS has enabled the power well*/
+ return true;
+ }
+
+ is_enabled = !!power_well->count;
+ mutex_unlock(&power_domains->lock);
+
+ return is_enabled;
+}
+
+static void
+intel_lpsp_capable_info(struct seq_file *m, struct drm_connector *connector)
+{
+ struct intel_encoder *encoder =
+ intel_attached_encoder(to_intel_connector(connector));
+ struct drm_i915_private *dev_priv = to_i915(connector->dev);
+ bool lpsp_capable = false;
+
+ if (IS_TIGERLAKE(dev_priv) && encoder->port <= PORT_C) {
+ lpsp_capable = true;
+ } else if (INTEL_GEN(dev_priv) >= 11 && intel_have_embedded_panel(connector)) {
+ lpsp_capable = true;
+ } else if (INTEL_GEN(dev_priv) >= 9 && (encoder->port == PORT_A &&
+ intel_have_gen9_lpsp_panel(connector))) {
+ lpsp_capable = true;
+ } else if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) &&
+ connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
+ lpsp_capable = true;
+ } else {
+ seq_puts(m, "LPSP not supported\n");
+ return;
+ }
+
+ lpsp_capable ? seq_puts(m, "LPSP capable\n") : seq_puts(m, "LPSP incapable\n");
+}
+
+static void
+intel_lpsp_enable_info(struct seq_file *m, struct drm_connector *connector)
+{
+ struct drm_i915_private *dev_priv = to_i915(connector->dev);
+ bool is_lpsp = false;
+
+ if (INTEL_GEN(dev_priv) >= 11) {
+ is_lpsp = !intel_lpsp_power_well_enabled(dev_priv,
+ ICL_DISP_PW_3);
+ } else if (INTEL_GEN(dev_priv) >= 9) {
+ is_lpsp = !intel_lpsp_power_well_enabled(dev_priv,
+ SKL_DISP_PW_2);
+ } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
+ is_lpsp = !intel_lpsp_power_well_enabled(dev_priv,
+ HSW_DISP_PW_GLOBAL);
+ } else {
+ seq_puts(m, "LPSP not supported\n");
+ return;
+ }
+
+ is_lpsp ? seq_puts(m, "LPSP enabled\n") : seq_puts(m, "LPSP disabled\n");
+}
+
static void intel_dp_info(struct seq_file *m,
struct intel_connector *intel_connector)
{
@@ -1987,6 +2075,17 @@ static int i915_hdcp_sink_capability_show(struct seq_file *m, void *data)
}
DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability);
+static int i915_lpsp_info_show(struct seq_file *m, void *data)
+{
+ struct drm_connector *connector = m->private;
+
+ intel_lpsp_capable_info(m, connector);
+ intel_lpsp_enable_info(m, connector);
+
+ return 0;
+}
+DEFINE_SHOW_ATTRIBUTE(i915_lpsp_info);
+
static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
{
struct drm_connector *connector = m->private;
@@ -2130,5 +2229,8 @@ int intel_connector_debugfs_add(struct drm_connector *connector)
debugfs_create_file("i915_dsc_fec_support", S_IRUGO, root,
connector, &i915_dsc_fec_support_fops);
+ debugfs_create_file("i915_lpsp_info", S_IRUGO, root,
+ connector, &i915_lpsp_info_fops);
+
return 0;
}
--
2.25.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] [PATCH v2 3/3] drm/i915: Add connector dbgfs for all connectors
2020-03-23 7:13 [Intel-gfx] [PATCH v2 0/3] i915 lpsp support for lpsp igt Anshuman Gupta
2020-03-23 7:13 ` [Intel-gfx] [PATCH v2 1/3] drm/i915: Power well id for ICL PG3 Anshuman Gupta
2020-03-23 7:13 ` [Intel-gfx] [PATCH v2 2/3] drm/i915: Add i915_lpsp_info debugfs Anshuman Gupta
@ 2020-03-23 7:13 ` Anshuman Gupta
2020-03-23 11:12 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915 lpsp support for lpsp igt (rev3) Patchwork
` (2 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Anshuman Gupta @ 2020-03-23 7:13 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ankit.k.nautiyal, martin.peres
Add connector debugfs attributes for each intel
connector which is getting register.
v2:
- adding connector debugfs for each connector in
intel_connector_register() to fix CI failure for legacy connectors.
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_connector.c | 3 +++
drivers/gpu/drm/i915/display/intel_dp.c | 3 ---
drivers/gpu/drm/i915/display/intel_hdmi.c | 3 ---
3 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_connector.c b/drivers/gpu/drm/i915/display/intel_connector.c
index 903e49659f56..0cf5fe326a0b 100644
--- a/drivers/gpu/drm/i915/display/intel_connector.c
+++ b/drivers/gpu/drm/i915/display/intel_connector.c
@@ -33,6 +33,7 @@
#include "i915_drv.h"
#include "intel_connector.h"
+#include "intel_display_debugfs.h"
#include "intel_display_types.h"
#include "intel_hdcp.h"
@@ -123,6 +124,8 @@ int intel_connector_register(struct drm_connector *connector)
goto err_backlight;
}
+ intel_connector_debugfs_add(connector);
+
return 0;
err_backlight:
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 49d01d33de69..db90322a6315 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -48,7 +48,6 @@
#include "intel_audio.h"
#include "intel_connector.h"
#include "intel_ddi.h"
-#include "intel_display_debugfs.h"
#include "intel_display_types.h"
#include "intel_dp.h"
#include "intel_dp_link_training.h"
@@ -6204,8 +6203,6 @@ intel_dp_connector_register(struct drm_connector *connector)
if (ret)
return ret;
- intel_connector_debugfs_add(connector);
-
DRM_DEBUG_KMS("registering %s bus for %s\n",
intel_dp->aux.name, connector->kdev->kobj.name);
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 39930232b253..2d4dced7143e 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -44,7 +44,6 @@
#include "intel_audio.h"
#include "intel_connector.h"
#include "intel_ddi.h"
-#include "intel_display_debugfs.h"
#include "intel_display_types.h"
#include "intel_dp.h"
#include "intel_dpio_phy.h"
@@ -2813,8 +2812,6 @@ intel_hdmi_connector_register(struct drm_connector *connector)
if (ret)
return ret;
- intel_connector_debugfs_add(connector);
-
intel_hdmi_create_i2c_symlink(connector);
return ret;
--
2.25.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915 lpsp support for lpsp igt (rev3)
2020-03-23 7:13 [Intel-gfx] [PATCH v2 0/3] i915 lpsp support for lpsp igt Anshuman Gupta
` (2 preceding siblings ...)
2020-03-23 7:13 ` [Intel-gfx] [PATCH v2 3/3] drm/i915: Add connector dbgfs for all connectors Anshuman Gupta
@ 2020-03-23 11:12 ` Patchwork
2020-03-23 11:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-03-23 15:35 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
5 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2020-03-23 11:12 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
== Series Details ==
Series: i915 lpsp support for lpsp igt (rev3)
URL : https://patchwork.freedesktop.org/series/74648/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
bf39cdd33479 drm/i915: Power well id for ICL PG3
6711ab7084cf drm/i915: Add i915_lpsp_info debugfs
-:143: WARNING:SYMBOLIC_PERMS: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'.
#143: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs.c:2232:
+ debugfs_create_file("i915_lpsp_info", S_IRUGO, root,
total: 0 errors, 1 warnings, 0 checks, 125 lines checked
870cab0334d9 drm/i915: Add connector dbgfs for all connectors
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for i915 lpsp support for lpsp igt (rev3)
2020-03-23 7:13 [Intel-gfx] [PATCH v2 0/3] i915 lpsp support for lpsp igt Anshuman Gupta
` (3 preceding siblings ...)
2020-03-23 11:12 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915 lpsp support for lpsp igt (rev3) Patchwork
@ 2020-03-23 11:36 ` Patchwork
2020-03-23 15:35 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
5 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2020-03-23 11:36 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
== Series Details ==
Series: i915 lpsp support for lpsp igt (rev3)
URL : https://patchwork.freedesktop.org/series/74648/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8175 -> Patchwork_17049
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/index.html
Known issues
------------
Here are the changes found in Patchwork_17049 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_rpm@module-reload:
- fi-kbl-8809g: [PASS][1] -> [SKIP][2] ([fdo#109271])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/fi-kbl-8809g/igt@i915_pm_rpm@module-reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/fi-kbl-8809g/igt@i915_pm_rpm@module-reload.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-icl-u2: [PASS][3] -> [FAIL][4] ([i915#217])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#217]: https://gitlab.freedesktop.org/drm/intel/issues/217
Participating hosts (47 -> 42)
------------------------------
Missing (5): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_5527 -> IGTPW_4338
* Linux: CI_DRM_8175 -> Patchwork_17049
CI-20190529: 20190529
CI_DRM_8175: 75b2b15f2ab26f5373a13ece8e5d40b472333d0e @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_4338: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4338/index.html
IGT_5527: 0ab05a51a059645d2e12e553a1de1d97451f57c5 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17049: 870cab0334d9bfcb979622504bb1fa545ff2cda8 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
870cab0334d9 drm/i915: Add connector dbgfs for all connectors
6711ab7084cf drm/i915: Add i915_lpsp_info debugfs
bf39cdd33479 drm/i915: Power well id for ICL PG3
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for i915 lpsp support for lpsp igt (rev3)
2020-03-23 7:13 [Intel-gfx] [PATCH v2 0/3] i915 lpsp support for lpsp igt Anshuman Gupta
` (4 preceding siblings ...)
2020-03-23 11:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-03-23 15:35 ` Patchwork
5 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2020-03-23 15:35 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
== Series Details ==
Series: i915 lpsp support for lpsp igt (rev3)
URL : https://patchwork.freedesktop.org/series/74648/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8175_full -> Patchwork_17049_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_17049_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_17049_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_17049_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_pm_rpm@system-suspend:
- shard-tglb: [PASS][1] -> [SKIP][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-tglb3/igt@i915_pm_rpm@system-suspend.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-tglb2/igt@i915_pm_rpm@system-suspend.html
- shard-iclb: [PASS][3] -> [SKIP][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-iclb1/igt@i915_pm_rpm@system-suspend.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-iclb1/igt@i915_pm_rpm@system-suspend.html
#### Warnings ####
* igt@i915_pm_lpsp@non-edp:
- shard-iclb: [SKIP][5] ([fdo#109301]) -> [SKIP][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-iclb7/igt@i915_pm_lpsp@non-edp.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-iclb7/igt@i915_pm_lpsp@non-edp.html
- shard-tglb: [SKIP][7] ([fdo#109301]) -> [SKIP][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-tglb6/igt@i915_pm_lpsp@non-edp.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-tglb2/igt@i915_pm_lpsp@non-edp.html
* igt@i915_pm_lpsp@screens-disabled:
- shard-snb: [SKIP][9] ([fdo#109271]) -> [FAIL][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-snb6/igt@i915_pm_lpsp@screens-disabled.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-snb6/igt@i915_pm_lpsp@screens-disabled.html
Known issues
------------
Here are the changes found in Patchwork_17049_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_busy@extended-parallel-vcs1:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#112080]) +11 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-iclb1/igt@gem_busy@extended-parallel-vcs1.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-iclb5/igt@gem_busy@extended-parallel-vcs1.html
* igt@gem_ctx_isolation@rcs0-s3:
- shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) +3 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-kbl4/igt@gem_ctx_isolation@rcs0-s3.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-kbl4/igt@gem_ctx_isolation@rcs0-s3.html
* igt@gem_ctx_persistence@close-replace-race:
- shard-tglb: [PASS][15] -> [INCOMPLETE][16] ([i915#1402])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-tglb6/igt@gem_ctx_persistence@close-replace-race.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-tglb8/igt@gem_ctx_persistence@close-replace-race.html
* igt@gem_exec_async@concurrent-writes-bsd:
- shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#112146]) +6 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-iclb7/igt@gem_exec_async@concurrent-writes-bsd.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-iclb1/igt@gem_exec_async@concurrent-writes-bsd.html
* igt@gem_exec_schedule@implicit-write-read-bsd1:
- shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109276] / [i915#677]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-iclb2/igt@gem_exec_schedule@implicit-write-read-bsd1.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-iclb7/igt@gem_exec_schedule@implicit-write-read-bsd1.html
* igt@gem_exec_schedule@pi-shared-iova-bsd:
- shard-iclb: [PASS][21] -> [SKIP][22] ([i915#677]) +1 similar issue
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-iclb8/igt@gem_exec_schedule@pi-shared-iova-bsd.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-iclb1/igt@gem_exec_schedule@pi-shared-iova-bsd.html
* igt@gem_exec_schedule@preempt-queue-bsd1:
- shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109276]) +22 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-iclb4/igt@gem_exec_schedule@preempt-queue-bsd1.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-iclb6/igt@gem_exec_schedule@preempt-queue-bsd1.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-glk: [PASS][25] -> [FAIL][26] ([i915#644])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-glk1/igt@gem_ppgtt@flink-and-close-vma-leak.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-glk3/igt@gem_ppgtt@flink-and-close-vma-leak.html
- shard-kbl: [PASS][27] -> [FAIL][28] ([i915#644])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-kbl2/igt@gem_ppgtt@flink-and-close-vma-leak.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-kbl3/igt@gem_ppgtt@flink-and-close-vma-leak.html
- shard-skl: [PASS][29] -> [FAIL][30] ([i915#644])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-skl2/igt@gem_ppgtt@flink-and-close-vma-leak.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-skl10/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][31] -> [FAIL][32] ([i915#454])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-iclb7/igt@i915_pm_dc@dc6-psr.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-iclb2/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_rpm@system-suspend:
- shard-skl: [PASS][33] -> [SKIP][34] ([fdo#109271])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-skl1/igt@i915_pm_rpm@system-suspend.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-skl8/igt@i915_pm_rpm@system-suspend.html
- shard-glk: [PASS][35] -> [SKIP][36] ([fdo#109271])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-glk8/igt@i915_pm_rpm@system-suspend.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-glk1/igt@i915_pm_rpm@system-suspend.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-kbl: [PASS][37] -> [INCOMPLETE][38] ([i915#155])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-kbl7/igt@i915_suspend@fence-restore-tiled2untiled.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-kbl3/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@kms_cursor_crc@pipe-a-cursor-256x256-random:
- shard-glk: [PASS][39] -> [FAIL][40] ([i915#54])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-glk5/igt@kms_cursor_crc@pipe-a-cursor-256x256-random.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-glk3/igt@kms_cursor_crc@pipe-a-cursor-256x256-random.html
* igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding:
- shard-skl: [PASS][41] -> [FAIL][42] ([i915#54])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-skl8/igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-skl8/igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding.html
* igt@kms_cursor_crc@pipe-b-cursor-64x21-sliding:
- shard-apl: [PASS][43] -> [FAIL][44] ([i915#54])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-apl6/igt@kms_cursor_crc@pipe-b-cursor-64x21-sliding.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-apl4/igt@kms_cursor_crc@pipe-b-cursor-64x21-sliding.html
* igt@kms_cursor_legacy@flip-vs-cursor-crc-legacy:
- shard-skl: [PASS][45] -> [FAIL][46] ([IGT#5])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-crc-legacy.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-skl5/igt@kms_cursor_legacy@flip-vs-cursor-crc-legacy.html
* igt@kms_flip@plain-flip-fb-recreate:
- shard-skl: [PASS][47] -> [FAIL][48] ([i915#34])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-skl1/igt@kms_flip@plain-flip-fb-recreate.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-skl1/igt@kms_flip@plain-flip-fb-recreate.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-pwrite:
- shard-skl: [PASS][49] -> [FAIL][50] ([i915#49])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-skl10/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-pwrite.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-skl7/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-pwrite.html
* igt@kms_hdmi_inject@inject-audio:
- shard-tglb: [PASS][51] -> [SKIP][52] ([i915#433])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-tglb7/igt@kms_hdmi_inject@inject-audio.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-tglb6/igt@kms_hdmi_inject@inject-audio.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [PASS][53] -> [FAIL][54] ([i915#1188])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-skl7/igt@kms_hdr@bpc-switch-suspend.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-skl10/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- shard-apl: [PASS][55] -> [DMESG-WARN][56] ([i915#180]) +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-apl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-apl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][57] -> [FAIL][58] ([fdo#108145] / [i915#265]) +1 similar issue
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-glk: [PASS][59] -> [FAIL][60] ([i915#899])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-glk1/igt@kms_plane_lowres@pipe-a-tiling-x.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-glk7/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_psr@psr2_dpms:
- shard-iclb: [PASS][61] -> [SKIP][62] ([fdo#109441])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-iclb2/igt@kms_psr@psr2_dpms.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-iclb5/igt@kms_psr@psr2_dpms.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][63] -> [FAIL][64] ([i915#31])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-apl2/igt@kms_setmode@basic.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-apl4/igt@kms_setmode@basic.html
* igt@perf@gen12-mi-rpc:
- shard-tglb: [PASS][65] -> [FAIL][66] ([i915#1085])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-tglb1/igt@perf@gen12-mi-rpc.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-tglb8/igt@perf@gen12-mi-rpc.html
#### Possible fixes ####
* igt@gem_busy@busy-vcs1:
- shard-iclb: [SKIP][67] ([fdo#112080]) -> [PASS][68] +11 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-iclb6/igt@gem_busy@busy-vcs1.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-iclb2/igt@gem_busy@busy-vcs1.html
* igt@gem_ctx_persistence@engines-mixed-process@vcs0:
- shard-skl: [FAIL][69] ([i915#679]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-skl10/igt@gem_ctx_persistence@engines-mixed-process@vcs0.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-skl5/igt@gem_ctx_persistence@engines-mixed-process@vcs0.html
* igt@gem_ctx_persistence@engines-mixed-process@vecs0:
- shard-skl: [INCOMPLETE][71] ([i915#1197] / [i915#1239]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-skl10/igt@gem_ctx_persistence@engines-mixed-process@vecs0.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-skl5/igt@gem_ctx_persistence@engines-mixed-process@vecs0.html
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [SKIP][73] ([fdo#110841]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-iclb1/igt@gem_ctx_shared@exec-single-timeline-bsd.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-iclb6/igt@gem_ctx_shared@exec-single-timeline-bsd.html
* igt@gem_exec_schedule@implicit-read-write-bsd1:
- shard-iclb: [SKIP][75] ([fdo#109276] / [i915#677]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-iclb3/igt@gem_exec_schedule@implicit-read-write-bsd1.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-iclb4/igt@gem_exec_schedule@implicit-read-write-bsd1.html
* igt@gem_exec_schedule@out-order-bsd2:
- shard-iclb: [SKIP][77] ([fdo#109276]) -> [PASS][78] +19 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-iclb8/igt@gem_exec_schedule@out-order-bsd2.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-iclb2/igt@gem_exec_schedule@out-order-bsd2.html
* igt@gem_exec_schedule@pi-common-bsd:
- shard-iclb: [SKIP][79] ([i915#677]) -> [PASS][80] +1 similar issue
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-iclb4/igt@gem_exec_schedule@pi-common-bsd.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-iclb6/igt@gem_exec_schedule@pi-common-bsd.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [SKIP][81] ([fdo#112146]) -> [PASS][82] +3 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-iclb2/igt@gem_exec_schedule@preemptive-hang-bsd.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-iclb3/igt@gem_exec_schedule@preemptive-hang-bsd.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-apl: [FAIL][83] ([i915#644]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-apl6/igt@gem_ppgtt@flink-and-close-vma-leak.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-apl2/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@i915_pm_lpsp@edp-panel-fitter:
- shard-iclb: [SKIP][85] ([fdo#109301]) -> [PASS][86] +2 similar issues
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-iclb1/igt@i915_pm_lpsp@edp-panel-fitter.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-iclb3/igt@i915_pm_lpsp@edp-panel-fitter.html
* igt@i915_pm_lpsp@screens-disabled:
- shard-skl: [SKIP][87] ([fdo#109271]) -> [PASS][88] +2 similar issues
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-skl5/igt@i915_pm_lpsp@screens-disabled.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-skl8/igt@i915_pm_lpsp@screens-disabled.html
- shard-tglb: [SKIP][89] ([fdo#109301]) -> [PASS][90] +2 similar issues
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-tglb2/igt@i915_pm_lpsp@screens-disabled.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-tglb1/igt@i915_pm_lpsp@screens-disabled.html
- shard-kbl: [SKIP][91] ([fdo#109271]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-kbl3/igt@i915_pm_lpsp@screens-disabled.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-kbl7/igt@i915_pm_lpsp@screens-disabled.html
- shard-apl: [SKIP][93] ([fdo#109271]) -> [PASS][94]
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-apl3/igt@i915_pm_lpsp@screens-disabled.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-apl4/igt@i915_pm_lpsp@screens-disabled.html
- shard-glk: [SKIP][95] ([fdo#109271]) -> [PASS][96]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-glk1/igt@i915_pm_lpsp@screens-disabled.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-glk1/igt@i915_pm_lpsp@screens-disabled.html
* igt@kms_cursor_crc@pipe-a-cursor-128x128-offscreen:
- shard-skl: [FAIL][97] ([i915#54]) -> [PASS][98]
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-skl10/igt@kms_cursor_crc@pipe-a-cursor-128x128-offscreen.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-skl4/igt@kms_cursor_crc@pipe-a-cursor-128x128-offscreen.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-apl: [INCOMPLETE][99] ([fdo#103927]) -> [PASS][100]
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-apl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-apl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [DMESG-WARN][101] ([i915#180]) -> [PASS][102] +6 similar issues
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-kbl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-kbl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-pwrite:
- shard-glk: [FAIL][103] ([i915#49]) -> [PASS][104]
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-glk6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-pwrite.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-glk9/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbc-modesetfrombusy:
- shard-snb: [SKIP][105] ([fdo#109271]) -> [PASS][106] +2 similar issues
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-snb2/igt@kms_frontbuffer_tracking@fbc-modesetfrombusy.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-snb5/igt@kms_frontbuffer_tracking@fbc-modesetfrombusy.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [FAIL][107] ([i915#1188]) -> [PASS][108]
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-skl1/igt@kms_hdr@bpc-switch-dpms.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-skl4/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- shard-skl: [FAIL][109] ([i915#53]) -> [PASS][110]
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-skl10/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-skl3/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
* igt@kms_plane@plane-panning-bottom-right-pipe-a-planes:
- shard-skl: [FAIL][111] ([i915#1036]) -> [PASS][112]
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-skl10/igt@kms_plane@plane-panning-bottom-right-pipe-a-planes.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-skl6/igt@kms_plane@plane-panning-bottom-right-pipe-a-planes.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-apl: [DMESG-WARN][113] ([i915#180]) -> [PASS][114] +3 similar issues
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-apl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
- shard-kbl: [INCOMPLETE][115] ([i915#155] / [i915#648]) -> [PASS][116]
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-kbl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-kbl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_plane_lowres@pipe-a-tiling-y:
- shard-glk: [FAIL][117] ([i915#899]) -> [PASS][118]
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-glk2/igt@kms_plane_lowres@pipe-a-tiling-y.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-glk3/igt@kms_plane_lowres@pipe-a-tiling-y.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [SKIP][119] ([fdo#109441]) -> [PASS][120] +1 similar issue
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-iclb4/igt@kms_psr@psr2_primary_mmap_cpu.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend:
- shard-kbl: [INCOMPLETE][121] ([i915#155]) -> [PASS][122]
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-kbl6/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-kbl1/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
#### Warnings ####
* igt@gem_userptr_blits@sync-unmap-after-close:
- shard-snb: [DMESG-WARN][123] ([fdo#111870] / [i915#478]) -> [DMESG-WARN][124] ([fdo#110789] / [fdo#111870] / [i915#478])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8175/shard-snb2/igt@gem_userptr_blits@sync-unmap-after-close.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/shard-snb6/igt@gem_userptr_blits@sync-unmap-after-close.html
[IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109301]: https://bugs.freedesktop.org/show_bug.cgi?id=109301
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110789]: https://bugs.freedesktop.org/show_bug.cgi?id=110789
[fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
[fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
[i915#1036]: https://gitlab.freedesktop.org/drm/intel/issues/1036
[i915#1085]: https://gitlab.freedesktop.org/drm/intel/issues/1085
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1197]: https://gitlab.freedesktop.org/drm/intel/issues/1197
[i915#1239]: https://gitlab.freedesktop.org/drm/intel/issues/1239
[i915#1402]: https://gitlab.freedesktop.org/drm/intel/issues/1402
[i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
[i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#478]: https://gitlab.freedesktop.org/drm/intel/issues/478
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#53]: https://gitlab.freedesktop.org/drm/intel/issues/53
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
[i915#648]: https://gitlab.freedesktop.org/drm/intel/issues/648
[i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
[i915#679]: https://gitlab.freedesktop.org/drm/intel/issues/679
[i915#899]: https://gitlab.freedesktop.org/drm/intel/issues/899
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_5527 -> IGTPW_4338
* Linux: CI_DRM_8175 -> Patchwork_17049
CI-20190529: 20190529
CI_DRM_8175: 75b2b15f2ab26f5373a13ece8e5d40b472333d0e @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_4338: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4338/index.html
IGT_5527: 0ab05a51a059645d2e12e553a1de1d97451f57c5 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17049: 870cab0334d9bfcb979622504bb1fa545ff2cda8 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17049/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH v2 2/3] drm/i915: Add i915_lpsp_info debugfs
2020-03-24 15:53 ` Jani Nikula
@ 2020-03-25 8:00 ` Anshuman Gupta
0 siblings, 0 replies; 10+ messages in thread
From: Anshuman Gupta @ 2020-03-25 8:00 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, ankit.k.nautiyal, martin.peres
On 2020-03-24 at 17:53:08 +0200, Jani Nikula wrote:
> On Tue, 24 Mar 2020, Anshuman Gupta <anshuman.gupta@intel.com> wrote:
> > New i915_pm_lpsp igt solution approach relies on connector specific
> > debugfs attribute i915_lpsp_info, it exposes whether an output is
> > capable of driving lpsp and exposes lpsp enablement info.
> >
> > v2:
> > - CI fixup.
> >
> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > ---
> > .../drm/i915/display/intel_display_debugfs.c | 104 ++++++++++++++++++
> > 1 file changed, 104 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > index 424f4e52f783..eb9d88341d48 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > @@ -9,6 +9,7 @@
> > #include "i915_debugfs.h"
> > #include "intel_csr.h"
> > #include "intel_display_debugfs.h"
> > +#include "intel_display_power.h"
> > #include "intel_display_types.h"
> > #include "intel_dp.h"
> > #include "intel_fbc.h"
> > @@ -611,6 +612,95 @@ static void intel_hdcp_info(struct seq_file *m,
> > seq_puts(m, "\n");
> > }
> >
> > +static bool intel_have_embedded_panel(struct drm_connector *connector)
> > +{
> > + return connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
> > + connector->connector_type == DRM_MODE_CONNECTOR_eDP;
>
> I know you don't care for this use case, but the function naming leads
> one to believe this checks for at least LVDS panels too.
>
> > +}
> > +
> > +static bool intel_have_gen9_lpsp_panel(struct drm_connector *connector)
> > +{
> > + return intel_have_embedded_panel(connector) ||
> > + connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort;
> > +}
> > +
> > +static int
> > +intel_lpsp_power_well_enabled(struct drm_i915_private *dev_priv,
> > + enum i915_power_well_id power_well_id)
> > +{
> > + struct i915_power_domains *power_domains = &dev_priv->power_domains;
> > + struct i915_power_well *power_well = NULL, *pw_itr;
> > + bool is_enabled;
> > +
> > + mutex_lock(&power_domains->lock);
> > +
> > + for_each_power_well(dev_priv, pw_itr)
> > + if (pw_itr->desc->id == power_well_id) {
> > + power_well = pw_itr;
> > + break;
> > + }
>
> I don't think this code has any business looking inside the guts of the
> power well code. I see that intel_hdcp.c does this kind of loop too, and
> that *also* shouldn't be doing that.
>
> See intel_display_power_well_is_enabled(). Does what you want, and does
> it correctly. So really, the whole intel_lpsp_power_well_enabled()
> function shouldn't be added.
Thanks Jani for review comments, actually at v1 version i had used
used intel_display_power_well_is_enabled,
but i was getting below DMEAG_WARN on a CI run,
"PM wakelock ref not held during HW access"
Apperently it seemed to me intel_display_power_well_is_enabled() is meant for
internal use in intel_display_power.c as it was not declared in header and it
didn't held any PM wakeref.
May be i require below sequence to use intel_display_power_well_is_enabled,
wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
intel_display_power_well_is_enabled()
intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
Please correct me if i am wrong here.
>
> > +
> > + if (drm_WARN_ON(&dev_priv->drm, !power_well)) {
> > + mutex_unlock(&power_domains->lock);
> > + /* Assume that BIOS has enabled the power well*/
> > + return true;
> > + }
> > +
> > + is_enabled = !!power_well->count;
> > + mutex_unlock(&power_domains->lock);
> > +
> > + return is_enabled;
> > +}
> > +
> > +static void
> > +intel_lpsp_capable_info(struct seq_file *m, struct drm_connector *connector)
> > +{
> > + struct intel_encoder *encoder =
> > + intel_attached_encoder(to_intel_connector(connector));
> > + struct drm_i915_private *dev_priv = to_i915(connector->dev);
> > + bool lpsp_capable = false;
> > +
> > + if (IS_TIGERLAKE(dev_priv) && encoder->port <= PORT_C) {
> > + lpsp_capable = true;
> > + } else if (INTEL_GEN(dev_priv) >= 11 && intel_have_embedded_panel(connector)) {
> > + lpsp_capable = true;
> > + } else if (INTEL_GEN(dev_priv) >= 9 && (encoder->port == PORT_A &&
> > + intel_have_gen9_lpsp_panel(connector))) {
> > + lpsp_capable = true;
> > + } else if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) &&
> > + connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
> > + lpsp_capable = true;
> > + } else {
> > + seq_puts(m, "LPSP not supported\n");
> > + return;
> > + }
>
> The whole if ladder above looks suspect, and I'm not sure your helpers
> are helping here.
>
> > +
> > + lpsp_capable ? seq_puts(m, "LPSP capable\n") : seq_puts(m, "LPSP incapable\n");
>
> lpsp_capable is always true when you end up here.
>
> > +}
> > +
> > +static void
> > +intel_lpsp_enable_info(struct seq_file *m, struct drm_connector *connector)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(connector->dev);
> > + bool is_lpsp = false;
> > +
> > + if (INTEL_GEN(dev_priv) >= 11) {
> > + is_lpsp = !intel_lpsp_power_well_enabled(dev_priv,
> > + ICL_DISP_PW_3);
> > + } else if (INTEL_GEN(dev_priv) >= 9) {
> > + is_lpsp = !intel_lpsp_power_well_enabled(dev_priv,
> > + SKL_DISP_PW_2);
> > + } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> > + is_lpsp = !intel_lpsp_power_well_enabled(dev_priv,
> > + HSW_DISP_PW_GLOBAL);
>
> The abstraction should probably be to figure out the correct power well
> id based on the platform, and then using the generic power well enabled
> call.
>
> > + } else {
> > + seq_puts(m, "LPSP not supported\n");
>
> The "LPSP not supported" case differs from lpsp capable. Huh?
My bad while fixing regression on legacy platform i messed it,
i will fix this.
>
> > + return;
> > + }
> > +
> > + is_lpsp ? seq_puts(m, "LPSP enabled\n") : seq_puts(m, "LPSP disabled\n");
> > +}
> > +
> > static void intel_dp_info(struct seq_file *m,
> > struct intel_connector *intel_connector)
> > {
> > @@ -1987,6 +2077,17 @@ static int i915_hdcp_sink_capability_show(struct seq_file *m, void *data)
> > }
> > DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability);
> >
> > +static int i915_lpsp_info_show(struct seq_file *m, void *data)
> > +{
> > + struct drm_connector *connector = m->private;
> > +
> > + intel_lpsp_capable_info(m, connector);
> > + intel_lpsp_enable_info(m, connector);
>
> I'm not sure having these two separate do you any good. Probably would
> help *not* separating these.
>
> > +
> > + return 0;
> > +}
> > +DEFINE_SHOW_ATTRIBUTE(i915_lpsp_info);
> > +
> > static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
> > {
> > struct drm_connector *connector = m->private;
> > @@ -2130,5 +2231,8 @@ int intel_connector_debugfs_add(struct drm_connector *connector)
> > debugfs_create_file("i915_dsc_fec_support", S_IRUGO, root,
> > connector, &i915_dsc_fec_support_fops);
> >
> > + debugfs_create_file("i915_lpsp_info", 0444, root,
> > + connector, &i915_lpsp_info_fops);
>
> The question is, why are you creating this for connectors that do not
> and can not support lpsp to begin with? Your igt test should check for
> the existence of the file anyway.
igt checks for file existence and it will assert the subtest but this
will also fail the test as earlier legacy platform were passing non-lpsp
i915_pm_rpm test considering all non-edp paneld are non-lpsp
https://patchwork.freedesktop.org/patch/358652/?series=74647&rev=4
May be igt lib function i915_output_is_lpsp_capable() should return
false for lgeacy platform and legacy connector,
Please correct me if there is any other better way to handle that.
>
> BR,
> Jani.
>
>
> > +
> > return 0;
> > }
>
> --
> Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH v2 2/3] drm/i915: Add i915_lpsp_info debugfs
2020-03-24 13:25 ` [Intel-gfx] [PATCH v2 2/3] drm/i915: Add i915_lpsp_info debugfs Anshuman Gupta
@ 2020-03-24 15:53 ` Jani Nikula
2020-03-25 8:00 ` Anshuman Gupta
0 siblings, 1 reply; 10+ messages in thread
From: Jani Nikula @ 2020-03-24 15:53 UTC (permalink / raw)
To: Anshuman Gupta, intel-gfx; +Cc: ankit.k.nautiyal, martin.peres
On Tue, 24 Mar 2020, Anshuman Gupta <anshuman.gupta@intel.com> wrote:
> New i915_pm_lpsp igt solution approach relies on connector specific
> debugfs attribute i915_lpsp_info, it exposes whether an output is
> capable of driving lpsp and exposes lpsp enablement info.
>
> v2:
> - CI fixup.
>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> .../drm/i915/display/intel_display_debugfs.c | 104 ++++++++++++++++++
> 1 file changed, 104 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 424f4e52f783..eb9d88341d48 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -9,6 +9,7 @@
> #include "i915_debugfs.h"
> #include "intel_csr.h"
> #include "intel_display_debugfs.h"
> +#include "intel_display_power.h"
> #include "intel_display_types.h"
> #include "intel_dp.h"
> #include "intel_fbc.h"
> @@ -611,6 +612,95 @@ static void intel_hdcp_info(struct seq_file *m,
> seq_puts(m, "\n");
> }
>
> +static bool intel_have_embedded_panel(struct drm_connector *connector)
> +{
> + return connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
> + connector->connector_type == DRM_MODE_CONNECTOR_eDP;
I know you don't care for this use case, but the function naming leads
one to believe this checks for at least LVDS panels too.
> +}
> +
> +static bool intel_have_gen9_lpsp_panel(struct drm_connector *connector)
> +{
> + return intel_have_embedded_panel(connector) ||
> + connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort;
> +}
> +
> +static int
> +intel_lpsp_power_well_enabled(struct drm_i915_private *dev_priv,
> + enum i915_power_well_id power_well_id)
> +{
> + struct i915_power_domains *power_domains = &dev_priv->power_domains;
> + struct i915_power_well *power_well = NULL, *pw_itr;
> + bool is_enabled;
> +
> + mutex_lock(&power_domains->lock);
> +
> + for_each_power_well(dev_priv, pw_itr)
> + if (pw_itr->desc->id == power_well_id) {
> + power_well = pw_itr;
> + break;
> + }
I don't think this code has any business looking inside the guts of the
power well code. I see that intel_hdcp.c does this kind of loop too, and
that *also* shouldn't be doing that.
See intel_display_power_well_is_enabled(). Does what you want, and does
it correctly. So really, the whole intel_lpsp_power_well_enabled()
function shouldn't be added.
> +
> + if (drm_WARN_ON(&dev_priv->drm, !power_well)) {
> + mutex_unlock(&power_domains->lock);
> + /* Assume that BIOS has enabled the power well*/
> + return true;
> + }
> +
> + is_enabled = !!power_well->count;
> + mutex_unlock(&power_domains->lock);
> +
> + return is_enabled;
> +}
> +
> +static void
> +intel_lpsp_capable_info(struct seq_file *m, struct drm_connector *connector)
> +{
> + struct intel_encoder *encoder =
> + intel_attached_encoder(to_intel_connector(connector));
> + struct drm_i915_private *dev_priv = to_i915(connector->dev);
> + bool lpsp_capable = false;
> +
> + if (IS_TIGERLAKE(dev_priv) && encoder->port <= PORT_C) {
> + lpsp_capable = true;
> + } else if (INTEL_GEN(dev_priv) >= 11 && intel_have_embedded_panel(connector)) {
> + lpsp_capable = true;
> + } else if (INTEL_GEN(dev_priv) >= 9 && (encoder->port == PORT_A &&
> + intel_have_gen9_lpsp_panel(connector))) {
> + lpsp_capable = true;
> + } else if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) &&
> + connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
> + lpsp_capable = true;
> + } else {
> + seq_puts(m, "LPSP not supported\n");
> + return;
> + }
The whole if ladder above looks suspect, and I'm not sure your helpers
are helping here.
> +
> + lpsp_capable ? seq_puts(m, "LPSP capable\n") : seq_puts(m, "LPSP incapable\n");
lpsp_capable is always true when you end up here.
> +}
> +
> +static void
> +intel_lpsp_enable_info(struct seq_file *m, struct drm_connector *connector)
> +{
> + struct drm_i915_private *dev_priv = to_i915(connector->dev);
> + bool is_lpsp = false;
> +
> + if (INTEL_GEN(dev_priv) >= 11) {
> + is_lpsp = !intel_lpsp_power_well_enabled(dev_priv,
> + ICL_DISP_PW_3);
> + } else if (INTEL_GEN(dev_priv) >= 9) {
> + is_lpsp = !intel_lpsp_power_well_enabled(dev_priv,
> + SKL_DISP_PW_2);
> + } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> + is_lpsp = !intel_lpsp_power_well_enabled(dev_priv,
> + HSW_DISP_PW_GLOBAL);
The abstraction should probably be to figure out the correct power well
id based on the platform, and then using the generic power well enabled
call.
> + } else {
> + seq_puts(m, "LPSP not supported\n");
The "LPSP not supported" case differs from lpsp capable. Huh?
> + return;
> + }
> +
> + is_lpsp ? seq_puts(m, "LPSP enabled\n") : seq_puts(m, "LPSP disabled\n");
> +}
> +
> static void intel_dp_info(struct seq_file *m,
> struct intel_connector *intel_connector)
> {
> @@ -1987,6 +2077,17 @@ static int i915_hdcp_sink_capability_show(struct seq_file *m, void *data)
> }
> DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability);
>
> +static int i915_lpsp_info_show(struct seq_file *m, void *data)
> +{
> + struct drm_connector *connector = m->private;
> +
> + intel_lpsp_capable_info(m, connector);
> + intel_lpsp_enable_info(m, connector);
I'm not sure having these two separate do you any good. Probably would
help *not* separating these.
> +
> + return 0;
> +}
> +DEFINE_SHOW_ATTRIBUTE(i915_lpsp_info);
> +
> static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
> {
> struct drm_connector *connector = m->private;
> @@ -2130,5 +2231,8 @@ int intel_connector_debugfs_add(struct drm_connector *connector)
> debugfs_create_file("i915_dsc_fec_support", S_IRUGO, root,
> connector, &i915_dsc_fec_support_fops);
>
> + debugfs_create_file("i915_lpsp_info", 0444, root,
> + connector, &i915_lpsp_info_fops);
The question is, why are you creating this for connectors that do not
and can not support lpsp to begin with? Your igt test should check for
the existence of the file anyway.
BR,
Jani.
> +
> return 0;
> }
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] [PATCH v2 2/3] drm/i915: Add i915_lpsp_info debugfs
2020-03-24 13:25 [Intel-gfx] [PATCH v2 0/3 RESEND] i915 lpsp support for lpsp igt Anshuman Gupta
@ 2020-03-24 13:25 ` Anshuman Gupta
2020-03-24 15:53 ` Jani Nikula
0 siblings, 1 reply; 10+ messages in thread
From: Anshuman Gupta @ 2020-03-24 13:25 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ankit.k.nautiyal, martin.peres
New i915_pm_lpsp igt solution approach relies on connector specific
debugfs attribute i915_lpsp_info, it exposes whether an output is
capable of driving lpsp and exposes lpsp enablement info.
v2:
- CI fixup.
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
.../drm/i915/display/intel_display_debugfs.c | 104 ++++++++++++++++++
1 file changed, 104 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 424f4e52f783..eb9d88341d48 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -9,6 +9,7 @@
#include "i915_debugfs.h"
#include "intel_csr.h"
#include "intel_display_debugfs.h"
+#include "intel_display_power.h"
#include "intel_display_types.h"
#include "intel_dp.h"
#include "intel_fbc.h"
@@ -611,6 +612,95 @@ static void intel_hdcp_info(struct seq_file *m,
seq_puts(m, "\n");
}
+static bool intel_have_embedded_panel(struct drm_connector *connector)
+{
+ return connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
+ connector->connector_type == DRM_MODE_CONNECTOR_eDP;
+}
+
+static bool intel_have_gen9_lpsp_panel(struct drm_connector *connector)
+{
+ return intel_have_embedded_panel(connector) ||
+ connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort;
+}
+
+static int
+intel_lpsp_power_well_enabled(struct drm_i915_private *dev_priv,
+ enum i915_power_well_id power_well_id)
+{
+ struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_well *power_well = NULL, *pw_itr;
+ bool is_enabled;
+
+ mutex_lock(&power_domains->lock);
+
+ for_each_power_well(dev_priv, pw_itr)
+ if (pw_itr->desc->id == power_well_id) {
+ power_well = pw_itr;
+ break;
+ }
+
+ if (drm_WARN_ON(&dev_priv->drm, !power_well)) {
+ mutex_unlock(&power_domains->lock);
+ /* Assume that BIOS has enabled the power well*/
+ return true;
+ }
+
+ is_enabled = !!power_well->count;
+ mutex_unlock(&power_domains->lock);
+
+ return is_enabled;
+}
+
+static void
+intel_lpsp_capable_info(struct seq_file *m, struct drm_connector *connector)
+{
+ struct intel_encoder *encoder =
+ intel_attached_encoder(to_intel_connector(connector));
+ struct drm_i915_private *dev_priv = to_i915(connector->dev);
+ bool lpsp_capable = false;
+
+ if (IS_TIGERLAKE(dev_priv) && encoder->port <= PORT_C) {
+ lpsp_capable = true;
+ } else if (INTEL_GEN(dev_priv) >= 11 && intel_have_embedded_panel(connector)) {
+ lpsp_capable = true;
+ } else if (INTEL_GEN(dev_priv) >= 9 && (encoder->port == PORT_A &&
+ intel_have_gen9_lpsp_panel(connector))) {
+ lpsp_capable = true;
+ } else if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) &&
+ connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
+ lpsp_capable = true;
+ } else {
+ seq_puts(m, "LPSP not supported\n");
+ return;
+ }
+
+ lpsp_capable ? seq_puts(m, "LPSP capable\n") : seq_puts(m, "LPSP incapable\n");
+}
+
+static void
+intel_lpsp_enable_info(struct seq_file *m, struct drm_connector *connector)
+{
+ struct drm_i915_private *dev_priv = to_i915(connector->dev);
+ bool is_lpsp = false;
+
+ if (INTEL_GEN(dev_priv) >= 11) {
+ is_lpsp = !intel_lpsp_power_well_enabled(dev_priv,
+ ICL_DISP_PW_3);
+ } else if (INTEL_GEN(dev_priv) >= 9) {
+ is_lpsp = !intel_lpsp_power_well_enabled(dev_priv,
+ SKL_DISP_PW_2);
+ } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
+ is_lpsp = !intel_lpsp_power_well_enabled(dev_priv,
+ HSW_DISP_PW_GLOBAL);
+ } else {
+ seq_puts(m, "LPSP not supported\n");
+ return;
+ }
+
+ is_lpsp ? seq_puts(m, "LPSP enabled\n") : seq_puts(m, "LPSP disabled\n");
+}
+
static void intel_dp_info(struct seq_file *m,
struct intel_connector *intel_connector)
{
@@ -1987,6 +2077,17 @@ static int i915_hdcp_sink_capability_show(struct seq_file *m, void *data)
}
DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability);
+static int i915_lpsp_info_show(struct seq_file *m, void *data)
+{
+ struct drm_connector *connector = m->private;
+
+ intel_lpsp_capable_info(m, connector);
+ intel_lpsp_enable_info(m, connector);
+
+ return 0;
+}
+DEFINE_SHOW_ATTRIBUTE(i915_lpsp_info);
+
static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
{
struct drm_connector *connector = m->private;
@@ -2130,5 +2231,8 @@ int intel_connector_debugfs_add(struct drm_connector *connector)
debugfs_create_file("i915_dsc_fec_support", S_IRUGO, root,
connector, &i915_dsc_fec_support_fops);
+ debugfs_create_file("i915_lpsp_info", 0444, root,
+ connector, &i915_lpsp_info_fops);
+
return 0;
}
--
2.25.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
end of thread, other threads:[~2020-03-25 8:10 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-03-23 7:13 [Intel-gfx] [PATCH v2 0/3] i915 lpsp support for lpsp igt Anshuman Gupta
2020-03-23 7:13 ` [Intel-gfx] [PATCH v2 1/3] drm/i915: Power well id for ICL PG3 Anshuman Gupta
2020-03-23 7:13 ` [Intel-gfx] [PATCH v2 2/3] drm/i915: Add i915_lpsp_info debugfs Anshuman Gupta
2020-03-23 7:13 ` [Intel-gfx] [PATCH v2 3/3] drm/i915: Add connector dbgfs for all connectors Anshuman Gupta
2020-03-23 11:12 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915 lpsp support for lpsp igt (rev3) Patchwork
2020-03-23 11:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-03-23 15:35 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-03-24 13:25 [Intel-gfx] [PATCH v2 0/3 RESEND] i915 lpsp support for lpsp igt Anshuman Gupta
2020-03-24 13:25 ` [Intel-gfx] [PATCH v2 2/3] drm/i915: Add i915_lpsp_info debugfs Anshuman Gupta
2020-03-24 15:53 ` Jani Nikula
2020-03-25 8:00 ` Anshuman Gupta
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