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* [Intel-gfx] [PATCH 1/2] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context
@ 2020-03-26 22:35 Chris Wilson
  2020-03-26 22:35 ` [Intel-gfx] [PATCH 2/2] drm/i915/execlists: Explicitly reset both reg and context runtime Chris Wilson
                   ` (2 more replies)
  0 siblings, 3 replies; 5+ messages in thread
From: Chris Wilson @ 2020-03-26 22:35 UTC (permalink / raw)
  To: intel-gfx

In what seems remarkably similar to the w/a required to not reload an
idle context with HEAD==TAIL, it appears we must prevent the HW from
switching to an idle context in ELSP[1], while simultaneously trying to
preempt the HW to run another context and a continuation of the idle
context (which is no longer idle).

  process_csb: vecs0: cs-irq head=0, tail=1
  process_csb: vecs0: csb[1]: status=0x00000882:0x00000020
  trace_ports: vecs0: preempted { 8c0:30!, 0:0 }
  trace_ports: vecs0: promote { 8b2:32!, 8c0:30 }
  trace_ports: vecs0: submit { 8b8:32, 8c0:32 }
  process_csb: vecs0: cs-irq head=1, tail=2
  process_csb: vecs0: csb[2]: status=0x00000814:0x00000040
  trace_ports: vecs0: completed { 8b2:32!, 8c0:30 }
  process_csb: vecs0: cs-irq head=2, tail=5
  process_csb: vecs0: csb[3]: status=0x00000812:0x00000020
  trace_ports: vecs0: preempted { 8c0:30!, 0:0 }
  trace_ports: vecs0: promote { 8b8:32!, 8c0:32 }
  process_csb: vecs0: csb[4]: status=0x00000814:0x00000060
  trace_ports: vecs0: completed { 8b8:32!, 8c0:32 }
  process_csb: vecs0: csb[5]: status=0x00000818:0x00000020
  trace_ports: vecs0: completed { 8c0:32, 0:0 }
  process_csb: vecs0: ring:{start:0x00021000, head:03f8, tail:03f8, ctl:00000000, mode:00000200}
  process_csb: vecs0: rq:{start:00021000, head:03c0, tail:0400, seqno:8c0:32, hwsp:30},
  process_csb: vecs0: ctx:{start:00021000, head:03f8, tail:03f8},
  process_csb: GEM_BUG_ON("context completed before request")

Fortunately, we just so happen to have a semaphore in place to prevent
the ring HEAD from proceeding past the end of a request that we can use
to fix the HEAD in position as we reprogram ELSP.

Closes: https://gitlab.freedesktop.org/drm/intel/issues/1501
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 68 ++++++++++++++---------------
 1 file changed, 34 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index b12355048501..132816235d8a 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1854,7 +1854,7 @@ static inline void clear_ports(struct i915_request **ports, int count)
 	memset_p((void **)ports, NULL, count);
 }
 
-static void execlists_dequeue(struct intel_engine_cs *engine)
+static bool execlists_dequeue(struct intel_engine_cs *engine)
 {
 	struct intel_engine_execlists * const execlists = &engine->execlists;
 	struct i915_request **port = execlists->pending;
@@ -1928,13 +1928,6 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
 				     execlists->queue_priority_hint);
 			record_preemption(execlists);
 
-			/*
-			 * Don't let the RING_HEAD advance past the breadcrumb
-			 * as we unwind (and until we resubmit) so that we do
-			 * not accidentally tell it to go backwards.
-			 */
-			ring_set_paused(engine, 1);
-
 			/*
 			 * Note that we have not stopped the GPU at this point,
 			 * so we are unwinding the incomplete requests as they
@@ -1954,7 +1947,6 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
 				     last->sched.attr.priority,
 				     execlists->queue_priority_hint);
 
-			ring_set_paused(engine, 1);
 			defer_active(engine);
 
 			/*
@@ -1988,7 +1980,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
 				 * of timeslices, our queue might be.
 				 */
 				start_timeslice(engine);
-				return;
+				return false;
 			}
 		}
 	}
@@ -2021,9 +2013,10 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
 			}
 
 			if (last && !can_merge_rq(last, rq)) {
+				/* leave this for another sibling */
 				spin_unlock(&ve->base.active.lock);
 				start_timeslice(engine);
-				return; /* leave this for another sibling */
+				return false;
 			}
 
 			ENGINE_TRACE(engine,
@@ -2193,32 +2186,30 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
 	 * interrupt for secondary ports).
 	 */
 	execlists->queue_priority_hint = queue_prio(execlists);
+	if (!submit)
+		return false;
 
-	if (submit) {
-		*port = execlists_schedule_in(last, port - execlists->pending);
-		execlists->switch_priority_hint =
-			switch_prio(engine, *execlists->pending);
-
-		/*
-		 * Skip if we ended up with exactly the same set of requests,
-		 * e.g. trying to timeslice a pair of ordered contexts
-		 */
-		if (!memcmp(active, execlists->pending,
-			    (port - execlists->pending + 1) * sizeof(*port))) {
-			do
-				execlists_schedule_out(fetch_and_zero(port));
-			while (port-- != execlists->pending);
+	*port = execlists_schedule_in(last, port - execlists->pending);
+	execlists->switch_priority_hint =
+		switch_prio(engine, *execlists->pending);
 
-			goto skip_submit;
-		}
-		clear_ports(port + 1, last_port - port);
+	/*
+	 * Skip if we ended up with exactly the same set of requests,
+	 * e.g. trying to timeslice a pair of ordered contexts
+	 */
+	if (!memcmp(active, execlists->pending,
+		    (port - execlists->pending + 1) * sizeof(*port))) {
+		do
+			execlists_schedule_out(fetch_and_zero(port));
+		while (port-- != execlists->pending);
 
-		execlists_submit_ports(engine);
-		set_preempt_timeout(engine, *active);
-	} else {
-skip_submit:
-		ring_set_paused(engine, 0);
+		return false;
 	}
+	clear_ports(port + 1, last_port - port);
+
+	execlists_submit_ports(engine);
+	set_preempt_timeout(engine, *active);
+	return true;
 }
 
 static void
@@ -2478,7 +2469,16 @@ static void __execlists_submission_tasklet(struct intel_engine_cs *const engine)
 	lockdep_assert_held(&engine->active.lock);
 	if (!READ_ONCE(engine->execlists.pending[0])) {
 		rcu_read_lock(); /* protect peeking at execlists->active */
-		execlists_dequeue(engine);
+
+		/*
+		 * Don't let the RING_HEAD advance past the breadcrumb
+		 * as we unwind (and until we resubmit) so that we do
+		 * not accidentally tell it to go backwards.
+		 */
+		ring_set_paused(engine, 1);
+		if (!execlists_dequeue(engine))
+			ring_set_paused(engine, 0);
+
 		rcu_read_unlock();
 	}
 }
-- 
2.20.1

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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 5+ messages in thread

* [Intel-gfx] [PATCH 2/2] drm/i915/execlists: Explicitly reset both reg and context runtime
  2020-03-26 22:35 [Intel-gfx] [PATCH 1/2] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context Chris Wilson
@ 2020-03-26 22:35 ` Chris Wilson
  2020-03-26 23:47 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context Patchwork
  2020-03-27  0:17 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
  2 siblings, 0 replies; 5+ messages in thread
From: Chris Wilson @ 2020-03-26 22:35 UTC (permalink / raw)
  To: intel-gfx

Upon a GPU reset, we copy the default context image over top of the
guilty image. This will rollback the CTX_TIMESTAMP register to before
our value of ce->runtime.last. Reset both back to 0 so that we do not
encounter an underflow on the next schedule out after resume.

This should not be a huge issue in practice, as hangs should be rare in
correct code.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 24 +++++++++++++-----------
 1 file changed, 13 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 132816235d8a..987dbdf2542e 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -238,6 +238,17 @@ __execlists_update_reg_state(const struct intel_context *ce,
 			     const struct intel_engine_cs *engine,
 			     u32 head);
 
+static u32 intel_context_get_runtime(const struct intel_context *ce)
+{
+	/*
+	 * We can use either ppHWSP[16] which is recorded before the context
+	 * switch (and so excludes the cost of context switches) or use the
+	 * value from the context image itself, which is saved/restored earlier
+	 * and so includes the cost of the save.
+	 */
+	return READ_ONCE(ce->lrc_reg_state[CTX_TIMESTAMP]);
+}
+
 static void mark_eio(struct i915_request *rq)
 {
 	if (i915_request_completed(rq))
@@ -1154,6 +1165,7 @@ static void restore_default_state(struct intel_context *ce,
 		       engine->context_size - PAGE_SIZE);
 
 	execlists_init_reg_state(regs, ce, engine, ce->ring, false);
+	ce->runtime.last = intel_context_get_runtime(ce);
 }
 
 static void reset_active(struct i915_request *rq,
@@ -1195,17 +1207,6 @@ static void reset_active(struct i915_request *rq,
 	ce->lrc_desc |= CTX_DESC_FORCE_RESTORE;
 }
 
-static u32 intel_context_get_runtime(const struct intel_context *ce)
-{
-	/*
-	 * We can use either ppHWSP[16] which is recorded before the context
-	 * switch (and so excludes the cost of context switches) or use the
-	 * value from the context image itself, which is saved/restored earlier
-	 * and so includes the cost of the save.
-	 */
-	return READ_ONCE(ce->lrc_reg_state[CTX_TIMESTAMP]);
-}
-
 static void st_update_runtime_underflow(struct intel_context *ce, s32 dt)
 {
 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
@@ -4581,6 +4582,7 @@ static void init_common_reg_state(u32 * const regs,
 	regs[CTX_CONTEXT_CONTROL] = ctl;
 
 	regs[CTX_RING_CTL] = RING_CTL_SIZE(ring->size) | RING_VALID;
+	regs[CTX_TIMESTAMP] = 0;
 }
 
 static void init_wa_bb_reg_state(u32 * const regs,
-- 
2.20.1

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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 5+ messages in thread

* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context
  2020-03-26 22:35 [Intel-gfx] [PATCH 1/2] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context Chris Wilson
  2020-03-26 22:35 ` [Intel-gfx] [PATCH 2/2] drm/i915/execlists: Explicitly reset both reg and context runtime Chris Wilson
@ 2020-03-26 23:47 ` Patchwork
  2020-03-27  0:17 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
  2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2020-03-26 23:47 UTC (permalink / raw)
  To: Chris Wilson; +Cc: intel-gfx

== Series Details ==

Series: series starting with [1/2] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context
URL   : https://patchwork.freedesktop.org/series/75137/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
5868edb0b7b7 drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context
-:29: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#29: 
  process_csb: vecs0: ring:{start:0x00021000, head:03f8, tail:03f8, ctl:00000000, mode:00000200}

total: 0 errors, 1 warnings, 0 checks, 116 lines checked
ad443fa00c35 drm/i915/execlists: Explicitly reset both reg and context runtime

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 5+ messages in thread

* [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context
  2020-03-26 22:35 [Intel-gfx] [PATCH 1/2] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context Chris Wilson
  2020-03-26 22:35 ` [Intel-gfx] [PATCH 2/2] drm/i915/execlists: Explicitly reset both reg and context runtime Chris Wilson
  2020-03-26 23:47 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context Patchwork
@ 2020-03-27  0:17 ` Patchwork
  2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2020-03-27  0:17 UTC (permalink / raw)
  To: Chris Wilson; +Cc: intel-gfx

== Series Details ==

Series: series starting with [1/2] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context
URL   : https://patchwork.freedesktop.org/series/75137/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_8197 -> Patchwork_17105
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_17105 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_17105, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17105/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_17105:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live@execlists:
    - fi-skl-guc:         [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8197/fi-skl-guc/igt@i915_selftest@live@execlists.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17105/fi-skl-guc/igt@i915_selftest@live@execlists.html
    - fi-cfl-guc:         [PASS][3] -> [INCOMPLETE][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8197/fi-cfl-guc/igt@i915_selftest@live@execlists.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17105/fi-cfl-guc/igt@i915_selftest@live@execlists.html

  
Known issues
------------

  Here are the changes found in Patchwork_17105 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live@execlists:
    - fi-apl-guc:         [PASS][5] -> [INCOMPLETE][6] ([fdo#103927])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8197/fi-apl-guc/igt@i915_selftest@live@execlists.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17105/fi-apl-guc/igt@i915_selftest@live@execlists.html
    - fi-icl-dsi:         [PASS][7] -> [INCOMPLETE][8] ([i915#140])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8197/fi-icl-dsi/igt@i915_selftest@live@execlists.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17105/fi-icl-dsi/igt@i915_selftest@live@execlists.html
    - fi-cml-u2:          [PASS][9] -> [INCOMPLETE][10] ([i915#283])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8197/fi-cml-u2/igt@i915_selftest@live@execlists.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17105/fi-cml-u2/igt@i915_selftest@live@execlists.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@late_gt_pm:
    - fi-bwr-2160:        [INCOMPLETE][11] -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8197/fi-bwr-2160/igt@i915_selftest@live@late_gt_pm.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17105/fi-bwr-2160/igt@i915_selftest@live@late_gt_pm.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140
  [i915#283]: https://gitlab.freedesktop.org/drm/intel/issues/283
  [i915#647]: https://gitlab.freedesktop.org/drm/intel/issues/647


Participating hosts (44 -> 35)
------------------------------

  Additional (2): fi-kbl-r fi-kbl-7500u 
  Missing    (11): fi-hsw-4770r fi-bxt-dsi fi-bdw-samus fi-bsw-n3050 fi-byt-j1900 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ilk-650 fi-kbl-7560u fi-skl-6600u 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_8197 -> Patchwork_17105

  CI-20190529: 20190529
  CI_DRM_8197: 198bab1da198b9d6d5c36d52704dd4abab6e81a8 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5539: e7aae12e37771a8b7796ba252574eb832a5839c3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_17105: ad443fa00c35a13b98b4452da2be652582c3f1d5 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

ad443fa00c35 drm/i915/execlists: Explicitly reset both reg and context runtime
5868edb0b7b7 drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17105/index.html
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 5+ messages in thread

* [Intel-gfx] [PATCH 1/2] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context
@ 2020-03-26 23:18 Chris Wilson
  0 siblings, 0 replies; 5+ messages in thread
From: Chris Wilson @ 2020-03-26 23:18 UTC (permalink / raw)
  To: intel-gfx

In what seems remarkably similar to the w/a required to not reload an
idle context with HEAD==TAIL, it appears we must prevent the HW from
switching to an idle context in ELSP[1], while simultaneously trying to
preempt the HW to run another context and a continuation of the idle
context (which is no longer idle).

  process_csb: vecs0: cs-irq head=0, tail=1
  process_csb: vecs0: csb[1]: status=0x00000882:0x00000020
  trace_ports: vecs0: preempted { 8c0:30!, 0:0 }
  trace_ports: vecs0: promote { 8b2:32!, 8c0:30 }
  trace_ports: vecs0: submit { 8b8:32, 8c0:32 }
  process_csb: vecs0: cs-irq head=1, tail=2
  process_csb: vecs0: csb[2]: status=0x00000814:0x00000040
  trace_ports: vecs0: completed { 8b2:32!, 8c0:30 }
  process_csb: vecs0: cs-irq head=2, tail=5
  process_csb: vecs0: csb[3]: status=0x00000812:0x00000020
  trace_ports: vecs0: preempted { 8c0:30!, 0:0 }
  trace_ports: vecs0: promote { 8b8:32!, 8c0:32 }
  process_csb: vecs0: csb[4]: status=0x00000814:0x00000060
  trace_ports: vecs0: completed { 8b8:32!, 8c0:32 }
  process_csb: vecs0: csb[5]: status=0x00000818:0x00000020
  trace_ports: vecs0: completed { 8c0:32, 0:0 }
  process_csb: vecs0: ring:{start:0x00021000, head:03f8, tail:03f8, ctl:00000000, mode:00000200}
  process_csb: vecs0: rq:{start:00021000, head:03c0, tail:0400, seqno:8c0:32, hwsp:30},
  process_csb: vecs0: ctx:{start:00021000, head:03f8, tail:03f8},
  process_csb: GEM_BUG_ON("context completed before request")

Fortunately, we just so happen to have a semaphore in place to prevent
the ring HEAD from proceeding past the end of a request that we can use
to fix the HEAD in position as we reprogram ELSP.

Closes: https://gitlab.freedesktop.org/drm/intel/issues/1501
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 72 ++++++++++++++---------------
 1 file changed, 36 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index b12355048501..4edda15eba26 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1854,7 +1854,7 @@ static inline void clear_ports(struct i915_request **ports, int count)
 	memset_p((void **)ports, NULL, count);
 }
 
-static void execlists_dequeue(struct intel_engine_cs *engine)
+static bool execlists_dequeue(struct intel_engine_cs *engine)
 {
 	struct intel_engine_execlists * const execlists = &engine->execlists;
 	struct i915_request **port = execlists->pending;
@@ -1928,13 +1928,6 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
 				     execlists->queue_priority_hint);
 			record_preemption(execlists);
 
-			/*
-			 * Don't let the RING_HEAD advance past the breadcrumb
-			 * as we unwind (and until we resubmit) so that we do
-			 * not accidentally tell it to go backwards.
-			 */
-			ring_set_paused(engine, 1);
-
 			/*
 			 * Note that we have not stopped the GPU at this point,
 			 * so we are unwinding the incomplete requests as they
@@ -1954,7 +1947,6 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
 				     last->sched.attr.priority,
 				     execlists->queue_priority_hint);
 
-			ring_set_paused(engine, 1);
 			defer_active(engine);
 
 			/*
@@ -1988,7 +1980,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
 				 * of timeslices, our queue might be.
 				 */
 				start_timeslice(engine);
-				return;
+				return false;
 			}
 		}
 	}
@@ -2021,9 +2013,10 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
 			}
 
 			if (last && !can_merge_rq(last, rq)) {
+				/* leave this for another sibling */
 				spin_unlock(&ve->base.active.lock);
 				start_timeslice(engine);
-				return; /* leave this for another sibling */
+				return false;
 			}
 
 			ENGINE_TRACE(engine,
@@ -2193,32 +2186,31 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
 	 * interrupt for secondary ports).
 	 */
 	execlists->queue_priority_hint = queue_prio(execlists);
+	if (!submit)
+		return false;
 
-	if (submit) {
-		*port = execlists_schedule_in(last, port - execlists->pending);
-		execlists->switch_priority_hint =
-			switch_prio(engine, *execlists->pending);
+	*port = execlists_schedule_in(last, port - execlists->pending);
+	execlists->switch_priority_hint =
+		switch_prio(engine, *execlists->pending);
 
-		/*
-		 * Skip if we ended up with exactly the same set of requests,
-		 * e.g. trying to timeslice a pair of ordered contexts
-		 */
-		if (!memcmp(active, execlists->pending,
-			    (port - execlists->pending + 1) * sizeof(*port))) {
-			do
-				execlists_schedule_out(fetch_and_zero(port));
-			while (port-- != execlists->pending);
-
-			goto skip_submit;
-		}
-		clear_ports(port + 1, last_port - port);
+	/*
+	 * Skip if we ended up with exactly the same set of requests,
+	 * e.g. trying to timeslice a pair of ordered contexts
+	 */
+	if (!memcmp(active, execlists->pending,
+		    (port - execlists->pending + 1) * sizeof(*port))) {
+		do
+			execlists_schedule_out(fetch_and_zero(port));
+		while (port-- != execlists->pending);
 
-		execlists_submit_ports(engine);
-		set_preempt_timeout(engine, *active);
-	} else {
-skip_submit:
-		ring_set_paused(engine, 0);
+		return false;
 	}
+	clear_ports(port + 1, last_port - port);
+
+	execlists_submit_ports(engine);
+	set_preempt_timeout(engine, *active);
+	tasklet_hi_schedule(&execlists->tasklet);
+	return true;
 }
 
 static void
@@ -2478,7 +2470,16 @@ static void __execlists_submission_tasklet(struct intel_engine_cs *const engine)
 	lockdep_assert_held(&engine->active.lock);
 	if (!READ_ONCE(engine->execlists.pending[0])) {
 		rcu_read_lock(); /* protect peeking at execlists->active */
-		execlists_dequeue(engine);
+
+		/*
+		 * Don't let the RING_HEAD advance past the breadcrumb
+		 * as we unwind (and until we resubmit) so that we do
+		 * not accidentally tell it to go backwards.
+		 */
+		ring_set_paused(engine, 1);
+		if (!execlists_dequeue(engine))
+			ring_set_paused(engine, 0);
+
 		rcu_read_unlock();
 	}
 }
@@ -2816,8 +2817,7 @@ static void execlists_reset(struct intel_engine_cs *engine, const char *msg)
 	ring_set_paused(engine, 1); /* Freeze the current request in place */
 	if (execlists_capture(engine))
 		intel_engine_reset(engine, msg);
-	else
-		ring_set_paused(engine, 0);
+	ring_set_paused(engine, 0);
 
 	tasklet_enable(&engine->execlists.tasklet);
 	clear_and_wake_up_bit(bit, lock);
-- 
2.20.1

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^ permalink raw reply related	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2020-03-27  0:17 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-03-26 22:35 [Intel-gfx] [PATCH 1/2] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context Chris Wilson
2020-03-26 22:35 ` [Intel-gfx] [PATCH 2/2] drm/i915/execlists: Explicitly reset both reg and context runtime Chris Wilson
2020-03-26 23:47 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context Patchwork
2020-03-27  0:17 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2020-03-26 23:18 [Intel-gfx] [PATCH 1/2] " Chris Wilson

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