* [Intel-gfx] [PATCH] drm/i915: Revert CDCLK changes to unbreak geminilake
@ 2020-05-25 8:07 Chris Wilson
2020-05-25 8:07 ` Lisovskiy, Stanislav
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: Chris Wilson @ 2020-05-25 8:07 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
This reverts
cac91e671ad5 ("drm/i915: Fix includes and local vars order")
82ea174dc542 ("drm/i915: Remove unneeded hack now for CDCLK")
cd1915460861 ("drm/i915: Adjust CDCLK accordingly to our DBuf bw needs")
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 127 +------------------
drivers/gpu/drm/i915/display/intel_bw.h | 10 --
drivers/gpu/drm/i915/display/intel_cdclk.c | 41 +++---
drivers/gpu/drm/i915/display/intel_display.c | 39 +-----
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/intel_pm.c | 33 +----
drivers/gpu/drm/i915/intel_pm.h | 6 +-
7 files changed, 29 insertions(+), 228 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index a79bd7aeb03b..98bbe719cf4f 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -5,12 +5,12 @@
#include <drm/drm_atomic_state_helper.h>
-#include "intel_atomic.h"
#include "intel_bw.h"
-#include "intel_cdclk.h"
#include "intel_display_types.h"
-#include "intel_pm.h"
#include "intel_sideband.h"
+#include "intel_atomic.h"
+#include "intel_pm.h"
+
/* Parameters for Qclk Geyserville (QGV) */
struct intel_qgv_point {
@@ -428,127 +428,6 @@ intel_atomic_get_bw_state(struct intel_atomic_state *state)
return to_intel_bw_state(bw_state);
}
-int skl_bw_calc_min_cdclk(struct intel_atomic_state *state)
-{
- struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- struct intel_bw_state *new_bw_state = NULL;
- struct intel_bw_state *old_bw_state = NULL;
- const struct intel_crtc_state *crtc_state;
- struct intel_crtc *crtc;
- int max_bw = 0;
- int slice_id;
- int i;
-
- for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
- enum plane_id plane_id;
- struct intel_dbuf_bw *crtc_bw;
-
- new_bw_state = intel_atomic_get_bw_state(state);
- if (IS_ERR(new_bw_state))
- return PTR_ERR(new_bw_state);
-
- crtc_bw = &new_bw_state->dbuf_bw[crtc->pipe];
-
- memset(&crtc_bw->used_bw, 0, sizeof(crtc_bw->used_bw));
-
- for_each_plane_id_on_crtc(crtc, plane_id) {
- const struct skl_ddb_entry *plane_alloc =
- &crtc_state->wm.skl.plane_ddb_y[plane_id];
- const struct skl_ddb_entry *uv_plane_alloc =
- &crtc_state->wm.skl.plane_ddb_uv[plane_id];
- unsigned int data_rate = crtc_state->data_rate[plane_id];
- unsigned int dbuf_mask = 0;
-
- dbuf_mask |= skl_ddb_dbuf_slice_mask(dev_priv, plane_alloc);
- dbuf_mask |= skl_ddb_dbuf_slice_mask(dev_priv, uv_plane_alloc);
-
- /*
- * FIXME: To calculate that more properly we probably
- * need to to split per plane data_rate into data_rate_y
- * and data_rate_uv for multiplanar formats in order not
- * to get accounted those twice if they happen to reside
- * on different slices.
- * However for pre-icl this would work anyway because
- * we have only single slice and for icl+ uv plane has
- * non-zero data rate.
- * So in worst case those calculation are a bit
- * pessimistic, which shouldn't pose any significant
- * problem anyway.
- */
- for_each_dbuf_slice_in_mask(slice_id, dbuf_mask)
- crtc_bw->used_bw[slice_id] += data_rate;
- }
-
- for_each_dbuf_slice(slice_id) {
- /*
- * Current experimental observations show that contrary
- * to BSpec we get underruns once we exceed 64 * CDCLK
- * for slices in total.
- * As a temporary measure in order not to keep CDCLK
- * bumped up all the time we calculate CDCLK according
- * to this formula for overall bw consumed by slices.
- */
- max_bw += crtc_bw->used_bw[slice_id];
- }
-
- new_bw_state->min_cdclk = max_bw / 64;
-
- old_bw_state = intel_atomic_get_old_bw_state(state);
- }
-
- if (!old_bw_state)
- return 0;
-
- if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) {
- int ret = intel_atomic_lock_global_state(&new_bw_state->base);
-
- if (ret)
- return ret;
- }
-
- return 0;
-}
-
-int intel_bw_calc_min_cdclk(struct intel_atomic_state *state)
-{
- int i;
- const struct intel_crtc_state *crtc_state;
- struct intel_crtc *crtc;
- int min_cdclk = 0;
- struct intel_bw_state *new_bw_state = NULL;
- struct intel_bw_state *old_bw_state = NULL;
-
- for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
- struct intel_cdclk_state *cdclk_state;
-
- new_bw_state = intel_atomic_get_bw_state(state);
- if (IS_ERR(new_bw_state))
- return PTR_ERR(new_bw_state);
-
- cdclk_state = intel_atomic_get_cdclk_state(state);
- if (IS_ERR(cdclk_state))
- return PTR_ERR(cdclk_state);
-
- min_cdclk = max(cdclk_state->min_cdclk[crtc->pipe], min_cdclk);
-
- new_bw_state->min_cdclk = min_cdclk;
-
- old_bw_state = intel_atomic_get_old_bw_state(state);
- }
-
- if (!old_bw_state)
- return 0;
-
- if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) {
- int ret = intel_atomic_lock_global_state(&new_bw_state->base);
-
- if (ret)
- return ret;
- }
-
- return 0;
-}
-
int intel_bw_atomic_check(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index 46c6eecbd917..bbcaaa73ec1b 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -9,20 +9,14 @@
#include <drm/drm_atomic.h>
#include "intel_display.h"
-#include "intel_display_power.h"
#include "intel_global_state.h"
struct drm_i915_private;
struct intel_atomic_state;
struct intel_crtc_state;
-struct intel_dbuf_bw {
- int used_bw[I915_MAX_DBUF_SLICES];
-};
-
struct intel_bw_state {
struct intel_global_state base;
- struct intel_dbuf_bw dbuf_bw[I915_MAX_PIPES];
/*
* Contains a bit mask, used to determine, whether correspondent
@@ -42,8 +36,6 @@ struct intel_bw_state {
/* bitmask of active pipes */
u8 active_pipes;
-
- int min_cdclk;
};
#define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base)
@@ -64,7 +56,5 @@ void intel_bw_crtc_update(struct intel_bw_state *bw_state,
const struct intel_crtc_state *crtc_state);
int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
u32 points_mask);
-int intel_bw_calc_min_cdclk(struct intel_atomic_state *state);
-int skl_bw_calc_min_cdclk(struct intel_atomic_state *state);
#endif /* __INTEL_BW_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index f9b0fc7317de..9419a4724357 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -21,10 +21,7 @@
* DEALINGS IN THE SOFTWARE.
*/
-#include <linux/time.h>
-
#include "intel_atomic.h"
-#include "intel_bw.h"
#include "intel_cdclk.h"
#include "intel_display_types.h"
#include "intel_sideband.h"
@@ -2071,6 +2068,18 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
/* Account for additional needs from the planes */
min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
+ /*
+ * HACK. Currently for TGL platforms we calculate
+ * min_cdclk initially based on pixel_rate divided
+ * by 2, accounting for also plane requirements,
+ * however in some cases the lowest possible CDCLK
+ * doesn't work and causing the underruns.
+ * Explicitly stating here that this seems to be currently
+ * rather a Hack, than final solution.
+ */
+ if (IS_TIGERLAKE(dev_priv))
+ min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate);
+
if (min_cdclk > dev_priv->max_cdclk_freq) {
drm_dbg_kms(&dev_priv->drm,
"required cdclk (%d kHz) exceeds max (%d kHz)\n",
@@ -2084,9 +2093,11 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
{
struct intel_atomic_state *state = cdclk_state->base.state;
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc *crtc;
struct intel_crtc_state *crtc_state;
int min_cdclk, i;
+ enum pipe pipe;
for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
int ret;
@@ -2106,18 +2117,8 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
}
min_cdclk = cdclk_state->force_min_cdclk;
-
- for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
- struct intel_bw_state *bw_state;
-
- min_cdclk = max(cdclk_state->min_cdclk[crtc->pipe], min_cdclk);
-
- bw_state = intel_atomic_get_bw_state(state);
- if (IS_ERR(bw_state))
- return PTR_ERR(bw_state);
-
- min_cdclk = max(bw_state->min_cdclk, min_cdclk);
- }
+ for_each_pipe(dev_priv, pipe)
+ min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk);
return min_cdclk;
}
@@ -2789,30 +2790,25 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
{
if (INTEL_GEN(dev_priv) >= 12) {
dev_priv->display.set_cdclk = bxt_set_cdclk;
- dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
dev_priv->cdclk.table = icl_cdclk_table;
} else if (IS_ELKHARTLAKE(dev_priv)) {
dev_priv->display.set_cdclk = bxt_set_cdclk;
- dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
dev_priv->display.calc_voltage_level = ehl_calc_voltage_level;
dev_priv->cdclk.table = icl_cdclk_table;
} else if (INTEL_GEN(dev_priv) >= 11) {
dev_priv->display.set_cdclk = bxt_set_cdclk;
- dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
dev_priv->display.calc_voltage_level = icl_calc_voltage_level;
dev_priv->cdclk.table = icl_cdclk_table;
} else if (IS_CANNONLAKE(dev_priv)) {
- dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
dev_priv->display.set_cdclk = bxt_set_cdclk;
dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
dev_priv->display.calc_voltage_level = cnl_calc_voltage_level;
dev_priv->cdclk.table = cnl_cdclk_table;
} else if (IS_GEN9_LP(dev_priv)) {
- dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
dev_priv->display.set_cdclk = bxt_set_cdclk;
dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
dev_priv->display.calc_voltage_level = bxt_calc_voltage_level;
@@ -2821,23 +2817,18 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
else
dev_priv->cdclk.table = bxt_cdclk_table;
} else if (IS_GEN9_BC(dev_priv)) {
- dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
dev_priv->display.set_cdclk = skl_set_cdclk;
dev_priv->display.modeset_calc_cdclk = skl_modeset_calc_cdclk;
} else if (IS_BROADWELL(dev_priv)) {
- dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
dev_priv->display.set_cdclk = bdw_set_cdclk;
dev_priv->display.modeset_calc_cdclk = bdw_modeset_calc_cdclk;
} else if (IS_CHERRYVIEW(dev_priv)) {
- dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
dev_priv->display.set_cdclk = chv_set_cdclk;
dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
} else if (IS_VALLEYVIEW(dev_priv)) {
- dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
dev_priv->display.set_cdclk = vlv_set_cdclk;
dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
} else {
- dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
dev_priv->display.modeset_calc_cdclk = fixed_modeset_calc_cdclk;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f40b909952cc..fe3706a0aca1 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14707,14 +14707,16 @@ static int intel_atomic_check_planes(struct intel_atomic_state *state)
static int intel_atomic_check_cdclk(struct intel_atomic_state *state,
bool *need_cdclk_calc)
{
- struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_cdclk_state *new_cdclk_state;
int i;
struct intel_plane_state *plane_state;
struct intel_plane *plane;
int ret;
- struct intel_cdclk_state *new_cdclk_state;
- struct intel_crtc_state *new_crtc_state;
- struct intel_crtc *crtc;
+
+ new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
+ if (new_cdclk_state && new_cdclk_state->force_min_cdclk_changed)
+ *need_cdclk_calc = true;
+
/*
* active_planes bitmask has been updated, and potentially
* affected planes are part of the state. We can now
@@ -14726,35 +14728,6 @@ static int intel_atomic_check_cdclk(struct intel_atomic_state *state,
return ret;
}
- new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
-
- if (new_cdclk_state && new_cdclk_state->force_min_cdclk_changed)
- *need_cdclk_calc = true;
-
- ret = dev_priv->display.bw_calc_min_cdclk(state);
- if (ret)
- return ret;
-
- if (!new_cdclk_state)
- return 0;
-
- for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
- struct intel_bw_state *bw_state;
- int min_cdclk = 0;
-
- min_cdclk = max(new_cdclk_state->min_cdclk[crtc->pipe], min_cdclk);
-
- bw_state = intel_atomic_get_bw_state(state);
- if (IS_ERR(bw_state))
- return PTR_ERR(bw_state);
-
- /*
- * Currently do this change only if we need to increase
- */
- if (bw_state->min_cdclk > min_cdclk)
- *need_cdclk_calc = true;
- }
-
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 98f2c448cd92..10383e01efde 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -273,7 +273,6 @@ struct drm_i915_display_funcs {
void (*set_cdclk)(struct drm_i915_private *dev_priv,
const struct intel_cdclk_config *cdclk_config,
enum pipe pipe);
- int (*bw_calc_min_cdclk)(struct intel_atomic_state *state);
int (*get_fifo_size)(struct drm_i915_private *dev_priv,
enum i9xx_plane_id i9xx_plane);
int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b134a1b9d738..4d885ef0bac5 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -33,7 +33,6 @@
#include <drm/drm_plane_helper.h>
#include "display/intel_atomic.h"
-#include "display/intel_bw.h"
#include "display/intel_display_types.h"
#include "display/intel_fbc.h"
#include "display/intel_sprite.h"
@@ -44,6 +43,7 @@
#include "i915_fixed.h"
#include "i915_irq.h"
#include "i915_trace.h"
+#include "display/intel_bw.h"
#include "intel_pm.h"
#include "intel_sideband.h"
#include "../../../platform/x86/intel_ips.h"
@@ -4031,9 +4031,10 @@ icl_get_first_dbuf_slice_offset(u32 dbuf_slice_mask,
return offset;
}
-u16 intel_get_ddb_size(struct drm_i915_private *dev_priv)
+static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv)
{
u16 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
+
drm_WARN_ON(&dev_priv->drm, ddb_size == 0);
if (INTEL_GEN(dev_priv) < 11)
@@ -4042,34 +4043,6 @@ u16 intel_get_ddb_size(struct drm_i915_private *dev_priv)
return ddb_size;
}
-u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv,
- const struct skl_ddb_entry *entry)
-{
- u32 slice_mask = 0;
- u16 ddb_size = intel_get_ddb_size(dev_priv);
- u16 num_supported_slices = INTEL_INFO(dev_priv)->num_supported_dbuf_slices;
- u16 slice_size = ddb_size / num_supported_slices;
- u16 start_slice;
- u16 end_slice;
-
- if (!skl_ddb_entry_size(entry))
- return 0;
-
- start_slice = entry->start / slice_size;
- end_slice = (entry->end - 1) / slice_size;
-
- /*
- * Per plane DDB entry can in a really worst case be on multiple slices
- * but single entry is anyway contigious.
- */
- while (start_slice <= end_slice) {
- slice_mask |= BIT(start_slice);
- start_slice++;
- }
-
- return slice_mask;
-}
-
static u8 skl_compute_dbuf_slices(const struct intel_crtc_state *crtc_state,
u8 active_pipes);
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index a2473594c2db..6636d2a057cd 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -8,10 +8,10 @@
#include <linux/types.h>
-#include "display/intel_bw.h"
#include "display/intel_global_state.h"
#include "i915_reg.h"
+#include "display/intel_bw.h"
struct drm_device;
struct drm_i915_private;
@@ -39,10 +39,6 @@ u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv);
void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
struct skl_ddb_entry *ddb_y,
struct skl_ddb_entry *ddb_uv);
-void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv);
-u16 intel_get_ddb_size(struct drm_i915_private *dev_priv);
-u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv,
- const struct skl_ddb_entry *entry);
void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
struct skl_pipe_wm *out);
void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
--
2.20.1
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Revert CDCLK changes to unbreak geminilake
2020-05-25 8:07 [Intel-gfx] [PATCH] drm/i915: Revert CDCLK changes to unbreak geminilake Chris Wilson
@ 2020-05-25 8:07 ` Lisovskiy, Stanislav
2020-05-25 8:16 ` Chris Wilson
2020-05-25 8:30 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
` (2 subsequent siblings)
3 siblings, 1 reply; 7+ messages in thread
From: Lisovskiy, Stanislav @ 2020-05-25 8:07 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Mon, May 25, 2020 at 09:07:31AM +0100, Chris Wilson wrote:
> This reverts
> cac91e671ad5 ("drm/i915: Fix includes and local vars order")
> 82ea174dc542 ("drm/i915: Remove unneeded hack now for CDCLK")
> cd1915460861 ("drm/i915: Adjust CDCLK accordingly to our DBuf bw needs")
>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
I guess we still need to check more precisely if this patch caused
this - or have you already bisected that?
It is rather strange that it breaks only a GLK and only single test.
Stan
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 127 +------------------
> drivers/gpu/drm/i915/display/intel_bw.h | 10 --
> drivers/gpu/drm/i915/display/intel_cdclk.c | 41 +++---
> drivers/gpu/drm/i915/display/intel_display.c | 39 +-----
> drivers/gpu/drm/i915/i915_drv.h | 1 -
> drivers/gpu/drm/i915/intel_pm.c | 33 +----
> drivers/gpu/drm/i915/intel_pm.h | 6 +-
> 7 files changed, 29 insertions(+), 228 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index a79bd7aeb03b..98bbe719cf4f 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -5,12 +5,12 @@
>
> #include <drm/drm_atomic_state_helper.h>
>
> -#include "intel_atomic.h"
> #include "intel_bw.h"
> -#include "intel_cdclk.h"
> #include "intel_display_types.h"
> -#include "intel_pm.h"
> #include "intel_sideband.h"
> +#include "intel_atomic.h"
> +#include "intel_pm.h"
> +
>
> /* Parameters for Qclk Geyserville (QGV) */
> struct intel_qgv_point {
> @@ -428,127 +428,6 @@ intel_atomic_get_bw_state(struct intel_atomic_state *state)
> return to_intel_bw_state(bw_state);
> }
>
> -int skl_bw_calc_min_cdclk(struct intel_atomic_state *state)
> -{
> - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - struct intel_bw_state *new_bw_state = NULL;
> - struct intel_bw_state *old_bw_state = NULL;
> - const struct intel_crtc_state *crtc_state;
> - struct intel_crtc *crtc;
> - int max_bw = 0;
> - int slice_id;
> - int i;
> -
> - for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
> - enum plane_id plane_id;
> - struct intel_dbuf_bw *crtc_bw;
> -
> - new_bw_state = intel_atomic_get_bw_state(state);
> - if (IS_ERR(new_bw_state))
> - return PTR_ERR(new_bw_state);
> -
> - crtc_bw = &new_bw_state->dbuf_bw[crtc->pipe];
> -
> - memset(&crtc_bw->used_bw, 0, sizeof(crtc_bw->used_bw));
> -
> - for_each_plane_id_on_crtc(crtc, plane_id) {
> - const struct skl_ddb_entry *plane_alloc =
> - &crtc_state->wm.skl.plane_ddb_y[plane_id];
> - const struct skl_ddb_entry *uv_plane_alloc =
> - &crtc_state->wm.skl.plane_ddb_uv[plane_id];
> - unsigned int data_rate = crtc_state->data_rate[plane_id];
> - unsigned int dbuf_mask = 0;
> -
> - dbuf_mask |= skl_ddb_dbuf_slice_mask(dev_priv, plane_alloc);
> - dbuf_mask |= skl_ddb_dbuf_slice_mask(dev_priv, uv_plane_alloc);
> -
> - /*
> - * FIXME: To calculate that more properly we probably
> - * need to to split per plane data_rate into data_rate_y
> - * and data_rate_uv for multiplanar formats in order not
> - * to get accounted those twice if they happen to reside
> - * on different slices.
> - * However for pre-icl this would work anyway because
> - * we have only single slice and for icl+ uv plane has
> - * non-zero data rate.
> - * So in worst case those calculation are a bit
> - * pessimistic, which shouldn't pose any significant
> - * problem anyway.
> - */
> - for_each_dbuf_slice_in_mask(slice_id, dbuf_mask)
> - crtc_bw->used_bw[slice_id] += data_rate;
> - }
> -
> - for_each_dbuf_slice(slice_id) {
> - /*
> - * Current experimental observations show that contrary
> - * to BSpec we get underruns once we exceed 64 * CDCLK
> - * for slices in total.
> - * As a temporary measure in order not to keep CDCLK
> - * bumped up all the time we calculate CDCLK according
> - * to this formula for overall bw consumed by slices.
> - */
> - max_bw += crtc_bw->used_bw[slice_id];
> - }
> -
> - new_bw_state->min_cdclk = max_bw / 64;
> -
> - old_bw_state = intel_atomic_get_old_bw_state(state);
> - }
> -
> - if (!old_bw_state)
> - return 0;
> -
> - if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) {
> - int ret = intel_atomic_lock_global_state(&new_bw_state->base);
> -
> - if (ret)
> - return ret;
> - }
> -
> - return 0;
> -}
> -
> -int intel_bw_calc_min_cdclk(struct intel_atomic_state *state)
> -{
> - int i;
> - const struct intel_crtc_state *crtc_state;
> - struct intel_crtc *crtc;
> - int min_cdclk = 0;
> - struct intel_bw_state *new_bw_state = NULL;
> - struct intel_bw_state *old_bw_state = NULL;
> -
> - for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
> - struct intel_cdclk_state *cdclk_state;
> -
> - new_bw_state = intel_atomic_get_bw_state(state);
> - if (IS_ERR(new_bw_state))
> - return PTR_ERR(new_bw_state);
> -
> - cdclk_state = intel_atomic_get_cdclk_state(state);
> - if (IS_ERR(cdclk_state))
> - return PTR_ERR(cdclk_state);
> -
> - min_cdclk = max(cdclk_state->min_cdclk[crtc->pipe], min_cdclk);
> -
> - new_bw_state->min_cdclk = min_cdclk;
> -
> - old_bw_state = intel_atomic_get_old_bw_state(state);
> - }
> -
> - if (!old_bw_state)
> - return 0;
> -
> - if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) {
> - int ret = intel_atomic_lock_global_state(&new_bw_state->base);
> -
> - if (ret)
> - return ret;
> - }
> -
> - return 0;
> -}
> -
> int intel_bw_atomic_check(struct intel_atomic_state *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
> index 46c6eecbd917..bbcaaa73ec1b 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.h
> +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> @@ -9,20 +9,14 @@
> #include <drm/drm_atomic.h>
>
> #include "intel_display.h"
> -#include "intel_display_power.h"
> #include "intel_global_state.h"
>
> struct drm_i915_private;
> struct intel_atomic_state;
> struct intel_crtc_state;
>
> -struct intel_dbuf_bw {
> - int used_bw[I915_MAX_DBUF_SLICES];
> -};
> -
> struct intel_bw_state {
> struct intel_global_state base;
> - struct intel_dbuf_bw dbuf_bw[I915_MAX_PIPES];
>
> /*
> * Contains a bit mask, used to determine, whether correspondent
> @@ -42,8 +36,6 @@ struct intel_bw_state {
>
> /* bitmask of active pipes */
> u8 active_pipes;
> -
> - int min_cdclk;
> };
>
> #define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base)
> @@ -64,7 +56,5 @@ void intel_bw_crtc_update(struct intel_bw_state *bw_state,
> const struct intel_crtc_state *crtc_state);
> int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
> u32 points_mask);
> -int intel_bw_calc_min_cdclk(struct intel_atomic_state *state);
> -int skl_bw_calc_min_cdclk(struct intel_atomic_state *state);
>
> #endif /* __INTEL_BW_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index f9b0fc7317de..9419a4724357 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -21,10 +21,7 @@
> * DEALINGS IN THE SOFTWARE.
> */
>
> -#include <linux/time.h>
> -
> #include "intel_atomic.h"
> -#include "intel_bw.h"
> #include "intel_cdclk.h"
> #include "intel_display_types.h"
> #include "intel_sideband.h"
> @@ -2071,6 +2068,18 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
> /* Account for additional needs from the planes */
> min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
>
> + /*
> + * HACK. Currently for TGL platforms we calculate
> + * min_cdclk initially based on pixel_rate divided
> + * by 2, accounting for also plane requirements,
> + * however in some cases the lowest possible CDCLK
> + * doesn't work and causing the underruns.
> + * Explicitly stating here that this seems to be currently
> + * rather a Hack, than final solution.
> + */
> + if (IS_TIGERLAKE(dev_priv))
> + min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate);
> +
> if (min_cdclk > dev_priv->max_cdclk_freq) {
> drm_dbg_kms(&dev_priv->drm,
> "required cdclk (%d kHz) exceeds max (%d kHz)\n",
> @@ -2084,9 +2093,11 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
> static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
> {
> struct intel_atomic_state *state = cdclk_state->base.state;
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> struct intel_crtc *crtc;
> struct intel_crtc_state *crtc_state;
> int min_cdclk, i;
> + enum pipe pipe;
>
> for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
> int ret;
> @@ -2106,18 +2117,8 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
> }
>
> min_cdclk = cdclk_state->force_min_cdclk;
> -
> - for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
> - struct intel_bw_state *bw_state;
> -
> - min_cdclk = max(cdclk_state->min_cdclk[crtc->pipe], min_cdclk);
> -
> - bw_state = intel_atomic_get_bw_state(state);
> - if (IS_ERR(bw_state))
> - return PTR_ERR(bw_state);
> -
> - min_cdclk = max(bw_state->min_cdclk, min_cdclk);
> - }
> + for_each_pipe(dev_priv, pipe)
> + min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk);
>
> return min_cdclk;
> }
> @@ -2789,30 +2790,25 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
> {
> if (INTEL_GEN(dev_priv) >= 12) {
> dev_priv->display.set_cdclk = bxt_set_cdclk;
> - dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
> dev_priv->cdclk.table = icl_cdclk_table;
> } else if (IS_ELKHARTLAKE(dev_priv)) {
> dev_priv->display.set_cdclk = bxt_set_cdclk;
> - dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> dev_priv->display.calc_voltage_level = ehl_calc_voltage_level;
> dev_priv->cdclk.table = icl_cdclk_table;
> } else if (INTEL_GEN(dev_priv) >= 11) {
> dev_priv->display.set_cdclk = bxt_set_cdclk;
> - dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> dev_priv->display.calc_voltage_level = icl_calc_voltage_level;
> dev_priv->cdclk.table = icl_cdclk_table;
> } else if (IS_CANNONLAKE(dev_priv)) {
> - dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> dev_priv->display.set_cdclk = bxt_set_cdclk;
> dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> dev_priv->display.calc_voltage_level = cnl_calc_voltage_level;
> dev_priv->cdclk.table = cnl_cdclk_table;
> } else if (IS_GEN9_LP(dev_priv)) {
> - dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> dev_priv->display.set_cdclk = bxt_set_cdclk;
> dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> dev_priv->display.calc_voltage_level = bxt_calc_voltage_level;
> @@ -2821,23 +2817,18 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
> else
> dev_priv->cdclk.table = bxt_cdclk_table;
> } else if (IS_GEN9_BC(dev_priv)) {
> - dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> dev_priv->display.set_cdclk = skl_set_cdclk;
> dev_priv->display.modeset_calc_cdclk = skl_modeset_calc_cdclk;
> } else if (IS_BROADWELL(dev_priv)) {
> - dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
> dev_priv->display.set_cdclk = bdw_set_cdclk;
> dev_priv->display.modeset_calc_cdclk = bdw_modeset_calc_cdclk;
> } else if (IS_CHERRYVIEW(dev_priv)) {
> - dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
> dev_priv->display.set_cdclk = chv_set_cdclk;
> dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
> } else if (IS_VALLEYVIEW(dev_priv)) {
> - dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
> dev_priv->display.set_cdclk = vlv_set_cdclk;
> dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
> } else {
> - dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
> dev_priv->display.modeset_calc_cdclk = fixed_modeset_calc_cdclk;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index f40b909952cc..fe3706a0aca1 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14707,14 +14707,16 @@ static int intel_atomic_check_planes(struct intel_atomic_state *state)
> static int intel_atomic_check_cdclk(struct intel_atomic_state *state,
> bool *need_cdclk_calc)
> {
> - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_cdclk_state *new_cdclk_state;
> int i;
> struct intel_plane_state *plane_state;
> struct intel_plane *plane;
> int ret;
> - struct intel_cdclk_state *new_cdclk_state;
> - struct intel_crtc_state *new_crtc_state;
> - struct intel_crtc *crtc;
> +
> + new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
> + if (new_cdclk_state && new_cdclk_state->force_min_cdclk_changed)
> + *need_cdclk_calc = true;
> +
> /*
> * active_planes bitmask has been updated, and potentially
> * affected planes are part of the state. We can now
> @@ -14726,35 +14728,6 @@ static int intel_atomic_check_cdclk(struct intel_atomic_state *state,
> return ret;
> }
>
> - new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
> -
> - if (new_cdclk_state && new_cdclk_state->force_min_cdclk_changed)
> - *need_cdclk_calc = true;
> -
> - ret = dev_priv->display.bw_calc_min_cdclk(state);
> - if (ret)
> - return ret;
> -
> - if (!new_cdclk_state)
> - return 0;
> -
> - for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> - struct intel_bw_state *bw_state;
> - int min_cdclk = 0;
> -
> - min_cdclk = max(new_cdclk_state->min_cdclk[crtc->pipe], min_cdclk);
> -
> - bw_state = intel_atomic_get_bw_state(state);
> - if (IS_ERR(bw_state))
> - return PTR_ERR(bw_state);
> -
> - /*
> - * Currently do this change only if we need to increase
> - */
> - if (bw_state->min_cdclk > min_cdclk)
> - *need_cdclk_calc = true;
> - }
> -
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 98f2c448cd92..10383e01efde 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -273,7 +273,6 @@ struct drm_i915_display_funcs {
> void (*set_cdclk)(struct drm_i915_private *dev_priv,
> const struct intel_cdclk_config *cdclk_config,
> enum pipe pipe);
> - int (*bw_calc_min_cdclk)(struct intel_atomic_state *state);
> int (*get_fifo_size)(struct drm_i915_private *dev_priv,
> enum i9xx_plane_id i9xx_plane);
> int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index b134a1b9d738..4d885ef0bac5 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -33,7 +33,6 @@
> #include <drm/drm_plane_helper.h>
>
> #include "display/intel_atomic.h"
> -#include "display/intel_bw.h"
> #include "display/intel_display_types.h"
> #include "display/intel_fbc.h"
> #include "display/intel_sprite.h"
> @@ -44,6 +43,7 @@
> #include "i915_fixed.h"
> #include "i915_irq.h"
> #include "i915_trace.h"
> +#include "display/intel_bw.h"
> #include "intel_pm.h"
> #include "intel_sideband.h"
> #include "../../../platform/x86/intel_ips.h"
> @@ -4031,9 +4031,10 @@ icl_get_first_dbuf_slice_offset(u32 dbuf_slice_mask,
> return offset;
> }
>
> -u16 intel_get_ddb_size(struct drm_i915_private *dev_priv)
> +static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv)
> {
> u16 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
> +
> drm_WARN_ON(&dev_priv->drm, ddb_size == 0);
>
> if (INTEL_GEN(dev_priv) < 11)
> @@ -4042,34 +4043,6 @@ u16 intel_get_ddb_size(struct drm_i915_private *dev_priv)
> return ddb_size;
> }
>
> -u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv,
> - const struct skl_ddb_entry *entry)
> -{
> - u32 slice_mask = 0;
> - u16 ddb_size = intel_get_ddb_size(dev_priv);
> - u16 num_supported_slices = INTEL_INFO(dev_priv)->num_supported_dbuf_slices;
> - u16 slice_size = ddb_size / num_supported_slices;
> - u16 start_slice;
> - u16 end_slice;
> -
> - if (!skl_ddb_entry_size(entry))
> - return 0;
> -
> - start_slice = entry->start / slice_size;
> - end_slice = (entry->end - 1) / slice_size;
> -
> - /*
> - * Per plane DDB entry can in a really worst case be on multiple slices
> - * but single entry is anyway contigious.
> - */
> - while (start_slice <= end_slice) {
> - slice_mask |= BIT(start_slice);
> - start_slice++;
> - }
> -
> - return slice_mask;
> -}
> -
> static u8 skl_compute_dbuf_slices(const struct intel_crtc_state *crtc_state,
> u8 active_pipes);
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
> index a2473594c2db..6636d2a057cd 100644
> --- a/drivers/gpu/drm/i915/intel_pm.h
> +++ b/drivers/gpu/drm/i915/intel_pm.h
> @@ -8,10 +8,10 @@
>
> #include <linux/types.h>
>
> -#include "display/intel_bw.h"
> #include "display/intel_global_state.h"
>
> #include "i915_reg.h"
> +#include "display/intel_bw.h"
>
> struct drm_device;
> struct drm_i915_private;
> @@ -39,10 +39,6 @@ u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv);
> void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
> struct skl_ddb_entry *ddb_y,
> struct skl_ddb_entry *ddb_uv);
> -void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv);
> -u16 intel_get_ddb_size(struct drm_i915_private *dev_priv);
> -u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv,
> - const struct skl_ddb_entry *entry);
> void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
> struct skl_pipe_wm *out);
> void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
> --
> 2.20.1
>
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Revert CDCLK changes to unbreak geminilake
2020-05-25 8:16 ` Chris Wilson
@ 2020-05-25 8:15 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 7+ messages in thread
From: Lisovskiy, Stanislav @ 2020-05-25 8:15 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Mon, May 25, 2020 at 09:16:54AM +0100, Chris Wilson wrote:
> Quoting Lisovskiy, Stanislav (2020-05-25 09:07:54)
> > On Mon, May 25, 2020 at 09:07:31AM +0100, Chris Wilson wrote:
> > > This reverts
> > > cac91e671ad5 ("drm/i915: Fix includes and local vars order")
> > > 82ea174dc542 ("drm/i915: Remove unneeded hack now for CDCLK")
> > > cd1915460861 ("drm/i915: Adjust CDCLK accordingly to our DBuf bw needs")
> > >
> > > Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > Cc: Manasi Navare <manasi.d.navare@intel.com>
> > > Cc: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
> >
> >
> > I guess we still need to check more precisely if this patch caused
> > this - or have you already bisected that?
>
> This was found by unwinding the patches on CI.
>
> > It is rather strange that it breaks only a GLK and only single test.
>
> Bug detection is purely serendipitous.
> -Chris
Ok then lets rewind those - then it will become clear at least.
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Revert CDCLK changes to unbreak geminilake
2020-05-25 8:07 ` Lisovskiy, Stanislav
@ 2020-05-25 8:16 ` Chris Wilson
2020-05-25 8:15 ` Lisovskiy, Stanislav
0 siblings, 1 reply; 7+ messages in thread
From: Chris Wilson @ 2020-05-25 8:16 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
Quoting Lisovskiy, Stanislav (2020-05-25 09:07:54)
> On Mon, May 25, 2020 at 09:07:31AM +0100, Chris Wilson wrote:
> > This reverts
> > cac91e671ad5 ("drm/i915: Fix includes and local vars order")
> > 82ea174dc542 ("drm/i915: Remove unneeded hack now for CDCLK")
> > cd1915460861 ("drm/i915: Adjust CDCLK accordingly to our DBuf bw needs")
> >
> > Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > Cc: Manasi Navare <manasi.d.navare@intel.com>
> > Cc: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
>
>
> I guess we still need to check more precisely if this patch caused
> this - or have you already bisected that?
This was found by unwinding the patches on CI.
> It is rather strange that it breaks only a GLK and only single test.
Bug detection is purely serendipitous.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Revert CDCLK changes to unbreak geminilake
2020-05-25 8:07 [Intel-gfx] [PATCH] drm/i915: Revert CDCLK changes to unbreak geminilake Chris Wilson
2020-05-25 8:07 ` Lisovskiy, Stanislav
@ 2020-05-25 8:30 ` Patchwork
2020-05-25 8:53 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-05-25 9:59 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
3 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2020-05-25 8:30 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Revert CDCLK changes to unbreak geminilake
URL : https://patchwork.freedesktop.org/series/77628/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c692f23a099e drm/i915: Revert CDCLK changes to unbreak geminilake
-:10: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit cac91e671ad5 ("drm/i915: Fix includes and local vars order")'
#10:
cac91e671ad5 ("drm/i915: Fix includes and local vars order")
-:11: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 82ea174dc542 ("drm/i915: Remove unneeded hack now for CDCLK")'
#11:
82ea174dc542 ("drm/i915: Remove unneeded hack now for CDCLK")
-:12: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit cd1915460861 ("drm/i915: Adjust CDCLK accordingly to our DBuf bw needs")'
#12:
cd1915460861 ("drm/i915: Adjust CDCLK accordingly to our DBuf bw needs")
-:497: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)
total: 4 errors, 0 warnings, 0 checks, 431 lines checked
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Revert CDCLK changes to unbreak geminilake
2020-05-25 8:07 [Intel-gfx] [PATCH] drm/i915: Revert CDCLK changes to unbreak geminilake Chris Wilson
2020-05-25 8:07 ` Lisovskiy, Stanislav
2020-05-25 8:30 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
@ 2020-05-25 8:53 ` Patchwork
2020-05-25 9:59 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
3 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2020-05-25 8:53 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Revert CDCLK changes to unbreak geminilake
URL : https://patchwork.freedesktop.org/series/77628/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8529 -> Patchwork_17768
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17768/index.html
Known issues
------------
Here are the changes found in Patchwork_17768 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@hangcheck:
- fi-icl-u2: [PASS][1] -> [INCOMPLETE][2] ([i915#1580] / [i915#926])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8529/fi-icl-u2/igt@i915_selftest@live@hangcheck.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17768/fi-icl-u2/igt@i915_selftest@live@hangcheck.html
#### Possible fixes ####
* igt@i915_pm_rpm@module-reload:
- fi-glk-dsi: [TIMEOUT][3] ([i915#1288]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8529/fi-glk-dsi/igt@i915_pm_rpm@module-reload.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17768/fi-glk-dsi/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@coherency:
- fi-bwr-2160: [INCOMPLETE][5] ([i915#489]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8529/fi-bwr-2160/igt@i915_selftest@live@coherency.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17768/fi-bwr-2160/igt@i915_selftest@live@coherency.html
[i915#1288]: https://gitlab.freedesktop.org/drm/intel/issues/1288
[i915#1580]: https://gitlab.freedesktop.org/drm/intel/issues/1580
[i915#489]: https://gitlab.freedesktop.org/drm/intel/issues/489
[i915#926]: https://gitlab.freedesktop.org/drm/intel/issues/926
Participating hosts (45 -> 43)
------------------------------
Additional (3): fi-hsw-4770 fi-kbl-7560u fi-cfl-guc
Missing (5): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_8529 -> Patchwork_17768
CI-20190529: 20190529
CI_DRM_8529: 9ae23ae1b437ee0d75ed2153eca05ecbd8c417bd @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5676: ff03d458f708583c8f9296f97c38df312055651a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17768: c692f23a099e2662e3ca395fb39187c1d7e71284 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
c692f23a099e drm/i915: Revert CDCLK changes to unbreak geminilake
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17768/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Revert CDCLK changes to unbreak geminilake
2020-05-25 8:07 [Intel-gfx] [PATCH] drm/i915: Revert CDCLK changes to unbreak geminilake Chris Wilson
` (2 preceding siblings ...)
2020-05-25 8:53 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-05-25 9:59 ` Patchwork
3 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2020-05-25 9:59 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Revert CDCLK changes to unbreak geminilake
URL : https://patchwork.freedesktop.org/series/77628/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8529_full -> Patchwork_17768_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_17768_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s3:
- shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([i915#180])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8529/shard-kbl4/igt@gem_exec_suspend@basic-s3.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17768/shard-kbl7/igt@gem_exec_suspend@basic-s3.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-apl: [PASS][3] -> [DMESG-WARN][4] ([i915#180] / [i915#95])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8529/shard-apl7/igt@gem_workarounds@suspend-resume-fd.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17768/shard-apl6/igt@gem_workarounds@suspend-resume-fd.html
* igt@i915_pm_dc@dc6-psr:
- shard-skl: [PASS][5] -> [FAIL][6] ([i915#454])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8529/shard-skl8/igt@i915_pm_dc@dc6-psr.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17768/shard-skl1/igt@i915_pm_dc@dc6-psr.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: [PASS][7] -> [DMESG-WARN][8] ([i915#180]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8529/shard-apl7/igt@i915_suspend@sysfs-reader.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17768/shard-apl6/igt@i915_suspend@sysfs-reader.html
* igt@kms_draw_crc@draw-method-xrgb8888-pwrite-ytiled:
- shard-skl: [PASS][9] -> [FAIL][10] ([i915#52] / [i915#54]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8529/shard-skl3/igt@kms_draw_crc@draw-method-xrgb8888-pwrite-ytiled.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17768/shard-skl7/igt@kms_draw_crc@draw-method-xrgb8888-pwrite-ytiled.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [PASS][11] -> [FAIL][12] ([i915#1188]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8529/shard-skl2/igt@kms_hdr@bpc-switch-dpms.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17768/shard-skl1/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- shard-kbl: [PASS][13] -> [INCOMPLETE][14] ([i915#155])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8529/shard-kbl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17768/shard-kbl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [PASS][15] -> [FAIL][16] ([fdo#108145] / [i915#265])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8529/shard-skl3/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17768/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109441]) +2 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8529/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17768/shard-iclb4/igt@kms_psr@psr2_primary_mmap_cpu.html
#### Possible fixes ####
* {igt@gem_ctx_isolation@preservation-s3@bcs0}:
- shard-kbl: [DMESG-WARN][19] ([i915#180]) -> [PASS][20] +2 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8529/shard-kbl7/igt@gem_ctx_isolation@preservation-s3@bcs0.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17768/shard-kbl4/igt@gem_ctx_isolation@preservation-s3@bcs0.html
* igt@gem_ctx_persistence@processes:
- shard-skl: [FAIL][21] ([i915#1528]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8529/shard-skl8/igt@gem_ctx_persistence@processes.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17768/shard-skl1/igt@gem_ctx_persistence@processes.html
* igt@kms_color@pipe-b-ctm-negative:
- shard-skl: [FAIL][23] ([i915#131]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8529/shard-skl3/igt@kms_color@pipe-b-ctm-negative.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17768/shard-skl10/igt@kms_color@pipe-b-ctm-negative.html
* igt@kms_cursor_legacy@cursora-vs-flipb-toggle:
- shard-glk: [DMESG-WARN][25] -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8529/shard-glk9/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17768/shard-glk2/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html
* {igt@kms_flip@flip-vs-suspend-interruptible@c-dp1}:
- shard-apl: [DMESG-WARN][27] ([i915#180]) -> [PASS][28] +2 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8529/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17768/shard-apl7/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [FAIL][29] ([fdo#108145] / [i915#265]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8529/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17768/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [SKIP][31] ([fdo#109441]) -> [PASS][32] +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8529/shard-iclb5/igt@kms_psr@psr2_cursor_render.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17768/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
* igt@kms_setmode@basic:
- shard-kbl: [FAIL][33] ([i915#31]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8529/shard-kbl3/igt@kms_setmode@basic.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17768/shard-kbl2/igt@kms_setmode@basic.html
#### Warnings ####
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-skl: [SKIP][35] ([fdo#109271]) -> [SKIP][36] ([fdo#109271] / [i915#658])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8529/shard-skl7/igt@i915_pm_dc@dc3co-vpb-simulation.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17768/shard-skl9/igt@i915_pm_dc@dc3co-vpb-simulation.html
- shard-glk: [SKIP][37] ([fdo#109271]) -> [SKIP][38] ([fdo#109271] / [i915#658])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8529/shard-glk5/igt@i915_pm_dc@dc3co-vpb-simulation.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17768/shard-glk5/igt@i915_pm_dc@dc3co-vpb-simulation.html
- shard-apl: [SKIP][39] ([fdo#109271]) -> [SKIP][40] ([fdo#109271] / [i915#658])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8529/shard-apl1/igt@i915_pm_dc@dc3co-vpb-simulation.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17768/shard-apl4/igt@i915_pm_dc@dc3co-vpb-simulation.html
- shard-kbl: [SKIP][41] ([fdo#109271]) -> [SKIP][42] ([fdo#109271] / [i915#658])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8529/shard-kbl3/igt@i915_pm_dc@dc3co-vpb-simulation.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17768/shard-kbl7/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@i915_pm_dc@dc6-dpms:
- shard-tglb: [SKIP][43] ([i915#468]) -> [FAIL][44] ([i915#454])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8529/shard-tglb2/igt@i915_pm_dc@dc6-dpms.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17768/shard-tglb8/igt@i915_pm_dc@dc6-dpms.html
* igt@kms_color@pipe-a-ctm-0-25:
- shard-tglb: [FAIL][45] ([i915#1149] / [i915#315]) -> [FAIL][46] ([i915#1149] / [i915#315] / [i915#402])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8529/shard-tglb8/igt@kms_color@pipe-a-ctm-0-25.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17768/shard-tglb8/igt@kms_color@pipe-a-ctm-0-25.html
* igt@kms_content_protection@atomic-dpms:
- shard-apl: [FAIL][47] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][48] ([i915#1319]) +1 similar issue
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8529/shard-apl7/igt@kms_content_protection@atomic-dpms.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17768/shard-apl6/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@lic:
- shard-apl: [FAIL][49] ([fdo#110321]) -> [TIMEOUT][50] ([i915#1319])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8529/shard-apl1/igt@kms_content_protection@lic.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17768/shard-apl2/igt@kms_content_protection@lic.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
- shard-apl: [FAIL][51] ([fdo#108145] / [i915#265]) -> [FAIL][52] ([fdo#108145] / [i915#265] / [i915#95])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8529/shard-apl8/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17768/shard-apl4/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html
* igt@kms_psr2_su@page_flip:
- shard-iclb: [SKIP][53] ([fdo#109642] / [fdo#111068]) -> [FAIL][54] ([i915#608])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8529/shard-iclb5/igt@kms_psr2_su@page_flip.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17768/shard-iclb2/igt@kms_psr2_su@page_flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321
[fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#131]: https://gitlab.freedesktop.org/drm/intel/issues/131
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468
[i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#608]: https://gitlab.freedesktop.org/drm/intel/issues/608
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_8529 -> Patchwork_17768
CI-20190529: 20190529
CI_DRM_8529: 9ae23ae1b437ee0d75ed2153eca05ecbd8c417bd @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5676: ff03d458f708583c8f9296f97c38df312055651a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17768: c692f23a099e2662e3ca395fb39187c1d7e71284 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17768/index.html
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Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2020-05-25 9:59 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-05-25 8:07 [Intel-gfx] [PATCH] drm/i915: Revert CDCLK changes to unbreak geminilake Chris Wilson
2020-05-25 8:07 ` Lisovskiy, Stanislav
2020-05-25 8:16 ` Chris Wilson
2020-05-25 8:15 ` Lisovskiy, Stanislav
2020-05-25 8:30 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2020-05-25 8:53 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-05-25 9:59 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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