From: Chris Wilson <chris@chris-wilson.co.uk>
To: intel-gfx@lists.freedesktop.org
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Subject: [Intel-gfx] [PATCH 11/36] drm/i915/gt: Enable busy-stats for ring-scheduler
Date: Mon, 1 Jun 2020 08:24:21 +0100 [thread overview]
Message-ID: <20200601072446.19548-11-chris@chris-wilson.co.uk> (raw)
In-Reply-To: <20200601072446.19548-1-chris@chris-wilson.co.uk>
Couple up the context in/out accounting to record how long each engine
is busy handling requests. This is exposed to userspace for more accurate
measurements, and also enables our soft-rps timer.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_engine_stats.h | 49 +++++++++++
drivers/gpu/drm/i915/gt/intel_lrc.c | 34 +-------
.../gpu/drm/i915/gt/intel_ring_scheduler.c | 4 +
drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 86 +++++++++++++++++++
drivers/gpu/drm/i915/gt/selftest_rps.c | 5 ++
5 files changed, 145 insertions(+), 33 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_stats.h
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_stats.h b/drivers/gpu/drm/i915/gt/intel_engine_stats.h
new file mode 100644
index 000000000000..58491eae3482
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_engine_stats.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#ifndef __INTEL_ENGINE_STATS_H__
+#define __INTEL_ENGINE_STATS_H__
+
+#include <linux/atomic.h>
+#include <linux/ktime.h>
+#include <linux/seqlock.h>
+
+#include "i915_gem.h" /* GEM_BUG_ON */
+#include "intel_engine.h"
+
+static inline void intel_engine_context_in(struct intel_engine_cs *engine)
+{
+ unsigned long flags;
+
+ if (atomic_add_unless(&engine->stats.active, 1, 0))
+ return;
+
+ write_seqlock_irqsave(&engine->stats.lock, flags);
+ if (!atomic_add_unless(&engine->stats.active, 1, 0)) {
+ engine->stats.start = ktime_get();
+ atomic_inc(&engine->stats.active);
+ }
+ write_sequnlock_irqrestore(&engine->stats.lock, flags);
+}
+
+static inline void intel_engine_context_out(struct intel_engine_cs *engine)
+{
+ unsigned long flags;
+
+ GEM_BUG_ON(!atomic_read(&engine->stats.active));
+
+ if (atomic_add_unless(&engine->stats.active, -1, 1))
+ return;
+
+ write_seqlock_irqsave(&engine->stats.lock, flags);
+ if (atomic_dec_and_test(&engine->stats.active)) {
+ engine->stats.total =
+ ktime_add(engine->stats.total,
+ ktime_sub(ktime_get(), engine->stats.start));
+ }
+ write_sequnlock_irqrestore(&engine->stats.lock, flags);
+}
+
+#endif /* __INTEL_ENGINE_STATS_H__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 6fc0966b75ff..13ef4f58cb08 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -139,6 +139,7 @@
#include "i915_vgpu.h"
#include "intel_context.h"
#include "intel_engine_pm.h"
+#include "intel_engine_stats.h"
#include "intel_gt.h"
#include "intel_gt_pm.h"
#include "intel_gt_requests.h"
@@ -1187,39 +1188,6 @@ execlists_context_status_change(struct i915_request *rq, unsigned long status)
status, rq);
}
-static void intel_engine_context_in(struct intel_engine_cs *engine)
-{
- unsigned long flags;
-
- if (atomic_add_unless(&engine->stats.active, 1, 0))
- return;
-
- write_seqlock_irqsave(&engine->stats.lock, flags);
- if (!atomic_add_unless(&engine->stats.active, 1, 0)) {
- engine->stats.start = ktime_get();
- atomic_inc(&engine->stats.active);
- }
- write_sequnlock_irqrestore(&engine->stats.lock, flags);
-}
-
-static void intel_engine_context_out(struct intel_engine_cs *engine)
-{
- unsigned long flags;
-
- GEM_BUG_ON(!atomic_read(&engine->stats.active));
-
- if (atomic_add_unless(&engine->stats.active, -1, 1))
- return;
-
- write_seqlock_irqsave(&engine->stats.lock, flags);
- if (atomic_dec_and_test(&engine->stats.active)) {
- engine->stats.total =
- ktime_add(engine->stats.total,
- ktime_sub(ktime_get(), engine->stats.start));
- }
- write_sequnlock_irqrestore(&engine->stats.lock, flags);
-}
-
static void
execlists_check_context(const struct intel_context *ce,
const struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c b/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c
index c8cd435d1c51..aaff554865b1 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c
@@ -9,6 +9,7 @@
#include "i915_drv.h"
#include "intel_context.h"
+#include "intel_engine_stats.h"
#include "intel_gt.h"
#include "intel_gt_pm.h"
#include "intel_gt_requests.h"
@@ -59,6 +60,7 @@ static struct i915_request *
schedule_in(struct intel_engine_cs *engine, struct i915_request *rq)
{
__intel_gt_pm_get(engine->gt);
+ intel_engine_context_in(engine);
return i915_request_get(rq);
}
@@ -71,6 +73,7 @@ schedule_out(struct intel_engine_cs *engine, struct i915_request *rq)
intel_engine_add_retire(engine, ce->timeline);
i915_request_put(rq);
+ intel_engine_context_out(engine);
intel_gt_pm_put_async(engine->gt);
}
@@ -747,6 +750,7 @@ int intel_ring_scheduler_setup(struct intel_engine_cs *engine)
engine->legacy.ring = ring;
engine->flags |= I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
+ engine->flags |= I915_ENGINE_SUPPORTS_STATS;
/* Finally, take ownership and responsibility for cleanup! */
engine->release = ring_release;
diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
index cbf6b0735272..5e48c7571b4d 100644
--- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
@@ -7,6 +7,91 @@
#include "i915_selftest.h"
#include "selftest_engine.h"
#include "selftests/igt_atomic.h"
+#include "selftests/igt_flush_test.h"
+#include "selftests/igt_spinner.h"
+
+static int live_engine_busy_stats(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ struct igt_spinner spin;
+ int err;
+
+ /*
+ * Check that if an engine supports busy-stats, they tell the truth.
+ */
+
+ if (igt_spinner_init(&spin, gt))
+ return -ENOMEM;
+
+ GEM_BUG_ON(intel_gt_pm_is_awake(gt));
+ for_each_engine(engine, gt, id) {
+ struct i915_request *rq;
+ ktime_t dt, de;
+
+ if (!intel_engine_supports_stats(engine))
+ continue;
+
+ if (!intel_engine_can_store_dword(engine))
+ continue;
+
+ if (intel_gt_pm_wait_for_idle(gt)) {
+ err = -EBUSY;
+ break;
+ }
+
+ dt = ktime_get();
+ de = intel_engine_get_busy_time(engine);
+ usleep_range(100, 200);
+ dt = ktime_sub(ktime_get(), dt);
+ de = ktime_sub(intel_engine_get_busy_time(engine), de);
+ if (de > 10) {
+ pr_err("%s: reported %lldns [%d%%] busyness while sleeping [for %lldns]\n",
+ engine->name,
+ de, (int)div64_u64(100 * de, dt), dt);
+ err = -EINVAL;
+ break;
+ }
+
+ rq = igt_spinner_create_request(&spin,
+ engine->kernel_context,
+ MI_NOOP);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ break;
+ }
+ i915_request_add(rq);
+
+ if (!igt_wait_for_spinner(&spin, rq)) {
+ intel_gt_set_wedged(engine->gt);
+ err = -ETIME;
+ break;
+ }
+
+ dt = ktime_get();
+ de = intel_engine_get_busy_time(engine);
+ usleep_range(100, 200);
+ dt = ktime_sub(ktime_get(), dt);
+ de = ktime_sub(intel_engine_get_busy_time(engine), de);
+ if (100 * de < 95 * dt) {
+ pr_err("%s: reported only %lldns [%d%%] busyness while spinning [for %lldns]\n",
+ engine->name,
+ de, (int)div64_u64(100 * de, dt), dt);
+ err = -EINVAL;
+ break;
+ }
+
+ igt_spinner_end(&spin);
+ if (igt_flush_test(gt->i915)) {
+ err = -EIO;
+ break;
+ }
+ }
+
+ igt_spinner_fini(&spin);
+ return err;
+}
static int live_engine_pm(void *arg)
{
@@ -77,6 +162,7 @@ static int live_engine_pm(void *arg)
int live_engine_pm_selftests(struct intel_gt *gt)
{
static const struct i915_subtest tests[] = {
+ SUBTEST(live_engine_busy_stats),
SUBTEST(live_engine_pm),
};
diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c
index 5049c3dd08a6..5e364fb31aea 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rps.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
@@ -1252,6 +1252,11 @@ int live_rps_dynamic(void *arg)
if (igt_spinner_init(&spin, gt))
return -ENOMEM;
+ if (intel_rps_has_interrupts(rps))
+ pr_info("RPS has interrupt support\n");
+ if (intel_rps_uses_timer(rps))
+ pr_info("RPS has timer support\n");
+
for_each_engine(engine, gt, id) {
struct i915_request *rq;
struct {
--
2.20.1
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next prev parent reply other threads:[~2020-06-01 7:25 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-01 7:24 [Intel-gfx] [PATCH 01/36] drm/i915: Handle very early engine initialisation failure Chris Wilson
2020-06-01 7:24 ` [Intel-gfx] [PATCH 02/36] drm/i915/gt: Split low level gen2-7 CS emitters Chris Wilson
2020-06-02 9:04 ` Mika Kuoppala
2020-06-01 7:24 ` [Intel-gfx] [PATCH 03/36] drm/i915/gt: Move legacy context wa to intel_workarounds Chris Wilson
2020-06-02 9:05 ` Mika Kuoppala
2020-06-01 7:24 ` [Intel-gfx] [PATCH 04/36] drm/i915: Trim the ironlake+ irq handler Chris Wilson
2020-06-01 11:49 ` Mika Kuoppala
2020-06-01 12:00 ` Chris Wilson
2020-06-01 12:08 ` Chris Wilson
2020-06-01 7:24 ` [Intel-gfx] [PATCH 05/36] Restore "drm/i915: drop engine_pin/unpin_breadcrumbs_irq" Chris Wilson
2020-06-01 7:24 ` [Intel-gfx] [PATCH 06/36] drm/i915/gt: Couple tasklet scheduling for all CS interrupts Chris Wilson
2020-06-01 7:24 ` [Intel-gfx] [PATCH 07/36] drm/i915/gt: Support creation of 'internal' rings Chris Wilson
2020-06-01 7:24 ` [Intel-gfx] [PATCH 08/36] drm/i915/gt: Use client timeline address for seqno writes Chris Wilson
2020-06-01 7:24 ` [Intel-gfx] [PATCH 09/36] drm/i915: Support inter-engine semaphores on gen6/7 Chris Wilson
2020-06-01 7:24 ` [Intel-gfx] [PATCH 10/36] drm/i915/gt: Infrastructure for ring scheduling Chris Wilson
2020-06-01 7:24 ` Chris Wilson [this message]
2020-06-01 8:03 ` [Intel-gfx] [PATCH] drm/i915/gt: Enable busy-stats for ring-scheduler Chris Wilson
2020-06-01 7:24 ` [Intel-gfx] [PATCH 12/36] drm/i915/gt: Track if an engine requires forcewake w/a Chris Wilson
2020-06-01 12:17 ` Mika Kuoppala
2020-06-01 7:24 ` [Intel-gfx] [PATCH 13/36] drm/i915: Relinquish forcewake immediately after manual grouping Chris Wilson
2020-06-01 12:20 ` Mika Kuoppala
2020-06-01 7:24 ` [Intel-gfx] [PATCH 14/36] drm/i915/gt: Implement ring scheduler for gen6/7 Chris Wilson
2020-06-01 7:24 ` [Intel-gfx] [PATCH 15/36] drm/i915/gt: Enable ring scheduling " Chris Wilson
2020-06-01 7:24 ` [Intel-gfx] [PATCH 16/36] drm/i915/gem: Mark the buffer pool as active for the cmdparser Chris Wilson
2020-06-01 7:24 ` [Intel-gfx] [PATCH 17/36] drm/i915/gem: Async GPU relocations only Chris Wilson
2020-06-01 7:24 ` [Intel-gfx] [PATCH 18/36] drm/i915: Add list_for_each_entry_safe_continue_reverse Chris Wilson
2020-06-01 7:24 ` [Intel-gfx] [PATCH 19/36] drm/i915/gem: Separate reloc validation into an earlier step Chris Wilson
2020-06-01 7:24 ` [Intel-gfx] [PATCH 20/36] drm/i915/gem: Lift GPU relocation allocation Chris Wilson
2020-06-01 7:24 ` [Intel-gfx] [PATCH 21/36] drm/i915/gem: Build the reloc request first Chris Wilson
2020-06-01 7:24 ` [Intel-gfx] [PATCH 22/36] drm/i915/gem: Add all GPU reloc awaits/signals en masse Chris Wilson
2020-06-01 7:24 ` [Intel-gfx] [PATCH 23/36] dma-buf: Proxy fence, an unsignaled fence placeholder Chris Wilson
2020-06-01 7:24 ` [Intel-gfx] [PATCH 24/36] drm/i915: Unpeel awaits on a proxy fence Chris Wilson
2020-06-01 7:24 ` [Intel-gfx] [PATCH 25/36] drm/i915/gem: Make relocations atomic within execbuf Chris Wilson
2020-06-01 7:24 ` [Intel-gfx] [PATCH 26/36] drm/syncobj: Allow use of dma-fence-proxy Chris Wilson
2020-06-01 7:24 ` [Intel-gfx] [PATCH 27/36] drm/i915/gem: Teach execbuf how to wait on future syncobj Chris Wilson
2020-06-01 7:24 ` [Intel-gfx] [PATCH 28/36] drm/i915/gem: Allow combining submit-fences with syncobj Chris Wilson
2020-06-01 7:24 ` [Intel-gfx] [PATCH 29/36] drm/i915/gt: Declare when we enabled timeslicing Chris Wilson
2020-06-01 7:24 ` [Intel-gfx] [PATCH 30/36] drm/i915: Drop I915_IDLE_ENGINES_TIMEOUT Chris Wilson
2020-06-01 7:24 ` [Intel-gfx] [PATCH 31/36] drm/i915: Always defer fenced work to the worker Chris Wilson
2020-06-01 7:24 ` [Intel-gfx] [PATCH 32/36] drm/i915/gem: Assign context id for async work Chris Wilson
2020-06-01 7:24 ` [Intel-gfx] [PATCH 33/36] drm/i915: Export a preallocate variant of i915_active_acquire() Chris Wilson
2020-06-01 7:24 ` [Intel-gfx] [PATCH 34/36] drm/i915/gem: Separate the ww_mutex walker into its own list Chris Wilson
2020-06-01 7:24 ` [Intel-gfx] [PATCH 35/36] drm/i915/gem: Asynchronous GTT unbinding Chris Wilson
2020-06-01 7:24 ` [Intel-gfx] [PATCH 36/36] drm/i915/gem: Bind the fence async for execbuf Chris Wilson
2020-06-01 7:34 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/36] drm/i915: Handle very early engine initialisation failure Patchwork
2020-06-01 7:36 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-06-01 7:56 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2020-06-01 8:30 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/36] drm/i915: Handle very early engine initialisation failure (rev2) Patchwork
2020-06-01 8:31 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-06-01 8:51 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-06-01 11:00 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-06-01 11:39 ` Chris Wilson
2020-06-01 11:31 ` [Intel-gfx] [PATCH 01/36] drm/i915: Handle very early engine initialisation failure Mika Kuoppala
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