* [Intel-gfx] [PATCH v2] drm/i915: Fix wrong CDCLK adjustment changes
@ 2020-06-01 17:30 Stanislav Lisovskiy
2020-06-01 19:13 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix wrong CDCLK adjustment changes (rev2) Patchwork
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Stanislav Lisovskiy @ 2020-06-01 17:30 UTC (permalink / raw)
To: intel-gfx; +Cc: dan.carpenter
Previous patch didn't take into account all pipes
but only those in state, which could cause wrong
CDCLK conclcusions and calculations.
Also there was a severe issue with min_cdclk being
assigned to 0 every compare cycle.
Too bad this was found by me only after merge.
This could be also causing the issues in test, however
not clear - anyway marking this as fixing the
"Adjust CDCLK accordingly to our DBuf bw needs".
v2: - s/pipe/crtc->pipe/
- save a bit of instructions by
skipping inactive pipes, without
getting 0 DBuf slice mask for it.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Fixes: cd1915460861 ("Adjust CDCLK accordingly to our DBuf bw needs")
---
drivers/gpu/drm/i915/display/intel_bw.c | 52 +++++++++++++-------
drivers/gpu/drm/i915/display/intel_cdclk.c | 19 ++++---
drivers/gpu/drm/i915/display/intel_display.c | 26 +++++-----
3 files changed, 55 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index a79bd7aeb03b..bd060404d249 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -437,6 +437,7 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state)
struct intel_crtc *crtc;
int max_bw = 0;
int slice_id;
+ enum pipe pipe;
int i;
for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
@@ -447,10 +448,15 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state)
if (IS_ERR(new_bw_state))
return PTR_ERR(new_bw_state);
+ old_bw_state = intel_atomic_get_old_bw_state(state);
+
crtc_bw = &new_bw_state->dbuf_bw[crtc->pipe];
memset(&crtc_bw->used_bw, 0, sizeof(crtc_bw->used_bw));
+ if (!crtc_state->hw.active)
+ continue;
+
for_each_plane_id_on_crtc(crtc, plane_id) {
const struct skl_ddb_entry *plane_alloc =
&crtc_state->wm.skl.plane_ddb_y[plane_id];
@@ -478,6 +484,15 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state)
for_each_dbuf_slice_in_mask(slice_id, dbuf_mask)
crtc_bw->used_bw[slice_id] += data_rate;
}
+ }
+
+ if (!old_bw_state)
+ return 0;
+
+ for_each_pipe(dev_priv, pipe) {
+ struct intel_dbuf_bw *crtc_bw;
+
+ crtc_bw = &new_bw_state->dbuf_bw[pipe];
for_each_dbuf_slice(slice_id) {
/*
@@ -490,14 +505,9 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state)
*/
max_bw += crtc_bw->used_bw[slice_id];
}
-
- new_bw_state->min_cdclk = max_bw / 64;
-
- old_bw_state = intel_atomic_get_old_bw_state(state);
}
- if (!old_bw_state)
- return 0;
+ new_bw_state->min_cdclk = max_bw / 64;
if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) {
int ret = intel_atomic_lock_global_state(&new_bw_state->base);
@@ -511,34 +521,38 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state)
int intel_bw_calc_min_cdclk(struct intel_atomic_state *state)
{
- int i;
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_bw_state *new_bw_state = NULL;
+ struct intel_bw_state *old_bw_state = NULL;
const struct intel_crtc_state *crtc_state;
struct intel_crtc *crtc;
int min_cdclk = 0;
- struct intel_bw_state *new_bw_state = NULL;
- struct intel_bw_state *old_bw_state = NULL;
+ enum pipe pipe;
+ int i;
for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
- struct intel_cdclk_state *cdclk_state;
-
new_bw_state = intel_atomic_get_bw_state(state);
if (IS_ERR(new_bw_state))
return PTR_ERR(new_bw_state);
- cdclk_state = intel_atomic_get_cdclk_state(state);
- if (IS_ERR(cdclk_state))
- return PTR_ERR(cdclk_state);
-
- min_cdclk = max(cdclk_state->min_cdclk[crtc->pipe], min_cdclk);
-
- new_bw_state->min_cdclk = min_cdclk;
-
old_bw_state = intel_atomic_get_old_bw_state(state);
}
if (!old_bw_state)
return 0;
+ for_each_pipe(dev_priv, pipe) {
+ struct intel_cdclk_state *cdclk_state;
+
+ cdclk_state = intel_atomic_get_new_cdclk_state(state);
+ if (!cdclk_state)
+ return 0;
+
+ min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk);
+ }
+
+ new_bw_state->min_cdclk = min_cdclk;
+
if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) {
int ret = intel_atomic_lock_global_state(&new_bw_state->base);
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index f9b0fc7317de..08468b121d02 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2084,9 +2084,12 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
{
struct intel_atomic_state *state = cdclk_state->base.state;
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_bw_state *bw_state = NULL;
struct intel_crtc *crtc;
struct intel_crtc_state *crtc_state;
int min_cdclk, i;
+ enum pipe pipe;
for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
int ret;
@@ -2095,6 +2098,10 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
if (min_cdclk < 0)
return min_cdclk;
+ bw_state = intel_atomic_get_bw_state(state);
+ if (IS_ERR(bw_state))
+ return PTR_ERR(bw_state);
+
if (cdclk_state->min_cdclk[i] == min_cdclk)
continue;
@@ -2106,15 +2113,11 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
}
min_cdclk = cdclk_state->force_min_cdclk;
+ for_each_pipe(dev_priv, pipe) {
+ min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk);
- for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
- struct intel_bw_state *bw_state;
-
- min_cdclk = max(cdclk_state->min_cdclk[crtc->pipe], min_cdclk);
-
- bw_state = intel_atomic_get_bw_state(state);
- if (IS_ERR(bw_state))
- return PTR_ERR(bw_state);
+ if (!bw_state)
+ continue;
min_cdclk = max(bw_state->min_cdclk, min_cdclk);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f40b909952cc..66af8f3053ed 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14708,13 +14708,14 @@ static int intel_atomic_check_cdclk(struct intel_atomic_state *state,
bool *need_cdclk_calc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- int i;
+ struct intel_cdclk_state *new_cdclk_state;
struct intel_plane_state *plane_state;
+ struct intel_bw_state *new_bw_state;
struct intel_plane *plane;
+ int min_cdclk = 0;
+ enum pipe pipe;
int ret;
- struct intel_cdclk_state *new_cdclk_state;
- struct intel_crtc_state *new_crtc_state;
- struct intel_crtc *crtc;
+ int i;
/*
* active_planes bitmask has been updated, and potentially
* affected planes are part of the state. We can now
@@ -14735,23 +14736,18 @@ static int intel_atomic_check_cdclk(struct intel_atomic_state *state,
if (ret)
return ret;
- if (!new_cdclk_state)
- return 0;
-
- for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
- struct intel_bw_state *bw_state;
- int min_cdclk = 0;
+ new_bw_state = intel_atomic_get_new_bw_state(state);
- min_cdclk = max(new_cdclk_state->min_cdclk[crtc->pipe], min_cdclk);
+ if (!new_cdclk_state || !new_bw_state)
+ return 0;
- bw_state = intel_atomic_get_bw_state(state);
- if (IS_ERR(bw_state))
- return PTR_ERR(bw_state);
+ for_each_pipe(dev_priv, pipe) {
+ min_cdclk = max(new_cdclk_state->min_cdclk[pipe], min_cdclk);
/*
* Currently do this change only if we need to increase
*/
- if (bw_state->min_cdclk > min_cdclk)
+ if (new_bw_state->min_cdclk > min_cdclk)
*need_cdclk_calc = true;
}
--
2.24.1.485.gad05a3d8e5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix wrong CDCLK adjustment changes (rev2)
2020-06-01 17:30 [Intel-gfx] [PATCH v2] drm/i915: Fix wrong CDCLK adjustment changes Stanislav Lisovskiy
@ 2020-06-01 19:13 ` Patchwork
2020-06-01 20:43 ` [Intel-gfx] [PATCH v2] drm/i915: Fix wrong CDCLK adjustment changes Manasi Navare
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2020-06-01 19:13 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Fix wrong CDCLK adjustment changes (rev2)
URL : https://patchwork.freedesktop.org/series/77654/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8566 -> Patchwork_17834
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/index.html
Known issues
------------
Here are the changes found in Patchwork_17834 that come from known issues:
### IGT changes ###
#### Possible fixes ####
* igt@i915_pm_rpm@module-reload:
- fi-glk-dsi: [TIMEOUT][1] ([i915#1288] / [i915#1958]) -> [PASS][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/fi-glk-dsi/igt@i915_pm_rpm@module-reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/fi-glk-dsi/igt@i915_pm_rpm@module-reload.html
#### Warnings ####
* igt@i915_pm_rpm@module-reload:
- fi-kbl-x1275: [SKIP][3] ([fdo#109271]) -> [FAIL][4] ([i915#62])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1288]: https://gitlab.freedesktop.org/drm/intel/issues/1288
[i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
Participating hosts (50 -> 45)
------------------------------
Additional (1): fi-kbl-soraka
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_8566 -> Patchwork_17834
CI-20190529: 20190529
CI_DRM_8566: fed6b89dd6f3c4e2e909805815c5728b1fd65ce5 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5689: 587cbed206689abbad60689d4a32bf9caf0cc124 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17834: 6bfe3f7a62bd1c9345f4789886a8030a10e81d32 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
6bfe3f7a62bd drm/i915: Fix wrong CDCLK adjustment changes
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Intel-gfx] [PATCH v2] drm/i915: Fix wrong CDCLK adjustment changes
2020-06-01 17:30 [Intel-gfx] [PATCH v2] drm/i915: Fix wrong CDCLK adjustment changes Stanislav Lisovskiy
2020-06-01 19:13 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix wrong CDCLK adjustment changes (rev2) Patchwork
@ 2020-06-01 20:43 ` Manasi Navare
2020-06-02 1:36 ` [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Fix wrong CDCLK adjustment changes (rev2) Patchwork
2020-06-04 18:16 ` [Intel-gfx] [PATCH v2] drm/i915: Fix wrong CDCLK adjustment changes Manasi Navare
3 siblings, 0 replies; 5+ messages in thread
From: Manasi Navare @ 2020-06-01 20:43 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx, dan.carpenter
On Mon, Jun 01, 2020 at 08:30:58PM +0300, Stanislav Lisovskiy wrote:
> Previous patch didn't take into account all pipes
> but only those in state, which could cause wrong
> CDCLK conclcusions and calculations.
> Also there was a severe issue with min_cdclk being
> assigned to 0 every compare cycle.
>
> Too bad this was found by me only after merge.
> This could be also causing the issues in test, however
> not clear - anyway marking this as fixing the
> "Adjust CDCLK accordingly to our DBuf bw needs".
>
> v2: - s/pipe/crtc->pipe/
> - save a bit of instructions by
> skipping inactive pipes, without
> getting 0 DBuf slice mask for it.
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Fixes: cd1915460861 ("Adjust CDCLK accordingly to our DBuf bw needs")
Looks good to me,
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Manasi
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 52 +++++++++++++-------
> drivers/gpu/drm/i915/display/intel_cdclk.c | 19 ++++---
> drivers/gpu/drm/i915/display/intel_display.c | 26 +++++-----
> 3 files changed, 55 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index a79bd7aeb03b..bd060404d249 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -437,6 +437,7 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state)
> struct intel_crtc *crtc;
> int max_bw = 0;
> int slice_id;
> + enum pipe pipe;
> int i;
>
> for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
> @@ -447,10 +448,15 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state)
> if (IS_ERR(new_bw_state))
> return PTR_ERR(new_bw_state);
>
> + old_bw_state = intel_atomic_get_old_bw_state(state);
> +
> crtc_bw = &new_bw_state->dbuf_bw[crtc->pipe];
>
> memset(&crtc_bw->used_bw, 0, sizeof(crtc_bw->used_bw));
>
> + if (!crtc_state->hw.active)
> + continue;
> +
> for_each_plane_id_on_crtc(crtc, plane_id) {
> const struct skl_ddb_entry *plane_alloc =
> &crtc_state->wm.skl.plane_ddb_y[plane_id];
> @@ -478,6 +484,15 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state)
> for_each_dbuf_slice_in_mask(slice_id, dbuf_mask)
> crtc_bw->used_bw[slice_id] += data_rate;
> }
> + }
> +
> + if (!old_bw_state)
> + return 0;
> +
> + for_each_pipe(dev_priv, pipe) {
> + struct intel_dbuf_bw *crtc_bw;
> +
> + crtc_bw = &new_bw_state->dbuf_bw[pipe];
>
> for_each_dbuf_slice(slice_id) {
> /*
> @@ -490,14 +505,9 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state)
> */
> max_bw += crtc_bw->used_bw[slice_id];
> }
> -
> - new_bw_state->min_cdclk = max_bw / 64;
> -
> - old_bw_state = intel_atomic_get_old_bw_state(state);
> }
>
> - if (!old_bw_state)
> - return 0;
> + new_bw_state->min_cdclk = max_bw / 64;
>
> if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) {
> int ret = intel_atomic_lock_global_state(&new_bw_state->base);
> @@ -511,34 +521,38 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state)
>
> int intel_bw_calc_min_cdclk(struct intel_atomic_state *state)
> {
> - int i;
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_bw_state *new_bw_state = NULL;
> + struct intel_bw_state *old_bw_state = NULL;
> const struct intel_crtc_state *crtc_state;
> struct intel_crtc *crtc;
> int min_cdclk = 0;
> - struct intel_bw_state *new_bw_state = NULL;
> - struct intel_bw_state *old_bw_state = NULL;
> + enum pipe pipe;
> + int i;
>
> for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
> - struct intel_cdclk_state *cdclk_state;
> -
> new_bw_state = intel_atomic_get_bw_state(state);
> if (IS_ERR(new_bw_state))
> return PTR_ERR(new_bw_state);
>
> - cdclk_state = intel_atomic_get_cdclk_state(state);
> - if (IS_ERR(cdclk_state))
> - return PTR_ERR(cdclk_state);
> -
> - min_cdclk = max(cdclk_state->min_cdclk[crtc->pipe], min_cdclk);
> -
> - new_bw_state->min_cdclk = min_cdclk;
> -
> old_bw_state = intel_atomic_get_old_bw_state(state);
> }
>
> if (!old_bw_state)
> return 0;
>
> + for_each_pipe(dev_priv, pipe) {
> + struct intel_cdclk_state *cdclk_state;
> +
> + cdclk_state = intel_atomic_get_new_cdclk_state(state);
> + if (!cdclk_state)
> + return 0;
> +
> + min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk);
> + }
> +
> + new_bw_state->min_cdclk = min_cdclk;
> +
> if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) {
> int ret = intel_atomic_lock_global_state(&new_bw_state->base);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index f9b0fc7317de..08468b121d02 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2084,9 +2084,12 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
> static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
> {
> struct intel_atomic_state *state = cdclk_state->base.state;
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_bw_state *bw_state = NULL;
> struct intel_crtc *crtc;
> struct intel_crtc_state *crtc_state;
> int min_cdclk, i;
> + enum pipe pipe;
>
> for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
> int ret;
> @@ -2095,6 +2098,10 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
> if (min_cdclk < 0)
> return min_cdclk;
>
> + bw_state = intel_atomic_get_bw_state(state);
> + if (IS_ERR(bw_state))
> + return PTR_ERR(bw_state);
> +
> if (cdclk_state->min_cdclk[i] == min_cdclk)
> continue;
>
> @@ -2106,15 +2113,11 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
> }
>
> min_cdclk = cdclk_state->force_min_cdclk;
> + for_each_pipe(dev_priv, pipe) {
> + min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk);
>
> - for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
> - struct intel_bw_state *bw_state;
> -
> - min_cdclk = max(cdclk_state->min_cdclk[crtc->pipe], min_cdclk);
> -
> - bw_state = intel_atomic_get_bw_state(state);
> - if (IS_ERR(bw_state))
> - return PTR_ERR(bw_state);
> + if (!bw_state)
> + continue;
>
> min_cdclk = max(bw_state->min_cdclk, min_cdclk);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index f40b909952cc..66af8f3053ed 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14708,13 +14708,14 @@ static int intel_atomic_check_cdclk(struct intel_atomic_state *state,
> bool *need_cdclk_calc)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - int i;
> + struct intel_cdclk_state *new_cdclk_state;
> struct intel_plane_state *plane_state;
> + struct intel_bw_state *new_bw_state;
> struct intel_plane *plane;
> + int min_cdclk = 0;
> + enum pipe pipe;
> int ret;
> - struct intel_cdclk_state *new_cdclk_state;
> - struct intel_crtc_state *new_crtc_state;
> - struct intel_crtc *crtc;
> + int i;
> /*
> * active_planes bitmask has been updated, and potentially
> * affected planes are part of the state. We can now
> @@ -14735,23 +14736,18 @@ static int intel_atomic_check_cdclk(struct intel_atomic_state *state,
> if (ret)
> return ret;
>
> - if (!new_cdclk_state)
> - return 0;
> -
> - for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> - struct intel_bw_state *bw_state;
> - int min_cdclk = 0;
> + new_bw_state = intel_atomic_get_new_bw_state(state);
>
> - min_cdclk = max(new_cdclk_state->min_cdclk[crtc->pipe], min_cdclk);
> + if (!new_cdclk_state || !new_bw_state)
> + return 0;
>
> - bw_state = intel_atomic_get_bw_state(state);
> - if (IS_ERR(bw_state))
> - return PTR_ERR(bw_state);
> + for_each_pipe(dev_priv, pipe) {
> + min_cdclk = max(new_cdclk_state->min_cdclk[pipe], min_cdclk);
>
> /*
> * Currently do this change only if we need to increase
> */
> - if (bw_state->min_cdclk > min_cdclk)
> + if (new_bw_state->min_cdclk > min_cdclk)
> *need_cdclk_calc = true;
> }
>
> --
> 2.24.1.485.gad05a3d8e5
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Fix wrong CDCLK adjustment changes (rev2)
2020-06-01 17:30 [Intel-gfx] [PATCH v2] drm/i915: Fix wrong CDCLK adjustment changes Stanislav Lisovskiy
2020-06-01 19:13 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix wrong CDCLK adjustment changes (rev2) Patchwork
2020-06-01 20:43 ` [Intel-gfx] [PATCH v2] drm/i915: Fix wrong CDCLK adjustment changes Manasi Navare
@ 2020-06-02 1:36 ` Patchwork
2020-06-04 18:16 ` [Intel-gfx] [PATCH v2] drm/i915: Fix wrong CDCLK adjustment changes Manasi Navare
3 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2020-06-02 1:36 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Fix wrong CDCLK adjustment changes (rev2)
URL : https://patchwork.freedesktop.org/series/77654/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8566_full -> Patchwork_17834_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_17834_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@perf_pmu@faulting-read@uc}:
- shard-apl: NOTRUN -> [DMESG-WARN][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-apl4/igt@perf_pmu@faulting-read@uc.html
Known issues
------------
Here are the changes found in Patchwork_17834_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@engines-mixed-process@rcs0:
- shard-apl: [PASS][2] -> [FAIL][3] ([i915#1528])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-apl8/igt@gem_ctx_persistence@engines-mixed-process@rcs0.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-apl8/igt@gem_ctx_persistence@engines-mixed-process@rcs0.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl: [PASS][4] -> [DMESG-WARN][5] ([i915#180]) +1 similar issue
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-apl4/igt@i915_suspend@fence-restore-tiled2untiled.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-apl2/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-180:
- shard-glk: [PASS][6] -> [FAIL][7] ([i915#1119] / [i915#118] / [i915#95])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-glk6/igt@kms_big_fb@y-tiled-64bpp-rotate-180.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-glk8/igt@kms_big_fb@y-tiled-64bpp-rotate-180.html
* igt@kms_cursor_legacy@pipe-b-torture-bo:
- shard-tglb: [PASS][8] -> [DMESG-WARN][9] ([i915#128])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-tglb1/igt@kms_cursor_legacy@pipe-b-torture-bo.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-tglb5/igt@kms_cursor_legacy@pipe-b-torture-bo.html
* igt@kms_draw_crc@fill-fb:
- shard-apl: [PASS][10] -> [FAIL][11] ([i915#95])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-apl4/igt@kms_draw_crc@fill-fb.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-apl2/igt@kms_draw_crc@fill-fb.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [PASS][12] -> [FAIL][13] ([i915#1188])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-skl5/igt@kms_hdr@bpc-switch-dpms.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-skl6/igt@kms_hdr@bpc-switch-dpms.html
- shard-kbl: [PASS][14] -> [FAIL][15] ([i915#1188])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-kbl3/igt@kms_hdr@bpc-switch-dpms.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-kbl6/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [PASS][16] -> [SKIP][17] ([fdo#109642] / [fdo#111068])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-iclb5/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_primary_render:
- shard-iclb: [PASS][18] -> [SKIP][19] ([fdo#109441])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-iclb2/igt@kms_psr@psr2_primary_render.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-iclb3/igt@kms_psr@psr2_primary_render.html
* igt@kms_vblank@pipe-c-ts-continuation-suspend:
- shard-kbl: [PASS][20] -> [DMESG-WARN][21] ([i915#180])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-kbl3/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-kbl1/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
#### Possible fixes ####
* igt@gem_exec_reloc@basic-gtt-wc:
- shard-hsw: [DMESG-WARN][22] ([i915#1927]) -> [PASS][23]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-hsw1/igt@gem_exec_reloc@basic-gtt-wc.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-hsw2/igt@gem_exec_reloc@basic-gtt-wc.html
* igt@kms_color@pipe-a-gamma:
- shard-hsw: [INCOMPLETE][24] ([i915#1927] / [i915#61]) -> [PASS][25]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-hsw1/igt@kms_color@pipe-a-gamma.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-hsw4/igt@kms_color@pipe-a-gamma.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-kbl: [DMESG-WARN][26] ([i915#180]) -> [PASS][27]
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-kbl6/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-kbl3/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_cursor_legacy@cursora-vs-flipb-toggle:
- shard-glk: [DMESG-FAIL][28] ([i915#1925] / [i915#1926]) -> [PASS][29] +1 similar issue
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-glk4/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-glk6/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [FAIL][30] ([i915#1188]) -> [PASS][31] +1 similar issue
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-skl7/igt@kms_hdr@bpc-switch-suspend.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-skl9/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [FAIL][32] ([fdo#108145] / [i915#265]) -> [PASS][33] +1 similar issue
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [SKIP][34] ([fdo#109441]) -> [PASS][35] +5 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-iclb4/igt@kms_psr@psr2_cursor_render.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: [DMESG-WARN][36] ([i915#180]) -> [PASS][37] +3 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-apl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-apl8/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* {igt@perf@blocking-parameterized}:
- shard-hsw: [FAIL][38] ([i915#1542]) -> [PASS][39]
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-hsw8/igt@perf@blocking-parameterized.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-hsw1/igt@perf@blocking-parameterized.html
#### Warnings ####
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: [SKIP][40] ([i915#658]) -> [SKIP][41] ([i915#588])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-iclb3/igt@i915_pm_dc@dc3co-vpb-simulation.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@i915_pm_dc@dc6-psr:
- shard-tglb: [FAIL][42] ([i915#454]) -> [SKIP][43] ([i915#468])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-tglb1/igt@i915_pm_dc@dc6-psr.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-tglb2/igt@i915_pm_dc@dc6-psr.html
* igt@kms_content_protection@atomic:
- shard-apl: [FAIL][44] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][45] ([i915#1319])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-apl7/igt@kms_content_protection@atomic.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-apl1/igt@kms_content_protection@atomic.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
- shard-apl: [FAIL][46] ([fdo#108145] / [i915#265] / [i915#95]) -> [FAIL][47] ([fdo#108145] / [i915#265])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-apl8/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-apl8/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321
[fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[i915#1119]: https://gitlab.freedesktop.org/drm/intel/issues/1119
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1925]: https://gitlab.freedesktop.org/drm/intel/issues/1925
[i915#1926]: https://gitlab.freedesktop.org/drm/intel/issues/1926
[i915#1927]: https://gitlab.freedesktop.org/drm/intel/issues/1927
[i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468
[i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
[i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_8566 -> Patchwork_17834
CI-20190529: 20190529
CI_DRM_8566: fed6b89dd6f3c4e2e909805815c5728b1fd65ce5 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5689: 587cbed206689abbad60689d4a32bf9caf0cc124 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17834: 6bfe3f7a62bd1c9345f4789886a8030a10e81d32 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Intel-gfx] [PATCH v2] drm/i915: Fix wrong CDCLK adjustment changes
2020-06-01 17:30 [Intel-gfx] [PATCH v2] drm/i915: Fix wrong CDCLK adjustment changes Stanislav Lisovskiy
` (2 preceding siblings ...)
2020-06-02 1:36 ` [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Fix wrong CDCLK adjustment changes (rev2) Patchwork
@ 2020-06-04 18:16 ` Manasi Navare
3 siblings, 0 replies; 5+ messages in thread
From: Manasi Navare @ 2020-06-04 18:16 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx, dan.carpenter
Pushed to dinq, thanks for the patch.
Manasi
On Mon, Jun 01, 2020 at 08:30:58PM +0300, Stanislav Lisovskiy wrote:
> Previous patch didn't take into account all pipes
> but only those in state, which could cause wrong
> CDCLK conclcusions and calculations.
> Also there was a severe issue with min_cdclk being
> assigned to 0 every compare cycle.
>
> Too bad this was found by me only after merge.
> This could be also causing the issues in test, however
> not clear - anyway marking this as fixing the
> "Adjust CDCLK accordingly to our DBuf bw needs".
>
> v2: - s/pipe/crtc->pipe/
> - save a bit of instructions by
> skipping inactive pipes, without
> getting 0 DBuf slice mask for it.
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Fixes: cd1915460861 ("Adjust CDCLK accordingly to our DBuf bw needs")
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 52 +++++++++++++-------
> drivers/gpu/drm/i915/display/intel_cdclk.c | 19 ++++---
> drivers/gpu/drm/i915/display/intel_display.c | 26 +++++-----
> 3 files changed, 55 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index a79bd7aeb03b..bd060404d249 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -437,6 +437,7 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state)
> struct intel_crtc *crtc;
> int max_bw = 0;
> int slice_id;
> + enum pipe pipe;
> int i;
>
> for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
> @@ -447,10 +448,15 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state)
> if (IS_ERR(new_bw_state))
> return PTR_ERR(new_bw_state);
>
> + old_bw_state = intel_atomic_get_old_bw_state(state);
> +
> crtc_bw = &new_bw_state->dbuf_bw[crtc->pipe];
>
> memset(&crtc_bw->used_bw, 0, sizeof(crtc_bw->used_bw));
>
> + if (!crtc_state->hw.active)
> + continue;
> +
> for_each_plane_id_on_crtc(crtc, plane_id) {
> const struct skl_ddb_entry *plane_alloc =
> &crtc_state->wm.skl.plane_ddb_y[plane_id];
> @@ -478,6 +484,15 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state)
> for_each_dbuf_slice_in_mask(slice_id, dbuf_mask)
> crtc_bw->used_bw[slice_id] += data_rate;
> }
> + }
> +
> + if (!old_bw_state)
> + return 0;
> +
> + for_each_pipe(dev_priv, pipe) {
> + struct intel_dbuf_bw *crtc_bw;
> +
> + crtc_bw = &new_bw_state->dbuf_bw[pipe];
>
> for_each_dbuf_slice(slice_id) {
> /*
> @@ -490,14 +505,9 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state)
> */
> max_bw += crtc_bw->used_bw[slice_id];
> }
> -
> - new_bw_state->min_cdclk = max_bw / 64;
> -
> - old_bw_state = intel_atomic_get_old_bw_state(state);
> }
>
> - if (!old_bw_state)
> - return 0;
> + new_bw_state->min_cdclk = max_bw / 64;
>
> if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) {
> int ret = intel_atomic_lock_global_state(&new_bw_state->base);
> @@ -511,34 +521,38 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state)
>
> int intel_bw_calc_min_cdclk(struct intel_atomic_state *state)
> {
> - int i;
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_bw_state *new_bw_state = NULL;
> + struct intel_bw_state *old_bw_state = NULL;
> const struct intel_crtc_state *crtc_state;
> struct intel_crtc *crtc;
> int min_cdclk = 0;
> - struct intel_bw_state *new_bw_state = NULL;
> - struct intel_bw_state *old_bw_state = NULL;
> + enum pipe pipe;
> + int i;
>
> for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
> - struct intel_cdclk_state *cdclk_state;
> -
> new_bw_state = intel_atomic_get_bw_state(state);
> if (IS_ERR(new_bw_state))
> return PTR_ERR(new_bw_state);
>
> - cdclk_state = intel_atomic_get_cdclk_state(state);
> - if (IS_ERR(cdclk_state))
> - return PTR_ERR(cdclk_state);
> -
> - min_cdclk = max(cdclk_state->min_cdclk[crtc->pipe], min_cdclk);
> -
> - new_bw_state->min_cdclk = min_cdclk;
> -
> old_bw_state = intel_atomic_get_old_bw_state(state);
> }
>
> if (!old_bw_state)
> return 0;
>
> + for_each_pipe(dev_priv, pipe) {
> + struct intel_cdclk_state *cdclk_state;
> +
> + cdclk_state = intel_atomic_get_new_cdclk_state(state);
> + if (!cdclk_state)
> + return 0;
> +
> + min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk);
> + }
> +
> + new_bw_state->min_cdclk = min_cdclk;
> +
> if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) {
> int ret = intel_atomic_lock_global_state(&new_bw_state->base);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index f9b0fc7317de..08468b121d02 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2084,9 +2084,12 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
> static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
> {
> struct intel_atomic_state *state = cdclk_state->base.state;
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_bw_state *bw_state = NULL;
> struct intel_crtc *crtc;
> struct intel_crtc_state *crtc_state;
> int min_cdclk, i;
> + enum pipe pipe;
>
> for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
> int ret;
> @@ -2095,6 +2098,10 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
> if (min_cdclk < 0)
> return min_cdclk;
>
> + bw_state = intel_atomic_get_bw_state(state);
> + if (IS_ERR(bw_state))
> + return PTR_ERR(bw_state);
> +
> if (cdclk_state->min_cdclk[i] == min_cdclk)
> continue;
>
> @@ -2106,15 +2113,11 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
> }
>
> min_cdclk = cdclk_state->force_min_cdclk;
> + for_each_pipe(dev_priv, pipe) {
> + min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk);
>
> - for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
> - struct intel_bw_state *bw_state;
> -
> - min_cdclk = max(cdclk_state->min_cdclk[crtc->pipe], min_cdclk);
> -
> - bw_state = intel_atomic_get_bw_state(state);
> - if (IS_ERR(bw_state))
> - return PTR_ERR(bw_state);
> + if (!bw_state)
> + continue;
>
> min_cdclk = max(bw_state->min_cdclk, min_cdclk);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index f40b909952cc..66af8f3053ed 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14708,13 +14708,14 @@ static int intel_atomic_check_cdclk(struct intel_atomic_state *state,
> bool *need_cdclk_calc)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - int i;
> + struct intel_cdclk_state *new_cdclk_state;
> struct intel_plane_state *plane_state;
> + struct intel_bw_state *new_bw_state;
> struct intel_plane *plane;
> + int min_cdclk = 0;
> + enum pipe pipe;
> int ret;
> - struct intel_cdclk_state *new_cdclk_state;
> - struct intel_crtc_state *new_crtc_state;
> - struct intel_crtc *crtc;
> + int i;
> /*
> * active_planes bitmask has been updated, and potentially
> * affected planes are part of the state. We can now
> @@ -14735,23 +14736,18 @@ static int intel_atomic_check_cdclk(struct intel_atomic_state *state,
> if (ret)
> return ret;
>
> - if (!new_cdclk_state)
> - return 0;
> -
> - for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> - struct intel_bw_state *bw_state;
> - int min_cdclk = 0;
> + new_bw_state = intel_atomic_get_new_bw_state(state);
>
> - min_cdclk = max(new_cdclk_state->min_cdclk[crtc->pipe], min_cdclk);
> + if (!new_cdclk_state || !new_bw_state)
> + return 0;
>
> - bw_state = intel_atomic_get_bw_state(state);
> - if (IS_ERR(bw_state))
> - return PTR_ERR(bw_state);
> + for_each_pipe(dev_priv, pipe) {
> + min_cdclk = max(new_cdclk_state->min_cdclk[pipe], min_cdclk);
>
> /*
> * Currently do this change only if we need to increase
> */
> - if (bw_state->min_cdclk > min_cdclk)
> + if (new_bw_state->min_cdclk > min_cdclk)
> *need_cdclk_calc = true;
> }
>
> --
> 2.24.1.485.gad05a3d8e5
>
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^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-06-04 18:15 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-06-01 17:30 [Intel-gfx] [PATCH v2] drm/i915: Fix wrong CDCLK adjustment changes Stanislav Lisovskiy
2020-06-01 19:13 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix wrong CDCLK adjustment changes (rev2) Patchwork
2020-06-01 20:43 ` [Intel-gfx] [PATCH v2] drm/i915: Fix wrong CDCLK adjustment changes Manasi Navare
2020-06-02 1:36 ` [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Fix wrong CDCLK adjustment changes (rev2) Patchwork
2020-06-04 18:16 ` [Intel-gfx] [PATCH v2] drm/i915: Fix wrong CDCLK adjustment changes Manasi Navare
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