[Intel-gfx] [PATCH] drm/i915/gt: Make the CTX_TIMESTAMP readable on !rcs

[Intel-gfx] [PATCH] drm/i915/gt: Make the CTX_TIMESTAMP readable on !rcs

[Chris Wilson]

For reasons that be, the HW only allows usersace to read its own
CTX_TIMESTAMP [context local HW runtime] on rcs. Make it available for
all by adding it to the whitelists.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
This probably means the change occurred in the glk/cfl timeframe...
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 94d66a9d760d..7afe5792d68c 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1253,9 +1253,15 @@ static void icl_whitelist_build(struct intel_engine_cs *engine)
 		/* hucStatus2RegOffset */
 		whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base),
 				  RING_FORCE_TO_NONPRIV_ACCESS_RD);
+		whitelist_reg_ext(w,
+				  RING_CTX_TIMESTAMP(engine->mmio_base),
+				  RING_FORCE_TO_NONPRIV_ACCESS_RD);
 		break;
 
 	default:
+		whitelist_reg_ext(w,
+				  RING_CTX_TIMESTAMP(engine->mmio_base),
+				  RING_FORCE_TO_NONPRIV_ACCESS_RD);
 		break;
 	}
 }
@@ -1287,6 +1293,9 @@ static void tgl_whitelist_build(struct intel_engine_cs *engine)
 		whitelist_reg(w, HIZ_CHICKEN);
 		break;
 	default:
+		whitelist_reg_ext(w,
+				  RING_CTX_TIMESTAMP(engine->mmio_base),
+				  RING_FORCE_TO_NONPRIV_ACCESS_RD);
 		break;
 	}
 }
-- 
2.20.1

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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gt: Make the CTX_TIMESTAMP readable on !rcs

[Patchwork]

== Series Details ==

Series: drm/i915/gt: Make the CTX_TIMESTAMP readable on !rcs
URL   : https://patchwork.freedesktop.org/series/77910/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_8571 -> Patchwork_17840
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_17840 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_17840, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17840/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_17840:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live@workarounds:
    - fi-icl-y:           [PASS][1] -> [DMESG-FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/fi-icl-y/igt@i915_selftest@live@workarounds.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17840/fi-icl-y/igt@i915_selftest@live@workarounds.html
    - fi-tgl-y:           [PASS][3] -> [DMESG-FAIL][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/fi-tgl-y/igt@i915_selftest@live@workarounds.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17840/fi-tgl-y/igt@i915_selftest@live@workarounds.html
    - fi-icl-guc:         [PASS][5] -> [DMESG-FAIL][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/fi-icl-guc/igt@i915_selftest@live@workarounds.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17840/fi-icl-guc/igt@i915_selftest@live@workarounds.html
    - fi-icl-u2:          [PASS][7] -> [DMESG-FAIL][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/fi-icl-u2/igt@i915_selftest@live@workarounds.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17840/fi-icl-u2/igt@i915_selftest@live@workarounds.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live@workarounds:
    - {fi-tgl-dsi}:       [PASS][9] -> [DMESG-FAIL][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/fi-tgl-dsi/igt@i915_selftest@live@workarounds.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17840/fi-tgl-dsi/igt@i915_selftest@live@workarounds.html
    - {fi-ehl-1}:         [PASS][11] -> [DMESG-FAIL][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/fi-ehl-1/igt@i915_selftest@live@workarounds.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17840/fi-ehl-1/igt@i915_selftest@live@workarounds.html
    - {fi-tgl-u}:         [PASS][13] -> [DMESG-FAIL][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/fi-tgl-u/igt@i915_selftest@live@workarounds.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17840/fi-tgl-u/igt@i915_selftest@live@workarounds.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).



Participating hosts (50 -> 44)
------------------------------

  Missing    (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_8571 -> Patchwork_17840

  CI-20190529: 20190529
  CI_DRM_8571: 0536dff30eff69abcf6355bdd9b9fdf45a560099 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5690: bea881189520a9cccbb1c1cb454ac5b6fdaea40e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_17840: ecf32dcbc65f20a3c18eab819236813936a61e10 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

ecf32dcbc65f drm/i915/gt: Make the CTX_TIMESTAMP readable on !rcs

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17840/index.html
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Re: [Intel-gfx] [PATCH] drm/i915/gt: Make the CTX_TIMESTAMP readable on !rcs

[Souza, Jose]

On Tue, 2020-06-02 at 16:48 +0100, Chris Wilson wrote:
> For reasons that be, the HW only allows usersace to read its own
> CTX_TIMESTAMP [context local HW runtime] on rcs. Make it available for
> all by adding it to the whitelists.
> 
> v2: The change took effect from Cometlake.
> v3: Ignore timestamps that autoincrement when validating the whitelist

I would have separated add the register to the whitelist from the selftest but anyways looks good.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c   | 25 ++++++++++++++++++-
>  .../gpu/drm/i915/gt/selftest_workarounds.c    | 17 +++++++++++++
>  2 files changed, 41 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 6e1accbcc045..0731bbcef06c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1206,6 +1206,18 @@ static void cfl_whitelist_build(struct intel_engine_cs *engine)
>  			  RING_FORCE_TO_NONPRIV_RANGE_4);
>  }
>  
> +static void cml_whitelist_build(struct intel_engine_cs *engine)
> +{
> +	struct i915_wa_list *w = &engine->whitelist;
> +
> +	if (engine->class != RENDER_CLASS)
> +		whitelist_reg_ext(w,
> +				  RING_CTX_TIMESTAMP(engine->mmio_base),
> +				  RING_FORCE_TO_NONPRIV_ACCESS_RD);
> +
> +	cfl_whitelist_build(engine);
> +}
> +
>  static void cnl_whitelist_build(struct intel_engine_cs *engine)
>  {
>  	struct i915_wa_list *w = &engine->whitelist;
> @@ -1256,9 +1268,15 @@ static void icl_whitelist_build(struct intel_engine_cs *engine)
>  		/* hucStatus2RegOffset */
>  		whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base),
>  				  RING_FORCE_TO_NONPRIV_ACCESS_RD);
> +		whitelist_reg_ext(w,
> +				  RING_CTX_TIMESTAMP(engine->mmio_base),
> +				  RING_FORCE_TO_NONPRIV_ACCESS_RD);
>  		break;
>  
>  	default:
> +		whitelist_reg_ext(w,
> +				  RING_CTX_TIMESTAMP(engine->mmio_base),
> +				  RING_FORCE_TO_NONPRIV_ACCESS_RD);
>  		break;
>  	}
>  }
> @@ -1290,6 +1308,9 @@ static void tgl_whitelist_build(struct intel_engine_cs *engine)
>  		whitelist_reg(w, HIZ_CHICKEN);
>  		break;
>  	default:
> +		whitelist_reg_ext(w,
> +				  RING_CTX_TIMESTAMP(engine->mmio_base),
> +				  RING_FORCE_TO_NONPRIV_ACCESS_RD);
>  		break;
>  	}
>  }
> @@ -1307,7 +1328,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
>  		icl_whitelist_build(engine);
>  	else if (IS_CANNONLAKE(i915))
>  		cnl_whitelist_build(engine);
> -	else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
> +	else if (IS_COMETLAKE(i915))
> +		cml_whitelist_build(engine);
> +	else if (IS_COFFEELAKE(i915))
>  		cfl_whitelist_build(engine);
>  	else if (IS_GEMINILAKE(i915))
>  		glk_whitelist_build(engine);
> diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> index 32785463ec9e..febc9e6692ba 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> @@ -417,6 +417,20 @@ static bool wo_register(struct intel_engine_cs *engine, u32 reg)
>  	return false;
>  }
>  
> +static bool timestamp(const struct intel_engine_cs *engine, u32 reg)
> +{
> +	reg = (reg - engine->mmio_base) & ~RING_FORCE_TO_NONPRIV_ACCESS_MASK;
> +	switch (reg) {
> +	case 0x358:
> +	case 0x35c:
> +	case 0x3a8:
> +		return true;
> +
> +	default:
> +		return false;
> +	}
> +}
> +
>  static bool ro_register(u32 reg)
>  {
>  	if ((reg & RING_FORCE_TO_NONPRIV_ACCESS_MASK) ==
> @@ -497,6 +511,9 @@ static int check_dirty_whitelist(struct intel_context *ce)
>  		if (wo_register(engine, reg))
>  			continue;
>  
> +		if (timestamp(engine, reg))
> +			continue; /* timestamps are expected to autoincrement */
> +
>  		ro_reg = ro_register(reg);
>  
>  		/* Clear non priv flags */
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[Intel-gfx] [PATCH] drm/i915/gt: Make the CTX_TIMESTAMP readable on !rcs

[Chris Wilson]

For reasons that be, the HW only allows usersace to read its own
CTX_TIMESTAMP [context local HW runtime] on rcs. Make it available for
all by adding it to the whitelists.

v2: The change took effect from Cometlake.
v3: Ignore timestamps that autoincrement when validating the whitelist

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 25 ++++++++++++++++++-
 .../gpu/drm/i915/gt/selftest_workarounds.c    | 17 +++++++++++++
 2 files changed, 41 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 6e1accbcc045..0731bbcef06c 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1206,6 +1206,18 @@ static void cfl_whitelist_build(struct intel_engine_cs *engine)
 			  RING_FORCE_TO_NONPRIV_RANGE_4);
 }
 
+static void cml_whitelist_build(struct intel_engine_cs *engine)
+{
+	struct i915_wa_list *w = &engine->whitelist;
+
+	if (engine->class != RENDER_CLASS)
+		whitelist_reg_ext(w,
+				  RING_CTX_TIMESTAMP(engine->mmio_base),
+				  RING_FORCE_TO_NONPRIV_ACCESS_RD);
+
+	cfl_whitelist_build(engine);
+}
+
 static void cnl_whitelist_build(struct intel_engine_cs *engine)
 {
 	struct i915_wa_list *w = &engine->whitelist;
@@ -1256,9 +1268,15 @@ static void icl_whitelist_build(struct intel_engine_cs *engine)
 		/* hucStatus2RegOffset */
 		whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base),
 				  RING_FORCE_TO_NONPRIV_ACCESS_RD);
+		whitelist_reg_ext(w,
+				  RING_CTX_TIMESTAMP(engine->mmio_base),
+				  RING_FORCE_TO_NONPRIV_ACCESS_RD);
 		break;
 
 	default:
+		whitelist_reg_ext(w,
+				  RING_CTX_TIMESTAMP(engine->mmio_base),
+				  RING_FORCE_TO_NONPRIV_ACCESS_RD);
 		break;
 	}
 }
@@ -1290,6 +1308,9 @@ static void tgl_whitelist_build(struct intel_engine_cs *engine)
 		whitelist_reg(w, HIZ_CHICKEN);
 		break;
 	default:
+		whitelist_reg_ext(w,
+				  RING_CTX_TIMESTAMP(engine->mmio_base),
+				  RING_FORCE_TO_NONPRIV_ACCESS_RD);
 		break;
 	}
 }
@@ -1307,7 +1328,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
 		icl_whitelist_build(engine);
 	else if (IS_CANNONLAKE(i915))
 		cnl_whitelist_build(engine);
-	else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
+	else if (IS_COMETLAKE(i915))
+		cml_whitelist_build(engine);
+	else if (IS_COFFEELAKE(i915))
 		cfl_whitelist_build(engine);
 	else if (IS_GEMINILAKE(i915))
 		glk_whitelist_build(engine);
diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
index 32785463ec9e..febc9e6692ba 100644
--- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
@@ -417,6 +417,20 @@ static bool wo_register(struct intel_engine_cs *engine, u32 reg)
 	return false;
 }
 
+static bool timestamp(const struct intel_engine_cs *engine, u32 reg)
+{
+	reg = (reg - engine->mmio_base) & ~RING_FORCE_TO_NONPRIV_ACCESS_MASK;
+	switch (reg) {
+	case 0x358:
+	case 0x35c:
+	case 0x3a8:
+		return true;
+
+	default:
+		return false;
+	}
+}
+
 static bool ro_register(u32 reg)
 {
 	if ((reg & RING_FORCE_TO_NONPRIV_ACCESS_MASK) ==
@@ -497,6 +511,9 @@ static int check_dirty_whitelist(struct intel_context *ce)
 		if (wo_register(engine, reg))
 			continue;
 
+		if (timestamp(engine, reg))
+			continue; /* timestamps are expected to autoincrement */
+
 		ro_reg = ro_register(reg);
 
 		/* Clear non priv flags */
-- 
2.20.1

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