[Intel-gfx] [PATCH 0/4] drm/i915: FBC fixes

[Intel-gfx] [PATCH 0/4] drm/i915: FBC fixes

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Leftovers from the earlier FBC series.

Ville Syrjälä (4):
  drm/i915/fbc: Use the correct plane stride
  drm/i915/fbc: Fix nuke for pre-snb platforms
  drm/i915/fbc: Enable fbc on i865
  drm/i915/fbc: Allow FBC to recompress after a 3D workload on i85x/i865

 drivers/gpu/drm/i915/display/intel_display.c |  3 +-
 drivers/gpu/drm/i915/display/intel_fbc.c     | 50 +++++++++++++++++---
 drivers/gpu/drm/i915/i915_pci.c              |  1 +
 drivers/gpu/drm/i915/i915_reg.h              |  1 +
 drivers/gpu/drm/i915/intel_pm.c              | 10 ++++
 5 files changed, 57 insertions(+), 8 deletions(-)

-- 
2.26.2

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[Intel-gfx] [PATCH 1/4] drm/i915/fbc: Use the correct plane stride

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Consult the actual plane stride instead of the fb stride. The two
will disagree when we remap the gtt. The plane stride is what the
hw will be fed so that's what we should look at for the FBC
retrictions/cfb allocation.

Since we no longer require a fence we are going to attempt using
FBC with remapping, and so we should look at correct stride.

With 90/270 degree rotation the plane stride is stored in units
of pixels, so we need to conver it to bytes for the purposes
of calculating the cfb stride. Not entirely sure if this matches
the hw behaviour though. Need to reverse engineer that at some
point...

We also need to reorder the pixel format check vs. stride check
to avoid triggering a spurious WARN(stride & 63) with cpp==1 and
plane stride==32.

v2: Try to deal with rotated stride and related WARN

Cc: José Roberto de Souza <jose.souza@intel.com>
Fixes: 691f7ba58d52 ("drm/i915/display/fbc: Make fences a nice-to-have for GEN9+")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_fbc.c | 16 ++++++++++------
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 69a0682ddb6a..d30c2a389294 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -695,9 +695,13 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
 	cache->plane.pixel_blend_mode = plane_state->hw.pixel_blend_mode;
 
 	cache->fb.format = fb->format;
-	cache->fb.stride = fb->pitches[0];
 	cache->fb.modifier = fb->modifier;
 
+	/* FIXME is this correct? */
+	cache->fb.stride = plane_state->color_plane[0].stride;
+	if (drm_rotation_90_or_270(plane_state->hw.rotation))
+		cache->fb.stride *= fb->format->cpp[0];
+
 	/* FBC1 compression interval: arbitrary choice of 1 second */
 	cache->interval = drm_mode_vrefresh(&crtc_state->hw.adjusted_mode);
 
@@ -797,6 +801,11 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
 		return false;
 	}
 
+	if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) {
+		fbc->no_fbc_reason = "pixel format is invalid";
+		return false;
+	}
+
 	if (!rotation_is_valid(dev_priv, cache->fb.format->format,
 			       cache->plane.rotation)) {
 		fbc->no_fbc_reason = "rotation unsupported";
@@ -813,11 +822,6 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
 		return false;
 	}
 
-	if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) {
-		fbc->no_fbc_reason = "pixel format is invalid";
-		return false;
-	}
-
 	if (cache->plane.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE &&
 	    cache->fb.format->has_alpha) {
 		fbc->no_fbc_reason = "per-pixel alpha blending is incompatible with FBC";
-- 
2.26.2

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[Intel-gfx] [PATCH 2/4] drm/i915/fbc: Fix nuke for pre-snb platforms

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The MSG_FBC_REND_STATE register only exists on snb+. For older
platforms (would also work for snb+) we can simply rewite DSPSURF
to trigger a flip nuke.

While generally RMW is considered harmful we'll use it here for
simplicity. And since FBC doesn't exist in i830 we don't have to
worry about the DSPSURF double buffering hardware fails present
on that platform.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_fbc.c | 34 +++++++++++++++++++++++-
 1 file changed, 33 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index d30c2a389294..036546ce8db8 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -187,8 +187,30 @@ static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv)
 	return intel_de_read(dev_priv, DPFC_CONTROL) & DPFC_CTL_EN;
 }
 
+static void i8xx_fbc_recompress(struct drm_i915_private *dev_priv)
+{
+	struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
+	enum i9xx_plane_id i9xx_plane = params->crtc.i9xx_plane;
+
+	spin_lock_irq(&dev_priv->uncore.lock);
+	intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane),
+			  intel_de_read_fw(dev_priv, DSPADDR(i9xx_plane)));
+	spin_unlock_irq(&dev_priv->uncore.lock);
+}
+
+static void i965_fbc_recompress(struct drm_i915_private *dev_priv)
+{
+	struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
+	enum i9xx_plane_id i9xx_plane = params->crtc.i9xx_plane;
+
+	spin_lock_irq(&dev_priv->uncore.lock);
+	intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
+			  intel_de_read_fw(dev_priv, DSPSURF(i9xx_plane)));
+	spin_unlock_irq(&dev_priv->uncore.lock);
+}
+
 /* This function forces a CFB recompression through the nuke operation. */
-static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
+static void snb_fbc_recompress(struct drm_i915_private *dev_priv)
 {
 	struct intel_fbc *fbc = &dev_priv->fbc;
 
@@ -198,6 +220,16 @@ static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
 	intel_de_posting_read(dev_priv, MSG_FBC_REND_STATE);
 }
 
+static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
+{
+	if (INTEL_GEN(dev_priv) >= 6)
+		snb_fbc_recompress(dev_priv);
+	else if (INTEL_GEN(dev_priv) >= 4)
+		i965_fbc_recompress(dev_priv);
+	else
+		i8xx_fbc_recompress(dev_priv);
+}
+
 static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
 {
 	struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
-- 
2.26.2

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[Intel-gfx] [PATCH 3/4] drm/i915/fbc: Enable fbc on i865

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Unlike all the other pre-snb desktop platforms i865 actually
supports FBC. Let's enable it.

Quote from the spec:
"DevSDG provides the same Run-Length Encoded Frame Buffer
 Compression (RLEFBC) function as exists in DevMGM."

As i865 only has the one pipe we want to skip massaging the
plane<->pipe assignment aimed at getting FBC+LVDS working on
the mobile platforms.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
 drivers/gpu/drm/i915/i915_pci.c              | 1 +
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 84e2a17b5ecb..653f6617d59a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -16332,7 +16332,8 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
 	 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
 	 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
 	 */
-	if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
+	if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4 &&
+	    INTEL_NUM_PIPES(dev_priv) == 2)
 		plane->i9xx_plane = (enum i9xx_plane_id) !pipe;
 	else
 		plane->i9xx_plane = (enum i9xx_plane_id) pipe;
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index e5fdf17cd9cd..0be3b66ce666 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -217,6 +217,7 @@ static const struct intel_device_info i85x_info = {
 static const struct intel_device_info i865g_info = {
 	I845_FEATURES,
 	PLATFORM(INTEL_I865G),
+	.display.has_fbc = 1,
 };
 
 #define GEN3_FEATURES \
-- 
2.26.2

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[Intel-gfx] [PATCH 4/4] drm/i915/fbc: Allow FBC to recompress after a 3D workload on i85x/i865

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Normally i85x/i865 3D activity will block FBC until a 2D blit
occurs. I suppose this was meant to avoid recompression while
3D activity is still going on but the frame hasn't yet been
presented. Unfortunately that also means that a page flipped
3D workload will permanently block FBC even if it only renders
a single frame and then does nothing.

Since we are using software render tracking anyway we might as
well flip the chicken bit so that 3D does not block FBC. This
will avoid the permament FBC blockage in the aforemention use
case, but thanks to the software tracking the compressor will
not disturb 3D rendering activity.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |  1 +
 drivers/gpu/drm/i915/intel_pm.c | 10 ++++++++++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9d6536afc94b..03590d2d75f7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2827,6 +2827,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define VLV_GU_CTL0	_MMIO(VLV_DISPLAY_BASE + 0x2030)
 #define VLV_GU_CTL1	_MMIO(VLV_DISPLAY_BASE + 0x2034)
 #define SCPD0		_MMIO(0x209c) /* 915+ only */
+#define  SCPD_FBC_IGNORE_3D			(1 << 6)
 #define  CSTATE_RENDER_CLOCK_GATE_DISABLE	(1 << 5)
 #define GEN2_IER	_MMIO(0x20a0)
 #define GEN2_IIR	_MMIO(0x20a4)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 565a2b9da3b3..2d980b83a1f1 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7471,6 +7471,16 @@ static void i85x_init_clock_gating(struct drm_i915_private *dev_priv)
 
 	I915_WRITE(MEM_MODE,
 		   _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
+
+	/*
+	 * Have FBC ignore 3D activity since we use software
+	 * render tracking, and otherwise a pure 3D workload
+	 * (even if it just renders a single frame and then does
+	 * abosultely nothing) would not allow FBC to recompress
+	 * until a 2D blit occurs.
+	 */
+	I915_WRITE(SCPD0,
+		   _MASKED_BIT_ENABLE(SCPD_FBC_IGNORE_3D));
 }
 
 static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
-- 
2.26.2

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: FBC fixes (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: FBC fixes (rev3)
URL   : https://patchwork.freedesktop.org/series/76714/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_8697 -> Patchwork_18070
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/index.html

Known issues
------------

  Here are the changes found in Patchwork_18070 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_cursor_legacy@basic-flip-before-cursor-legacy:
    - fi-bsw-kefka:       [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/fi-bsw-kefka/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/fi-bsw-kefka/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html

  
#### Possible fixes ####

  * igt@i915_pm_backlight@basic-brightness:
    - fi-whl-u:           [DMESG-WARN][3] ([i915#95]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/fi-whl-u/igt@i915_pm_backlight@basic-brightness.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/fi-whl-u/igt@i915_pm_backlight@basic-brightness.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - fi-bsw-kefka:       [DMESG-WARN][5] ([i915#1982]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html

  * igt@i915_selftest@live@execlists:
    - fi-kbl-guc:         [INCOMPLETE][7] ([i915#794]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/fi-kbl-guc/igt@i915_selftest@live@execlists.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/fi-kbl-guc/igt@i915_selftest@live@execlists.html

  * igt@i915_selftest@live@gt_pm:
    - fi-icl-y:           [DMESG-FAIL][9] ([i915#2111]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/fi-icl-y/igt@i915_selftest@live@gt_pm.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/fi-icl-y/igt@i915_selftest@live@gt_pm.html

  * igt@kms_busy@basic@flip:
    - fi-kbl-x1275:       [DMESG-WARN][11] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/fi-kbl-x1275/igt@kms_busy@basic@flip.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/fi-kbl-x1275/igt@kms_busy@basic@flip.html

  * igt@prime_self_import@basic-with_two_bos:
    - fi-tgl-u2:          [DMESG-WARN][13] -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/fi-tgl-u2/igt@prime_self_import@basic-with_two_bos.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/fi-tgl-u2/igt@prime_self_import@basic-with_two_bos.html

  
#### Warnings ####

  * igt@i915_pm_rpm@module-reload:
    - fi-kbl-x1275:       [DMESG-FAIL][15] ([i915#62]) -> [SKIP][16] ([fdo#109271])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html

  * igt@kms_force_connector_basic@force-connector-state:
    - fi-kbl-x1275:       [DMESG-WARN][17] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][18] ([i915#62] / [i915#92]) +2 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/fi-kbl-x1275/igt@kms_force_connector_basic@force-connector-state.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/fi-kbl-x1275/igt@kms_force_connector_basic@force-connector-state.html

  * igt@kms_force_connector_basic@prune-stale-modes:
    - fi-kbl-x1275:       [DMESG-WARN][19] ([i915#62] / [i915#92]) -> [DMESG-WARN][20] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/fi-kbl-x1275/igt@kms_force_connector_basic@prune-stale-modes.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/fi-kbl-x1275/igt@kms_force_connector_basic@prune-stale-modes.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2111]: https://gitlab.freedesktop.org/drm/intel/issues/2111
  [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
  [i915#794]: https://gitlab.freedesktop.org/drm/intel/issues/794
  [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95


Participating hosts (43 -> 37)
------------------------------

  Missing    (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_8697 -> Patchwork_18070

  CI-20190529: 20190529
  CI_DRM_8697: a9230e22c3c6a16047315beb00f49eef2e74ea0a @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5720: f35053d4b6d7bbcf6505ef67a8bd56acc7fb2eb2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_18070: 67bae0ce0e61122de7a83926ba23904dcb83c299 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

67bae0ce0e61 drm/i915/fbc: Allow FBC to recompress after a 3D workload on i85x/i865
31b1798fab67 drm/i915/fbc: Enable fbc on i865
23c980e79610 drm/i915/fbc: Fix nuke for pre-snb platforms
4d8cdd9354e7 drm/i915/fbc: Use the correct plane stride

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/index.html
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: FBC fixes (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: FBC fixes (rev3)
URL   : https://patchwork.freedesktop.org/series/76714/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_8697_full -> Patchwork_18070_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_18070_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_eio@in-flight-suspend:
    - shard-kbl:          [PASS][1] -> [DMESG-WARN][2] ([i915#180])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/shard-kbl6/igt@gem_eio@in-flight-suspend.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/shard-kbl6/igt@gem_eio@in-flight-suspend.html

  * igt@gem_exec_reloc@basic-concurrent0:
    - shard-glk:          [PASS][3] -> [FAIL][4] ([i915#1930])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/shard-glk6/igt@gem_exec_reloc@basic-concurrent0.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/shard-glk1/igt@gem_exec_reloc@basic-concurrent0.html

  * igt@gem_exec_whisper@basic-contexts-forked-all:
    - shard-snb:          [PASS][5] -> [INCOMPLETE][6] ([i915#82])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/shard-snb5/igt@gem_exec_whisper@basic-contexts-forked-all.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/shard-snb2/igt@gem_exec_whisper@basic-contexts-forked-all.html

  * igt@gem_exec_whisper@basic-forked-all:
    - shard-glk:          [PASS][7] -> [DMESG-WARN][8] ([i915#118] / [i915#95])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/shard-glk6/igt@gem_exec_whisper@basic-forked-all.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/shard-glk1/igt@gem_exec_whisper@basic-forked-all.html

  * igt@i915_pm_rc6_residency@rc6-fence:
    - shard-hsw:          [PASS][9] -> [WARN][10] ([i915#1519])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/shard-hsw2/igt@i915_pm_rc6_residency@rc6-fence.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/shard-hsw1/igt@i915_pm_rc6_residency@rc6-fence.html

  * igt@i915_pm_rc6_residency@rc6-idle:
    - shard-iclb:         [PASS][11] -> [FAIL][12] ([i915#1515])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/shard-iclb4/igt@i915_pm_rc6_residency@rc6-idle.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/shard-iclb5/igt@i915_pm_rc6_residency@rc6-idle.html

  * igt@i915_selftest@mock@requests:
    - shard-tglb:         [PASS][13] -> [INCOMPLETE][14] ([i915#2110])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/shard-tglb6/igt@i915_selftest@mock@requests.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/shard-tglb3/igt@i915_selftest@mock@requests.html

  * igt@kms_big_fb@linear-64bpp-rotate-0:
    - shard-glk:          [PASS][15] -> [DMESG-FAIL][16] ([i915#118] / [i915#95])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/shard-glk4/igt@kms_big_fb@linear-64bpp-rotate-0.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/shard-glk8/igt@kms_big_fb@linear-64bpp-rotate-0.html

  * igt@kms_cursor_legacy@pipe-a-forked-move:
    - shard-apl:          [PASS][17] -> [DMESG-WARN][18] ([i915#1635] / [i915#95]) +14 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/shard-apl2/igt@kms_cursor_legacy@pipe-a-forked-move.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/shard-apl1/igt@kms_cursor_legacy@pipe-a-forked-move.html

  * igt@kms_flip@flip-vs-wf_vblank-interruptible@a-dp1:
    - shard-kbl:          [PASS][19] -> [DMESG-WARN][20] ([i915#1982])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/shard-kbl6/igt@kms_flip@flip-vs-wf_vblank-interruptible@a-dp1.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/shard-kbl6/igt@kms_flip@flip-vs-wf_vblank-interruptible@a-dp1.html

  * igt@kms_flip@flip-vs-wf_vblank-interruptible@a-edp1:
    - shard-tglb:         [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) +2 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/shard-tglb8/igt@kms_flip@flip-vs-wf_vblank-interruptible@a-edp1.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/shard-tglb7/igt@kms_flip@flip-vs-wf_vblank-interruptible@a-edp1.html

  * igt@kms_plane@plane-panning-bottom-right-pipe-b-planes:
    - shard-skl:          [PASS][23] -> [DMESG-WARN][24] ([i915#1982]) +9 similar issues
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/shard-skl9/igt@kms_plane@plane-panning-bottom-right-pipe-b-planes.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/shard-skl3/igt@kms_plane@plane-panning-bottom-right-pipe-b-planes.html

  * igt@kms_plane_cursor@pipe-a-viewport-size-256:
    - shard-glk:          [PASS][25] -> [FAIL][26] ([i915#1559])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/shard-glk7/igt@kms_plane_cursor@pipe-a-viewport-size-256.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/shard-glk4/igt@kms_plane_cursor@pipe-a-viewport-size-256.html

  * igt@kms_psr@psr2_cursor_render:
    - shard-iclb:         [PASS][27] -> [SKIP][28] ([fdo#109441])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/shard-iclb6/igt@kms_psr@psr2_cursor_render.html

  * igt@kms_pwrite_crc:
    - shard-kbl:          [PASS][29] -> [DMESG-WARN][30] ([i915#93] / [i915#95]) +1 similar issue
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/shard-kbl6/igt@kms_pwrite_crc.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/shard-kbl6/igt@kms_pwrite_crc.html

  * igt@kms_vblank@pipe-c-ts-continuation-suspend:
    - shard-kbl:          [PASS][31] -> [INCOMPLETE][32] ([i915#155] / [i915#794])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/shard-kbl7/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/shard-kbl2/igt@kms_vblank@pipe-c-ts-continuation-suspend.html

  * igt@sw_sync@timeline_closed_signaled:
    - shard-tglb:         [PASS][33] -> [DMESG-WARN][34] ([i915#402])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/shard-tglb8/igt@sw_sync@timeline_closed_signaled.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/shard-tglb7/igt@sw_sync@timeline_closed_signaled.html

  
#### Possible fixes ####

  * igt@gem_ctx_persistence@engines-mixed-process@vcs0:
    - shard-tglb:         [FAIL][35] ([i915#1528]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/shard-tglb7/igt@gem_ctx_persistence@engines-mixed-process@vcs0.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/shard-tglb5/igt@gem_ctx_persistence@engines-mixed-process@vcs0.html

  * igt@gem_ctx_shared@q-independent@vecs0:
    - shard-iclb:         [DMESG-WARN][37] ([i915#1226]) -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/shard-iclb2/igt@gem_ctx_shared@q-independent@vecs0.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/shard-iclb6/igt@gem_ctx_shared@q-independent@vecs0.html

  * igt@i915_module_load@reload:
    - shard-tglb:         [DMESG-WARN][39] ([i915#402]) -> [PASS][40] +1 similar issue
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/shard-tglb8/igt@i915_module_load@reload.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/shard-tglb7/igt@i915_module_load@reload.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-iclb:         [INCOMPLETE][41] ([i915#926]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/shard-iclb2/igt@i915_module_load@reload-with-fault-injection.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/shard-iclb6/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pm_rpm@system-suspend-modeset:
    - shard-skl:          [INCOMPLETE][43] ([i915#151] / [i915#69]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/shard-skl5/igt@i915_pm_rpm@system-suspend-modeset.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/shard-skl1/igt@i915_pm_rpm@system-suspend-modeset.html

  * igt@i915_selftest@mock@requests:
    - shard-skl:          [INCOMPLETE][45] ([i915#198] / [i915#2110]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/shard-skl6/igt@i915_selftest@mock@requests.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/shard-skl4/igt@i915_selftest@mock@requests.html

  * igt@kms_big_fb@x-tiled-64bpp-rotate-0:
    - shard-glk:          [DMESG-FAIL][47] ([i915#118] / [i915#95]) -> [PASS][48] +1 similar issue
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/shard-glk8/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/shard-glk3/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html

  * igt@kms_big_fb@y-tiled-64bpp-rotate-180:
    - shard-apl:          [DMESG-WARN][49] ([i915#1982]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/shard-apl6/igt@kms_big_fb@y-tiled-64bpp-rotate-180.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/shard-apl1/igt@kms_big_fb@y-tiled-64bpp-rotate-180.html

  * igt@kms_ccs@pipe-a-bad-pixel-format:
    - shard-apl:          [DMESG-WARN][51] ([i915#1635] / [i915#95]) -> [PASS][52] +17 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/shard-apl6/igt@kms_ccs@pipe-a-bad-pixel-format.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/shard-apl1/igt@kms_ccs@pipe-a-bad-pixel-format.html

  * igt@kms_color@pipe-c-ctm-green-to-red:
    - shard-skl:          [DMESG-WARN][53] ([i915#1982]) -> [PASS][54] +6 similar issues
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/shard-skl7/igt@kms_color@pipe-c-ctm-green-to-red.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/shard-skl10/igt@kms_color@pipe-c-ctm-green-to-red.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-skl:          [FAIL][55] ([IGT#5]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
    - shard-kbl:          [DMESG-WARN][57] ([i915#180]) -> [PASS][58] +5 similar issues
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render:
    - shard-snb:          [TIMEOUT][59] ([i915#1958] / [i915#2119]) -> [PASS][60] +3 similar issues
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/shard-snb4/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/shard-snb4/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-skl:          [FAIL][61] ([i915#1188]) -> [PASS][62] +1 similar issue
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/shard-skl5/igt@kms_hdr@bpc-switch-dpms.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/shard-skl9/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [FAIL][63] ([fdo#108145] / [i915#265]) -> [PASS][64] +2 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_psr@psr2_cursor_plane_move:
    - shard-iclb:         [SKIP][65] ([fdo#109441]) -> [PASS][66] +1 similar issue
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/shard-iclb1/igt@kms_psr@psr2_cursor_plane_move.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html

  * igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend:
    - shard-skl:          [INCOMPLETE][67] ([i915#69]) -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/shard-skl7/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/shard-skl2/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html

  
#### Warnings ####

  * igt@gem_exec_reloc@basic-concurrent16:
    - shard-snb:          [TIMEOUT][69] ([i915#1958] / [i915#2119]) -> [FAIL][70] ([i915#1930])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/shard-snb4/igt@gem_exec_reloc@basic-concurrent16.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/shard-snb4/igt@gem_exec_reloc@basic-concurrent16.html

  * igt@gem_exec_reloc@basic-spin-others@vcs0:
    - shard-snb:          [WARN][71] ([i915#2036]) -> [WARN][72] ([i915#2021])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/shard-snb1/igt@gem_exec_reloc@basic-spin-others@vcs0.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/shard-snb4/igt@gem_exec_reloc@basic-spin-others@vcs0.html

  * igt@kms_color@pipe-a-ctm-0-75:
    - shard-tglb:         [FAIL][73] ([i915#1149] / [i915#315]) -> [DMESG-FAIL][74] ([i915#1149] / [i915#402])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/shard-tglb7/igt@kms_color@pipe-a-ctm-0-75.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/shard-tglb5/igt@kms_color@pipe-a-ctm-0-75.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-kbl:          [TIMEOUT][75] ([i915#1319] / [i915#1958] / [i915#2119]) -> [TIMEOUT][76] ([i915#1319] / [i915#2119])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/shard-kbl6/igt@kms_content_protection@atomic-dpms.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/shard-kbl1/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_cursor_crc@pipe-d-cursor-512x512-random:
    - shard-apl:          [SKIP][77] ([fdo#109271]) -> [SKIP][78] ([fdo#109271] / [i915#1635]) +9 similar issues
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/shard-apl2/igt@kms_cursor_crc@pipe-d-cursor-512x512-random.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/shard-apl1/igt@kms_cursor_crc@pipe-d-cursor-512x512-random.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-wc:
    - shard-apl:          [SKIP][79] ([fdo#109271] / [i915#1635]) -> [SKIP][80] ([fdo#109271]) +3 similar issues
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/shard-apl6/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-wc.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/shard-apl8/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-wc.html

  * igt@kms_plane_lowres@pipe-b-tiling-y:
    - shard-snb:          [TIMEOUT][81] ([i915#1958] / [i915#2119]) -> [SKIP][82] ([fdo#109271]) +1 similar issue
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/shard-snb4/igt@kms_plane_lowres@pipe-b-tiling-y.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/shard-snb4/igt@kms_plane_lowres@pipe-b-tiling-y.html

  * igt@runner@aborted:
    - shard-apl:          ([FAIL][83], [FAIL][84], [FAIL][85]) ([i915#1610] / [i915#1635] / [i915#2110]) -> [FAIL][86] ([i915#1635] / [i915#2110])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/shard-apl4/igt@runner@aborted.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/shard-apl1/igt@runner@aborted.html
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/shard-apl4/igt@runner@aborted.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/shard-apl1/igt@runner@aborted.html
    - shard-tglb:         [FAIL][87] ([i915#2110]) -> [FAIL][88] ([i915#1764] / [i915#2110])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8697/shard-tglb6/igt@runner@aborted.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/shard-tglb3/igt@runner@aborted.html

  
  [IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149
  [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
  [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
  [i915#1226]: https://gitlab.freedesktop.org/drm/intel/issues/1226
  [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
  [i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151
  [i915#1515]: https://gitlab.freedesktop.org/drm/intel/issues/1515
  [i915#1519]: https://gitlab.freedesktop.org/drm/intel/issues/1519
  [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528
  [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
  [i915#1559]: https://gitlab.freedesktop.org/drm/intel/issues/1559
  [i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610
  [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
  [i915#1764]: https://gitlab.freedesktop.org/drm/intel/issues/1764
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930
  [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958
  [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2021]: https://gitlab.freedesktop.org/drm/intel/issues/2021
  [i915#2036]: https://gitlab.freedesktop.org/drm/intel/issues/2036
  [i915#2110]: https://gitlab.freedesktop.org/drm/intel/issues/2110
  [i915#2119]: https://gitlab.freedesktop.org/drm/intel/issues/2119
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
  [i915#794]: https://gitlab.freedesktop.org/drm/intel/issues/794
  [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
  [i915#926]: https://gitlab.freedesktop.org/drm/intel/issues/926
  [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_8697 -> Patchwork_18070

  CI-20190529: 20190529
  CI_DRM_8697: a9230e22c3c6a16047315beb00f49eef2e74ea0a @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5720: f35053d4b6d7bbcf6505ef67a8bd56acc7fb2eb2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_18070: 67bae0ce0e61122de7a83926ba23904dcb83c299 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18070/index.html
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Re: [Intel-gfx] [PATCH 3/4] drm/i915/fbc: Enable fbc on i865

[Souza, Jose]

On Thu, 2020-07-02 at 18:37 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Unlike all the other pre-snb desktop platforms i865 actually
> supports FBC. Let's enable it.
> 
> Quote from the spec:
> "DevSDG provides the same Run-Length Encoded Frame Buffer
>  Compression (RLEFBC) function as exists in DevMGM."
> 
> As i865 only has the one pipe we want to skip massaging the
> plane<->pipe assignment aimed at getting FBC+LVDS working on
> the mobile platforms.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
>  drivers/gpu/drm/i915/i915_pci.c              | 1 +
>  2 files changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 84e2a17b5ecb..653f6617d59a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -16332,7 +16332,8 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
>  	 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
>  	 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
>  	 */
> -	if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
> +	if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4 &&
> +	    INTEL_NUM_PIPES(dev_priv) == 2)
>  		plane->i9xx_plane = (enum i9xx_plane_id) !pipe;
>  	else
>  		plane->i9xx_plane = (enum i9xx_plane_id) pipe;
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index e5fdf17cd9cd..0be3b66ce666 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -217,6 +217,7 @@ static const struct intel_device_info i85x_info = {
>  static const struct intel_device_info i865g_info = {
>  	I845_FEATURES,
>  	PLATFORM(INTEL_I865G),
> +	.display.has_fbc = 1,
>  };
>  
>  #define GEN3_FEATURES \
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Re: [Intel-gfx] [PATCH 4/4] drm/i915/fbc: Allow FBC to recompress after a 3D workload on i85x/i865

[Souza, Jose]

On Thu, 2020-07-02 at 18:37 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Normally i85x/i865 3D activity will block FBC until a 2D blit
> occurs. I suppose this was meant to avoid recompression while
> 3D activity is still going on but the frame hasn't yet been
> presented. Unfortunately that also means that a page flipped
> 3D workload will permanently block FBC even if it only renders
> a single frame and then does nothing.
> 
> Since we are using software render tracking anyway we might as
> well flip the chicken bit so that 3D does not block FBC. This
> will avoid the permament FBC blockage in the aforemention use
> case, but thanks to the software tracking the compressor will
> not disturb 3D rendering activity.

Register does what is described.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |  1 +
>  drivers/gpu/drm/i915/intel_pm.c | 10 ++++++++++
>  2 files changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9d6536afc94b..03590d2d75f7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2827,6 +2827,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define VLV_GU_CTL0	_MMIO(VLV_DISPLAY_BASE + 0x2030)
>  #define VLV_GU_CTL1	_MMIO(VLV_DISPLAY_BASE + 0x2034)
>  #define SCPD0		_MMIO(0x209c) /* 915+ only */
> +#define  SCPD_FBC_IGNORE_3D			(1 << 6)
>  #define  CSTATE_RENDER_CLOCK_GATE_DISABLE	(1 << 5)
>  #define GEN2_IER	_MMIO(0x20a0)
>  #define GEN2_IIR	_MMIO(0x20a4)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 565a2b9da3b3..2d980b83a1f1 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7471,6 +7471,16 @@ static void i85x_init_clock_gating(struct drm_i915_private *dev_priv)
>  
>  	I915_WRITE(MEM_MODE,
>  		   _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
> +
> +	/*
> +	 * Have FBC ignore 3D activity since we use software
> +	 * render tracking, and otherwise a pure 3D workload
> +	 * (even if it just renders a single frame and then does
> +	 * abosultely nothing) would not allow FBC to recompress
> +	 * until a 2D blit occurs.
> +	 */
> +	I915_WRITE(SCPD0,
> +		   _MASKED_BIT_ENABLE(SCPD_FBC_IGNORE_3D));
>  }
>  
>  static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
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Re: [Intel-gfx] [PATCH 2/4] drm/i915/fbc: Fix nuke for pre-snb platforms

[Souza, Jose]

On Thu, 2020-07-02 at 18:37 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The MSG_FBC_REND_STATE register only exists on snb+. For older
> platforms (would also work for snb+) we can simply rewite DSPSURF
> to trigger a flip nuke.
> 
> While generally RMW is considered harmful we'll use it here for
> simplicity. And since FBC doesn't exist in i830 we don't have to
> worry about the DSPSURF double buffering hardware fails present
> on that platform.

Did not found a explicit statement about writing DSPSURF will nuke compressed buffer but that makes sense, also checked that MSG_FBC_REND_STATE do not
exist this older platforms.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_fbc.c | 34 +++++++++++++++++++++++-
>  1 file changed, 33 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index d30c2a389294..036546ce8db8 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -187,8 +187,30 @@ static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv)
>  	return intel_de_read(dev_priv, DPFC_CONTROL) & DPFC_CTL_EN;
>  }
>  
> +static void i8xx_fbc_recompress(struct drm_i915_private *dev_priv)
> +{
> +	struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
> +	enum i9xx_plane_id i9xx_plane = params->crtc.i9xx_plane;
> +
> +	spin_lock_irq(&dev_priv->uncore.lock);
> +	intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane),
> +			  intel_de_read_fw(dev_priv, DSPADDR(i9xx_plane)));
> +	spin_unlock_irq(&dev_priv->uncore.lock);
> +}
> +
> +static void i965_fbc_recompress(struct drm_i915_private *dev_priv)
> +{
> +	struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
> +	enum i9xx_plane_id i9xx_plane = params->crtc.i9xx_plane;
> +
> +	spin_lock_irq(&dev_priv->uncore.lock);
> +	intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
> +			  intel_de_read_fw(dev_priv, DSPSURF(i9xx_plane)));
> +	spin_unlock_irq(&dev_priv->uncore.lock);
> +}
> +
>  /* This function forces a CFB recompression through the nuke operation. */
> -static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
> +static void snb_fbc_recompress(struct drm_i915_private *dev_priv)
>  {
>  	struct intel_fbc *fbc = &dev_priv->fbc;
>  
> @@ -198,6 +220,16 @@ static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
>  	intel_de_posting_read(dev_priv, MSG_FBC_REND_STATE);
>  }
>  
> +static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
> +{
> +	if (INTEL_GEN(dev_priv) >= 6)
> +		snb_fbc_recompress(dev_priv);
> +	else if (INTEL_GEN(dev_priv) >= 4)
> +		i965_fbc_recompress(dev_priv);
> +	else
> +		i8xx_fbc_recompress(dev_priv);
> +}
> +
>  static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
>  {
>  	struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
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Re: [Intel-gfx] [PATCH 1/4] drm/i915/fbc: Use the correct plane stride

[Souza, Jose]

On Thu, 2020-07-02 at 18:37 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Consult the actual plane stride instead of the fb stride. The two
> will disagree when we remap the gtt. The plane stride is what the
> hw will be fed so that's what we should look at for the FBC
> retrictions/cfb allocation.
> 
> Since we no longer require a fence we are going to attempt using
> FBC with remapping, and so we should look at correct stride.
> 
> With 90/270 degree rotation the plane stride is stored in units
> of pixels, so we need to conver it to bytes for the purposes
> of calculating the cfb stride. Not entirely sure if this matches
> the hw behaviour though. Need to reverse engineer that at some
> point...
> 
> We also need to reorder the pixel format check vs. stride check
> to avoid triggering a spurious WARN(stride & 63) with cpp==1 and
> plane stride==32.
> 
> v2: Try to deal with rotated stride and related WARN
> 

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> Cc: José Roberto de Souza <jose.souza@intel.com>
> Fixes: 691f7ba58d52 ("drm/i915/display/fbc: Make fences a nice-to-have for GEN9+")
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_fbc.c | 16 ++++++++++------
>  1 file changed, 10 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 69a0682ddb6a..d30c2a389294 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -695,9 +695,13 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
>  	cache->plane.pixel_blend_mode = plane_state->hw.pixel_blend_mode;
>  
>  	cache->fb.format = fb->format;
> -	cache->fb.stride = fb->pitches[0];
>  	cache->fb.modifier = fb->modifier;
>  
> +	/* FIXME is this correct? */
> +	cache->fb.stride = plane_state->color_plane[0].stride;
> +	if (drm_rotation_90_or_270(plane_state->hw.rotation))

If it was wrong our CI would caught this in BDW or SNB for example.

> +		cache->fb.stride *= fb->format->cpp[0];
> +
>  	/* FBC1 compression interval: arbitrary choice of 1 second */
>  	cache->interval = drm_mode_vrefresh(&crtc_state->hw.adjusted_mode);
>  
> @@ -797,6 +801,11 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
>  		return false;
>  	}
>  
> +	if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) {
> +		fbc->no_fbc_reason = "pixel format is invalid";
> +		return false;
> +	}
> +
>  	if (!rotation_is_valid(dev_priv, cache->fb.format->format,
>  			       cache->plane.rotation)) {
>  		fbc->no_fbc_reason = "rotation unsupported";
> @@ -813,11 +822,6 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
>  		return false;
>  	}
>  
> -	if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) {
> -		fbc->no_fbc_reason = "pixel format is invalid";
> -		return false;
> -	}
> -
>  	if (cache->plane.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE &&
>  	    cache->fb.format->has_alpha) {
>  		fbc->no_fbc_reason = "per-pixel alpha blending is incompatible with FBC";
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Re: [Intel-gfx] [PATCH 1/4] drm/i915/fbc: Use the correct plane stride

[Ville Syrjälä]

On Thu, Jul 02, 2020 at 11:24:04PM +0000, Souza, Jose wrote:
> On Thu, 2020-07-02 at 18:37 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Consult the actual plane stride instead of the fb stride. The two
> > will disagree when we remap the gtt. The plane stride is what the
> > hw will be fed so that's what we should look at for the FBC
> > retrictions/cfb allocation.
> > 
> > Since we no longer require a fence we are going to attempt using
> > FBC with remapping, and so we should look at correct stride.
> > 
> > With 90/270 degree rotation the plane stride is stored in units
> > of pixels, so we need to conver it to bytes for the purposes
> > of calculating the cfb stride. Not entirely sure if this matches
> > the hw behaviour though. Need to reverse engineer that at some
> > point...
> > 
> > We also need to reorder the pixel format check vs. stride check
> > to avoid triggering a spurious WARN(stride & 63) with cpp==1 and
> > plane stride==32.
> > 
> > v2: Try to deal with rotated stride and related WARN
> > 
> 
> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> 
> > Cc: José Roberto de Souza <jose.souza@intel.com>
> > Fixes: 691f7ba58d52 ("drm/i915/display/fbc: Make fences a nice-to-have for GEN9+")
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_fbc.c | 16 ++++++++++------
> >  1 file changed, 10 insertions(+), 6 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index 69a0682ddb6a..d30c2a389294 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -695,9 +695,13 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
> >  	cache->plane.pixel_blend_mode = plane_state->hw.pixel_blend_mode;
> >  
> >  	cache->fb.format = fb->format;
> > -	cache->fb.stride = fb->pitches[0];
> >  	cache->fb.modifier = fb->modifier;
> >  
> > +	/* FIXME is this correct? */
> > +	cache->fb.stride = plane_state->color_plane[0].stride;
> > +	if (drm_rotation_90_or_270(plane_state->hw.rotation))
> 
> If it was wrong our CI would caught this in BDW or SNB for example.

Not really. Well, certainly not on pre-skl since they don't do 90/270
rotation. And probably not even on skl+ since any wrong assumption
about how the cfb stride is calculated by the hw would just cause it
to scribble over stolen memory we didn't allocate. So unless we've
started to use stolen more extensively in recent times such problems
would probably go unnoticed.

> 
> > +		cache->fb.stride *= fb->format->cpp[0];
> > +
> >  	/* FBC1 compression interval: arbitrary choice of 1 second */
> >  	cache->interval = drm_mode_vrefresh(&crtc_state->hw.adjusted_mode);
> >  
> > @@ -797,6 +801,11 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
> >  		return false;
> >  	}
> >  
> > +	if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) {
> > +		fbc->no_fbc_reason = "pixel format is invalid";
> > +		return false;
> > +	}
> > +
> >  	if (!rotation_is_valid(dev_priv, cache->fb.format->format,
> >  			       cache->plane.rotation)) {
> >  		fbc->no_fbc_reason = "rotation unsupported";
> > @@ -813,11 +822,6 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
> >  		return false;
> >  	}
> >  
> > -	if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) {
> > -		fbc->no_fbc_reason = "pixel format is invalid";
> > -		return false;
> > -	}
> > -
> >  	if (cache->plane.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE &&
> >  	    cache->fb.format->has_alpha) {
> >  		fbc->no_fbc_reason = "per-pixel alpha blending is incompatible with FBC";

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH 2/4] drm/i915/fbc: Fix nuke for pre-snb platforms

[Ville Syrjälä]

On Thu, Jul 02, 2020 at 11:02:05PM +0000, Souza, Jose wrote:
> On Thu, 2020-07-02 at 18:37 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > The MSG_FBC_REND_STATE register only exists on snb+. For older
> > platforms (would also work for snb+) we can simply rewite DSPSURF
> > to trigger a flip nuke.
> > 
> > While generally RMW is considered harmful we'll use it here for
> > simplicity. And since FBC doesn't exist in i830 we don't have to
> > worry about the DSPSURF double buffering hardware fails present
> > on that platform.
> 
> Did not found a explicit statement about writing DSPSURF will nuke compressed buffer but that makes sense,

Flip nuke is certainly a thing, but flipping to the same address I think
might be somewhat undefined. IIRC I did test this however and it worked
just fine.

> also checked that MSG_FBC_REND_STATE do not
> exist this older platforms.
> 
> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> 
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_fbc.c | 34 +++++++++++++++++++++++-
> >  1 file changed, 33 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index d30c2a389294..036546ce8db8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -187,8 +187,30 @@ static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv)
> >  	return intel_de_read(dev_priv, DPFC_CONTROL) & DPFC_CTL_EN;
> >  }
> >  
> > +static void i8xx_fbc_recompress(struct drm_i915_private *dev_priv)
> > +{
> > +	struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
> > +	enum i9xx_plane_id i9xx_plane = params->crtc.i9xx_plane;
> > +
> > +	spin_lock_irq(&dev_priv->uncore.lock);
> > +	intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane),
> > +			  intel_de_read_fw(dev_priv, DSPADDR(i9xx_plane)));
> > +	spin_unlock_irq(&dev_priv->uncore.lock);
> > +}
> > +
> > +static void i965_fbc_recompress(struct drm_i915_private *dev_priv)
> > +{
> > +	struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
> > +	enum i9xx_plane_id i9xx_plane = params->crtc.i9xx_plane;
> > +
> > +	spin_lock_irq(&dev_priv->uncore.lock);
> > +	intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
> > +			  intel_de_read_fw(dev_priv, DSPSURF(i9xx_plane)));
> > +	spin_unlock_irq(&dev_priv->uncore.lock);
> > +}
> > +
> >  /* This function forces a CFB recompression through the nuke operation. */
> > -static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
> > +static void snb_fbc_recompress(struct drm_i915_private *dev_priv)
> >  {
> >  	struct intel_fbc *fbc = &dev_priv->fbc;
> >  
> > @@ -198,6 +220,16 @@ static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
> >  	intel_de_posting_read(dev_priv, MSG_FBC_REND_STATE);
> >  }
> >  
> > +static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
> > +{
> > +	if (INTEL_GEN(dev_priv) >= 6)
> > +		snb_fbc_recompress(dev_priv);
> > +	else if (INTEL_GEN(dev_priv) >= 4)
> > +		i965_fbc_recompress(dev_priv);
> > +	else
> > +		i8xx_fbc_recompress(dev_priv);
> > +}
> > +
> >  static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
> >  {
> >  	struct intel_fbc_reg_params *params = &dev_priv->fbc.params;

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH 1/4] drm/i915/fbc: Use the correct plane stride

[Souza, Jose]

On Fri, 2020-07-03 at 14:38 +0300, Ville Syrjälä wrote:
> On Thu, Jul 02, 2020 at 11:24:04PM +0000, Souza, Jose wrote:
> > On Thu, 2020-07-02 at 18:37 +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > Consult the actual plane stride instead of the fb stride. The two
> > > will disagree when we remap the gtt. The plane stride is what the
> > > hw will be fed so that's what we should look at for the FBC
> > > retrictions/cfb allocation.
> > > 
> > > Since we no longer require a fence we are going to attempt using
> > > FBC with remapping, and so we should look at correct stride.
> > > 
> > > With 90/270 degree rotation the plane stride is stored in units
> > > of pixels, so we need to conver it to bytes for the purposes
> > > of calculating the cfb stride. Not entirely sure if this matches
> > > the hw behaviour though. Need to reverse engineer that at some
> > > point...
> > > 
> > > We also need to reorder the pixel format check vs. stride check
> > > to avoid triggering a spurious WARN(stride & 63) with cpp==1 and
> > > plane stride==32.
> > > 
> > > v2: Try to deal with rotated stride and related WARN
> > > 
> > 
> > Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> > 
> > > Cc: José Roberto de Souza <jose.souza@intel.com>
> > > Fixes: 691f7ba58d52 ("drm/i915/display/fbc: Make fences a nice-to-have for GEN9+")
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_fbc.c | 16 ++++++++++------
> > >  1 file changed, 10 insertions(+), 6 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > index 69a0682ddb6a..d30c2a389294 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > @@ -695,9 +695,13 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
> > >  	cache->plane.pixel_blend_mode = plane_state->hw.pixel_blend_mode;
> > >  
> > >  	cache->fb.format = fb->format;
> > > -	cache->fb.stride = fb->pitches[0];
> > >  	cache->fb.modifier = fb->modifier;
> > >  
> > > +	/* FIXME is this correct? */
> > > +	cache->fb.stride = plane_state->color_plane[0].stride;
> > > +	if (drm_rotation_90_or_270(plane_state->hw.rotation))
> > 
> > If it was wrong our CI would caught this in BDW or SNB for example.
> 
> Not really. Well, certainly not on pre-skl since they don't do 90/270
> rotation. And probably not even on skl+ since any wrong assumption

Checking rotation_is_valid() GEN5 up to GEN8 allows 90/270 rotation.


> about how the cfb stride is calculated by the hw would just cause it
> to scribble over stolen memory we didn't allocate. So unless we've
> started to use stolen more extensively in recent times such problems
> would probably go unnoticed.
> 
> > > +		cache->fb.stride *= fb->format->cpp[0];
> > > +
> > >  	/* FBC1 compression interval: arbitrary choice of 1 second */
> > >  	cache->interval = drm_mode_vrefresh(&crtc_state->hw.adjusted_mode);
> > >  
> > > @@ -797,6 +801,11 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
> > >  		return false;
> > >  	}
> > >  
> > > +	if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) {
> > > +		fbc->no_fbc_reason = "pixel format is invalid";
> > > +		return false;
> > > +	}
> > > +
> > >  	if (!rotation_is_valid(dev_priv, cache->fb.format->format,
> > >  			       cache->plane.rotation)) {
> > >  		fbc->no_fbc_reason = "rotation unsupported";
> > > @@ -813,11 +822,6 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
> > >  		return false;
> > >  	}
> > >  
> > > -	if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) {
> > > -		fbc->no_fbc_reason = "pixel format is invalid";
> > > -		return false;
> > > -	}
> > > -
> > >  	if (cache->plane.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE &&
> > >  	    cache->fb.format->has_alpha) {
> > >  		fbc->no_fbc_reason = "per-pixel alpha blending is incompatible with FBC";
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Re: [Intel-gfx] [PATCH 1/4] drm/i915/fbc: Use the correct plane stride

[Rodrigo Vivi]

On Thu, Jul 02, 2020 at 06:37:20PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Consult the actual plane stride instead of the fb stride. The two
> will disagree when we remap the gtt. The plane stride is what the
> hw will be fed so that's what we should look at for the FBC
> retrictions/cfb allocation.
> 
> Since we no longer require a fence we are going to attempt using
> FBC with remapping, and so we should look at correct stride.
> 
> With 90/270 degree rotation the plane stride is stored in units
> of pixels, so we need to conver it to bytes for the purposes
> of calculating the cfb stride. Not entirely sure if this matches
> the hw behaviour though. Need to reverse engineer that at some
> point...
> 
> We also need to reorder the pixel format check vs. stride check
> to avoid triggering a spurious WARN(stride & 63) with cpp==1 and
> plane stride==32.
> 
> v2: Try to deal with rotated stride and related WARN
> 
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Fixes: 691f7ba58d52 ("drm/i915/display/fbc: Make fences a nice-to-have for GEN9+")

This patch didn't apply cleanly on drm-intel-fixes. If it is critical
for 5.8 please consider to provide a backported version.

Thanks,
Rodrigo.

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_fbc.c | 16 ++++++++++------
>  1 file changed, 10 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 69a0682ddb6a..d30c2a389294 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -695,9 +695,13 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
>  	cache->plane.pixel_blend_mode = plane_state->hw.pixel_blend_mode;
>  
>  	cache->fb.format = fb->format;
> -	cache->fb.stride = fb->pitches[0];
>  	cache->fb.modifier = fb->modifier;
>  
> +	/* FIXME is this correct? */
> +	cache->fb.stride = plane_state->color_plane[0].stride;
> +	if (drm_rotation_90_or_270(plane_state->hw.rotation))
> +		cache->fb.stride *= fb->format->cpp[0];
> +
>  	/* FBC1 compression interval: arbitrary choice of 1 second */
>  	cache->interval = drm_mode_vrefresh(&crtc_state->hw.adjusted_mode);
>  
> @@ -797,6 +801,11 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
>  		return false;
>  	}
>  
> +	if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) {
> +		fbc->no_fbc_reason = "pixel format is invalid";
> +		return false;
> +	}
> +
>  	if (!rotation_is_valid(dev_priv, cache->fb.format->format,
>  			       cache->plane.rotation)) {
>  		fbc->no_fbc_reason = "rotation unsupported";
> @@ -813,11 +822,6 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
>  		return false;
>  	}
>  
> -	if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) {
> -		fbc->no_fbc_reason = "pixel format is invalid";
> -		return false;
> -	}
> -
>  	if (cache->plane.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE &&
>  	    cache->fb.format->has_alpha) {
>  		fbc->no_fbc_reason = "per-pixel alpha blending is incompatible with FBC";
> -- 
> 2.26.2
> 
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Re: [Intel-gfx] [PATCH 1/4] drm/i915/fbc: Use the correct plane stride

[Ville Syrjälä]

On Mon, Jul 06, 2020 at 08:53:06PM +0000, Souza, Jose wrote:
> On Fri, 2020-07-03 at 14:38 +0300, Ville Syrjälä wrote:
> > On Thu, Jul 02, 2020 at 11:24:04PM +0000, Souza, Jose wrote:
> > > On Thu, 2020-07-02 at 18:37 +0300, Ville Syrjala wrote:
> > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > 
> > > > Consult the actual plane stride instead of the fb stride. The two
> > > > will disagree when we remap the gtt. The plane stride is what the
> > > > hw will be fed so that's what we should look at for the FBC
> > > > retrictions/cfb allocation.
> > > > 
> > > > Since we no longer require a fence we are going to attempt using
> > > > FBC with remapping, and so we should look at correct stride.
> > > > 
> > > > With 90/270 degree rotation the plane stride is stored in units
> > > > of pixels, so we need to conver it to bytes for the purposes
> > > > of calculating the cfb stride. Not entirely sure if this matches
> > > > the hw behaviour though. Need to reverse engineer that at some
> > > > point...
> > > > 
> > > > We also need to reorder the pixel format check vs. stride check
> > > > to avoid triggering a spurious WARN(stride & 63) with cpp==1 and
> > > > plane stride==32.
> > > > 
> > > > v2: Try to deal with rotated stride and related WARN
> > > > 
> > > 
> > > Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> > > 
> > > > Cc: José Roberto de Souza <jose.souza@intel.com>
> > > > Fixes: 691f7ba58d52 ("drm/i915/display/fbc: Make fences a nice-to-have for GEN9+")
> > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/display/intel_fbc.c | 16 ++++++++++------
> > > >  1 file changed, 10 insertions(+), 6 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > index 69a0682ddb6a..d30c2a389294 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > @@ -695,9 +695,13 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
> > > >  	cache->plane.pixel_blend_mode = plane_state->hw.pixel_blend_mode;
> > > >  
> > > >  	cache->fb.format = fb->format;
> > > > -	cache->fb.stride = fb->pitches[0];
> > > >  	cache->fb.modifier = fb->modifier;
> > > >  
> > > > +	/* FIXME is this correct? */
> > > > +	cache->fb.stride = plane_state->color_plane[0].stride;
> > > > +	if (drm_rotation_90_or_270(plane_state->hw.rotation))
> > > 
> > > If it was wrong our CI would caught this in BDW or SNB for example.
> > 
> > Not really. Well, certainly not on pre-skl since they don't do 90/270
> > rotation. And probably not even on skl+ since any wrong assumption
> 
> Checking rotation_is_valid() GEN5 up to GEN8 allows 90/270 rotation.

The display engine on pre-skl does not support 90/270 rotaiton *at all*.

> 
> 
> > about how the cfb stride is calculated by the hw would just cause it
> > to scribble over stolen memory we didn't allocate. So unless we've
> > started to use stolen more extensively in recent times such problems
> > would probably go unnoticed.
> > 
> > > > +		cache->fb.stride *= fb->format->cpp[0];
> > > > +
> > > >  	/* FBC1 compression interval: arbitrary choice of 1 second */
> > > >  	cache->interval = drm_mode_vrefresh(&crtc_state->hw.adjusted_mode);
> > > >  
> > > > @@ -797,6 +801,11 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
> > > >  		return false;
> > > >  	}
> > > >  
> > > > +	if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) {
> > > > +		fbc->no_fbc_reason = "pixel format is invalid";
> > > > +		return false;
> > > > +	}
> > > > +
> > > >  	if (!rotation_is_valid(dev_priv, cache->fb.format->format,
> > > >  			       cache->plane.rotation)) {
> > > >  		fbc->no_fbc_reason = "rotation unsupported";
> > > > @@ -813,11 +822,6 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
> > > >  		return false;
> > > >  	}
> > > >  
> > > > -	if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) {
> > > > -		fbc->no_fbc_reason = "pixel format is invalid";
> > > > -		return false;
> > > > -	}
> > > > -
> > > >  	if (cache->plane.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE &&
> > > >  	    cache->fb.format->has_alpha) {
> > > >  		fbc->no_fbc_reason = "per-pixel alpha blending is incompatible with FBC";

-- 
Ville Syrjälä
Intel
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