* [Intel-gfx] [PATCH v2 1/3] drm/i915/display/tgl: Use TGL DP tables for eDP ports without low power support
@ 2020-08-25 18:43 José Roberto de Souza
2020-08-25 18:43 ` [Intel-gfx] [PATCH v2 2/3] drm/i915/display/ehl: Use EHL " José Roberto de Souza
` (5 more replies)
0 siblings, 6 replies; 10+ messages in thread
From: José Roberto de Souza @ 2020-08-25 18:43 UTC (permalink / raw)
To: intel-gfx
Reusing icl_get_combo_buf_trans() for eDP was causing the wrong table
being used when the eDP port don't support low power voltage swing table.
Cc: Lee Shawn C <shawn.c.lee@intel.com>
Cc: Khaled Almahallawy <khaled.almahallawy@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 52 +++++++++++++++---------
1 file changed, 33 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index de5b216561d8..9a035bb7bd06 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1088,30 +1088,44 @@ tgl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.hobl) {
- struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-
- if (!intel_dp->hobl_failed && rate <= 540000) {
- /* Same table applies to TGL, RKL and DG1 */
- *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_edp_hbr2_hobl);
- return tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
+ switch (type) {
+ case INTEL_OUTPUT_HDMI:
+ *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
+ return icl_combo_phy_ddi_translations_hdmi;
+ case INTEL_OUTPUT_EDP:
+ if (dev_priv->vbt.edp.hobl) {
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ if (!intel_dp->hobl_failed && rate <= 540000) {
+ /* Same table applies to TGL, RKL and DG1 */
+ *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_edp_hbr2_hobl);
+ return tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
+ }
}
- }
- if (type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_EDP) {
- return icl_get_combo_buf_trans(encoder, type, rate, n_entries);
- } else if (rate > 270000) {
- if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
- *n_entries = ARRAY_SIZE(tgl_uy_combo_phy_ddi_translations_dp_hbr2);
- return tgl_uy_combo_phy_ddi_translations_dp_hbr2;
+ if (rate > 540000) {
+ *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
+ return icl_combo_phy_ddi_translations_edp_hbr3;
+ } else if (dev_priv->vbt.edp.low_vswing) {
+ *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
+ return icl_combo_phy_ddi_translations_edp_hbr2;
+ }
+ /* fall through */
+ default:
+ /* All combo DP and eDP ports that do not support low_vswing */
+ if (rate > 270000) {
+ if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
+ *n_entries = ARRAY_SIZE(tgl_uy_combo_phy_ddi_translations_dp_hbr2);
+ return tgl_uy_combo_phy_ddi_translations_dp_hbr2;
+ }
+
+ *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2);
+ return tgl_combo_phy_ddi_translations_dp_hbr2;
}
- *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2);
- return tgl_combo_phy_ddi_translations_dp_hbr2;
+ *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr);
+ return tgl_combo_phy_ddi_translations_dp_hbr;
}
-
- *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr);
- return tgl_combo_phy_ddi_translations_dp_hbr;
}
static const struct tgl_dkl_phy_ddi_buf_trans *
--
2.28.0
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] [PATCH v2 2/3] drm/i915/display/ehl: Use EHL DP tables for eDP ports without low power support
2020-08-25 18:43 [Intel-gfx] [PATCH v2 1/3] drm/i915/display/tgl: Use TGL DP tables for eDP ports without low power support José Roberto de Souza
@ 2020-08-25 18:43 ` José Roberto de Souza
2020-08-25 22:56 ` Matt Roper
2020-08-25 18:43 ` [Intel-gfx] [PATCH v2 3/3] drm/i915/ehl: Update voltage swing table José Roberto de Souza
` (4 subsequent siblings)
5 siblings, 1 reply; 10+ messages in thread
From: José Roberto de Souza @ 2020-08-25 18:43 UTC (permalink / raw)
To: intel-gfx
Reusing icl_get_combo_buf_trans() for eDP was causing the wrong table
being used when the eDP port don't support low power voltage swing table.
v2: Only use icl_combo_phy_ddi_translations_edp_hbr3 if low_vswing is
set as EHL combo phy supports HBR3 (Matt R)
Cc: Lee Shawn C <shawn.c.lee@intel.com>
Cc: Khaled Almahallawy <khaled.almahallawy@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 22 +++++++++++++++++++---
1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 9a035bb7bd06..699511872290 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1074,12 +1074,28 @@ static const struct cnl_ddi_buf_trans *
ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
int *n_entries)
{
- if (type != INTEL_OUTPUT_HDMI && type != INTEL_OUTPUT_EDP) {
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
+ switch (type) {
+ case INTEL_OUTPUT_HDMI:
+ *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
+ return icl_combo_phy_ddi_translations_hdmi;
+ case INTEL_OUTPUT_EDP:
+ if (dev_priv->vbt.edp.low_vswing) {
+ if (rate > 540000) {
+ *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
+ return icl_combo_phy_ddi_translations_edp_hbr3;
+ } else {
+ *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
+ return icl_combo_phy_ddi_translations_edp_hbr2;
+ }
+ }
+ /* fall through */
+ default:
+ /* All combo DP and eDP ports that do not support low_vswing */
*n_entries = ARRAY_SIZE(ehl_combo_phy_ddi_translations_dp);
return ehl_combo_phy_ddi_translations_dp;
}
-
- return icl_get_combo_buf_trans(encoder, type, rate, n_entries);
}
static const struct cnl_ddi_buf_trans *
--
2.28.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] [PATCH v2 3/3] drm/i915/ehl: Update voltage swing table
2020-08-25 18:43 [Intel-gfx] [PATCH v2 1/3] drm/i915/display/tgl: Use TGL DP tables for eDP ports without low power support José Roberto de Souza
2020-08-25 18:43 ` [Intel-gfx] [PATCH v2 2/3] drm/i915/display/ehl: Use EHL " José Roberto de Souza
@ 2020-08-25 18:43 ` José Roberto de Souza
2020-08-25 22:54 ` Matt Roper
2020-08-25 18:47 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/3] drm/i915/display/tgl: Use TGL DP tables for eDP ports without low power support Patchwork
` (3 subsequent siblings)
5 siblings, 1 reply; 10+ messages in thread
From: José Roberto de Souza @ 2020-08-25 18:43 UTC (permalink / raw)
To: intel-gfx
Update with latest tunning in the table.
BSpec: 21257
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 699511872290..c7e64e20a772 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -572,14 +572,14 @@ static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = {
/* NT mV Trans mV db */
{ 0xA, 0x33, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
{ 0xA, 0x47, 0x36, 0x00, 0x09 }, /* 350 500 3.1 */
- { 0xC, 0x64, 0x30, 0x00, 0x0F }, /* 350 700 6.0 */
- { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 350 900 8.2 */
+ { 0xC, 0x64, 0x34, 0x00, 0x0B }, /* 350 700 6.0 */
+ { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 350 900 8.2 */
{ 0xA, 0x46, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
- { 0xC, 0x64, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
- { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
+ { 0xC, 0x64, 0x38, 0x00, 0x07 }, /* 500 700 2.9 */
+ { 0x6, 0x7F, 0x32, 0x00, 0x0D }, /* 500 900 5.1 */
{ 0xC, 0x61, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */
- { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 600 900 3.5 */
- { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
+ { 0x6, 0x7F, 0x37, 0x00, 0x07 }, /* 600 900 3.5 */
+ { 0x6, 0x7F, 0x38, 0x00, 0x00 }, /* 900 900 0.0 */
};
struct icl_mg_phy_ddi_buf_trans {
--
2.28.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/3] drm/i915/display/tgl: Use TGL DP tables for eDP ports without low power support
2020-08-25 18:43 [Intel-gfx] [PATCH v2 1/3] drm/i915/display/tgl: Use TGL DP tables for eDP ports without low power support José Roberto de Souza
2020-08-25 18:43 ` [Intel-gfx] [PATCH v2 2/3] drm/i915/display/ehl: Use EHL " José Roberto de Souza
2020-08-25 18:43 ` [Intel-gfx] [PATCH v2 3/3] drm/i915/ehl: Update voltage swing table José Roberto de Souza
@ 2020-08-25 18:47 ` Patchwork
2020-08-25 19:04 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2020-08-25 18:47 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v2,1/3] drm/i915/display/tgl: Use TGL DP tables for eDP ports without low power support
URL : https://patchwork.freedesktop.org/series/80990/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5b6227b45a69 drm/i915/display/tgl: Use TGL DP tables for eDP ports without low power support
-:43: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#43: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1101:
+ *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_edp_hbr2_hobl);
-:62: WARNING:PREFER_FALLTHROUGH: Prefer 'fallthrough;' over fallthrough comment
#62: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1113:
+ /* fall through */
total: 0 errors, 2 warnings, 0 checks, 63 lines checked
3aa5a2ba6712 drm/i915/display/ehl: Use EHL DP tables for eDP ports without low power support
-:41: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or return
#41: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1088:
+ return icl_combo_phy_ddi_translations_edp_hbr3;
+ } else {
-:46: WARNING:PREFER_FALLTHROUGH: Prefer 'fallthrough;' over fallthrough comment
#46: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1093:
+ /* fall through */
total: 0 errors, 2 warnings, 0 checks, 31 lines checked
f88ee990640a drm/i915/ehl: Update voltage swing table
-:9: WARNING:TYPO_SPELLING: 'tunning' may be misspelled - perhaps 'tuning'?
#9:
Update with latest tunning in the table.
total: 0 errors, 1 warnings, 0 checks, 20 lines checked
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/3] drm/i915/display/tgl: Use TGL DP tables for eDP ports without low power support
2020-08-25 18:43 [Intel-gfx] [PATCH v2 1/3] drm/i915/display/tgl: Use TGL DP tables for eDP ports without low power support José Roberto de Souza
` (2 preceding siblings ...)
2020-08-25 18:47 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/3] drm/i915/display/tgl: Use TGL DP tables for eDP ports without low power support Patchwork
@ 2020-08-25 19:04 ` Patchwork
2020-08-25 20:13 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-08-25 22:55 ` [Intel-gfx] [PATCH v2 1/3] " Matt Roper
5 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2020-08-25 19:04 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 4649 bytes --]
== Series Details ==
Series: series starting with [v2,1/3] drm/i915/display/tgl: Use TGL DP tables for eDP ports without low power support
URL : https://patchwork.freedesktop.org/series/80990/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8924 -> Patchwork_18399
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/index.html
Known issues
------------
Here are the changes found in Patchwork_18399 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_module_load@reload:
- fi-tgl-u2: [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8924/fi-tgl-u2/igt@i915_module_load@reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/fi-tgl-u2/igt@i915_module_load@reload.html
* igt@kms_flip@basic-flip-vs-wf_vblank@b-edp1:
- fi-icl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8924/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vblank@b-edp1.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vblank@b-edp1.html
#### Possible fixes ####
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-byt-j1900: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8924/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8924/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-apl-guc: [INCOMPLETE][9] ([i915#1635] / [i915#337]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8924/fi-apl-guc/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/fi-apl-guc/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
#### Warnings ####
* igt@gem_exec_suspend@basic-s0:
- fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92]) -> [DMESG-WARN][12] ([i915#62] / [i915#92] / [i915#95]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8924/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html
* igt@i915_pm_rpm@module-reload:
- fi-kbl-x1275: [DMESG-FAIL][13] ([i915#62] / [i915#95]) -> [DMESG-FAIL][14] ([i915#62])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8924/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#337]: https://gitlab.freedesktop.org/drm/intel/issues/337
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (37 -> 34)
------------------------------
Missing (3): fi-byt-clapper fi-byt-squawks fi-bsw-cyan
Build changes
-------------
* Linux: CI_DRM_8924 -> Patchwork_18399
CI-20190529: 20190529
CI_DRM_8924: a8c0611e412aab46eab5475b0117d074892b96e2 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5770: f1d0c240ea2e631dfb9f493f37f8fb61cb2b1cf2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18399: f88ee990640a57e8215c745a94a8e5d2334d72b8 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f88ee990640a drm/i915/ehl: Update voltage swing table
3aa5a2ba6712 drm/i915/display/ehl: Use EHL DP tables for eDP ports without low power support
5b6227b45a69 drm/i915/display/tgl: Use TGL DP tables for eDP ports without low power support
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/index.html
[-- Attachment #1.2: Type: text/html, Size: 5958 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v2,1/3] drm/i915/display/tgl: Use TGL DP tables for eDP ports without low power support
2020-08-25 18:43 [Intel-gfx] [PATCH v2 1/3] drm/i915/display/tgl: Use TGL DP tables for eDP ports without low power support José Roberto de Souza
` (3 preceding siblings ...)
2020-08-25 19:04 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-08-25 20:13 ` Patchwork
2020-08-25 22:55 ` [Intel-gfx] [PATCH v2 1/3] " Matt Roper
5 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2020-08-25 20:13 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 16173 bytes --]
== Series Details ==
Series: series starting with [v2,1/3] drm/i915/display/tgl: Use TGL DP tables for eDP ports without low power support
URL : https://patchwork.freedesktop.org/series/80990/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8924_full -> Patchwork_18399_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_18399_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@device_reset@unbind-reset-rebind:
- shard-iclb: [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8924/shard-iclb7/igt@device_reset@unbind-reset-rebind.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/shard-iclb8/igt@device_reset@unbind-reset-rebind.html
* igt@gem_exec_whisper@basic-fds-priority:
- shard-glk: [PASS][3] -> [TIMEOUT][4] ([i915#1958]) +3 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8924/shard-glk6/igt@gem_exec_whisper@basic-fds-priority.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/shard-glk9/igt@gem_exec_whisper@basic-fds-priority.html
* igt@gem_exec_whisper@basic-forked:
- shard-glk: [PASS][5] -> [DMESG-WARN][6] ([i915#118] / [i915#95])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8924/shard-glk1/igt@gem_exec_whisper@basic-forked.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/shard-glk2/igt@gem_exec_whisper@basic-forked.html
* igt@gem_exec_whisper@basic-queues:
- shard-kbl: [PASS][7] -> [TIMEOUT][8] ([i915#1958]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8924/shard-kbl4/igt@gem_exec_whisper@basic-queues.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/shard-kbl1/igt@gem_exec_whisper@basic-queues.html
- shard-skl: [PASS][9] -> [TIMEOUT][10] ([i915#1958]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8924/shard-skl9/igt@gem_exec_whisper@basic-queues.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/shard-skl1/igt@gem_exec_whisper@basic-queues.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-180:
- shard-skl: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +10 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8924/shard-skl3/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/shard-skl7/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) +7 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8924/shard-kbl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_flip@flip-vs-suspend@c-hdmi-a1:
- shard-hsw: [PASS][15] -> [INCOMPLETE][16] ([i915#2055])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8924/shard-hsw1/igt@kms_flip@flip-vs-suspend@c-hdmi-a1.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/shard-hsw8/igt@kms_flip@flip-vs-suspend@c-hdmi-a1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1:
- shard-skl: [PASS][17] -> [FAIL][18] ([i915#2122])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8924/shard-skl6/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/shard-skl5/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-tglb: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8924/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [PASS][21] -> [FAIL][22] ([i915#1188]) +1 similar issue
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8924/shard-skl1/igt@kms_hdr@bpc-switch-suspend.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/shard-skl3/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [PASS][23] -> [FAIL][24] ([fdo#108145] / [i915#265])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8924/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend:
- shard-skl: [PASS][25] -> [INCOMPLETE][26] ([i915#198])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8924/shard-skl9/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/shard-skl8/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
#### Possible fixes ####
* igt@gem_exec_nop@basic-sequential:
- shard-tglb: [TIMEOUT][27] ([i915#1958]) -> [PASS][28] +2 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8924/shard-tglb1/igt@gem_exec_nop@basic-sequential.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/shard-tglb2/igt@gem_exec_nop@basic-sequential.html
* igt@gem_exec_parallel@engines@basic:
- shard-kbl: [INCOMPLETE][29] -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8924/shard-kbl1/igt@gem_exec_parallel@engines@basic.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/shard-kbl4/igt@gem_exec_parallel@engines@basic.html
* igt@gem_exec_reloc@basic-concurrent0:
- shard-skl: [TIMEOUT][31] ([i915#1958]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8924/shard-skl7/igt@gem_exec_reloc@basic-concurrent0.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/shard-skl10/igt@gem_exec_reloc@basic-concurrent0.html
* igt@gem_exec_whisper@basic-fds:
- shard-apl: [TIMEOUT][33] ([i915#1635] / [i915#1958]) -> [PASS][34] +1 similar issue
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8924/shard-apl3/igt@gem_exec_whisper@basic-fds.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/shard-apl8/igt@gem_exec_whisper@basic-fds.html
* igt@gem_exec_whisper@basic-fds-forked-all:
- shard-iclb: [TIMEOUT][35] ([i915#1958]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8924/shard-iclb7/igt@gem_exec_whisper@basic-fds-forked-all.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/shard-iclb6/igt@gem_exec_whisper@basic-fds-forked-all.html
* igt@gem_exec_whisper@basic-normal:
- shard-kbl: [TIMEOUT][37] ([i915#1958]) -> [PASS][38] +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8924/shard-kbl2/igt@gem_exec_whisper@basic-normal.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/shard-kbl7/igt@gem_exec_whisper@basic-normal.html
* igt@gem_exec_whisper@basic-queues-forked:
- shard-glk: [TIMEOUT][39] ([i915#1958]) -> [PASS][40] +1 similar issue
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8924/shard-glk7/igt@gem_exec_whisper@basic-queues-forked.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/shard-glk6/igt@gem_exec_whisper@basic-queues-forked.html
* igt@gem_sync@basic-store-all:
- shard-apl: [FAIL][41] ([i915#1635]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8924/shard-apl4/igt@gem_sync@basic-store-all.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/shard-apl2/igt@gem_sync@basic-store-all.html
- shard-kbl: [FAIL][43] -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8924/shard-kbl2/igt@gem_sync@basic-store-all.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/shard-kbl2/igt@gem_sync@basic-store-all.html
* igt@i915_pm_rpm@system-suspend:
- shard-kbl: [INCOMPLETE][45] ([i915#151] / [i915#155]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8924/shard-kbl4/igt@i915_pm_rpm@system-suspend.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/shard-kbl1/igt@i915_pm_rpm@system-suspend.html
* igt@i915_selftest@mock@requests:
- shard-skl: [INCOMPLETE][47] ([i915#198] / [i915#2278]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8924/shard-skl2/igt@i915_selftest@mock@requests.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/shard-skl1/igt@i915_selftest@mock@requests.html
* igt@kms_cursor_crc@pipe-b-cursor-128x128-sliding:
- shard-skl: [DMESG-FAIL][49] ([i915#1982] / [i915#54]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8924/shard-skl4/igt@kms_cursor_crc@pipe-b-cursor-128x128-sliding.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/shard-skl9/igt@kms_cursor_crc@pipe-b-cursor-128x128-sliding.html
* igt@kms_flip@2x-wf_vblank-ts-check@ab-vga1-hdmi-a1:
- shard-hsw: [DMESG-WARN][51] ([i915#1982]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8924/shard-hsw1/igt@kms_flip@2x-wf_vblank-ts-check@ab-vga1-hdmi-a1.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/shard-hsw8/igt@kms_flip@2x-wf_vblank-ts-check@ab-vga1-hdmi-a1.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [DMESG-WARN][53] ([i915#180]) -> [PASS][54] +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8924/shard-kbl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/shard-kbl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1:
- shard-skl: [FAIL][55] ([i915#2122]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8924/shard-skl6/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/shard-skl5/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack:
- shard-tglb: [DMESG-WARN][57] ([i915#1982]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8924/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack.html
* igt@kms_plane@plane-position-covered-pipe-b-planes:
- shard-skl: [DMESG-WARN][59] ([i915#1982]) -> [PASS][60] +9 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8924/shard-skl4/igt@kms_plane@plane-position-covered-pipe-b-planes.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/shard-skl5/igt@kms_plane@plane-position-covered-pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [FAIL][61] ([fdo#108145] / [i915#265]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8924/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_scaling@pipe-a-scaler-with-clipping-clamping:
- shard-iclb: [DMESG-WARN][63] ([i915#1982]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8924/shard-iclb3/igt@kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/shard-iclb3/igt@kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html
* igt@kms_vblank@crtc-id:
- shard-kbl: [DMESG-WARN][65] ([i915#1982]) -> [PASS][66] +1 similar issue
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8924/shard-kbl4/igt@kms_vblank@crtc-id.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/shard-kbl1/igt@kms_vblank@crtc-id.html
#### Warnings ####
* igt@gem_exec_reloc@basic-many-active@rcs0:
- shard-apl: [FAIL][67] ([i915#1635]) -> [FAIL][68] ([i915#1635] / [i915#2389])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8924/shard-apl8/igt@gem_exec_reloc@basic-many-active@rcs0.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/shard-apl3/igt@gem_exec_reloc@basic-many-active@rcs0.html
* igt@gem_exec_whisper@basic-forked-all:
- shard-glk: [DMESG-WARN][69] ([i915#118] / [i915#95]) -> [TIMEOUT][70] ([i915#1958])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8924/shard-glk5/igt@gem_exec_whisper@basic-forked-all.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/shard-glk1/igt@gem_exec_whisper@basic-forked-all.html
* igt@kms_content_protection@atomic:
- shard-kbl: [TIMEOUT][71] ([i915#1319]) -> [TIMEOUT][72] ([i915#1319] / [i915#1958])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8924/shard-kbl1/igt@kms_content_protection@atomic.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/shard-kbl7/igt@kms_content_protection@atomic.html
* igt@perf@polling-parameterized:
- shard-skl: [FAIL][73] ([i915#1542]) -> [DMESG-FAIL][74] ([i915#1982])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8924/shard-skl2/igt@perf@polling-parameterized.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/shard-skl1/igt@perf@polling-parameterized.html
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2055]: https://gitlab.freedesktop.org/drm/intel/issues/2055
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2278]: https://gitlab.freedesktop.org/drm/intel/issues/2278
[i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_8924 -> Patchwork_18399
CI-20190529: 20190529
CI_DRM_8924: a8c0611e412aab46eab5475b0117d074892b96e2 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5770: f1d0c240ea2e631dfb9f493f37f8fb61cb2b1cf2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18399: f88ee990640a57e8215c745a94a8e5d2334d72b8 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18399/index.html
[-- Attachment #1.2: Type: text/html, Size: 19681 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH v2 3/3] drm/i915/ehl: Update voltage swing table
2020-08-25 18:43 ` [Intel-gfx] [PATCH v2 3/3] drm/i915/ehl: Update voltage swing table José Roberto de Souza
@ 2020-08-25 22:54 ` Matt Roper
2020-08-26 20:10 ` Souza, Jose
0 siblings, 1 reply; 10+ messages in thread
From: Matt Roper @ 2020-08-25 22:54 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
On Tue, Aug 25, 2020 at 11:43:43AM -0700, José Roberto de Souza wrote:
> Update with latest tunning in the table.
>
> BSpec: 21257
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 699511872290..c7e64e20a772 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -572,14 +572,14 @@ static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = {
> /* NT mV Trans mV db */
> { 0xA, 0x33, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
> { 0xA, 0x47, 0x36, 0x00, 0x09 }, /* 350 500 3.1 */
> - { 0xC, 0x64, 0x30, 0x00, 0x0F }, /* 350 700 6.0 */
> - { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 350 900 8.2 */
> + { 0xC, 0x64, 0x34, 0x00, 0x0B }, /* 350 700 6.0 */
> + { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 350 900 8.2 */
> { 0xA, 0x46, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
> - { 0xC, 0x64, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
> - { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
> + { 0xC, 0x64, 0x38, 0x00, 0x07 }, /* 500 700 2.9 */
> + { 0x6, 0x7F, 0x32, 0x00, 0x0D }, /* 500 900 5.1 */
> { 0xC, 0x61, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */
> - { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 600 900 3.5 */
> - { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
> + { 0x6, 0x7F, 0x37, 0x00, 0x07 }, /* 600 900 3.5 */
> + { 0x6, 0x7F, 0x38, 0x00, 0x00 }, /* 900 900 0.0 */
I think it got missed at the bottom of my last response, but I see
slightly different values for the last two rows here in the EHL table.
Specifically the third column (cursor coeff dw4) -- I see 0x38 and 0x3F
as the last two values?
Matt
> };
>
> struct icl_mg_phy_ddi_buf_trans {
> --
> 2.28.0
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH v2 1/3] drm/i915/display/tgl: Use TGL DP tables for eDP ports without low power support
2020-08-25 18:43 [Intel-gfx] [PATCH v2 1/3] drm/i915/display/tgl: Use TGL DP tables for eDP ports without low power support José Roberto de Souza
` (4 preceding siblings ...)
2020-08-25 20:13 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2020-08-25 22:55 ` Matt Roper
5 siblings, 0 replies; 10+ messages in thread
From: Matt Roper @ 2020-08-25 22:55 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
On Tue, Aug 25, 2020 at 11:43:41AM -0700, José Roberto de Souza wrote:
> Reusing icl_get_combo_buf_trans() for eDP was causing the wrong table
> being used when the eDP port don't support low power voltage swing table.
>
> Cc: Lee Shawn C <shawn.c.lee@intel.com>
> Cc: Khaled Almahallawy <khaled.almahallawy@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 52 +++++++++++++++---------
> 1 file changed, 33 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index de5b216561d8..9a035bb7bd06 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1088,30 +1088,44 @@ tgl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> - if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.hobl) {
> - struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> -
> - if (!intel_dp->hobl_failed && rate <= 540000) {
> - /* Same table applies to TGL, RKL and DG1 */
> - *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_edp_hbr2_hobl);
> - return tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
> + switch (type) {
> + case INTEL_OUTPUT_HDMI:
> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
> + return icl_combo_phy_ddi_translations_hdmi;
> + case INTEL_OUTPUT_EDP:
> + if (dev_priv->vbt.edp.hobl) {
> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
> + if (!intel_dp->hobl_failed && rate <= 540000) {
> + /* Same table applies to TGL, RKL and DG1 */
> + *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_edp_hbr2_hobl);
> + return tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
> + }
> }
> - }
>
> - if (type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_EDP) {
> - return icl_get_combo_buf_trans(encoder, type, rate, n_entries);
> - } else if (rate > 270000) {
> - if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
> - *n_entries = ARRAY_SIZE(tgl_uy_combo_phy_ddi_translations_dp_hbr2);
> - return tgl_uy_combo_phy_ddi_translations_dp_hbr2;
> + if (rate > 540000) {
> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
> + return icl_combo_phy_ddi_translations_edp_hbr3;
> + } else if (dev_priv->vbt.edp.low_vswing) {
> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
> + return icl_combo_phy_ddi_translations_edp_hbr2;
> + }
> + /* fall through */
> + default:
> + /* All combo DP and eDP ports that do not support low_vswing */
> + if (rate > 270000) {
> + if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
> + *n_entries = ARRAY_SIZE(tgl_uy_combo_phy_ddi_translations_dp_hbr2);
> + return tgl_uy_combo_phy_ddi_translations_dp_hbr2;
> + }
> +
> + *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2);
> + return tgl_combo_phy_ddi_translations_dp_hbr2;
> }
>
> - *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2);
> - return tgl_combo_phy_ddi_translations_dp_hbr2;
> + *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr);
> + return tgl_combo_phy_ddi_translations_dp_hbr;
> }
> -
> - *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr);
> - return tgl_combo_phy_ddi_translations_dp_hbr;
> }
>
> static const struct tgl_dkl_phy_ddi_buf_trans *
> --
> 2.28.0
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH v2 2/3] drm/i915/display/ehl: Use EHL DP tables for eDP ports without low power support
2020-08-25 18:43 ` [Intel-gfx] [PATCH v2 2/3] drm/i915/display/ehl: Use EHL " José Roberto de Souza
@ 2020-08-25 22:56 ` Matt Roper
0 siblings, 0 replies; 10+ messages in thread
From: Matt Roper @ 2020-08-25 22:56 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
On Tue, Aug 25, 2020 at 11:43:42AM -0700, José Roberto de Souza wrote:
> Reusing icl_get_combo_buf_trans() for eDP was causing the wrong table
> being used when the eDP port don't support low power voltage swing table.
>
> v2: Only use icl_combo_phy_ddi_translations_edp_hbr3 if low_vswing is
> set as EHL combo phy supports HBR3 (Matt R)
>
> Cc: Lee Shawn C <shawn.c.lee@intel.com>
> Cc: Khaled Almahallawy <khaled.almahallawy@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 22 +++++++++++++++++++---
> 1 file changed, 19 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 9a035bb7bd06..699511872290 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1074,12 +1074,28 @@ static const struct cnl_ddi_buf_trans *
> ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
> int *n_entries)
> {
> - if (type != INTEL_OUTPUT_HDMI && type != INTEL_OUTPUT_EDP) {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +
> + switch (type) {
> + case INTEL_OUTPUT_HDMI:
> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
> + return icl_combo_phy_ddi_translations_hdmi;
> + case INTEL_OUTPUT_EDP:
> + if (dev_priv->vbt.edp.low_vswing) {
> + if (rate > 540000) {
> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
> + return icl_combo_phy_ddi_translations_edp_hbr3;
> + } else {
> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
> + return icl_combo_phy_ddi_translations_edp_hbr2;
> + }
> + }
> + /* fall through */
> + default:
> + /* All combo DP and eDP ports that do not support low_vswing */
> *n_entries = ARRAY_SIZE(ehl_combo_phy_ddi_translations_dp);
> return ehl_combo_phy_ddi_translations_dp;
> }
> -
> - return icl_get_combo_buf_trans(encoder, type, rate, n_entries);
> }
>
> static const struct cnl_ddi_buf_trans *
> --
> 2.28.0
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH v2 3/3] drm/i915/ehl: Update voltage swing table
2020-08-25 22:54 ` Matt Roper
@ 2020-08-26 20:10 ` Souza, Jose
0 siblings, 0 replies; 10+ messages in thread
From: Souza, Jose @ 2020-08-26 20:10 UTC (permalink / raw)
To: Roper, Matthew D; +Cc: intel-gfx
On Tue, 2020-08-25 at 15:54 -0700, Matt Roper wrote:
> On Tue, Aug 25, 2020 at 11:43:43AM -0700, José Roberto de Souza wrote:
> > Update with latest tunning in the table.
> >
> > BSpec: 21257
> > Cc: Matt Roper <
> > matthew.d.roper@intel.com
> > >
> > Signed-off-by: José Roberto de Souza <
> > jose.souza@intel.com
> > >
> > ---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 12 ++++++------
> > 1 file changed, 6 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 699511872290..c7e64e20a772 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -572,14 +572,14 @@ static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = {
> > /* NT mV Trans mV db */
> > { 0xA, 0x33, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
> > { 0xA, 0x47, 0x36, 0x00, 0x09 }, /* 350 500 3.1 */
> > - { 0xC, 0x64, 0x30, 0x00, 0x0F }, /* 350 700 6.0 */
> > - { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 350 900 8.2 */
> > + { 0xC, 0x64, 0x34, 0x00, 0x0B }, /* 350 700 6.0 */
> > + { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 350 900 8.2 */
> > { 0xA, 0x46, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
> > - { 0xC, 0x64, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
> > - { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
> > + { 0xC, 0x64, 0x38, 0x00, 0x07 }, /* 500 700 2.9 */
> > + { 0x6, 0x7F, 0x32, 0x00, 0x0D }, /* 500 900 5.1 */
> > { 0xC, 0x61, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */
> > - { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 600 900 3.5 */
> > - { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
> > + { 0x6, 0x7F, 0x37, 0x00, 0x07 }, /* 600 900 3.5 */
> > + { 0x6, 0x7F, 0x38, 0x00, 0x00 }, /* 900 900 0.0 */
>
> I think it got missed at the bottom of my last response, but I see
> slightly different values for the last two rows here in the EHL table.
> Specifically the third column (cursor coeff dw4) -- I see 0x38 and 0x3F
> as the last two values?
Ops, my bad. Fixing it
>
>
> Matt
>
> > };
> >
> > struct icl_mg_phy_ddi_buf_trans {
> > --
> > 2.28.0
> >
>
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2020-08-26 20:11 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-08-25 18:43 [Intel-gfx] [PATCH v2 1/3] drm/i915/display/tgl: Use TGL DP tables for eDP ports without low power support José Roberto de Souza
2020-08-25 18:43 ` [Intel-gfx] [PATCH v2 2/3] drm/i915/display/ehl: Use EHL " José Roberto de Souza
2020-08-25 22:56 ` Matt Roper
2020-08-25 18:43 ` [Intel-gfx] [PATCH v2 3/3] drm/i915/ehl: Update voltage swing table José Roberto de Souza
2020-08-25 22:54 ` Matt Roper
2020-08-26 20:10 ` Souza, Jose
2020-08-25 18:47 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/3] drm/i915/display/tgl: Use TGL DP tables for eDP ports without low power support Patchwork
2020-08-25 19:04 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-08-25 20:13 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-08-25 22:55 ` [Intel-gfx] [PATCH v2 1/3] " Matt Roper
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