From: "Huang, Sean Z" <sean.z.huang@intel.com>
To: Intel-gfx@lists.freedesktop.org
Cc: kumar.gaurav@intel.com
Subject: [Intel-gfx] [RFC-v23 05/13] drm/i915/pxp: Func to send hardware session termination
Date: Mon, 18 Jan 2021 23:43:12 -0800 [thread overview]
Message-ID: <20210119074320.28768-6-sean.z.huang@intel.com> (raw)
In-Reply-To: <20210119074320.28768-1-sean.z.huang@intel.com>
Implement the functions to allow PXP to send a GPU command, in
order to terminate the hardware session, so hardware can recycle
this session slot for the next usage.
rev21:
In intel_pxp_cmd.c:
- Remove the debug print as well as print_hex_dump()
- Should call i915_gem_object_flush_map() before unpin map
- Using "goto label" instead of bool such as is_engine_pm_get
- We should always return the error if any, instead of skip
with i915_request_set_error_once()
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 13 +++
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 124 +++++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 18 +++
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 4 +
5 files changed, 160 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index e3b7f6b5dadb..c931ef5e8a85 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -269,6 +269,7 @@ i915-y += i915_perf.o
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
pxp/intel_pxp_arb.o \
+ pxp/intel_pxp_cmd.o \
pxp/intel_pxp_context.o \
pxp/intel_pxp_tee.o
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 4f033907564a..f71677a84405 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -17,10 +17,23 @@
void intel_pxp_init(struct intel_pxp *pxp)
{
struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+ int i;
if (INTEL_GEN(gt->i915) < 12)
return;
+ /* Find the first VCS engine present */
+ for (i = 0; i < I915_MAX_VCS; i++) {
+ if (HAS_ENGINE(gt, _VCS(i))) {
+ pxp->vcs_engine = gt->engine[_VCS(i)];
+ break;
+ }
+ }
+ if (!pxp->vcs_engine) {
+ drm_err(>->i915->drm, "Could not find a VCS engine\n");
+ return;
+ }
+
intel_pxp_ctx_init(&pxp->ctx);
if (INTEL_GEN(gt->i915) == 12)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
new file mode 100644
index 000000000000..6898b8826302
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#include "intel_pxp_cmd.h"
+#include "i915_drv.h"
+#include "gt/intel_context.h"
+#include "gt/intel_engine_pm.h"
+
+struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp,
+ struct intel_context *ce,
+ struct intel_gt_buffer_pool_node *pool,
+ u32 *cmd_buf, int cmd_size_in_dw)
+{
+ struct i915_vma *batch = ERR_PTR(-EINVAL);
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+ u32 *cmd;
+
+ if (!ce || !ce->engine || !cmd_buf)
+ return ERR_PTR(-EINVAL);
+
+ if (cmd_size_in_dw * 4 > PAGE_SIZE) {
+ drm_err(>->i915->drm, "Failed to %s, invalid cmd_size_id_dw=[%d]\n",
+ __func__, cmd_size_in_dw);
+ return ERR_PTR(-EINVAL);
+ }
+
+ cmd = i915_gem_object_pin_map(pool->obj, I915_MAP_FORCE_WC);
+ if (IS_ERR(cmd)) {
+ drm_err(>->i915->drm, "Failed to i915_gem_object_pin_map()\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ memcpy(cmd, cmd_buf, cmd_size_in_dw * 4);
+
+ i915_gem_object_flush_map(pool->obj);
+ i915_gem_object_unpin_map(pool->obj);
+
+ batch = i915_vma_instance(pool->obj, ce->vm, NULL);
+ if (IS_ERR(batch)) {
+ drm_err(>->i915->drm, "Failed to i915_vma_instance()\n");
+ return batch;
+ }
+
+ return batch;
+}
+
+int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, int cmd_size_in_dw)
+{
+ int err = -EINVAL;
+ struct i915_vma *batch;
+ struct i915_request *rq;
+ struct intel_context *ce = NULL;
+ struct intel_gt_buffer_pool_node *pool = NULL;
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+ int size = cmd_size_in_dw * 4;
+
+ ce = pxp->vcs_engine->kernel_context;
+ if (!ce)
+ return -EINVAL;
+
+ if (!cmd || cmd_size_in_dw == 0)
+ return -EINVAL;
+
+ intel_engine_pm_get(ce->engine);
+
+ size = round_up(size, PAGE_SIZE);
+ pool = intel_gt_get_buffer_pool(gt, size);
+ if (IS_ERR(pool)) {
+ err = PTR_ERR(pool);
+ goto out_engine_pm_put;
+ }
+
+ batch = intel_pxp_cmd_get_batch(pxp, ce, pool, cmd, cmd_size_in_dw);
+ if (IS_ERR(batch)) {
+ err = PTR_ERR(batch);
+ goto out_engine_pool_put;
+ }
+
+ err = i915_vma_pin(batch, 0, 0, PIN_USER);
+ if (err)
+ goto out_engine_pool_put;
+
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto out_vma_unpin;
+ }
+
+ err = intel_gt_buffer_pool_mark_active(pool, rq);
+ if (err)
+ goto out_vma_unpin;
+
+ i915_vma_lock(batch);
+ err = i915_request_await_object(rq, batch->obj, false);
+ if (!err)
+ err = i915_vma_move_to_active(batch, rq, 0);
+ i915_vma_unlock(batch);
+ if (err)
+ goto out_vma_unpin;
+
+ if (ce->engine->emit_init_breadcrumb) {
+ err = ce->engine->emit_init_breadcrumb(rq);
+ if (err)
+ goto out_vma_unpin;
+ }
+
+ err = ce->engine->emit_bb_start(rq, batch->node.start,
+ batch->node.size, 0);
+ if (err)
+ goto out_vma_unpin;
+
+ i915_request_add(rq);
+
+out_vma_unpin:
+ i915_vma_unpin(batch);
+out_engine_pool_put:
+ intel_gt_buffer_pool_put(pool);
+out_engine_pm_put:
+ intel_engine_pm_put(ce->engine);
+
+ return err;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
new file mode 100644
index 000000000000..d04463962421
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_CMD_H__
+#define __INTEL_PXP_CMD_H__
+
+#include "gt/intel_gt_buffer_pool.h"
+#include "intel_pxp.h"
+
+struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp,
+ struct intel_context *ce,
+ struct intel_gt_buffer_pool_node *pool,
+ u32 *cmd_buf, int cmd_size_in_dw);
+
+int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, int cmd_size_in_dw);
+#endif /* __INTEL_PXP_SM_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
index e2bd320302c2..19d43b43e483 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
@@ -8,6 +8,8 @@
#include <linux/mutex.h>
+struct intel_engine_cs;
+
/* struct pxp_context - Represents combined view of driver and logical HW states. */
struct pxp_context {
/** @mutex: mutex to protect the pxp context */
@@ -22,6 +24,8 @@ struct pxp_context {
struct intel_pxp {
struct pxp_context ctx;
+
+ struct intel_engine_cs *vcs_engine;
};
#endif /* __INTEL_PXP_TYPES_H__ */
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-01-19 7:43 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-19 7:43 [Intel-gfx] [RFC-v23 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
2021-01-19 7:43 ` [Intel-gfx] [RFC-v23 01/13] drm/i915/pxp: Introduce Intel PXP component Huang, Sean Z
2021-01-21 16:08 ` Chris Wilson
2021-01-19 7:43 ` [Intel-gfx] [RFC-v23 02/13] drm/i915/pxp: set KCR reg init during the boot time Huang, Sean Z
2021-01-21 17:04 ` Chris Wilson
2021-01-19 7:43 ` [Intel-gfx] [RFC-v23 03/13] drm/i915/pxp: Implement funcs to create the TEE channel Huang, Sean Z
2021-01-19 7:43 ` [Intel-gfx] [RFC-v23 04/13] drm/i915/pxp: Create the arbitrary session after boot Huang, Sean Z
2021-01-19 7:43 ` Huang, Sean Z [this message]
2021-01-19 7:43 ` [Intel-gfx] [RFC-v23 06/13] drm/i915/pxp: Enable PXP irq worker and callback stub Huang, Sean Z
2021-01-19 7:43 ` [Intel-gfx] [RFC-v23 07/13] drm/i915/pxp: Destroy arb session upon teardown Huang, Sean Z
2021-01-19 7:43 ` [Intel-gfx] [RFC-v23 08/13] drm/i915/pxp: Enable PXP power management Huang, Sean Z
2021-01-19 7:43 ` [Intel-gfx] [RFC-v23 09/13] drm/i915/pxp: Expose session state for display protection flip Huang, Sean Z
2021-01-21 19:47 ` Rodrigo Vivi
2021-01-19 7:43 ` [Intel-gfx] [RFC-v23 10/13] mei: pxp: export pavp client to me client bus Huang, Sean Z
2021-01-19 7:43 ` [Intel-gfx] [RFC-v23 11/13] drm/i915/uapi: introduce drm_i915_gem_create_ext Huang, Sean Z
2021-01-19 7:43 ` [Intel-gfx] [RFC-v23 12/13] drm/i915/pxp: User interface for Protected buffer Huang, Sean Z
2021-01-19 7:43 ` [Intel-gfx] [RFC-v23 13/13] drm/i915/pxp: Add plane decryption support Huang, Sean Z
2021-01-19 9:35 ` Gupta, Anshuman
2021-01-21 20:30 ` Ville Syrjälä
2021-01-21 20:50 ` Gaurav, Kumar
2021-01-21 21:00 ` Ville Syrjälä
2021-01-21 21:34 ` Gaurav, Kumar
2021-01-22 11:58 ` Ville Syrjälä
2021-01-22 17:25 ` Gaurav, Kumar
2021-01-19 12:33 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Intel PXP component - Mesa single session (rev23) Patchwork
2021-01-19 13:03 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-01-23 14:18 ` [Intel-gfx] [RFC-v23 00/13] Introduce Intel PXP component - Mesa single session Lionel Landwerlin
2021-01-23 21:47 ` Gaurav, Kumar
2021-01-25 15:38 ` Lionel Landwerlin
2021-01-25 16:22 ` Gaurav, Kumar
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210119074320.28768-6-sean.z.huang@intel.com \
--to=sean.z.huang@intel.com \
--cc=Intel-gfx@lists.freedesktop.org \
--cc=kumar.gaurav@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).