* [Intel-gfx] [PATCH v2 1/2] drm/i915/selftests: Exercise relative mmio paths to non-privileged registers
@ 2021-01-14 10:38 Chris Wilson
2021-01-14 10:38 ` [Intel-gfx] [PATCH v2 2/2] drm/i915/selftests: Exercise cross-process context isolation Chris Wilson
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: Chris Wilson @ 2021-01-14 10:38 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
Verify that context isolation is also preserved when accessing
context-local registers with relative-mmio commands.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 88 ++++++++++++++++++++------
1 file changed, 67 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 920979a89413..a55cbf524692 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -911,7 +911,9 @@ create_user_vma(struct i915_address_space *vm, unsigned long size)
}
static struct i915_vma *
-store_context(struct intel_context *ce, struct i915_vma *scratch)
+store_context(struct intel_context *ce,
+ struct i915_vma *scratch,
+ bool relative)
{
struct i915_vma *batch;
u32 dw, x, *cs, *hw;
@@ -940,6 +942,9 @@ store_context(struct intel_context *ce, struct i915_vma *scratch)
hw += LRC_STATE_OFFSET / sizeof(*hw);
do {
u32 len = hw[dw] & 0x7f;
+ u32 cmd = MI_STORE_REGISTER_MEM_GEN8;
+ u32 offset = 0;
+ u32 mask = ~0;
if (hw[dw] == 0) {
dw++;
@@ -951,11 +956,19 @@ store_context(struct intel_context *ce, struct i915_vma *scratch)
continue;
}
+ if (hw[dw] & MI_LRI_LRM_CS_MMIO) {
+ mask = 0xfff;
+ if (relative)
+ cmd |= MI_LRI_LRM_CS_MMIO;
+ else
+ offset = ce->engine->mmio_base;
+ }
+
dw++;
len = (len + 1) / 2;
while (len--) {
- *cs++ = MI_STORE_REGISTER_MEM_GEN8;
- *cs++ = hw[dw];
+ *cs++ = cmd;
+ *cs++ = (hw[dw] & mask) + offset;
*cs++ = lower_32_bits(scratch->node.start + x);
*cs++ = upper_32_bits(scratch->node.start + x);
@@ -994,6 +1007,7 @@ static struct i915_request *
record_registers(struct intel_context *ce,
struct i915_vma *before,
struct i915_vma *after,
+ bool relative,
u32 *sema)
{
struct i915_vma *b_before, *b_after;
@@ -1001,11 +1015,11 @@ record_registers(struct intel_context *ce,
u32 *cs;
int err;
- b_before = store_context(ce, before);
+ b_before = store_context(ce, before, relative);
if (IS_ERR(b_before))
return ERR_CAST(b_before);
- b_after = store_context(ce, after);
+ b_after = store_context(ce, after, relative);
if (IS_ERR(b_after)) {
rq = ERR_CAST(b_after);
goto err_before;
@@ -1075,7 +1089,8 @@ record_registers(struct intel_context *ce,
goto err_after;
}
-static struct i915_vma *load_context(struct intel_context *ce, u32 poison)
+static struct i915_vma *
+load_context(struct intel_context *ce, u32 poison, bool relative)
{
struct i915_vma *batch;
u32 dw, *cs, *hw;
@@ -1102,7 +1117,10 @@ static struct i915_vma *load_context(struct intel_context *ce, u32 poison)
hw = defaults;
hw += LRC_STATE_OFFSET / sizeof(*hw);
do {
+ u32 cmd = MI_INSTR(0x22, 0);
u32 len = hw[dw] & 0x7f;
+ u32 offset = 0;
+ u32 mask = ~0;
if (hw[dw] == 0) {
dw++;
@@ -1114,11 +1132,19 @@ static struct i915_vma *load_context(struct intel_context *ce, u32 poison)
continue;
}
+ if (hw[dw] & MI_LRI_LRM_CS_MMIO) {
+ mask = 0xfff;
+ if (relative)
+ cmd |= MI_LRI_LRM_CS_MMIO;
+ else
+ offset = ce->engine->mmio_base;
+ }
+
dw++;
+ *cs++ = cmd | len;
len = (len + 1) / 2;
- *cs++ = MI_LOAD_REGISTER_IMM(len);
while (len--) {
- *cs++ = hw[dw];
+ *cs++ = (hw[dw] & mask) + offset;
*cs++ = poison;
dw += 2;
}
@@ -1135,14 +1161,18 @@ static struct i915_vma *load_context(struct intel_context *ce, u32 poison)
return batch;
}
-static int poison_registers(struct intel_context *ce, u32 poison, u32 *sema)
+static int
+poison_registers(struct intel_context *ce,
+ u32 poison,
+ bool relative,
+ u32 *sema)
{
struct i915_request *rq;
struct i915_vma *batch;
u32 *cs;
int err;
- batch = load_context(ce, poison);
+ batch = load_context(ce, poison, relative);
if (IS_ERR(batch))
return PTR_ERR(batch);
@@ -1192,7 +1222,7 @@ static int compare_isolation(struct intel_engine_cs *engine,
struct i915_vma *ref[2],
struct i915_vma *result[2],
struct intel_context *ce,
- u32 poison)
+ u32 poison, bool relative)
{
u32 x, dw, *hw, *lrc;
u32 *A[2], *B[2];
@@ -1241,6 +1271,7 @@ static int compare_isolation(struct intel_engine_cs *engine,
hw += LRC_STATE_OFFSET / sizeof(*hw);
do {
u32 len = hw[dw] & 0x7f;
+ bool is_relative = relative;
if (hw[dw] == 0) {
dw++;
@@ -1252,6 +1283,9 @@ static int compare_isolation(struct intel_engine_cs *engine,
continue;
}
+ if (!(hw[dw] & MI_LRI_LRM_CS_MMIO))
+ is_relative = false;
+
dw++;
len = (len + 1) / 2;
while (len--) {
@@ -1263,9 +1297,10 @@ static int compare_isolation(struct intel_engine_cs *engine,
break;
default:
- pr_err("%s[%d]: Mismatch for register %4x, default %08x, reference %08x, result (%08x, %08x), poison %08x, context %08x\n",
- engine->name, dw,
- hw[dw], hw[dw + 1],
+ pr_err("%s[%d]: Mismatch for register %4x [using relative? %s], default %08x, reference %08x, result (%08x, %08x), poison %08x, context %08x\n",
+ engine->name, dw, hw[dw],
+ yesno(is_relative),
+ hw[dw + 1],
A[0][x], B[0][x], B[1][x],
poison, lrc[dw + 1]);
err = -EINVAL;
@@ -1291,7 +1326,8 @@ static int compare_isolation(struct intel_engine_cs *engine,
return err;
}
-static int __lrc_isolation(struct intel_engine_cs *engine, u32 poison)
+static int
+__lrc_isolation(struct intel_engine_cs *engine, u32 poison, bool relative)
{
u32 *sema = memset32(engine->status_page.addr + 1000, 0, 1);
struct i915_vma *ref[2], *result[2];
@@ -1321,7 +1357,7 @@ static int __lrc_isolation(struct intel_engine_cs *engine, u32 poison)
goto err_ref0;
}
- rq = record_registers(A, ref[0], ref[1], sema);
+ rq = record_registers(A, ref[0], ref[1], relative, sema);
if (IS_ERR(rq)) {
err = PTR_ERR(rq);
goto err_ref1;
@@ -1349,13 +1385,13 @@ static int __lrc_isolation(struct intel_engine_cs *engine, u32 poison)
goto err_result0;
}
- rq = record_registers(A, result[0], result[1], sema);
+ rq = record_registers(A, result[0], result[1], relative, sema);
if (IS_ERR(rq)) {
err = PTR_ERR(rq);
goto err_result1;
}
- err = poison_registers(B, poison, sema);
+ err = poison_registers(B, poison, relative, sema);
if (err) {
WRITE_ONCE(*sema, -1);
i915_request_put(rq);
@@ -1369,7 +1405,7 @@ static int __lrc_isolation(struct intel_engine_cs *engine, u32 poison)
}
i915_request_put(rq);
- err = compare_isolation(engine, ref, result, A, poison);
+ err = compare_isolation(engine, ref, result, A, poison, relative);
err_result1:
i915_vma_put(result[1]);
@@ -1431,13 +1467,23 @@ static int live_lrc_isolation(void *arg)
for (i = 0; i < ARRAY_SIZE(poison); i++) {
int result;
- result = __lrc_isolation(engine, poison[i]);
+ result = __lrc_isolation(engine, poison[i], false);
if (result && !err)
err = result;
- result = __lrc_isolation(engine, ~poison[i]);
+ result = __lrc_isolation(engine, ~poison[i], false);
if (result && !err)
err = result;
+
+ if (intel_engine_has_relative_mmio(engine)) {
+ result = __lrc_isolation(engine, poison[i], true);
+ if (result && !err)
+ err = result;
+
+ result = __lrc_isolation(engine, ~poison[i], true);
+ if (result && !err)
+ err = result;
+ }
}
intel_engine_pm_put(engine);
if (igt_flush_test(gt->i915)) {
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Intel-gfx] [PATCH v2 2/2] drm/i915/selftests: Exercise cross-process context isolation
2021-01-14 10:38 [Intel-gfx] [PATCH v2 1/2] drm/i915/selftests: Exercise relative mmio paths to non-privileged registers Chris Wilson
@ 2021-01-14 10:38 ` Chris Wilson
2021-01-14 13:39 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/selftests: Exercise relative mmio paths to non-privileged registers Patchwork
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Chris Wilson @ 2021-01-14 10:38 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
Verify that one context running on engine A cannot manipulate another
client's context concurrently running on engine B using unprivileged
access.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 275 +++++++++++++++++++++----
1 file changed, 238 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index a55cbf524692..319ec19bcf30 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -912,6 +912,7 @@ create_user_vma(struct i915_address_space *vm, unsigned long size)
static struct i915_vma *
store_context(struct intel_context *ce,
+ struct intel_engine_cs *engine,
struct i915_vma *scratch,
bool relative)
{
@@ -929,7 +930,7 @@ store_context(struct intel_context *ce,
return ERR_CAST(cs);
}
- defaults = shmem_pin_map(ce->engine->default_state);
+ defaults = shmem_pin_map(engine->default_state);
if (!defaults) {
i915_gem_object_unpin_map(batch->obj);
i915_vma_put(batch);
@@ -961,7 +962,7 @@ store_context(struct intel_context *ce,
if (relative)
cmd |= MI_LRI_LRM_CS_MMIO;
else
- offset = ce->engine->mmio_base;
+ offset = engine->mmio_base;
}
dw++;
@@ -980,7 +981,7 @@ store_context(struct intel_context *ce,
*cs++ = MI_BATCH_BUFFER_END;
- shmem_unpin_map(ce->engine->default_state, defaults);
+ shmem_unpin_map(engine->default_state, defaults);
i915_gem_object_flush_map(batch->obj);
i915_gem_object_unpin_map(batch->obj);
@@ -1003,23 +1004,48 @@ static int move_to_active(struct i915_request *rq,
return err;
}
+struct hwsp_semaphore {
+ u32 ggtt;
+ u32 *va;
+};
+
+static struct hwsp_semaphore hwsp_semaphore(struct intel_engine_cs *engine)
+{
+ struct hwsp_semaphore s;
+
+ s.va = memset32(engine->status_page.addr + 1000, 0, 1);
+ s.ggtt = (i915_ggtt_offset(engine->status_page.vma) +
+ offset_in_page(s.va));
+
+ return s;
+}
+
+static u32 *emit_noops(u32 *cs, int count)
+{
+ while (count--)
+ *cs++ = MI_NOOP;
+
+ return cs;
+}
+
static struct i915_request *
record_registers(struct intel_context *ce,
+ struct intel_engine_cs *engine,
struct i915_vma *before,
struct i915_vma *after,
bool relative,
- u32 *sema)
+ const struct hwsp_semaphore *sema)
{
struct i915_vma *b_before, *b_after;
struct i915_request *rq;
u32 *cs;
int err;
- b_before = store_context(ce, before, relative);
+ b_before = store_context(ce, engine, before, relative);
if (IS_ERR(b_before))
return ERR_CAST(b_before);
- b_after = store_context(ce, after, relative);
+ b_after = store_context(ce, engine, after, relative);
if (IS_ERR(b_after)) {
rq = ERR_CAST(b_after);
goto err_before;
@@ -1045,7 +1071,7 @@ record_registers(struct intel_context *ce,
if (err)
goto err_rq;
- cs = intel_ring_begin(rq, 14);
+ cs = intel_ring_begin(rq, 18);
if (IS_ERR(cs)) {
err = PTR_ERR(cs);
goto err_rq;
@@ -1056,16 +1082,28 @@ record_registers(struct intel_context *ce,
*cs++ = lower_32_bits(b_before->node.start);
*cs++ = upper_32_bits(b_before->node.start);
- *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
- *cs++ = MI_SEMAPHORE_WAIT |
- MI_SEMAPHORE_GLOBAL_GTT |
- MI_SEMAPHORE_POLL |
- MI_SEMAPHORE_SAD_NEQ_SDD;
- *cs++ = 0;
- *cs++ = i915_ggtt_offset(ce->engine->status_page.vma) +
- offset_in_page(sema);
- *cs++ = 0;
- *cs++ = MI_NOOP;
+ if (sema) {
+ WRITE_ONCE(*sema->va, -1);
+
+ /* Signal the poisoner */
+ *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
+ *cs++ = sema->ggtt;
+ *cs++ = 0;
+ *cs++ = 0;
+
+ /* Then wait for the poison to settle */
+ *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
+ *cs++ = MI_SEMAPHORE_WAIT |
+ MI_SEMAPHORE_GLOBAL_GTT |
+ MI_SEMAPHORE_POLL |
+ MI_SEMAPHORE_SAD_NEQ_SDD;
+ *cs++ = 0;
+ *cs++ = sema->ggtt;
+ *cs++ = 0;
+ *cs++ = MI_NOOP;
+ } else {
+ cs = emit_noops(cs, 10);
+ }
*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
*cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8);
@@ -1074,7 +1112,6 @@ record_registers(struct intel_context *ce,
intel_ring_advance(rq, cs);
- WRITE_ONCE(*sema, 0);
i915_request_get(rq);
i915_request_add(rq);
err_after:
@@ -1090,7 +1127,9 @@ record_registers(struct intel_context *ce,
}
static struct i915_vma *
-load_context(struct intel_context *ce, u32 poison, bool relative)
+load_context(struct intel_context *ce,
+ struct intel_engine_cs *engine,
+ u32 poison, bool relative)
{
struct i915_vma *batch;
u32 dw, *cs, *hw;
@@ -1106,7 +1145,7 @@ load_context(struct intel_context *ce, u32 poison, bool relative)
return ERR_CAST(cs);
}
- defaults = shmem_pin_map(ce->engine->default_state);
+ defaults = shmem_pin_map(engine->default_state);
if (!defaults) {
i915_gem_object_unpin_map(batch->obj);
i915_vma_put(batch);
@@ -1137,7 +1176,7 @@ load_context(struct intel_context *ce, u32 poison, bool relative)
if (relative)
cmd |= MI_LRI_LRM_CS_MMIO;
else
- offset = ce->engine->mmio_base;
+ offset = engine->mmio_base;
}
dw++;
@@ -1153,7 +1192,7 @@ load_context(struct intel_context *ce, u32 poison, bool relative)
*cs++ = MI_BATCH_BUFFER_END;
- shmem_unpin_map(ce->engine->default_state, defaults);
+ shmem_unpin_map(engine->default_state, defaults);
i915_gem_object_flush_map(batch->obj);
i915_gem_object_unpin_map(batch->obj);
@@ -1163,16 +1202,17 @@ load_context(struct intel_context *ce, u32 poison, bool relative)
static int
poison_registers(struct intel_context *ce,
+ struct intel_engine_cs *engine,
u32 poison,
bool relative,
- u32 *sema)
+ const struct hwsp_semaphore *sema)
{
struct i915_request *rq;
struct i915_vma *batch;
u32 *cs;
int err;
- batch = load_context(ce, poison, relative);
+ batch = load_context(ce, engine, poison, relative);
if (IS_ERR(batch))
return PTR_ERR(batch);
@@ -1186,20 +1226,29 @@ poison_registers(struct intel_context *ce,
if (err)
goto err_rq;
- cs = intel_ring_begin(rq, 8);
+ cs = intel_ring_begin(rq, 14);
if (IS_ERR(cs)) {
err = PTR_ERR(cs);
goto err_rq;
}
+ *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
+ *cs++ = MI_SEMAPHORE_WAIT |
+ MI_SEMAPHORE_GLOBAL_GTT |
+ MI_SEMAPHORE_POLL |
+ MI_SEMAPHORE_SAD_EQ_SDD;
+ *cs++ = 0;
+ *cs++ = sema->ggtt;
+ *cs++ = 0;
+ *cs++ = MI_NOOP;
+
*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
*cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8);
*cs++ = lower_32_bits(batch->node.start);
*cs++ = upper_32_bits(batch->node.start);
*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
- *cs++ = i915_ggtt_offset(ce->engine->status_page.vma) +
- offset_in_page(sema);
+ *cs++ = sema->ggtt;
*cs++ = 0;
*cs++ = 1;
@@ -1259,7 +1308,7 @@ static int compare_isolation(struct intel_engine_cs *engine,
}
lrc += LRC_STATE_OFFSET / sizeof(*hw);
- defaults = shmem_pin_map(ce->engine->default_state);
+ defaults = shmem_pin_map(engine->default_state);
if (!defaults) {
err = -ENOMEM;
goto err_lrc;
@@ -1312,7 +1361,7 @@ static int compare_isolation(struct intel_engine_cs *engine,
} while (dw < PAGE_SIZE / sizeof(u32) &&
(hw[dw] & ~BIT(0)) != MI_BATCH_BUFFER_END);
- shmem_unpin_map(ce->engine->default_state, defaults);
+ shmem_unpin_map(engine->default_state, defaults);
err_lrc:
i915_gem_object_unpin_map(ce->state->obj);
err_B1:
@@ -1329,7 +1378,7 @@ static int compare_isolation(struct intel_engine_cs *engine,
static int
__lrc_isolation(struct intel_engine_cs *engine, u32 poison, bool relative)
{
- u32 *sema = memset32(engine->status_page.addr + 1000, 0, 1);
+ struct hwsp_semaphore sema = hwsp_semaphore(engine);
struct i915_vma *ref[2], *result[2];
struct intel_context *A, *B;
struct i915_request *rq;
@@ -1357,15 +1406,12 @@ __lrc_isolation(struct intel_engine_cs *engine, u32 poison, bool relative)
goto err_ref0;
}
- rq = record_registers(A, ref[0], ref[1], relative, sema);
+ rq = record_registers(A, engine, ref[0], ref[1], relative, NULL);
if (IS_ERR(rq)) {
err = PTR_ERR(rq);
goto err_ref1;
}
- WRITE_ONCE(*sema, 1);
- wmb();
-
if (i915_request_wait(rq, 0, HZ / 2) < 0) {
i915_request_put(rq);
err = -ETIME;
@@ -1385,15 +1431,15 @@ __lrc_isolation(struct intel_engine_cs *engine, u32 poison, bool relative)
goto err_result0;
}
- rq = record_registers(A, result[0], result[1], relative, sema);
+ rq = record_registers(A, engine, result[0], result[1], relative, &sema);
if (IS_ERR(rq)) {
err = PTR_ERR(rq);
goto err_result1;
}
- err = poison_registers(B, poison, relative, sema);
+ err = poison_registers(B, engine, poison, relative, &sema);
if (err) {
- WRITE_ONCE(*sema, -1);
+ WRITE_ONCE(*sema.va, -1);
i915_request_put(rq);
goto err_result1;
}
@@ -1495,6 +1541,160 @@ static int live_lrc_isolation(void *arg)
return err;
}
+static int __lrc_cross(struct intel_engine_cs *a,
+ struct intel_engine_cs *b,
+ u32 poison)
+{
+ struct hwsp_semaphore sema = hwsp_semaphore(a);
+ struct i915_vma *ref[2], *result[2];
+ struct intel_context *A, *B;
+ struct i915_request *rq;
+ int err;
+
+ GEM_BUG_ON(a->gt->ggtt != b->gt->ggtt);
+
+ pr_debug("Context on %s, poisoning from %s with %08x\n",
+ a->name, b->name, poison);
+
+ A = intel_context_create(a);
+ if (IS_ERR(A))
+ return PTR_ERR(A);
+
+ B = intel_context_create(b);
+ if (IS_ERR(B)) {
+ err = PTR_ERR(B);
+ goto err_A;
+ }
+
+ ref[0] = create_user_vma(A->vm, SZ_64K);
+ if (IS_ERR(ref[0])) {
+ err = PTR_ERR(ref[0]);
+ goto err_B;
+ }
+
+ ref[1] = create_user_vma(A->vm, SZ_64K);
+ if (IS_ERR(ref[1])) {
+ err = PTR_ERR(ref[1]);
+ goto err_ref0;
+ }
+
+ rq = record_registers(A, a, ref[0], ref[1], false, NULL);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto err_ref1;
+ }
+
+ if (i915_request_wait(rq, 0, HZ / 2) < 0) {
+ i915_request_put(rq);
+ err = -ETIME;
+ goto err_ref1;
+ }
+ i915_request_put(rq);
+
+ result[0] = create_user_vma(A->vm, SZ_64K);
+ if (IS_ERR(result[0])) {
+ err = PTR_ERR(result[0]);
+ goto err_ref1;
+ }
+
+ result[1] = create_user_vma(A->vm, SZ_64K);
+ if (IS_ERR(result[1])) {
+ err = PTR_ERR(result[1]);
+ goto err_result0;
+ }
+
+ rq = record_registers(A, a, result[0], result[1], false, &sema);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto err_result1;
+ }
+
+ err = poison_registers(B, a, poison, false, &sema);
+ if (err) {
+ WRITE_ONCE(*sema.va, -1);
+ i915_request_put(rq);
+ goto err_result1;
+ }
+
+ if (i915_request_wait(rq, 0, HZ / 2) < 0) {
+ i915_request_put(rq);
+ err = -ETIME;
+ goto err_result1;
+ }
+ i915_request_put(rq);
+
+ err = compare_isolation(a, ref, result, A, poison, false);
+
+err_result1:
+ i915_vma_put(result[1]);
+err_result0:
+ i915_vma_put(result[0]);
+err_ref1:
+ i915_vma_put(ref[1]);
+err_ref0:
+ i915_vma_put(ref[0]);
+err_B:
+ intel_context_put(B);
+err_A:
+ intel_context_put(A);
+ return err;
+}
+
+static int live_lrc_cross(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *a, *b;
+ enum intel_engine_id a_id, b_id;
+ const u32 poison[] = {
+ STACK_MAGIC,
+ 0x3a3a3a3a,
+ 0x5c5c5c5c,
+ 0xffffffff,
+ 0xffff0000,
+ };
+ int err = 0;
+ int i;
+
+ /*
+ * Our goal is to try and tamper with another client's context
+ * running concurrently. The HW's goal is to stop us.
+ */
+
+ for_each_engine(a, gt, a_id) {
+ if (!IS_ENABLED(CONFIG_DRM_I915_SELFTEST_BROKEN) &&
+ skip_isolation(a))
+ continue;
+
+ intel_engine_pm_get(a);
+ for_each_engine(b, gt, b_id) {
+ if (a == b)
+ continue;
+
+ intel_engine_pm_get(b);
+ for (i = 0; i < ARRAY_SIZE(poison); i++) {
+ int result;
+
+ result = __lrc_cross(a, b, poison[i]);
+ if (result && !err)
+ err = result;
+
+ result = __lrc_cross(a, b, ~poison[i]);
+ if (result && !err)
+ err = result;
+ }
+ intel_engine_pm_put(b);
+ }
+ intel_engine_pm_put(a);
+
+ if (igt_flush_test(gt->i915)) {
+ err = -EIO;
+ break;
+ }
+ }
+
+ return err;
+}
+
static int indirect_ctx_submit_req(struct intel_context *ce)
{
struct i915_request *rq;
@@ -1885,6 +2085,7 @@ int intel_lrc_live_selftests(struct drm_i915_private *i915)
SUBTEST(live_lrc_isolation),
SUBTEST(live_lrc_timestamp),
SUBTEST(live_lrc_garbage),
+ SUBTEST(live_lrc_cross),
SUBTEST(live_pphwsp_runtime),
SUBTEST(live_lrc_indirect_ctx_bb),
};
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/selftests: Exercise relative mmio paths to non-privileged registers
2021-01-14 10:38 [Intel-gfx] [PATCH v2 1/2] drm/i915/selftests: Exercise relative mmio paths to non-privileged registers Chris Wilson
2021-01-14 10:38 ` [Intel-gfx] [PATCH v2 2/2] drm/i915/selftests: Exercise cross-process context isolation Chris Wilson
@ 2021-01-14 13:39 ` Patchwork
2021-01-14 18:29 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-01-19 18:01 ` [Intel-gfx] [PATCH v2 1/2] " Matt Roper
3 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2021-01-14 13:39 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 3114 bytes --]
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/selftests: Exercise relative mmio paths to non-privileged registers
URL : https://patchwork.freedesktop.org/series/85865/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9607 -> Patchwork_19354
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/index.html
Known issues
------------
Here are the changes found in Patchwork_19354 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_hangman@error-state-basic:
- fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#402])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/fi-tgl-y/igt@i915_hangman@error-state-basic.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/fi-tgl-y/igt@i915_hangman@error-state-basic.html
* igt@i915_selftest@live@active:
- fi-kbl-soraka: [PASS][3] -> [DMESG-FAIL][4] ([i915#2291] / [i915#666])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/fi-kbl-soraka/igt@i915_selftest@live@active.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/fi-kbl-soraka/igt@i915_selftest@live@active.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7500u: [PASS][5] -> [FAIL][6] ([i915#2128])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
#### Possible fixes ####
* igt@gem_render_tiled_blits@basic:
- fi-tgl-y: [DMESG-WARN][7] ([i915#402]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/fi-tgl-y/igt@gem_render_tiled_blits@basic.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/fi-tgl-y/igt@gem_render_tiled_blits@basic.html
[i915#2128]: https://gitlab.freedesktop.org/drm/intel/issues/2128
[i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#666]: https://gitlab.freedesktop.org/drm/intel/issues/666
Participating hosts (41 -> 38)
------------------------------
Missing (3): fi-ctg-p8600 fi-bsw-cyan fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9607 -> Patchwork_19354
CI-20190529: 20190529
CI_DRM_9607: 1cd1433e50924f963a31d50a0bfcccb1f872544f @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5957: 2a2b3418f7458dfa1fac255cc5c71603f617690a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19354: 633f3050f2b666de909387521bc86f0df7e11f81 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
633f3050f2b6 drm/i915/selftests: Exercise cross-process context isolation
e31030c86d7e drm/i915/selftests: Exercise relative mmio paths to non-privileged registers
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/index.html
[-- Attachment #1.2: Type: text/html, Size: 3871 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v2,1/2] drm/i915/selftests: Exercise relative mmio paths to non-privileged registers
2021-01-14 10:38 [Intel-gfx] [PATCH v2 1/2] drm/i915/selftests: Exercise relative mmio paths to non-privileged registers Chris Wilson
2021-01-14 10:38 ` [Intel-gfx] [PATCH v2 2/2] drm/i915/selftests: Exercise cross-process context isolation Chris Wilson
2021-01-14 13:39 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/selftests: Exercise relative mmio paths to non-privileged registers Patchwork
@ 2021-01-14 18:29 ` Patchwork
2021-01-19 18:01 ` [Intel-gfx] [PATCH v2 1/2] " Matt Roper
3 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2021-01-14 18:29 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 22652 bytes --]
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/selftests: Exercise relative mmio paths to non-privileged registers
URL : https://patchwork.freedesktop.org/series/85865/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9607_full -> Patchwork_19354_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_19354_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@drm_import_export@flink:
- shard-glk: [PASS][1] -> [INCOMPLETE][2] ([i915#2369])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-glk5/igt@drm_import_export@flink.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-glk8/igt@drm_import_export@flink.html
* igt@gem_ctx_persistence@smoketest:
- shard-tglb: [PASS][3] -> [FAIL][4] ([i915#2896])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-tglb3/igt@gem_ctx_persistence@smoketest.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-tglb8/igt@gem_ctx_persistence@smoketest.html
* igt@gem_exec_reloc@basic-many-active@vcs1:
- shard-iclb: NOTRUN -> [FAIL][5] ([i915#2389])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-iclb1/igt@gem_exec_reloc@basic-many-active@vcs1.html
* igt@gem_mmap_gtt@coherency:
- shard-iclb: NOTRUN -> [SKIP][6] ([fdo#109292])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-iclb5/igt@gem_mmap_gtt@coherency.html
* igt@i915_suspend@sysfs-reader:
- shard-iclb: [PASS][7] -> [INCOMPLETE][8] ([i915#1185])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-iclb3/igt@i915_suspend@sysfs-reader.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-iclb3/igt@i915_suspend@sysfs-reader.html
* igt@kms_ccs@pipe-c-crc-sprite-planes-basic:
- shard-skl: NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111304]) +2 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-skl4/igt@kms_ccs@pipe-c-crc-sprite-planes-basic.html
* igt@kms_chamelium@hdmi-hpd-storm-disable:
- shard-iclb: NOTRUN -> [SKIP][10] ([fdo#109284] / [fdo#111827])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-iclb5/igt@kms_chamelium@hdmi-hpd-storm-disable.html
* igt@kms_chamelium@vga-hpd:
- shard-skl: NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +9 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-skl8/igt@kms_chamelium@vga-hpd.html
* igt@kms_color_chamelium@pipe-d-ctm-max:
- shard-iclb: NOTRUN -> [SKIP][12] ([fdo#109278] / [fdo#109284] / [fdo#111827])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-iclb5/igt@kms_color_chamelium@pipe-d-ctm-max.html
* igt@kms_concurrent@pipe-c:
- shard-skl: [PASS][13] -> [DMESG-WARN][14] ([i915#1982])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-skl8/igt@kms_concurrent@pipe-c.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-skl3/igt@kms_concurrent@pipe-c.html
* igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen:
- shard-iclb: [PASS][15] -> [DMESG-WARN][16] ([i915#1226])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-iclb2/igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-iclb2/igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-64x21-offscreen:
- shard-skl: [PASS][17] -> [FAIL][18] ([i915#54]) +12 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-skl6/igt@kms_cursor_crc@pipe-c-cursor-64x21-offscreen.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-skl9/igt@kms_cursor_crc@pipe-c-cursor-64x21-offscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-512x512-offscreen:
- shard-iclb: NOTRUN -> [SKIP][19] ([fdo#109278])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-iclb5/igt@kms_cursor_crc@pipe-d-cursor-512x512-offscreen.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic:
- shard-tglb: [PASS][20] -> [FAIL][21] ([i915#2346])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-tglb2/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-tglb6/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
* igt@kms_flip@flip-vs-suspend-interruptible@b-dp1:
- shard-kbl: [PASS][22] -> [DMESG-WARN][23] ([i915#180])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html
* igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1:
- shard-skl: [PASS][24] -> [FAIL][25] ([i915#2122]) +1 similar issue
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-skl4/igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-skl5/igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs:
- shard-skl: NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#2672])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-skl10/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite:
- shard-skl: NOTRUN -> [SKIP][27] ([fdo#109271]) +86 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-skl4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-suspend:
- shard-iclb: [PASS][28] -> [INCOMPLETE][29] ([i915#1185] / [i915#123])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-render:
- shard-iclb: NOTRUN -> [SKIP][30] ([fdo#109280]) +1 similar issue
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-iclb5/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-render.html
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-d:
- shard-skl: NOTRUN -> [SKIP][31] ([fdo#109271] / [i915#533])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-skl10/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: NOTRUN -> [FAIL][32] ([fdo#108145] / [i915#265]) +1 similar issue
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_plane_lowres@pipe-c-tiling-x:
- shard-kbl: [PASS][33] -> [DMESG-WARN][34] ([i915#180] / [i915#78]) +1 similar issue
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-kbl4/igt@kms_plane_lowres@pipe-c-tiling-x.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-kbl2/igt@kms_plane_lowres@pipe-c-tiling-x.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [PASS][35] -> [SKIP][36] ([fdo#109441])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-iclb3/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@kms_vrr@flip-basic:
- shard-iclb: NOTRUN -> [SKIP][37] ([fdo#109502])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-iclb5/igt@kms_vrr@flip-basic.html
* igt@perf@polling:
- shard-skl: NOTRUN -> [FAIL][38] ([i915#1542])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-skl10/igt@perf@polling.html
* igt@perf@polling-parameterized:
- shard-tglb: [PASS][39] -> [FAIL][40] ([i915#1542])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-tglb5/igt@perf@polling-parameterized.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-tglb1/igt@perf@polling-parameterized.html
#### Possible fixes ####
* {igt@gem_exec_fair@basic-flow@rcs0}:
- shard-tglb: [FAIL][41] ([i915#2842]) -> [PASS][42] +3 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-tglb7/igt@gem_exec_fair@basic-flow@rcs0.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-tglb3/igt@gem_exec_fair@basic-flow@rcs0.html
* {igt@gem_exec_fair@basic-none-share@rcs0}:
- shard-apl: [SKIP][43] ([fdo#109271]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-apl2/igt@gem_exec_fair@basic-none-share@rcs0.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-apl6/igt@gem_exec_fair@basic-none-share@rcs0.html
* {igt@gem_exec_fair@basic-none@vcs0}:
- shard-kbl: [FAIL][45] ([i915#2842]) -> [PASS][46] +3 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-kbl4/igt@gem_exec_fair@basic-none@vcs0.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-kbl1/igt@gem_exec_fair@basic-none@vcs0.html
* {igt@gem_exec_fair@basic-pace@vecs0}:
- shard-kbl: [SKIP][47] ([fdo#109271]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-kbl7/igt@gem_exec_fair@basic-pace@vecs0.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-kbl6/igt@gem_exec_fair@basic-pace@vecs0.html
* {igt@gem_exec_fair@basic-throttle@rcs0}:
- shard-glk: [FAIL][49] ([i915#2842]) -> [PASS][50] +1 similar issue
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-glk6/igt@gem_exec_fair@basic-throttle@rcs0.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-glk1/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_parallel@engines@fds:
- shard-iclb: [INCOMPLETE][51] ([i915#2295]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-iclb5/igt@gem_exec_parallel@engines@fds.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-iclb5/igt@gem_exec_parallel@engines@fds.html
* {igt@gem_exec_schedule@u-fairslice@vcs0}:
- shard-skl: [DMESG-WARN][53] ([i915#1610] / [i915#2803]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-skl4/igt@gem_exec_schedule@u-fairslice@vcs0.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-skl5/igt@gem_exec_schedule@u-fairslice@vcs0.html
* igt@gem_exec_whisper@basic-queues-forked:
- shard-glk: [DMESG-WARN][55] ([i915#118] / [i915#95]) -> [PASS][56] +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-glk9/igt@gem_exec_whisper@basic-queues-forked.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-glk6/igt@gem_exec_whisper@basic-queues-forked.html
* {igt@gem_spin_batch@spin-each}:
- shard-skl: [FAIL][57] ([i915#2898]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-skl8/igt@gem_spin_batch@spin-each.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-skl8/igt@gem_spin_batch@spin-each.html
* igt@i915_suspend@debugfs-reader:
- shard-skl: [INCOMPLETE][59] -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-skl8/igt@i915_suspend@debugfs-reader.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-skl8/igt@i915_suspend@debugfs-reader.html
* igt@kms_color@pipe-c-degamma:
- shard-skl: [FAIL][61] ([i915#71]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-skl5/igt@kms_color@pipe-c-degamma.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-skl7/igt@kms_color@pipe-c-degamma.html
* igt@kms_concurrent@pipe-b:
- shard-kbl: [DMESG-WARN][63] ([i915#180] / [i915#78]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-kbl2/igt@kms_concurrent@pipe-b.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-kbl2/igt@kms_concurrent@pipe-b.html
* igt@kms_cursor_crc@pipe-c-cursor-64x21-random:
- shard-skl: [FAIL][65] ([i915#54]) -> [PASS][66] +6 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-skl7/igt@kms_cursor_crc@pipe-c-cursor-64x21-random.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-skl3/igt@kms_cursor_crc@pipe-c-cursor-64x21-random.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1:
- shard-apl: [FAIL][67] ([i915#79]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-apl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-apl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1.html
* igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a2:
- shard-glk: [FAIL][69] ([i915#79]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-glk9/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a2.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-glk4/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a2.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1:
- shard-skl: [FAIL][71] ([i915#2122]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-skl10/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-skl2/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-skl: [INCOMPLETE][73] ([i915#198]) -> [PASS][74] +2 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-skl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-skl10/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [FAIL][75] ([fdo#108145] / [i915#265]) -> [PASS][76] +1 similar issue
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [SKIP][77] ([fdo#109441]) -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-iclb6/igt@kms_psr@psr2_cursor_render.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
#### Warnings ####
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-iclb: [WARN][79] ([i915#2681] / [i915#2684]) -> [WARN][80] ([i915#1804] / [i915#2684])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-iclb1/igt@i915_pm_rc6_residency@rc6-fence.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-iclb7/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][81] ([i915#1804] / [i915#2684]) -> [FAIL][82] ([i915#2680] / [i915#2681])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-iclb6/igt@i915_pm_rc6_residency@rc6-idle.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-iclb1/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@runner@aborted:
- shard-kbl: [FAIL][83] ([i915#2295] / [i915#2505]) -> ([FAIL][84], [FAIL][85]) ([i915#2295])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-kbl6/igt@runner@aborted.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-kbl1/igt@runner@aborted.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-kbl3/igt@runner@aborted.html
- shard-iclb: [FAIL][86] ([i915#2295] / [i915#2724]) -> ([FAIL][87], [FAIL][88]) ([i915#2295] / [i915#2426] / [i915#2724])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-iclb2/igt@runner@aborted.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-iclb7/igt@runner@aborted.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-iclb3/igt@runner@aborted.html
- shard-glk: ([FAIL][89], [FAIL][90]) ([i915#2295] / [k.org#202321]) -> ([FAIL][91], [FAIL][92], [FAIL][93]) ([i915#2295] / [i915#2722] / [k.org#202321])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-glk7/igt@runner@aborted.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-glk5/igt@runner@aborted.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-glk4/igt@runner@aborted.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-glk8/igt@runner@aborted.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-glk8/igt@runner@aborted.html
- shard-skl: ([FAIL][94], [FAIL][95]) ([i915#2295] / [i915#2426]) -> [FAIL][96] ([i915#2295])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-skl7/igt@runner@aborted.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9607/shard-skl4/igt@runner@aborted.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/shard-skl6/igt@runner@aborted.html
### Piglit changes ###
#### Issues hit ####
* spec@glsl-1.30@execution@tex-miplevel-selection texture(bias) 2darray:
- pig-snb-2600: NOTRUN -> [FAIL][97] ([mesa#1812])
[97]: None
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109292]: https://bugs.freedesktop.org/show_bug.cgi?id=109292
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109502]: https://bugs.freedesktop.org/show_bug.cgi?id=109502
[fdo#111304]: https://bugs.freedesktop.org/show_bug.cgi?id=111304
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1185]: https://gitlab.freedesktop.org/drm/intel/issues/1185
[i915#1226]: https://gitlab.freedesktop.org/drm/intel/issues/1226
[i915#123]: https://gitlab.freedesktop.org/drm/intel/issues/123
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2369]: https://gitlab.freedesktop.org/drm/intel/issues/2369
[i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2505]: https://gitlab.freedesktop.org/drm/intel/issues/2505
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2680]: https://gitlab.freedesktop.org/drm/intel/issues/2680
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#2724]: https://gitlab.freedesktop.org/drm/intel/issues/2724
[i915#2803]: https://gitlab.freedesktop.org/drm/intel/issues/2803
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2896]: https://gitlab.freedesktop.org/drm/intel/issues/2896
[i915#2898]: https://gitlab.freedesktop.org/drm/intel/issues/2898
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#71]: https://gitlab.freedesktop.org/drm/intel/issues/71
[i915#78]: https://gitlab.freedesktop.org/drm/intel/issues/78
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
[mesa#1812]: https://gitlab.freedesktop.org/mesa/mesa/issues/1812
Participating hosts (10 -> 11)
------------------------------
Additional (1): pig-snb-2600
Build changes
-------------
* Linux: CI_DRM_9607 -> Patchwork_19354
CI-20190529: 20190529
CI_DRM_9607: 1cd1433e50924f963a31d50a0bfcccb1f872544f @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5957: 2a2b3418f7458dfa1fac255cc5c71603f617690a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19354: 633f3050f2b666de909387521bc86f0df7e11f81 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19354/index.html
[-- Attachment #1.2: Type: text/html, Size: 26814 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/selftests: Exercise relative mmio paths to non-privileged registers
2021-01-14 10:38 [Intel-gfx] [PATCH v2 1/2] drm/i915/selftests: Exercise relative mmio paths to non-privileged registers Chris Wilson
` (2 preceding siblings ...)
2021-01-14 18:29 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2021-01-19 18:01 ` Matt Roper
2021-01-20 9:43 ` Chris Wilson
3 siblings, 1 reply; 6+ messages in thread
From: Matt Roper @ 2021-01-19 18:01 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Thu, Jan 14, 2021 at 10:38:21AM +0000, Chris Wilson wrote:
> Verify that context isolation is also preserved when accessing
> context-local registers with relative-mmio commands.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/gt/selftest_lrc.c | 88 ++++++++++++++++++++------
> 1 file changed, 67 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
> index 920979a89413..a55cbf524692 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
> @@ -911,7 +911,9 @@ create_user_vma(struct i915_address_space *vm, unsigned long size)
> }
>
> static struct i915_vma *
> -store_context(struct intel_context *ce, struct i915_vma *scratch)
> +store_context(struct intel_context *ce,
> + struct i915_vma *scratch,
> + bool relative)
> {
> struct i915_vma *batch;
> u32 dw, x, *cs, *hw;
> @@ -940,6 +942,9 @@ store_context(struct intel_context *ce, struct i915_vma *scratch)
> hw += LRC_STATE_OFFSET / sizeof(*hw);
> do {
> u32 len = hw[dw] & 0x7f;
> + u32 cmd = MI_STORE_REGISTER_MEM_GEN8;
> + u32 offset = 0;
> + u32 mask = ~0;
>
> if (hw[dw] == 0) {
> dw++;
> @@ -951,11 +956,19 @@ store_context(struct intel_context *ce, struct i915_vma *scratch)
> continue;
> }
>
> + if (hw[dw] & MI_LRI_LRM_CS_MMIO) {
> + mask = 0xfff;
> + if (relative)
> + cmd |= MI_LRI_LRM_CS_MMIO;
> + else
> + offset = ce->engine->mmio_base;
> + }
Do we also need to handle bit 17 (MMIO remap) here too? E.g., a context
running on a VCS2 engine could have addresses that reference VCS0 if
this bit is set.
Matt
> +
> dw++;
> len = (len + 1) / 2;
> while (len--) {
> - *cs++ = MI_STORE_REGISTER_MEM_GEN8;
> - *cs++ = hw[dw];
> + *cs++ = cmd;
> + *cs++ = (hw[dw] & mask) + offset;
> *cs++ = lower_32_bits(scratch->node.start + x);
> *cs++ = upper_32_bits(scratch->node.start + x);
>
> @@ -994,6 +1007,7 @@ static struct i915_request *
> record_registers(struct intel_context *ce,
> struct i915_vma *before,
> struct i915_vma *after,
> + bool relative,
> u32 *sema)
> {
> struct i915_vma *b_before, *b_after;
> @@ -1001,11 +1015,11 @@ record_registers(struct intel_context *ce,
> u32 *cs;
> int err;
>
> - b_before = store_context(ce, before);
> + b_before = store_context(ce, before, relative);
> if (IS_ERR(b_before))
> return ERR_CAST(b_before);
>
> - b_after = store_context(ce, after);
> + b_after = store_context(ce, after, relative);
> if (IS_ERR(b_after)) {
> rq = ERR_CAST(b_after);
> goto err_before;
> @@ -1075,7 +1089,8 @@ record_registers(struct intel_context *ce,
> goto err_after;
> }
>
> -static struct i915_vma *load_context(struct intel_context *ce, u32 poison)
> +static struct i915_vma *
> +load_context(struct intel_context *ce, u32 poison, bool relative)
> {
> struct i915_vma *batch;
> u32 dw, *cs, *hw;
> @@ -1102,7 +1117,10 @@ static struct i915_vma *load_context(struct intel_context *ce, u32 poison)
> hw = defaults;
> hw += LRC_STATE_OFFSET / sizeof(*hw);
> do {
> + u32 cmd = MI_INSTR(0x22, 0);
> u32 len = hw[dw] & 0x7f;
> + u32 offset = 0;
> + u32 mask = ~0;
>
> if (hw[dw] == 0) {
> dw++;
> @@ -1114,11 +1132,19 @@ static struct i915_vma *load_context(struct intel_context *ce, u32 poison)
> continue;
> }
>
> + if (hw[dw] & MI_LRI_LRM_CS_MMIO) {
> + mask = 0xfff;
> + if (relative)
> + cmd |= MI_LRI_LRM_CS_MMIO;
> + else
> + offset = ce->engine->mmio_base;
> + }
> +
> dw++;
> + *cs++ = cmd | len;
> len = (len + 1) / 2;
> - *cs++ = MI_LOAD_REGISTER_IMM(len);
> while (len--) {
> - *cs++ = hw[dw];
> + *cs++ = (hw[dw] & mask) + offset;
> *cs++ = poison;
> dw += 2;
> }
> @@ -1135,14 +1161,18 @@ static struct i915_vma *load_context(struct intel_context *ce, u32 poison)
> return batch;
> }
>
> -static int poison_registers(struct intel_context *ce, u32 poison, u32 *sema)
> +static int
> +poison_registers(struct intel_context *ce,
> + u32 poison,
> + bool relative,
> + u32 *sema)
> {
> struct i915_request *rq;
> struct i915_vma *batch;
> u32 *cs;
> int err;
>
> - batch = load_context(ce, poison);
> + batch = load_context(ce, poison, relative);
> if (IS_ERR(batch))
> return PTR_ERR(batch);
>
> @@ -1192,7 +1222,7 @@ static int compare_isolation(struct intel_engine_cs *engine,
> struct i915_vma *ref[2],
> struct i915_vma *result[2],
> struct intel_context *ce,
> - u32 poison)
> + u32 poison, bool relative)
> {
> u32 x, dw, *hw, *lrc;
> u32 *A[2], *B[2];
> @@ -1241,6 +1271,7 @@ static int compare_isolation(struct intel_engine_cs *engine,
> hw += LRC_STATE_OFFSET / sizeof(*hw);
> do {
> u32 len = hw[dw] & 0x7f;
> + bool is_relative = relative;
>
> if (hw[dw] == 0) {
> dw++;
> @@ -1252,6 +1283,9 @@ static int compare_isolation(struct intel_engine_cs *engine,
> continue;
> }
>
> + if (!(hw[dw] & MI_LRI_LRM_CS_MMIO))
> + is_relative = false;
> +
> dw++;
> len = (len + 1) / 2;
> while (len--) {
> @@ -1263,9 +1297,10 @@ static int compare_isolation(struct intel_engine_cs *engine,
> break;
>
> default:
> - pr_err("%s[%d]: Mismatch for register %4x, default %08x, reference %08x, result (%08x, %08x), poison %08x, context %08x\n",
> - engine->name, dw,
> - hw[dw], hw[dw + 1],
> + pr_err("%s[%d]: Mismatch for register %4x [using relative? %s], default %08x, reference %08x, result (%08x, %08x), poison %08x, context %08x\n",
> + engine->name, dw, hw[dw],
> + yesno(is_relative),
> + hw[dw + 1],
> A[0][x], B[0][x], B[1][x],
> poison, lrc[dw + 1]);
> err = -EINVAL;
> @@ -1291,7 +1326,8 @@ static int compare_isolation(struct intel_engine_cs *engine,
> return err;
> }
>
> -static int __lrc_isolation(struct intel_engine_cs *engine, u32 poison)
> +static int
> +__lrc_isolation(struct intel_engine_cs *engine, u32 poison, bool relative)
> {
> u32 *sema = memset32(engine->status_page.addr + 1000, 0, 1);
> struct i915_vma *ref[2], *result[2];
> @@ -1321,7 +1357,7 @@ static int __lrc_isolation(struct intel_engine_cs *engine, u32 poison)
> goto err_ref0;
> }
>
> - rq = record_registers(A, ref[0], ref[1], sema);
> + rq = record_registers(A, ref[0], ref[1], relative, sema);
> if (IS_ERR(rq)) {
> err = PTR_ERR(rq);
> goto err_ref1;
> @@ -1349,13 +1385,13 @@ static int __lrc_isolation(struct intel_engine_cs *engine, u32 poison)
> goto err_result0;
> }
>
> - rq = record_registers(A, result[0], result[1], sema);
> + rq = record_registers(A, result[0], result[1], relative, sema);
> if (IS_ERR(rq)) {
> err = PTR_ERR(rq);
> goto err_result1;
> }
>
> - err = poison_registers(B, poison, sema);
> + err = poison_registers(B, poison, relative, sema);
> if (err) {
> WRITE_ONCE(*sema, -1);
> i915_request_put(rq);
> @@ -1369,7 +1405,7 @@ static int __lrc_isolation(struct intel_engine_cs *engine, u32 poison)
> }
> i915_request_put(rq);
>
> - err = compare_isolation(engine, ref, result, A, poison);
> + err = compare_isolation(engine, ref, result, A, poison, relative);
>
> err_result1:
> i915_vma_put(result[1]);
> @@ -1431,13 +1467,23 @@ static int live_lrc_isolation(void *arg)
> for (i = 0; i < ARRAY_SIZE(poison); i++) {
> int result;
>
> - result = __lrc_isolation(engine, poison[i]);
> + result = __lrc_isolation(engine, poison[i], false);
> if (result && !err)
> err = result;
>
> - result = __lrc_isolation(engine, ~poison[i]);
> + result = __lrc_isolation(engine, ~poison[i], false);
> if (result && !err)
> err = result;
> +
> + if (intel_engine_has_relative_mmio(engine)) {
> + result = __lrc_isolation(engine, poison[i], true);
> + if (result && !err)
> + err = result;
> +
> + result = __lrc_isolation(engine, ~poison[i], true);
> + if (result && !err)
> + err = result;
> + }
> }
> intel_engine_pm_put(engine);
> if (igt_flush_test(gt->i915)) {
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/selftests: Exercise relative mmio paths to non-privileged registers
2021-01-19 18:01 ` [Intel-gfx] [PATCH v2 1/2] " Matt Roper
@ 2021-01-20 9:43 ` Chris Wilson
0 siblings, 0 replies; 6+ messages in thread
From: Chris Wilson @ 2021-01-20 9:43 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
Quoting Matt Roper (2021-01-19 18:01:54)
> On Thu, Jan 14, 2021 at 10:38:21AM +0000, Chris Wilson wrote:
> > Verify that context isolation is also preserved when accessing
> > context-local registers with relative-mmio commands.
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > ---
> > drivers/gpu/drm/i915/gt/selftest_lrc.c | 88 ++++++++++++++++++++------
> > 1 file changed, 67 insertions(+), 21 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
> > index 920979a89413..a55cbf524692 100644
> > --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
> > +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
> > @@ -911,7 +911,9 @@ create_user_vma(struct i915_address_space *vm, unsigned long size)
> > }
> >
> > static struct i915_vma *
> > -store_context(struct intel_context *ce, struct i915_vma *scratch)
> > +store_context(struct intel_context *ce,
> > + struct i915_vma *scratch,
> > + bool relative)
> > {
> > struct i915_vma *batch;
> > u32 dw, x, *cs, *hw;
> > @@ -940,6 +942,9 @@ store_context(struct intel_context *ce, struct i915_vma *scratch)
> > hw += LRC_STATE_OFFSET / sizeof(*hw);
> > do {
> > u32 len = hw[dw] & 0x7f;
> > + u32 cmd = MI_STORE_REGISTER_MEM_GEN8;
> > + u32 offset = 0;
> > + u32 mask = ~0;
> >
> > if (hw[dw] == 0) {
> > dw++;
> > @@ -951,11 +956,19 @@ store_context(struct intel_context *ce, struct i915_vma *scratch)
> > continue;
> > }
> >
> > + if (hw[dw] & MI_LRI_LRM_CS_MMIO) {
> > + mask = 0xfff;
> > + if (relative)
> > + cmd |= MI_LRI_LRM_CS_MMIO;
> > + else
> > + offset = ce->engine->mmio_base;
> > + }
>
> Do we also need to handle bit 17 (MMIO remap) here too? E.g., a context
> running on a VCS2 engine could have addresses that reference VCS0 if
> this bit is set.
That bit is not used in the context images yet. I hope that is not being
ignored by selftests in the future.
As it stands, the selftests will report the discrepancy if the HW is
using another remap bit.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-01-20 9:43 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-01-14 10:38 [Intel-gfx] [PATCH v2 1/2] drm/i915/selftests: Exercise relative mmio paths to non-privileged registers Chris Wilson
2021-01-14 10:38 ` [Intel-gfx] [PATCH v2 2/2] drm/i915/selftests: Exercise cross-process context isolation Chris Wilson
2021-01-14 13:39 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/selftests: Exercise relative mmio paths to non-privileged registers Patchwork
2021-01-14 18:29 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-01-19 18:01 ` [Intel-gfx] [PATCH v2 1/2] " Matt Roper
2021-01-20 9:43 ` Chris Wilson
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