* [Intel-gfx] [PATCH 1/4] drm/i915/pps: refactor init abstractions
@ 2021-01-20 10:18 Jani Nikula
2021-01-20 10:18 ` [Intel-gfx] [PATCH 2/4] drm/i915/pps: move pps code over from intel_display.c and refactor Jani Nikula
` (6 more replies)
0 siblings, 7 replies; 13+ messages in thread
From: Jani Nikula @ 2021-01-20 10:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Once you realize there is no need to hold the pps mutex when calling
pps_init_timestamps() in intel_pps_init(), we can reuse
intel_pps_encoder_reset() which has the same code.
Since intel_dp_pps_init() is only called from one place now, move it
inline to remove one "init" function altogether.
Finally, remove some initialization from
vlv_initial_power_sequencer_setup() and do it in the caller to highlight
the similarity, not the difference, in the platforms.
v2: Fix comment (Anshuman)
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_pps.c | 37 ++++++++----------------
1 file changed, 12 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index 58eff6289d12..da6ee0b52741 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -305,9 +305,6 @@ vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
dig_port->base.base.base.id,
dig_port->base.base.name,
pipe_name(intel_dp->pps_pipe));
-
- pps_init_delays(intel_dp);
- pps_init_registers(intel_dp, false);
}
void intel_pps_reset_all(struct drm_i915_private *dev_priv)
@@ -1342,20 +1339,9 @@ static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd
(intel_de_read(dev_priv, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
}
-static void intel_dp_pps_init(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-
- if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- vlv_initial_power_sequencer_setup(intel_dp);
- } else {
- pps_init_delays(intel_dp);
- pps_init_registers(intel_dp, false);
- }
-}
-
void intel_pps_encoder_reset(struct intel_dp *intel_dp)
{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
intel_wakeref_t wakeref;
if (!intel_dp_is_edp(intel_dp))
@@ -1363,23 +1349,24 @@ void intel_pps_encoder_reset(struct intel_dp *intel_dp)
with_intel_pps_lock(intel_dp, wakeref) {
/*
- * Reinit the power sequencer, in case BIOS did something nasty
- * with it.
+ * Reinit the power sequencer also on the resume path, in case
+ * BIOS did something nasty with it.
*/
- intel_dp_pps_init(intel_dp);
+ if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
+ vlv_initial_power_sequencer_setup(intel_dp);
+
+ pps_init_delays(intel_dp);
+ pps_init_registers(intel_dp, false);
+
intel_pps_vdd_sanitize(intel_dp);
}
}
void intel_pps_init(struct intel_dp *intel_dp)
{
- intel_wakeref_t wakeref;
-
INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work);
- with_intel_pps_lock(intel_dp, wakeref) {
- pps_init_timestamps(intel_dp);
- intel_dp_pps_init(intel_dp);
- intel_pps_vdd_sanitize(intel_dp);
- }
+ pps_init_timestamps(intel_dp);
+
+ intel_pps_encoder_reset(intel_dp);
}
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [Intel-gfx] [PATCH 2/4] drm/i915/pps: move pps code over from intel_display.c and refactor
2021-01-20 10:18 [Intel-gfx] [PATCH 1/4] drm/i915/pps: refactor init abstractions Jani Nikula
@ 2021-01-20 10:18 ` Jani Nikula
2021-01-20 10:18 ` [Intel-gfx] [PATCH 3/4] drm/i915/dp: abstract struct intel_dp pps members to a sub-struct Jani Nikula
` (5 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Jani Nikula @ 2021-01-20 10:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
intel_display.c has some pps functions that belong to intel_pps.c. Move
them over.
While at it, refactor the duplicate intel_pps_init() in intel_display.c
into an orthogonal intel_pps_setup() in intel_pps.c, and call it earlier
in intel_modeset_init_nogem().
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 41 ++------------------
drivers/gpu/drm/i915/display/intel_display.h | 1 -
drivers/gpu/drm/i915/display/intel_pps.c | 34 ++++++++++++++++
drivers/gpu/drm/i915/display/intel_pps.h | 3 ++
drivers/gpu/drm/i915/i915_drv.c | 1 +
5 files changed, 42 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7373f54b216e..20c087552a95 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -83,6 +83,7 @@
#include "intel_overlay.h"
#include "intel_pipe_crc.h"
#include "intel_pm.h"
+#include "intel_pps.h"
#include "intel_psr.h"
#include "intel_quirks.h"
#include "intel_sideband.h"
@@ -13791,48 +13792,12 @@ static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
return true;
}
-void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
-{
- int pps_num;
- int pps_idx;
-
- if (HAS_DDI(dev_priv))
- return;
- /*
- * This w/a is needed at least on CPT/PPT, but to be sure apply it
- * everywhere where registers can be write protected.
- */
- if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- pps_num = 2;
- else
- pps_num = 1;
-
- for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
- u32 val = intel_de_read(dev_priv, PP_CONTROL(pps_idx));
-
- val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
- intel_de_write(dev_priv, PP_CONTROL(pps_idx), val);
- }
-}
-
-static void intel_pps_init(struct drm_i915_private *dev_priv)
-{
- if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
- dev_priv->pps_mmio_base = PCH_PPS_BASE;
- else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- dev_priv->pps_mmio_base = VLV_PPS_BASE;
- else
- dev_priv->pps_mmio_base = PPS_BASE;
-
- intel_pps_unlock_regs_wa(dev_priv);
-}
-
static void intel_setup_outputs(struct drm_i915_private *dev_priv)
{
struct intel_encoder *encoder;
bool dpd_is_edp = false;
- intel_pps_init(dev_priv);
+ intel_pps_unlock_regs_wa(dev_priv);
if (!HAS_DISPLAY(dev_priv))
return;
@@ -14844,6 +14809,8 @@ int intel_modeset_init_nogem(struct drm_i915_private *i915)
intel_panel_sanitize_ssc(i915);
+ intel_pps_setup(i915);
+
intel_gmbus_setup(i915);
drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n",
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index bb72de152949..64ffa34544a7 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -546,7 +546,6 @@ unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info
unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info);
bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
int intel_display_suspend(struct drm_device *dev);
-void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
void intel_encoder_destroy(struct drm_encoder *encoder);
struct drm_display_mode *
intel_encoder_current_mode(struct intel_encoder *encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index da6ee0b52741..69d9d41b6d22 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -1370,3 +1370,37 @@ void intel_pps_init(struct intel_dp *intel_dp)
intel_pps_encoder_reset(intel_dp);
}
+
+void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
+{
+ int pps_num;
+ int pps_idx;
+
+ if (HAS_DDI(dev_priv))
+ return;
+ /*
+ * This w/a is needed at least on CPT/PPT, but to be sure apply it
+ * everywhere where registers can be write protected.
+ */
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
+ pps_num = 2;
+ else
+ pps_num = 1;
+
+ for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
+ u32 val = intel_de_read(dev_priv, PP_CONTROL(pps_idx));
+
+ val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
+ intel_de_write(dev_priv, PP_CONTROL(pps_idx), val);
+ }
+}
+
+void intel_pps_setup(struct drm_i915_private *i915)
+{
+ if (HAS_PCH_SPLIT(i915) || IS_GEN9_LP(i915))
+ i915->pps_mmio_base = PCH_PPS_BASE;
+ else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
+ i915->pps_mmio_base = VLV_PPS_BASE;
+ else
+ i915->pps_mmio_base = PPS_BASE;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_pps.h b/drivers/gpu/drm/i915/display/intel_pps.h
index 22045c5cdc86..fbbcca782e7b 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.h
+++ b/drivers/gpu/drm/i915/display/intel_pps.h
@@ -46,4 +46,7 @@ void intel_pps_reset_all(struct drm_i915_private *i915);
void vlv_pps_init(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
+void intel_pps_unlock_regs_wa(struct drm_i915_private *i915);
+void intel_pps_setup(struct drm_i915_private *i915);
+
#endif /* __INTEL_PPS_H__ */
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index f5666b44ea9d..b37b189e219c 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -58,6 +58,7 @@
#include "display/intel_hotplug.h"
#include "display/intel_overlay.h"
#include "display/intel_pipe_crc.h"
+#include "display/intel_pps.h"
#include "display/intel_sprite.h"
#include "display/intel_vga.h"
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [Intel-gfx] [PATCH 3/4] drm/i915/dp: abstract struct intel_dp pps members to a sub-struct
2021-01-20 10:18 [Intel-gfx] [PATCH 1/4] drm/i915/pps: refactor init abstractions Jani Nikula
2021-01-20 10:18 ` [Intel-gfx] [PATCH 2/4] drm/i915/pps: move pps code over from intel_display.c and refactor Jani Nikula
@ 2021-01-20 10:18 ` Jani Nikula
2021-01-20 17:30 ` Rodrigo Vivi
2021-01-20 10:18 ` [Intel-gfx] [PATCH 4/4] drm/i915/dp: split out aux functionality to intel_dp_aux.c Jani Nikula
` (4 subsequent siblings)
6 siblings, 1 reply; 13+ messages in thread
From: Jani Nikula @ 2021-01-20 10:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Add some namespacing to highlight what belongs where. No functional
changes.
Cc: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../drm/i915/display/intel_display_debugfs.c | 8 +-
.../drm/i915/display/intel_display_types.h | 61 +++---
drivers/gpu/drm/i915/display/intel_dp.c | 14 +-
drivers/gpu/drm/i915/display/intel_pps.c | 192 +++++++++---------
4 files changed, 140 insertions(+), 135 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index cd7e5519ee7d..885d2d3c91a3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -2155,13 +2155,13 @@ static int i915_panel_show(struct seq_file *m, void *data)
return -ENODEV;
seq_printf(m, "Panel power up delay: %d\n",
- intel_dp->panel_power_up_delay);
+ intel_dp->pps.panel_power_up_delay);
seq_printf(m, "Panel power down delay: %d\n",
- intel_dp->panel_power_down_delay);
+ intel_dp->pps.panel_power_down_delay);
seq_printf(m, "Backlight on delay: %d\n",
- intel_dp->backlight_on_delay);
+ intel_dp->pps.backlight_on_delay);
seq_printf(m, "Backlight off delay: %d\n",
- intel_dp->backlight_off_delay);
+ intel_dp->pps.backlight_off_delay);
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index b601e804f854..1a9243426a25 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1369,6 +1369,38 @@ struct intel_dp_pcon_frl {
int trained_rate_gbps;
};
+struct intel_pps {
+ int panel_power_up_delay;
+ int panel_power_down_delay;
+ int panel_power_cycle_delay;
+ int backlight_on_delay;
+ int backlight_off_delay;
+ struct delayed_work panel_vdd_work;
+ bool want_panel_vdd;
+ unsigned long last_power_on;
+ unsigned long last_backlight_off;
+ ktime_t panel_power_off_time;
+ intel_wakeref_t vdd_wakeref;
+
+ /*
+ * Pipe whose power sequencer is currently locked into
+ * this port. Only relevant on VLV/CHV.
+ */
+ enum pipe pps_pipe;
+ /*
+ * Pipe currently driving the port. Used for preventing
+ * the use of the PPS for any pipe currentrly driving
+ * external DP as that will mess things up on VLV.
+ */
+ enum pipe active_pipe;
+ /*
+ * Set if the sequencer may be reset due to a power transition,
+ * requiring a reinitialization. Only relevant on BXT.
+ */
+ bool pps_reset;
+ struct edp_power_seq pps_delays;
+};
+
struct intel_dp {
i915_reg_t output_reg;
u32 DP;
@@ -1408,35 +1440,8 @@ struct intel_dp {
struct drm_dp_aux aux;
u32 aux_busy_last_status;
u8 train_set[4];
- int panel_power_up_delay;
- int panel_power_down_delay;
- int panel_power_cycle_delay;
- int backlight_on_delay;
- int backlight_off_delay;
- struct delayed_work panel_vdd_work;
- bool want_panel_vdd;
- unsigned long last_power_on;
- unsigned long last_backlight_off;
- ktime_t panel_power_off_time;
- intel_wakeref_t vdd_wakeref;
- /*
- * Pipe whose power sequencer is currently locked into
- * this port. Only relevant on VLV/CHV.
- */
- enum pipe pps_pipe;
- /*
- * Pipe currently driving the port. Used for preventing
- * the use of the PPS for any pipe currentrly driving
- * external DP as that will mess things up on VLV.
- */
- enum pipe active_pipe;
- /*
- * Set if the sequencer may be reset due to a power transition,
- * requiring a reinitialization. Only relevant on BXT.
- */
- bool pps_reset;
- struct edp_power_seq pps_delays;
+ struct intel_pps pps;
bool can_mst; /* this port supports mst */
bool is_mst;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 8b9c20555f0e..d815087a26aa 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4129,7 +4129,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
}
- msleep(intel_dp->panel_power_down_delay);
+ msleep(intel_dp->pps.panel_power_down_delay);
intel_dp->DP = DP;
@@ -4137,7 +4137,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
intel_wakeref_t wakeref;
with_intel_pps_lock(intel_dp, wakeref)
- intel_dp->active_pipe = INVALID_PIPE;
+ intel_dp->pps.active_pipe = INVALID_PIPE;
}
}
@@ -6368,7 +6368,7 @@ void intel_dp_encoder_reset(struct drm_encoder *encoder)
intel_wakeref_t wakeref;
with_intel_pps_lock(intel_dp, wakeref)
- intel_dp->active_pipe = vlv_active_pipe(intel_dp);
+ intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
}
intel_pps_encoder_reset(intel_dp);
@@ -7139,7 +7139,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
pipe = vlv_active_pipe(intel_dp);
if (pipe != PIPE_A && pipe != PIPE_B)
- pipe = intel_dp->pps_pipe;
+ pipe = intel_dp->pps.pps_pipe;
if (pipe != PIPE_A && pipe != PIPE_B)
pipe = PIPE_A;
@@ -7216,8 +7216,8 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
intel_dp_set_source_rates(intel_dp);
intel_dp->reset_link_params = true;
- intel_dp->pps_pipe = INVALID_PIPE;
- intel_dp->active_pipe = INVALID_PIPE;
+ intel_dp->pps.pps_pipe = INVALID_PIPE;
+ intel_dp->pps.active_pipe = INVALID_PIPE;
/* Preserve the current hw state. */
intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
@@ -7235,7 +7235,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
}
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- intel_dp->active_pipe = vlv_active_pipe(intel_dp);
+ intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
/*
* For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index 69d9d41b6d22..c4867a8020a5 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -44,7 +44,7 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- enum pipe pipe = intel_dp->pps_pipe;
+ enum pipe pipe = intel_dp->pps.pps_pipe;
bool pll_enabled, release_cl_override = false;
enum dpio_phy phy = DPIO_PHY(pipe);
enum dpio_channel ch = vlv_pipe_to_channel(pipe);
@@ -130,18 +130,18 @@ static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
if (encoder->type == INTEL_OUTPUT_EDP) {
drm_WARN_ON(&dev_priv->drm,
- intel_dp->active_pipe != INVALID_PIPE &&
- intel_dp->active_pipe !=
- intel_dp->pps_pipe);
+ intel_dp->pps.active_pipe != INVALID_PIPE &&
+ intel_dp->pps.active_pipe !=
+ intel_dp->pps.pps_pipe);
- if (intel_dp->pps_pipe != INVALID_PIPE)
- pipes &= ~(1 << intel_dp->pps_pipe);
+ if (intel_dp->pps.pps_pipe != INVALID_PIPE)
+ pipes &= ~(1 << intel_dp->pps.pps_pipe);
} else {
drm_WARN_ON(&dev_priv->drm,
- intel_dp->pps_pipe != INVALID_PIPE);
+ intel_dp->pps.pps_pipe != INVALID_PIPE);
- if (intel_dp->active_pipe != INVALID_PIPE)
- pipes &= ~(1 << intel_dp->active_pipe);
+ if (intel_dp->pps.active_pipe != INVALID_PIPE)
+ pipes &= ~(1 << intel_dp->pps.active_pipe);
}
}
@@ -163,11 +163,11 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
/* We should never land here with regular DP ports */
drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
- drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE &&
- intel_dp->active_pipe != intel_dp->pps_pipe);
+ drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE &&
+ intel_dp->pps.active_pipe != intel_dp->pps.pps_pipe);
- if (intel_dp->pps_pipe != INVALID_PIPE)
- return intel_dp->pps_pipe;
+ if (intel_dp->pps.pps_pipe != INVALID_PIPE)
+ return intel_dp->pps.pps_pipe;
pipe = vlv_find_free_pps(dev_priv);
@@ -179,11 +179,11 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
pipe = PIPE_A;
vlv_steal_power_sequencer(dev_priv, pipe);
- intel_dp->pps_pipe = pipe;
+ intel_dp->pps.pps_pipe = pipe;
drm_dbg_kms(&dev_priv->drm,
"picked pipe %c power sequencer for [ENCODER:%d:%s]\n",
- pipe_name(intel_dp->pps_pipe),
+ pipe_name(intel_dp->pps.pps_pipe),
dig_port->base.base.base.id,
dig_port->base.base.name);
@@ -197,7 +197,7 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
*/
vlv_power_sequencer_kick(intel_dp);
- return intel_dp->pps_pipe;
+ return intel_dp->pps.pps_pipe;
}
static int
@@ -211,10 +211,10 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp)
/* We should never land here with regular DP ports */
drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
- if (!intel_dp->pps_reset)
+ if (!intel_dp->pps.pps_reset)
return backlight_controller;
- intel_dp->pps_reset = false;
+ intel_dp->pps.pps_reset = false;
/*
* Only the HW needs to be reprogrammed, the SW state is fixed and
@@ -280,19 +280,19 @@ vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
/* try to find a pipe with this port selected */
/* first pick one where the panel is on */
- intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
- vlv_pipe_has_pp_on);
+ intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
+ vlv_pipe_has_pp_on);
/* didn't find one? pick one where vdd is on */
- if (intel_dp->pps_pipe == INVALID_PIPE)
- intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
- vlv_pipe_has_vdd_on);
+ if (intel_dp->pps.pps_pipe == INVALID_PIPE)
+ intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
+ vlv_pipe_has_vdd_on);
/* didn't find one? pick one with just the correct port */
- if (intel_dp->pps_pipe == INVALID_PIPE)
- intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
- vlv_pipe_any);
+ if (intel_dp->pps.pps_pipe == INVALID_PIPE)
+ intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
+ vlv_pipe_any);
/* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
- if (intel_dp->pps_pipe == INVALID_PIPE) {
+ if (intel_dp->pps.pps_pipe == INVALID_PIPE) {
drm_dbg_kms(&dev_priv->drm,
"no initial power sequencer for [ENCODER:%d:%s]\n",
dig_port->base.base.base.id,
@@ -304,7 +304,7 @@ vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
"initial power sequencer for [ENCODER:%d:%s]: pipe %c\n",
dig_port->base.base.base.id,
dig_port->base.base.name,
- pipe_name(intel_dp->pps_pipe));
+ pipe_name(intel_dp->pps.pps_pipe));
}
void intel_pps_reset_all(struct drm_i915_private *dev_priv)
@@ -331,15 +331,15 @@ void intel_pps_reset_all(struct drm_i915_private *dev_priv)
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
drm_WARN_ON(&dev_priv->drm,
- intel_dp->active_pipe != INVALID_PIPE);
+ intel_dp->pps.active_pipe != INVALID_PIPE);
if (encoder->type != INTEL_OUTPUT_EDP)
continue;
if (IS_GEN9_LP(dev_priv))
- intel_dp->pps_reset = true;
+ intel_dp->pps.pps_reset = true;
else
- intel_dp->pps_pipe = INVALID_PIPE;
+ intel_dp->pps.pps_pipe = INVALID_PIPE;
}
}
@@ -403,7 +403,7 @@ static bool edp_have_panel_power(struct intel_dp *intel_dp)
lockdep_assert_held(&dev_priv->pps_mutex);
if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
- intel_dp->pps_pipe == INVALID_PIPE)
+ intel_dp->pps.pps_pipe == INVALID_PIPE)
return false;
return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON) != 0;
@@ -416,7 +416,7 @@ static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
lockdep_assert_held(&dev_priv->pps_mutex);
if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
- intel_dp->pps_pipe == INVALID_PIPE)
+ intel_dp->pps.pps_pipe == INVALID_PIPE)
return false;
return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
@@ -506,13 +506,13 @@ static void wait_panel_power_cycle(struct intel_dp *intel_dp)
/* take the difference of currrent time and panel power off time
* and then make panel wait for t11_t12 if needed. */
panel_power_on_time = ktime_get_boottime();
- panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
+ panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->pps.panel_power_off_time);
/* When we disable the VDD override bit last we have to do the manual
* wait. */
- if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
+ if (panel_power_off_duration < (s64)intel_dp->pps.panel_power_cycle_delay)
wait_remaining_ms_from_jiffies(jiffies,
- intel_dp->panel_power_cycle_delay - panel_power_off_duration);
+ intel_dp->pps.panel_power_cycle_delay - panel_power_off_duration);
wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
}
@@ -530,14 +530,14 @@ void intel_pps_wait_power_cycle(struct intel_dp *intel_dp)
static void wait_backlight_on(struct intel_dp *intel_dp)
{
- wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
- intel_dp->backlight_on_delay);
+ wait_remaining_ms_from_jiffies(intel_dp->pps.last_power_on,
+ intel_dp->pps.backlight_on_delay);
}
static void edp_wait_backlight_off(struct intel_dp *intel_dp)
{
- wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
- intel_dp->backlight_off_delay);
+ wait_remaining_ms_from_jiffies(intel_dp->pps.last_backlight_off,
+ intel_dp->pps.backlight_off_delay);
}
/* Read the current pp_control value, unlocking the register if it
@@ -571,22 +571,22 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp)
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
u32 pp;
i915_reg_t pp_stat_reg, pp_ctrl_reg;
- bool need_to_disable = !intel_dp->want_panel_vdd;
+ bool need_to_disable = !intel_dp->pps.want_panel_vdd;
lockdep_assert_held(&dev_priv->pps_mutex);
if (!intel_dp_is_edp(intel_dp))
return false;
- cancel_delayed_work(&intel_dp->panel_vdd_work);
- intel_dp->want_panel_vdd = true;
+ cancel_delayed_work(&intel_dp->pps.panel_vdd_work);
+ intel_dp->pps.want_panel_vdd = true;
if (edp_have_panel_vdd(intel_dp))
return need_to_disable;
- drm_WARN_ON(&dev_priv->drm, intel_dp->vdd_wakeref);
- intel_dp->vdd_wakeref = intel_display_power_get(dev_priv,
- intel_aux_power_domain(dig_port));
+ drm_WARN_ON(&dev_priv->drm, intel_dp->pps.vdd_wakeref);
+ intel_dp->pps.vdd_wakeref = intel_display_power_get(dev_priv,
+ intel_aux_power_domain(dig_port));
drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD on\n",
dig_port->base.base.base.id,
@@ -614,7 +614,7 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp)
"[ENCODER:%d:%s] panel power wasn't enabled\n",
dig_port->base.base.base.id,
dig_port->base.base.name);
- msleep(intel_dp->panel_power_up_delay);
+ msleep(intel_dp->pps.panel_power_up_delay);
}
return need_to_disable;
@@ -652,7 +652,7 @@ static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
lockdep_assert_held(&dev_priv->pps_mutex);
- drm_WARN_ON(&dev_priv->drm, intel_dp->want_panel_vdd);
+ drm_WARN_ON(&dev_priv->drm, intel_dp->pps.want_panel_vdd);
if (!edp_have_panel_vdd(intel_dp))
return;
@@ -676,11 +676,11 @@ static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
intel_de_read(dev_priv, pp_ctrl_reg));
if ((pp & PANEL_POWER_ON) == 0)
- intel_dp->panel_power_off_time = ktime_get_boottime();
+ intel_dp->pps.panel_power_off_time = ktime_get_boottime();
intel_display_power_put(dev_priv,
intel_aux_power_domain(dig_port),
- fetch_and_zero(&intel_dp->vdd_wakeref));
+ fetch_and_zero(&intel_dp->pps.vdd_wakeref));
}
void intel_pps_vdd_off_sync(struct intel_dp *intel_dp)
@@ -690,7 +690,7 @@ void intel_pps_vdd_off_sync(struct intel_dp *intel_dp)
if (!intel_dp_is_edp(intel_dp))
return;
- cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
+ cancel_delayed_work_sync(&intel_dp->pps.panel_vdd_work);
/*
* vdd might still be enabled due to the delayed vdd off.
* Make sure vdd is actually turned off here.
@@ -701,13 +701,13 @@ void intel_pps_vdd_off_sync(struct intel_dp *intel_dp)
static void edp_panel_vdd_work(struct work_struct *__work)
{
- struct intel_dp *intel_dp =
- container_of(to_delayed_work(__work),
- struct intel_dp, panel_vdd_work);
+ struct intel_pps *pps = container_of(to_delayed_work(__work),
+ struct intel_pps, panel_vdd_work);
+ struct intel_dp *intel_dp = container_of(pps, struct intel_dp, pps);
intel_wakeref_t wakeref;
with_intel_pps_lock(intel_dp, wakeref) {
- if (!intel_dp->want_panel_vdd)
+ if (!intel_dp->pps.want_panel_vdd)
intel_pps_vdd_off_sync_unlocked(intel_dp);
}
}
@@ -721,8 +721,8 @@ static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
* down delay) to keep the panel power up across a sequence of
* operations.
*/
- delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
- schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
+ delay = msecs_to_jiffies(intel_dp->pps.panel_power_cycle_delay * 5);
+ schedule_delayed_work(&intel_dp->pps.panel_vdd_work, delay);
}
/*
@@ -739,11 +739,11 @@ void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync)
if (!intel_dp_is_edp(intel_dp))
return;
- I915_STATE_WARN(!intel_dp->want_panel_vdd, "[ENCODER:%d:%s] VDD not forced on",
+ I915_STATE_WARN(!intel_dp->pps.want_panel_vdd, "[ENCODER:%d:%s] VDD not forced on",
dp_to_dig_port(intel_dp)->base.base.base.id,
dp_to_dig_port(intel_dp)->base.base.name);
- intel_dp->want_panel_vdd = false;
+ intel_dp->pps.want_panel_vdd = false;
if (sync)
intel_pps_vdd_off_sync_unlocked(intel_dp);
@@ -791,7 +791,7 @@ void intel_pps_on_unlocked(struct intel_dp *intel_dp)
intel_de_posting_read(dev_priv, pp_ctrl_reg);
wait_panel_on(intel_dp);
- intel_dp->last_power_on = jiffies;
+ intel_dp->pps.last_power_on = jiffies;
if (IS_GEN(dev_priv, 5)) {
pp |= PANEL_POWER_RESET; /* restore panel reset bit */
@@ -826,7 +826,7 @@ void intel_pps_off_unlocked(struct intel_dp *intel_dp)
drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power off\n",
dig_port->base.base.base.id, dig_port->base.base.name);
- drm_WARN(&dev_priv->drm, !intel_dp->want_panel_vdd,
+ drm_WARN(&dev_priv->drm, !intel_dp->pps.want_panel_vdd,
"Need [ENCODER:%d:%s] VDD to turn off panel\n",
dig_port->base.base.base.id, dig_port->base.base.name);
@@ -838,18 +838,18 @@ void intel_pps_off_unlocked(struct intel_dp *intel_dp)
pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
- intel_dp->want_panel_vdd = false;
+ intel_dp->pps.want_panel_vdd = false;
intel_de_write(dev_priv, pp_ctrl_reg, pp);
intel_de_posting_read(dev_priv, pp_ctrl_reg);
wait_panel_off(intel_dp);
- intel_dp->panel_power_off_time = ktime_get_boottime();
+ intel_dp->pps.panel_power_off_time = ktime_get_boottime();
/* We got a reference when we enabled the VDD. */
intel_display_power_put(dev_priv,
intel_aux_power_domain(dig_port),
- fetch_and_zero(&intel_dp->vdd_wakeref));
+ fetch_and_zero(&intel_dp->pps.vdd_wakeref));
}
void intel_pps_off(struct intel_dp *intel_dp)
@@ -909,7 +909,7 @@ void intel_pps_backlight_off(struct intel_dp *intel_dp)
intel_de_posting_read(dev_priv, pp_ctrl_reg);
}
- intel_dp->last_backlight_off = jiffies;
+ intel_dp->pps.last_backlight_off = jiffies;
edp_wait_backlight_off(intel_dp);
}
@@ -943,10 +943,10 @@ static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
- enum pipe pipe = intel_dp->pps_pipe;
+ enum pipe pipe = intel_dp->pps.pps_pipe;
i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
- drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE);
+ drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE);
if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B))
return;
@@ -969,7 +969,7 @@ static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
intel_de_write(dev_priv, pp_on_reg, 0);
intel_de_posting_read(dev_priv, pp_on_reg);
- intel_dp->pps_pipe = INVALID_PIPE;
+ intel_dp->pps.pps_pipe = INVALID_PIPE;
}
static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
@@ -982,12 +982,12 @@ static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
for_each_intel_dp(&dev_priv->drm, encoder) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
- drm_WARN(&dev_priv->drm, intel_dp->active_pipe == pipe,
+ drm_WARN(&dev_priv->drm, intel_dp->pps.active_pipe == pipe,
"stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n",
pipe_name(pipe), encoder->base.base.id,
encoder->base.name);
- if (intel_dp->pps_pipe != pipe)
+ if (intel_dp->pps.pps_pipe != pipe)
continue;
drm_dbg_kms(&dev_priv->drm,
@@ -1009,10 +1009,10 @@ void vlv_pps_init(struct intel_encoder *encoder,
lockdep_assert_held(&dev_priv->pps_mutex);
- drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE);
+ drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE);
- if (intel_dp->pps_pipe != INVALID_PIPE &&
- intel_dp->pps_pipe != crtc->pipe) {
+ if (intel_dp->pps.pps_pipe != INVALID_PIPE &&
+ intel_dp->pps.pps_pipe != crtc->pipe) {
/*
* If another power sequencer was being used on this
* port previously make sure to turn off vdd there while
@@ -1027,17 +1027,17 @@ void vlv_pps_init(struct intel_encoder *encoder,
*/
vlv_steal_power_sequencer(dev_priv, crtc->pipe);
- intel_dp->active_pipe = crtc->pipe;
+ intel_dp->pps.active_pipe = crtc->pipe;
if (!intel_dp_is_edp(intel_dp))
return;
/* now it's all ours */
- intel_dp->pps_pipe = crtc->pipe;
+ intel_dp->pps.pps_pipe = crtc->pipe;
drm_dbg_kms(&dev_priv->drm,
"initializing pipe %c power sequencer for [ENCODER:%d:%s]\n",
- pipe_name(intel_dp->pps_pipe), encoder->base.base.id,
+ pipe_name(intel_dp->pps.pps_pipe), encoder->base.base.id,
encoder->base.name);
/* init power sequencer on this pipe and port */
@@ -1063,9 +1063,9 @@ static void intel_pps_vdd_sanitize(struct intel_dp *intel_dp)
*/
drm_dbg_kms(&dev_priv->drm,
"VDD left on by BIOS, adjusting state tracking\n");
- drm_WARN_ON(&dev_priv->drm, intel_dp->vdd_wakeref);
- intel_dp->vdd_wakeref = intel_display_power_get(dev_priv,
- intel_aux_power_domain(dig_port));
+ drm_WARN_ON(&dev_priv->drm, intel_dp->pps.vdd_wakeref);
+ intel_dp->pps.vdd_wakeref = intel_display_power_get(dev_priv,
+ intel_aux_power_domain(dig_port));
edp_panel_vdd_schedule_off(intel_dp);
}
@@ -1085,9 +1085,9 @@ bool intel_pps_have_power(struct intel_dp *intel_dp)
static void pps_init_timestamps(struct intel_dp *intel_dp)
{
- intel_dp->panel_power_off_time = ktime_get_boottime();
- intel_dp->last_power_on = jiffies;
- intel_dp->last_backlight_off = jiffies;
+ intel_dp->pps.panel_power_off_time = ktime_get_boottime();
+ intel_dp->pps.last_power_on = jiffies;
+ intel_dp->pps.last_backlight_off = jiffies;
}
static void
@@ -1137,7 +1137,7 @@ static void
intel_pps_verify_state(struct intel_dp *intel_dp)
{
struct edp_power_seq hw;
- struct edp_power_seq *sw = &intel_dp->pps_delays;
+ struct edp_power_seq *sw = &intel_dp->pps.pps_delays;
intel_pps_readout_hw_state(intel_dp, &hw);
@@ -1153,7 +1153,7 @@ static void pps_init_delays(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct edp_power_seq cur, vbt, spec,
- *final = &intel_dp->pps_delays;
+ *final = &intel_dp->pps.pps_delays;
lockdep_assert_held(&dev_priv->pps_mutex);
@@ -1210,22 +1210,22 @@ static void pps_init_delays(struct intel_dp *intel_dp)
#undef assign_final
#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
- intel_dp->panel_power_up_delay = get_delay(t1_t3);
- intel_dp->backlight_on_delay = get_delay(t8);
- intel_dp->backlight_off_delay = get_delay(t9);
- intel_dp->panel_power_down_delay = get_delay(t10);
- intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
+ intel_dp->pps.panel_power_up_delay = get_delay(t1_t3);
+ intel_dp->pps.backlight_on_delay = get_delay(t8);
+ intel_dp->pps.backlight_off_delay = get_delay(t9);
+ intel_dp->pps.panel_power_down_delay = get_delay(t10);
+ intel_dp->pps.panel_power_cycle_delay = get_delay(t11_t12);
#undef get_delay
drm_dbg_kms(&dev_priv->drm,
"panel power up delay %d, power down delay %d, power cycle delay %d\n",
- intel_dp->panel_power_up_delay,
- intel_dp->panel_power_down_delay,
- intel_dp->panel_power_cycle_delay);
+ intel_dp->pps.panel_power_up_delay,
+ intel_dp->pps.panel_power_down_delay,
+ intel_dp->pps.panel_power_cycle_delay);
drm_dbg_kms(&dev_priv->drm, "backlight on delay %d, off delay %d\n",
- intel_dp->backlight_on_delay,
- intel_dp->backlight_off_delay);
+ intel_dp->pps.backlight_on_delay,
+ intel_dp->pps.backlight_off_delay);
/*
* We override the HW backlight delays to 1 because we do manual waits
@@ -1251,7 +1251,7 @@ static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd
int div = RUNTIME_INFO(dev_priv)->rawclk_freq / 1000;
struct pps_registers regs;
enum port port = dp_to_dig_port(intel_dp)->base.port;
- const struct edp_power_seq *seq = &intel_dp->pps_delays;
+ const struct edp_power_seq *seq = &intel_dp->pps.pps_delays;
lockdep_assert_held(&dev_priv->pps_mutex);
@@ -1364,7 +1364,7 @@ void intel_pps_encoder_reset(struct intel_dp *intel_dp)
void intel_pps_init(struct intel_dp *intel_dp)
{
- INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work);
+ INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work);
pps_init_timestamps(intel_dp);
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [Intel-gfx] [PATCH 4/4] drm/i915/dp: split out aux functionality to intel_dp_aux.c
2021-01-20 10:18 [Intel-gfx] [PATCH 1/4] drm/i915/pps: refactor init abstractions Jani Nikula
2021-01-20 10:18 ` [Intel-gfx] [PATCH 2/4] drm/i915/pps: move pps code over from intel_display.c and refactor Jani Nikula
2021-01-20 10:18 ` [Intel-gfx] [PATCH 3/4] drm/i915/dp: abstract struct intel_dp pps members to a sub-struct Jani Nikula
@ 2021-01-20 10:18 ` Jani Nikula
2021-01-20 17:31 ` Rodrigo Vivi
2021-01-20 14:17 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915/pps: refactor init abstractions Patchwork
` (3 subsequent siblings)
6 siblings, 1 reply; 13+ messages in thread
From: Jani Nikula @ 2021-01-20 10:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Split out the DP aux functionality to a new intel_dp_aux.[ch]. This is a
surprisingly clean cut.
v2:
- Remove intel_dp_pack_aux declaration from intel_dp.h (Anshuman)
- Fixed some whitespace/comment checkpatch warnings
Cc: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 680 +------------------
drivers/gpu/drm/i915/display/intel_dp.h | 1 -
drivers/gpu/drm/i915/display/intel_dp_aux.c | 692 ++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dp_aux.h | 18 +
drivers/gpu/drm/i915/display/intel_psr.c | 3 +-
6 files changed, 714 insertions(+), 681 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_dp_aux.c
create mode 100644 drivers/gpu/drm/i915/display/intel_dp_aux.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 006dec54408d..ea1cc5736049 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -243,6 +243,7 @@ i915-y += \
display/intel_crt.o \
display/intel_ddi.o \
display/intel_dp.o \
+ display/intel_dp_aux.o \
display/intel_dp_aux_backlight.o \
display/intel_dp_hdcp.o \
display/intel_dp_link_training.o \
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index d815087a26aa..8979996f1747 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -41,13 +41,13 @@
#include "i915_debugfs.h"
#include "i915_drv.h"
-#include "i915_trace.h"
#include "intel_atomic.h"
#include "intel_audio.h"
#include "intel_connector.h"
#include "intel_ddi.h"
#include "intel_display_types.h"
#include "intel_dp.h"
+#include "intel_dp_aux.h"
#include "intel_dp_link_training.h"
#include "intel_dp_mst.h"
#include "intel_dpio_phy.h"
@@ -862,684 +862,6 @@ intel_dp_mode_valid(struct drm_connector *connector,
return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
}
-u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
-{
- int i;
- u32 v = 0;
-
- if (src_bytes > 4)
- src_bytes = 4;
- for (i = 0; i < src_bytes; i++)
- v |= ((u32)src[i]) << ((3 - i) * 8);
- return v;
-}
-
-static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes)
-{
- int i;
- if (dst_bytes > 4)
- dst_bytes = 4;
- for (i = 0; i < dst_bytes; i++)
- dst[i] = src >> ((3-i) * 8);
-}
-
-static u32
-intel_dp_aux_wait_done(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
- const unsigned int timeout_ms = 10;
- u32 status;
- bool done;
-
-#define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
- done = wait_event_timeout(i915->gmbus_wait_queue, C,
- msecs_to_jiffies_timeout(timeout_ms));
-
- /* just trace the final value */
- trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
-
- if (!done)
- drm_err(&i915->drm,
- "%s: did not complete or timeout within %ums (status 0x%08x)\n",
- intel_dp->aux.name, timeout_ms, status);
-#undef C
-
- return status;
-}
-
-static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-
- if (index)
- return 0;
-
- /*
- * The clock divider is based off the hrawclk, and would like to run at
- * 2MHz. So, take the hrawclk value and divide by 2000 and use that
- */
- return DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq, 2000);
-}
-
-static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- u32 freq;
-
- if (index)
- return 0;
-
- /*
- * The clock divider is based off the cdclk or PCH rawclk, and would
- * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
- * divide by 2000 and use that
- */
- if (dig_port->aux_ch == AUX_CH_A)
- freq = dev_priv->cdclk.hw.cdclk;
- else
- freq = RUNTIME_INFO(dev_priv)->rawclk_freq;
- return DIV_ROUND_CLOSEST(freq, 2000);
-}
-
-static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
-
- if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
- /* Workaround for non-ULT HSW */
- switch (index) {
- case 0: return 63;
- case 1: return 72;
- default: return 0;
- }
- }
-
- return ilk_get_aux_clock_divider(intel_dp, index);
-}
-
-static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
-{
- /*
- * SKL doesn't need us to program the AUX clock divider (Hardware will
- * derive the clock from CDCLK automatically). We still implement the
- * get_aux_clock_divider vfunc to plug-in into the existing code.
- */
- return index ? 0 : 1;
-}
-
-static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
- int send_bytes,
- u32 aux_clock_divider)
-{
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- struct drm_i915_private *dev_priv =
- to_i915(dig_port->base.base.dev);
- u32 precharge, timeout;
-
- if (IS_GEN(dev_priv, 6))
- precharge = 3;
- else
- precharge = 5;
-
- if (IS_BROADWELL(dev_priv))
- timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
- else
- timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
-
- return DP_AUX_CH_CTL_SEND_BUSY |
- DP_AUX_CH_CTL_DONE |
- DP_AUX_CH_CTL_INTERRUPT |
- DP_AUX_CH_CTL_TIME_OUT_ERROR |
- timeout |
- DP_AUX_CH_CTL_RECEIVE_ERROR |
- (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
- (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
- (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
-}
-
-static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
- int send_bytes,
- u32 unused)
-{
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- struct drm_i915_private *i915 =
- to_i915(dig_port->base.base.dev);
- enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
- u32 ret;
-
- ret = DP_AUX_CH_CTL_SEND_BUSY |
- DP_AUX_CH_CTL_DONE |
- DP_AUX_CH_CTL_INTERRUPT |
- DP_AUX_CH_CTL_TIME_OUT_ERROR |
- DP_AUX_CH_CTL_TIME_OUT_MAX |
- DP_AUX_CH_CTL_RECEIVE_ERROR |
- (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
- DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
- DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
-
- if (intel_phy_is_tc(i915, phy) &&
- dig_port->tc_mode == TC_PORT_TBT_ALT)
- ret |= DP_AUX_CH_CTL_TBT_IO;
-
- return ret;
-}
-
-static int
-intel_dp_aux_xfer(struct intel_dp *intel_dp,
- const u8 *send, int send_bytes,
- u8 *recv, int recv_size,
- u32 aux_send_ctl_flags)
-{
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- struct drm_i915_private *i915 =
- to_i915(dig_port->base.base.dev);
- struct intel_uncore *uncore = &i915->uncore;
- enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
- bool is_tc_port = intel_phy_is_tc(i915, phy);
- i915_reg_t ch_ctl, ch_data[5];
- u32 aux_clock_divider;
- enum intel_display_power_domain aux_domain;
- intel_wakeref_t aux_wakeref;
- intel_wakeref_t pps_wakeref;
- int i, ret, recv_bytes;
- int try, clock = 0;
- u32 status;
- bool vdd;
-
- ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
- for (i = 0; i < ARRAY_SIZE(ch_data); i++)
- ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
-
- if (is_tc_port)
- intel_tc_port_lock(dig_port);
-
- aux_domain = intel_aux_power_domain(dig_port);
-
- aux_wakeref = intel_display_power_get(i915, aux_domain);
- pps_wakeref = intel_pps_lock(intel_dp);
-
- /*
- * We will be called with VDD already enabled for dpcd/edid/oui reads.
- * In such cases we want to leave VDD enabled and it's up to upper layers
- * to turn it off. But for eg. i2c-dev access we need to turn it on/off
- * ourselves.
- */
- vdd = intel_pps_vdd_on_unlocked(intel_dp);
-
- /* dp aux is extremely sensitive to irq latency, hence request the
- * lowest possible wakeup latency and so prevent the cpu from going into
- * deep sleep states.
- */
- cpu_latency_qos_update_request(&intel_dp->pm_qos, 0);
-
- intel_pps_check_power_unlocked(intel_dp);
-
- /* Try to wait for any previous AUX channel activity */
- for (try = 0; try < 3; try++) {
- status = intel_uncore_read_notrace(uncore, ch_ctl);
- if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
- break;
- msleep(1);
- }
- /* just trace the final value */
- trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
-
- if (try == 3) {
- const u32 status = intel_uncore_read(uncore, ch_ctl);
-
- if (status != intel_dp->aux_busy_last_status) {
- drm_WARN(&i915->drm, 1,
- "%s: not started (status 0x%08x)\n",
- intel_dp->aux.name, status);
- intel_dp->aux_busy_last_status = status;
- }
-
- ret = -EBUSY;
- goto out;
- }
-
- /* Only 5 data registers! */
- if (drm_WARN_ON(&i915->drm, send_bytes > 20 || recv_size > 20)) {
- ret = -E2BIG;
- goto out;
- }
-
- while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
- u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
- send_bytes,
- aux_clock_divider);
-
- send_ctl |= aux_send_ctl_flags;
-
- /* Must try at least 3 times according to DP spec */
- for (try = 0; try < 5; try++) {
- /* Load the send data into the aux channel data registers */
- for (i = 0; i < send_bytes; i += 4)
- intel_uncore_write(uncore,
- ch_data[i >> 2],
- intel_dp_pack_aux(send + i,
- send_bytes - i));
-
- /* Send the command and wait for it to complete */
- intel_uncore_write(uncore, ch_ctl, send_ctl);
-
- status = intel_dp_aux_wait_done(intel_dp);
-
- /* Clear done status and any errors */
- intel_uncore_write(uncore,
- ch_ctl,
- status |
- DP_AUX_CH_CTL_DONE |
- DP_AUX_CH_CTL_TIME_OUT_ERROR |
- DP_AUX_CH_CTL_RECEIVE_ERROR);
-
- /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
- * 400us delay required for errors and timeouts
- * Timeout errors from the HW already meet this
- * requirement so skip to next iteration
- */
- if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
- continue;
-
- if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
- usleep_range(400, 500);
- continue;
- }
- if (status & DP_AUX_CH_CTL_DONE)
- goto done;
- }
- }
-
- if ((status & DP_AUX_CH_CTL_DONE) == 0) {
- drm_err(&i915->drm, "%s: not done (status 0x%08x)\n",
- intel_dp->aux.name, status);
- ret = -EBUSY;
- goto out;
- }
-
-done:
- /* Check for timeout or receive error.
- * Timeouts occur when the sink is not connected
- */
- if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
- drm_err(&i915->drm, "%s: receive error (status 0x%08x)\n",
- intel_dp->aux.name, status);
- ret = -EIO;
- goto out;
- }
-
- /* Timeouts occur when the device isn't connected, so they're
- * "normal" -- don't fill the kernel log with these */
- if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
- drm_dbg_kms(&i915->drm, "%s: timeout (status 0x%08x)\n",
- intel_dp->aux.name, status);
- ret = -ETIMEDOUT;
- goto out;
- }
-
- /* Unload any bytes sent back from the other side */
- recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
- DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
-
- /*
- * By BSpec: "Message sizes of 0 or >20 are not allowed."
- * We have no idea of what happened so we return -EBUSY so
- * drm layer takes care for the necessary retries.
- */
- if (recv_bytes == 0 || recv_bytes > 20) {
- drm_dbg_kms(&i915->drm,
- "%s: Forbidden recv_bytes = %d on aux transaction\n",
- intel_dp->aux.name, recv_bytes);
- ret = -EBUSY;
- goto out;
- }
-
- if (recv_bytes > recv_size)
- recv_bytes = recv_size;
-
- for (i = 0; i < recv_bytes; i += 4)
- intel_dp_unpack_aux(intel_uncore_read(uncore, ch_data[i >> 2]),
- recv + i, recv_bytes - i);
-
- ret = recv_bytes;
-out:
- cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
-
- if (vdd)
- intel_pps_vdd_off_unlocked(intel_dp, false);
-
- intel_pps_unlock(intel_dp, pps_wakeref);
- intel_display_power_put_async(i915, aux_domain, aux_wakeref);
-
- if (is_tc_port)
- intel_tc_port_unlock(dig_port);
-
- return ret;
-}
-
-#define BARE_ADDRESS_SIZE 3
-#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
-
-static void
-intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
- const struct drm_dp_aux_msg *msg)
-{
- txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
- txbuf[1] = (msg->address >> 8) & 0xff;
- txbuf[2] = msg->address & 0xff;
- txbuf[3] = msg->size - 1;
-}
-
-static u32 intel_dp_aux_xfer_flags(const struct drm_dp_aux_msg *msg)
-{
- /*
- * If we're trying to send the HDCP Aksv, we need to set a the Aksv
- * select bit to inform the hardware to send the Aksv after our header
- * since we can't access that data from software.
- */
- if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_WRITE &&
- msg->address == DP_AUX_HDCP_AKSV)
- return DP_AUX_CH_CTL_AUX_AKSV_SELECT;
-
- return 0;
-}
-
-static ssize_t
-intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
-{
- struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- u8 txbuf[20], rxbuf[20];
- size_t txsize, rxsize;
- u32 flags = intel_dp_aux_xfer_flags(msg);
- int ret;
-
- intel_dp_aux_header(txbuf, msg);
-
- switch (msg->request & ~DP_AUX_I2C_MOT) {
- case DP_AUX_NATIVE_WRITE:
- case DP_AUX_I2C_WRITE:
- case DP_AUX_I2C_WRITE_STATUS_UPDATE:
- txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
- rxsize = 2; /* 0 or 1 data bytes */
-
- if (drm_WARN_ON(&i915->drm, txsize > 20))
- return -E2BIG;
-
- drm_WARN_ON(&i915->drm, !msg->buffer != !msg->size);
-
- if (msg->buffer)
- memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
-
- ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
- rxbuf, rxsize, flags);
- if (ret > 0) {
- msg->reply = rxbuf[0] >> 4;
-
- if (ret > 1) {
- /* Number of bytes written in a short write. */
- ret = clamp_t(int, rxbuf[1], 0, msg->size);
- } else {
- /* Return payload size. */
- ret = msg->size;
- }
- }
- break;
-
- case DP_AUX_NATIVE_READ:
- case DP_AUX_I2C_READ:
- txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
- rxsize = msg->size + 1;
-
- if (drm_WARN_ON(&i915->drm, rxsize > 20))
- return -E2BIG;
-
- ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
- rxbuf, rxsize, flags);
- if (ret > 0) {
- msg->reply = rxbuf[0] >> 4;
- /*
- * Assume happy day, and copy the data. The caller is
- * expected to check msg->reply before touching it.
- *
- * Return payload size.
- */
- ret--;
- memcpy(msg->buffer, rxbuf + 1, ret);
- }
- break;
-
- default:
- ret = -EINVAL;
- break;
- }
-
- return ret;
-}
-
-
-static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- enum aux_ch aux_ch = dig_port->aux_ch;
-
- switch (aux_ch) {
- case AUX_CH_B:
- case AUX_CH_C:
- case AUX_CH_D:
- return DP_AUX_CH_CTL(aux_ch);
- default:
- MISSING_CASE(aux_ch);
- return DP_AUX_CH_CTL(AUX_CH_B);
- }
-}
-
-static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- enum aux_ch aux_ch = dig_port->aux_ch;
-
- switch (aux_ch) {
- case AUX_CH_B:
- case AUX_CH_C:
- case AUX_CH_D:
- return DP_AUX_CH_DATA(aux_ch, index);
- default:
- MISSING_CASE(aux_ch);
- return DP_AUX_CH_DATA(AUX_CH_B, index);
- }
-}
-
-static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- enum aux_ch aux_ch = dig_port->aux_ch;
-
- switch (aux_ch) {
- case AUX_CH_A:
- return DP_AUX_CH_CTL(aux_ch);
- case AUX_CH_B:
- case AUX_CH_C:
- case AUX_CH_D:
- return PCH_DP_AUX_CH_CTL(aux_ch);
- default:
- MISSING_CASE(aux_ch);
- return DP_AUX_CH_CTL(AUX_CH_A);
- }
-}
-
-static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- enum aux_ch aux_ch = dig_port->aux_ch;
-
- switch (aux_ch) {
- case AUX_CH_A:
- return DP_AUX_CH_DATA(aux_ch, index);
- case AUX_CH_B:
- case AUX_CH_C:
- case AUX_CH_D:
- return PCH_DP_AUX_CH_DATA(aux_ch, index);
- default:
- MISSING_CASE(aux_ch);
- return DP_AUX_CH_DATA(AUX_CH_A, index);
- }
-}
-
-static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- enum aux_ch aux_ch = dig_port->aux_ch;
-
- switch (aux_ch) {
- case AUX_CH_A:
- case AUX_CH_B:
- case AUX_CH_C:
- case AUX_CH_D:
- case AUX_CH_E:
- case AUX_CH_F:
- return DP_AUX_CH_CTL(aux_ch);
- default:
- MISSING_CASE(aux_ch);
- return DP_AUX_CH_CTL(AUX_CH_A);
- }
-}
-
-static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- enum aux_ch aux_ch = dig_port->aux_ch;
-
- switch (aux_ch) {
- case AUX_CH_A:
- case AUX_CH_B:
- case AUX_CH_C:
- case AUX_CH_D:
- case AUX_CH_E:
- case AUX_CH_F:
- return DP_AUX_CH_DATA(aux_ch, index);
- default:
- MISSING_CASE(aux_ch);
- return DP_AUX_CH_DATA(AUX_CH_A, index);
- }
-}
-
-static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- enum aux_ch aux_ch = dig_port->aux_ch;
-
- switch (aux_ch) {
- case AUX_CH_A:
- case AUX_CH_B:
- case AUX_CH_C:
- case AUX_CH_USBC1:
- case AUX_CH_USBC2:
- case AUX_CH_USBC3:
- case AUX_CH_USBC4:
- case AUX_CH_USBC5:
- case AUX_CH_USBC6:
- return DP_AUX_CH_CTL(aux_ch);
- default:
- MISSING_CASE(aux_ch);
- return DP_AUX_CH_CTL(AUX_CH_A);
- }
-}
-
-static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- enum aux_ch aux_ch = dig_port->aux_ch;
-
- switch (aux_ch) {
- case AUX_CH_A:
- case AUX_CH_B:
- case AUX_CH_C:
- case AUX_CH_USBC1:
- case AUX_CH_USBC2:
- case AUX_CH_USBC3:
- case AUX_CH_USBC4:
- case AUX_CH_USBC5:
- case AUX_CH_USBC6:
- return DP_AUX_CH_DATA(aux_ch, index);
- default:
- MISSING_CASE(aux_ch);
- return DP_AUX_CH_DATA(AUX_CH_A, index);
- }
-}
-
-static void
-intel_dp_aux_fini(struct intel_dp *intel_dp)
-{
- if (cpu_latency_qos_request_active(&intel_dp->pm_qos))
- cpu_latency_qos_remove_request(&intel_dp->pm_qos);
-
- kfree(intel_dp->aux.name);
-}
-
-static void
-intel_dp_aux_init(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- struct intel_encoder *encoder = &dig_port->base;
- enum aux_ch aux_ch = dig_port->aux_ch;
-
- if (INTEL_GEN(dev_priv) >= 12) {
- intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg;
- intel_dp->aux_ch_data_reg = tgl_aux_data_reg;
- } else if (INTEL_GEN(dev_priv) >= 9) {
- intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
- intel_dp->aux_ch_data_reg = skl_aux_data_reg;
- } else if (HAS_PCH_SPLIT(dev_priv)) {
- intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
- intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
- } else {
- intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
- intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
- }
-
- if (INTEL_GEN(dev_priv) >= 9)
- intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
- else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
- intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
- else if (HAS_PCH_SPLIT(dev_priv))
- intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
- else
- intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
-
- if (INTEL_GEN(dev_priv) >= 9)
- intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
- else
- intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
-
- drm_dp_aux_init(&intel_dp->aux);
-
- /* Failure to allocate our preferred name is not critical */
- if (INTEL_GEN(dev_priv) >= 12 && aux_ch >= AUX_CH_USBC1)
- intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX USBC%c/%s",
- aux_ch - AUX_CH_USBC1 + '1',
- encoder->base.name);
- else
- intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/%s",
- aux_ch_name(aux_ch),
- encoder->base.name);
-
- intel_dp->aux.transfer = intel_dp_aux_transfer;
- cpu_latency_qos_add_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
-}
-
bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
{
int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 40e70531296c..d80839139bfb 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -75,7 +75,6 @@ void intel_dp_mst_resume(struct drm_i915_private *dev_priv);
int intel_dp_max_link_rate(struct intel_dp *intel_dp);
int intel_dp_max_lane_count(struct intel_dp *intel_dp);
int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
-u32 intel_dp_pack_aux(const u8 *src, int src_bytes);
void intel_edp_drrs_enable(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
new file mode 100644
index 000000000000..c7c82a6cd63c
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -0,0 +1,692 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#include "i915_drv.h"
+#include "i915_trace.h"
+#include "intel_display_types.h"
+#include "intel_dp_aux.h"
+#include "intel_pps.h"
+#include "intel_tc.h"
+
+u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
+{
+ int i;
+ u32 v = 0;
+
+ if (src_bytes > 4)
+ src_bytes = 4;
+ for (i = 0; i < src_bytes; i++)
+ v |= ((u32)src[i]) << ((3 - i) * 8);
+ return v;
+}
+
+static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes)
+{
+ int i;
+
+ if (dst_bytes > 4)
+ dst_bytes = 4;
+ for (i = 0; i < dst_bytes; i++)
+ dst[i] = src >> ((3 - i) * 8);
+}
+
+static u32
+intel_dp_aux_wait_done(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
+ const unsigned int timeout_ms = 10;
+ u32 status;
+ bool done;
+
+#define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
+ done = wait_event_timeout(i915->gmbus_wait_queue, C,
+ msecs_to_jiffies_timeout(timeout_ms));
+
+ /* just trace the final value */
+ trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
+
+ if (!done)
+ drm_err(&i915->drm,
+ "%s: did not complete or timeout within %ums (status 0x%08x)\n",
+ intel_dp->aux.name, timeout_ms, status);
+#undef C
+
+ return status;
+}
+
+static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ if (index)
+ return 0;
+
+ /*
+ * The clock divider is based off the hrawclk, and would like to run at
+ * 2MHz. So, take the hrawclk value and divide by 2000 and use that
+ */
+ return DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq, 2000);
+}
+
+static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ u32 freq;
+
+ if (index)
+ return 0;
+
+ /*
+ * The clock divider is based off the cdclk or PCH rawclk, and would
+ * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
+ * divide by 2000 and use that
+ */
+ if (dig_port->aux_ch == AUX_CH_A)
+ freq = dev_priv->cdclk.hw.cdclk;
+ else
+ freq = RUNTIME_INFO(dev_priv)->rawclk_freq;
+ return DIV_ROUND_CLOSEST(freq, 2000);
+}
+
+static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+
+ if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
+ /* Workaround for non-ULT HSW */
+ switch (index) {
+ case 0: return 63;
+ case 1: return 72;
+ default: return 0;
+ }
+ }
+
+ return ilk_get_aux_clock_divider(intel_dp, index);
+}
+
+static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
+{
+ /*
+ * SKL doesn't need us to program the AUX clock divider (Hardware will
+ * derive the clock from CDCLK automatically). We still implement the
+ * get_aux_clock_divider vfunc to plug-in into the existing code.
+ */
+ return index ? 0 : 1;
+}
+
+static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
+ int send_bytes,
+ u32 aux_clock_divider)
+{
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ struct drm_i915_private *dev_priv =
+ to_i915(dig_port->base.base.dev);
+ u32 precharge, timeout;
+
+ if (IS_GEN(dev_priv, 6))
+ precharge = 3;
+ else
+ precharge = 5;
+
+ if (IS_BROADWELL(dev_priv))
+ timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
+ else
+ timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
+
+ return DP_AUX_CH_CTL_SEND_BUSY |
+ DP_AUX_CH_CTL_DONE |
+ DP_AUX_CH_CTL_INTERRUPT |
+ DP_AUX_CH_CTL_TIME_OUT_ERROR |
+ timeout |
+ DP_AUX_CH_CTL_RECEIVE_ERROR |
+ (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
+ (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
+ (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
+}
+
+static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
+ int send_bytes,
+ u32 unused)
+{
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ struct drm_i915_private *i915 =
+ to_i915(dig_port->base.base.dev);
+ enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
+ u32 ret;
+
+ ret = DP_AUX_CH_CTL_SEND_BUSY |
+ DP_AUX_CH_CTL_DONE |
+ DP_AUX_CH_CTL_INTERRUPT |
+ DP_AUX_CH_CTL_TIME_OUT_ERROR |
+ DP_AUX_CH_CTL_TIME_OUT_MAX |
+ DP_AUX_CH_CTL_RECEIVE_ERROR |
+ (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
+ DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
+ DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
+
+ if (intel_phy_is_tc(i915, phy) &&
+ dig_port->tc_mode == TC_PORT_TBT_ALT)
+ ret |= DP_AUX_CH_CTL_TBT_IO;
+
+ return ret;
+}
+
+static int
+intel_dp_aux_xfer(struct intel_dp *intel_dp,
+ const u8 *send, int send_bytes,
+ u8 *recv, int recv_size,
+ u32 aux_send_ctl_flags)
+{
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ struct drm_i915_private *i915 =
+ to_i915(dig_port->base.base.dev);
+ struct intel_uncore *uncore = &i915->uncore;
+ enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
+ bool is_tc_port = intel_phy_is_tc(i915, phy);
+ i915_reg_t ch_ctl, ch_data[5];
+ u32 aux_clock_divider;
+ enum intel_display_power_domain aux_domain;
+ intel_wakeref_t aux_wakeref;
+ intel_wakeref_t pps_wakeref;
+ int i, ret, recv_bytes;
+ int try, clock = 0;
+ u32 status;
+ bool vdd;
+
+ ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
+ for (i = 0; i < ARRAY_SIZE(ch_data); i++)
+ ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
+
+ if (is_tc_port)
+ intel_tc_port_lock(dig_port);
+
+ aux_domain = intel_aux_power_domain(dig_port);
+
+ aux_wakeref = intel_display_power_get(i915, aux_domain);
+ pps_wakeref = intel_pps_lock(intel_dp);
+
+ /*
+ * We will be called with VDD already enabled for dpcd/edid/oui reads.
+ * In such cases we want to leave VDD enabled and it's up to upper layers
+ * to turn it off. But for eg. i2c-dev access we need to turn it on/off
+ * ourselves.
+ */
+ vdd = intel_pps_vdd_on_unlocked(intel_dp);
+
+ /*
+ * dp aux is extremely sensitive to irq latency, hence request the
+ * lowest possible wakeup latency and so prevent the cpu from going into
+ * deep sleep states.
+ */
+ cpu_latency_qos_update_request(&intel_dp->pm_qos, 0);
+
+ intel_pps_check_power_unlocked(intel_dp);
+
+ /* Try to wait for any previous AUX channel activity */
+ for (try = 0; try < 3; try++) {
+ status = intel_uncore_read_notrace(uncore, ch_ctl);
+ if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
+ break;
+ msleep(1);
+ }
+ /* just trace the final value */
+ trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
+
+ if (try == 3) {
+ const u32 status = intel_uncore_read(uncore, ch_ctl);
+
+ if (status != intel_dp->aux_busy_last_status) {
+ drm_WARN(&i915->drm, 1,
+ "%s: not started (status 0x%08x)\n",
+ intel_dp->aux.name, status);
+ intel_dp->aux_busy_last_status = status;
+ }
+
+ ret = -EBUSY;
+ goto out;
+ }
+
+ /* Only 5 data registers! */
+ if (drm_WARN_ON(&i915->drm, send_bytes > 20 || recv_size > 20)) {
+ ret = -E2BIG;
+ goto out;
+ }
+
+ while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
+ u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
+ send_bytes,
+ aux_clock_divider);
+
+ send_ctl |= aux_send_ctl_flags;
+
+ /* Must try at least 3 times according to DP spec */
+ for (try = 0; try < 5; try++) {
+ /* Load the send data into the aux channel data registers */
+ for (i = 0; i < send_bytes; i += 4)
+ intel_uncore_write(uncore,
+ ch_data[i >> 2],
+ intel_dp_pack_aux(send + i,
+ send_bytes - i));
+
+ /* Send the command and wait for it to complete */
+ intel_uncore_write(uncore, ch_ctl, send_ctl);
+
+ status = intel_dp_aux_wait_done(intel_dp);
+
+ /* Clear done status and any errors */
+ intel_uncore_write(uncore,
+ ch_ctl,
+ status |
+ DP_AUX_CH_CTL_DONE |
+ DP_AUX_CH_CTL_TIME_OUT_ERROR |
+ DP_AUX_CH_CTL_RECEIVE_ERROR);
+
+ /*
+ * DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
+ * 400us delay required for errors and timeouts
+ * Timeout errors from the HW already meet this
+ * requirement so skip to next iteration
+ */
+ if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
+ continue;
+
+ if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
+ usleep_range(400, 500);
+ continue;
+ }
+ if (status & DP_AUX_CH_CTL_DONE)
+ goto done;
+ }
+ }
+
+ if ((status & DP_AUX_CH_CTL_DONE) == 0) {
+ drm_err(&i915->drm, "%s: not done (status 0x%08x)\n",
+ intel_dp->aux.name, status);
+ ret = -EBUSY;
+ goto out;
+ }
+
+done:
+ /*
+ * Check for timeout or receive error. Timeouts occur when the sink is
+ * not connected.
+ */
+ if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
+ drm_err(&i915->drm, "%s: receive error (status 0x%08x)\n",
+ intel_dp->aux.name, status);
+ ret = -EIO;
+ goto out;
+ }
+
+ /*
+ * Timeouts occur when the device isn't connected, so they're "normal"
+ * -- don't fill the kernel log with these
+ */
+ if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
+ drm_dbg_kms(&i915->drm, "%s: timeout (status 0x%08x)\n",
+ intel_dp->aux.name, status);
+ ret = -ETIMEDOUT;
+ goto out;
+ }
+
+ /* Unload any bytes sent back from the other side */
+ recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
+ DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
+
+ /*
+ * By BSpec: "Message sizes of 0 or >20 are not allowed."
+ * We have no idea of what happened so we return -EBUSY so
+ * drm layer takes care for the necessary retries.
+ */
+ if (recv_bytes == 0 || recv_bytes > 20) {
+ drm_dbg_kms(&i915->drm,
+ "%s: Forbidden recv_bytes = %d on aux transaction\n",
+ intel_dp->aux.name, recv_bytes);
+ ret = -EBUSY;
+ goto out;
+ }
+
+ if (recv_bytes > recv_size)
+ recv_bytes = recv_size;
+
+ for (i = 0; i < recv_bytes; i += 4)
+ intel_dp_unpack_aux(intel_uncore_read(uncore, ch_data[i >> 2]),
+ recv + i, recv_bytes - i);
+
+ ret = recv_bytes;
+out:
+ cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
+
+ if (vdd)
+ intel_pps_vdd_off_unlocked(intel_dp, false);
+
+ intel_pps_unlock(intel_dp, pps_wakeref);
+ intel_display_power_put_async(i915, aux_domain, aux_wakeref);
+
+ if (is_tc_port)
+ intel_tc_port_unlock(dig_port);
+
+ return ret;
+}
+
+#define BARE_ADDRESS_SIZE 3
+#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
+
+static void
+intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
+ const struct drm_dp_aux_msg *msg)
+{
+ txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
+ txbuf[1] = (msg->address >> 8) & 0xff;
+ txbuf[2] = msg->address & 0xff;
+ txbuf[3] = msg->size - 1;
+}
+
+static u32 intel_dp_aux_xfer_flags(const struct drm_dp_aux_msg *msg)
+{
+ /*
+ * If we're trying to send the HDCP Aksv, we need to set a the Aksv
+ * select bit to inform the hardware to send the Aksv after our header
+ * since we can't access that data from software.
+ */
+ if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_WRITE &&
+ msg->address == DP_AUX_HDCP_AKSV)
+ return DP_AUX_CH_CTL_AUX_AKSV_SELECT;
+
+ return 0;
+}
+
+static ssize_t
+intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
+{
+ struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ u8 txbuf[20], rxbuf[20];
+ size_t txsize, rxsize;
+ u32 flags = intel_dp_aux_xfer_flags(msg);
+ int ret;
+
+ intel_dp_aux_header(txbuf, msg);
+
+ switch (msg->request & ~DP_AUX_I2C_MOT) {
+ case DP_AUX_NATIVE_WRITE:
+ case DP_AUX_I2C_WRITE:
+ case DP_AUX_I2C_WRITE_STATUS_UPDATE:
+ txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
+ rxsize = 2; /* 0 or 1 data bytes */
+
+ if (drm_WARN_ON(&i915->drm, txsize > 20))
+ return -E2BIG;
+
+ drm_WARN_ON(&i915->drm, !msg->buffer != !msg->size);
+
+ if (msg->buffer)
+ memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
+
+ ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
+ rxbuf, rxsize, flags);
+ if (ret > 0) {
+ msg->reply = rxbuf[0] >> 4;
+
+ if (ret > 1) {
+ /* Number of bytes written in a short write. */
+ ret = clamp_t(int, rxbuf[1], 0, msg->size);
+ } else {
+ /* Return payload size. */
+ ret = msg->size;
+ }
+ }
+ break;
+
+ case DP_AUX_NATIVE_READ:
+ case DP_AUX_I2C_READ:
+ txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
+ rxsize = msg->size + 1;
+
+ if (drm_WARN_ON(&i915->drm, rxsize > 20))
+ return -E2BIG;
+
+ ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
+ rxbuf, rxsize, flags);
+ if (ret > 0) {
+ msg->reply = rxbuf[0] >> 4;
+ /*
+ * Assume happy day, and copy the data. The caller is
+ * expected to check msg->reply before touching it.
+ *
+ * Return payload size.
+ */
+ ret--;
+ memcpy(msg->buffer, rxbuf + 1, ret);
+ }
+ break;
+
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ return ret;
+}
+
+static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ enum aux_ch aux_ch = dig_port->aux_ch;
+
+ switch (aux_ch) {
+ case AUX_CH_B:
+ case AUX_CH_C:
+ case AUX_CH_D:
+ return DP_AUX_CH_CTL(aux_ch);
+ default:
+ MISSING_CASE(aux_ch);
+ return DP_AUX_CH_CTL(AUX_CH_B);
+ }
+}
+
+static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ enum aux_ch aux_ch = dig_port->aux_ch;
+
+ switch (aux_ch) {
+ case AUX_CH_B:
+ case AUX_CH_C:
+ case AUX_CH_D:
+ return DP_AUX_CH_DATA(aux_ch, index);
+ default:
+ MISSING_CASE(aux_ch);
+ return DP_AUX_CH_DATA(AUX_CH_B, index);
+ }
+}
+
+static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ enum aux_ch aux_ch = dig_port->aux_ch;
+
+ switch (aux_ch) {
+ case AUX_CH_A:
+ return DP_AUX_CH_CTL(aux_ch);
+ case AUX_CH_B:
+ case AUX_CH_C:
+ case AUX_CH_D:
+ return PCH_DP_AUX_CH_CTL(aux_ch);
+ default:
+ MISSING_CASE(aux_ch);
+ return DP_AUX_CH_CTL(AUX_CH_A);
+ }
+}
+
+static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ enum aux_ch aux_ch = dig_port->aux_ch;
+
+ switch (aux_ch) {
+ case AUX_CH_A:
+ return DP_AUX_CH_DATA(aux_ch, index);
+ case AUX_CH_B:
+ case AUX_CH_C:
+ case AUX_CH_D:
+ return PCH_DP_AUX_CH_DATA(aux_ch, index);
+ default:
+ MISSING_CASE(aux_ch);
+ return DP_AUX_CH_DATA(AUX_CH_A, index);
+ }
+}
+
+static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ enum aux_ch aux_ch = dig_port->aux_ch;
+
+ switch (aux_ch) {
+ case AUX_CH_A:
+ case AUX_CH_B:
+ case AUX_CH_C:
+ case AUX_CH_D:
+ case AUX_CH_E:
+ case AUX_CH_F:
+ return DP_AUX_CH_CTL(aux_ch);
+ default:
+ MISSING_CASE(aux_ch);
+ return DP_AUX_CH_CTL(AUX_CH_A);
+ }
+}
+
+static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ enum aux_ch aux_ch = dig_port->aux_ch;
+
+ switch (aux_ch) {
+ case AUX_CH_A:
+ case AUX_CH_B:
+ case AUX_CH_C:
+ case AUX_CH_D:
+ case AUX_CH_E:
+ case AUX_CH_F:
+ return DP_AUX_CH_DATA(aux_ch, index);
+ default:
+ MISSING_CASE(aux_ch);
+ return DP_AUX_CH_DATA(AUX_CH_A, index);
+ }
+}
+
+static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ enum aux_ch aux_ch = dig_port->aux_ch;
+
+ switch (aux_ch) {
+ case AUX_CH_A:
+ case AUX_CH_B:
+ case AUX_CH_C:
+ case AUX_CH_USBC1:
+ case AUX_CH_USBC2:
+ case AUX_CH_USBC3:
+ case AUX_CH_USBC4:
+ case AUX_CH_USBC5:
+ case AUX_CH_USBC6:
+ return DP_AUX_CH_CTL(aux_ch);
+ default:
+ MISSING_CASE(aux_ch);
+ return DP_AUX_CH_CTL(AUX_CH_A);
+ }
+}
+
+static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ enum aux_ch aux_ch = dig_port->aux_ch;
+
+ switch (aux_ch) {
+ case AUX_CH_A:
+ case AUX_CH_B:
+ case AUX_CH_C:
+ case AUX_CH_USBC1:
+ case AUX_CH_USBC2:
+ case AUX_CH_USBC3:
+ case AUX_CH_USBC4:
+ case AUX_CH_USBC5:
+ case AUX_CH_USBC6:
+ return DP_AUX_CH_DATA(aux_ch, index);
+ default:
+ MISSING_CASE(aux_ch);
+ return DP_AUX_CH_DATA(AUX_CH_A, index);
+ }
+}
+
+void intel_dp_aux_fini(struct intel_dp *intel_dp)
+{
+ if (cpu_latency_qos_request_active(&intel_dp->pm_qos))
+ cpu_latency_qos_remove_request(&intel_dp->pm_qos);
+
+ kfree(intel_dp->aux.name);
+}
+
+void intel_dp_aux_init(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ struct intel_encoder *encoder = &dig_port->base;
+ enum aux_ch aux_ch = dig_port->aux_ch;
+
+ if (INTEL_GEN(dev_priv) >= 12) {
+ intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg;
+ intel_dp->aux_ch_data_reg = tgl_aux_data_reg;
+ } else if (INTEL_GEN(dev_priv) >= 9) {
+ intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
+ intel_dp->aux_ch_data_reg = skl_aux_data_reg;
+ } else if (HAS_PCH_SPLIT(dev_priv)) {
+ intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
+ intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
+ } else {
+ intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
+ intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
+ }
+
+ if (INTEL_GEN(dev_priv) >= 9)
+ intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
+ else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
+ intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
+ else if (HAS_PCH_SPLIT(dev_priv))
+ intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
+ else
+ intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
+
+ if (INTEL_GEN(dev_priv) >= 9)
+ intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
+ else
+ intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
+
+ drm_dp_aux_init(&intel_dp->aux);
+
+ /* Failure to allocate our preferred name is not critical */
+ if (INTEL_GEN(dev_priv) >= 12 && aux_ch >= AUX_CH_USBC1)
+ intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX USBC%c/%s",
+ aux_ch - AUX_CH_USBC1 + '1',
+ encoder->base.name);
+ else
+ intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/%s",
+ aux_ch_name(aux_ch),
+ encoder->base.name);
+
+ intel_dp->aux.transfer = intel_dp_aux_transfer;
+ cpu_latency_qos_add_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.h b/drivers/gpu/drm/i915/display/intel_dp_aux.h
new file mode 100644
index 000000000000..cea58dd86c49
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#ifndef __INTEL_DP_AUX_H__
+#define __INTEL_DP_AUX_H__
+
+#include <linux/types.h>
+
+struct intel_dp;
+
+u32 intel_dp_pack_aux(const u8 *src, int src_bytes);
+
+void intel_dp_aux_fini(struct intel_dp *intel_dp);
+void intel_dp_aux_init(struct intel_dp *intel_dp);
+
+#endif /* __INTEL_DP_AUX_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 1e6c1fa59d4a..72d4c61e142e 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -28,9 +28,10 @@
#include "i915_drv.h"
#include "intel_atomic.h"
#include "intel_display_types.h"
+#include "intel_dp_aux.h"
+#include "intel_hdmi.h"
#include "intel_psr.h"
#include "intel_sprite.h"
-#include "intel_hdmi.h"
/**
* DOC: Panel Self Refresh (PSR/SRD)
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 13+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915/pps: refactor init abstractions
2021-01-20 10:18 [Intel-gfx] [PATCH 1/4] drm/i915/pps: refactor init abstractions Jani Nikula
` (2 preceding siblings ...)
2021-01-20 10:18 ` [Intel-gfx] [PATCH 4/4] drm/i915/dp: split out aux functionality to intel_dp_aux.c Jani Nikula
@ 2021-01-20 14:17 ` Patchwork
2021-01-20 14:19 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2021-01-20 14:17 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/4] drm/i915/pps: refactor init abstractions
URL : https://patchwork.freedesktop.org/series/86076/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
3210f99b0871 drm/i915/pps: refactor init abstractions
b59f412b98d3 drm/i915/pps: move pps code over from intel_display.c and refactor
6c274e339aa3 drm/i915/dp: abstract struct intel_dp pps members to a sub-struct
-:347: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#347: FILE: drivers/gpu/drm/i915/display/intel_pps.c:509:
+ panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->pps.panel_power_off_time);
-:355: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#355: FILE: drivers/gpu/drm/i915/display/intel_pps.c:515:
+ intel_dp->pps.panel_power_cycle_delay - panel_power_off_duration);
total: 0 errors, 2 warnings, 0 checks, 632 lines checked
c56c8a0d7677 drm/i915/dp: split out aux functionality to intel_dp_aux.c
-:745: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#745:
new file mode 100644
-:793: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#793: FILE: drivers/gpu/drm/i915/display/intel_dp_aux.c:44:
+#define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
-:984: WARNING:MSLEEP: msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.rst
#984: FILE: drivers/gpu/drm/i915/display/intel_dp_aux.c:235:
+ msleep(1);
total: 0 errors, 3 warnings, 0 checks, 1433 lines checked
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/4] drm/i915/pps: refactor init abstractions
2021-01-20 10:18 [Intel-gfx] [PATCH 1/4] drm/i915/pps: refactor init abstractions Jani Nikula
` (3 preceding siblings ...)
2021-01-20 14:17 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915/pps: refactor init abstractions Patchwork
@ 2021-01-20 14:19 ` Patchwork
2021-01-20 14:46 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-01-20 16:08 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
6 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2021-01-20 14:19 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/4] drm/i915/pps: refactor init abstractions
URL : https://patchwork.freedesktop.org/series/86076/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1328:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1450:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1504:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/intel_wakeref.c:137:19: warning: context imbalance in 'wakeref_auto_timeout' - unexpected unlock
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915/pps: refactor init abstractions
2021-01-20 10:18 [Intel-gfx] [PATCH 1/4] drm/i915/pps: refactor init abstractions Jani Nikula
` (4 preceding siblings ...)
2021-01-20 14:19 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2021-01-20 14:46 ` Patchwork
2021-01-20 16:08 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
6 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2021-01-20 14:46 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 4630 bytes --]
== Series Details ==
Series: series starting with [1/4] drm/i915/pps: refactor init abstractions
URL : https://patchwork.freedesktop.org/series/86076/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9650 -> Patchwork_19420
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/index.html
Known issues
------------
Here are the changes found in Patchwork_19420 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_prime@i915-to-amd:
- fi-snb-2520m: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/fi-snb-2520m/igt@amdgpu/amd_prime@i915-to-amd.html
* igt@fbdev@read:
- fi-tgl-y: [PASS][2] -> [DMESG-WARN][3] ([i915#402]) +1 similar issue
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-tgl-y/igt@fbdev@read.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/fi-tgl-y/igt@fbdev@read.html
* igt@i915_pm_rpm@module-reload:
- fi-kbl-guc: [PASS][4] -> [FAIL][5] ([i915#2203] / [i915#579])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-snb-2600: NOTRUN -> [SKIP][6] ([fdo#109271]) +30 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/fi-snb-2600/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-snb-2600: NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827]) +8 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/fi-snb-2600/igt@kms_chamelium@hdmi-crc-fast.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3:
- fi-snb-2600: [DMESG-WARN][8] ([i915#2772]) -> [PASS][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-snb-2600/igt@gem_exec_suspend@basic-s3.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/fi-snb-2600/igt@gem_exec_suspend@basic-s3.html
* igt@gem_render_tiled_blits@basic:
- fi-tgl-y: [DMESG-WARN][10] ([i915#402]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-tgl-y/igt@gem_render_tiled_blits@basic.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/fi-tgl-y/igt@gem_render_tiled_blits@basic.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2520m: [INCOMPLETE][12] -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-snb-2520m/igt@i915_selftest@live@hangcheck.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/fi-snb-2520m/igt@i915_selftest@live@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2772]: https://gitlab.freedesktop.org/drm/intel/issues/2772
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579
Participating hosts (43 -> 38)
------------------------------
Missing (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9650 -> Patchwork_19420
CI-20190529: 20190529
CI_DRM_9650: 3f989d1bb4cfd91e25549f9fd7a750412581dcc4 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5960: ace82fcd5f3623f8dde7c220a825873dc53dfae4 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19420: c56c8a0d76770a79728ee5f8fb534cc88d3070e9 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
c56c8a0d7677 drm/i915/dp: split out aux functionality to intel_dp_aux.c
6c274e339aa3 drm/i915/dp: abstract struct intel_dp pps members to a sub-struct
b59f412b98d3 drm/i915/pps: move pps code over from intel_display.c and refactor
3210f99b0871 drm/i915/pps: refactor init abstractions
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/index.html
[-- Attachment #1.2: Type: text/html, Size: 5519 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/4] drm/i915/pps: refactor init abstractions
2021-01-20 10:18 [Intel-gfx] [PATCH 1/4] drm/i915/pps: refactor init abstractions Jani Nikula
` (5 preceding siblings ...)
2021-01-20 14:46 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-01-20 16:08 ` Patchwork
6 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2021-01-20 16:08 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 22036 bytes --]
== Series Details ==
Series: series starting with [1/4] drm/i915/pps: refactor init abstractions
URL : https://patchwork.freedesktop.org/series/86076/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9650_full -> Patchwork_19420_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_19420_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@close-replace-race:
- shard-glk: [PASS][1] -> [TIMEOUT][2] ([i915#2918])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-glk6/igt@gem_ctx_persistence@close-replace-race.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-glk5/igt@gem_ctx_persistence@close-replace-race.html
* igt@gem_ctx_persistence@engines-mixed:
- shard-hsw: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-hsw6/igt@gem_ctx_persistence@engines-mixed.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][4] -> [FAIL][5] ([i915#2842]) +1 similar issue
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-tglb7/igt@gem_exec_fair@basic-flow@rcs0.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-tglb1/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [PASS][6] -> [FAIL][7] ([i915#2842]) +1 similar issue
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-kbl4/igt@gem_exec_fair@basic-none@vcs0.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-kbl4/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][8] ([i915#2842])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-iclb4/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_reloc@basic-many-active@vcs1:
- shard-iclb: NOTRUN -> [FAIL][9] ([i915#2389])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-iclb2/igt@gem_exec_reloc@basic-many-active@vcs1.html
* igt@gem_exec_schedule@u-fairslice@rcs0:
- shard-skl: [PASS][10] -> [DMESG-WARN][11] ([i915#1610] / [i915#2803])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl10/igt@gem_exec_schedule@u-fairslice@rcs0.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-skl7/igt@gem_exec_schedule@u-fairslice@rcs0.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-skl: [PASS][12] -> [FAIL][13] ([i915#644])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl5/igt@gem_ppgtt@flink-and-close-vma-leak.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-skl4/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@gem_render_copy@y-tiled-to-vebox-linear:
- shard-hsw: NOTRUN -> [SKIP][14] ([fdo#109271]) +124 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-hsw6/igt@gem_render_copy@y-tiled-to-vebox-linear.html
* igt@gem_vm_create@destroy-race:
- shard-tglb: [PASS][15] -> [TIMEOUT][16] ([i915#2795])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-tglb5/igt@gem_vm_create@destroy-race.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-tglb7/igt@gem_vm_create@destroy-race.html
* igt@gen3_mixed_blits:
- shard-kbl: NOTRUN -> [SKIP][17] ([fdo#109271]) +29 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-kbl1/igt@gen3_mixed_blits.html
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-kbl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#658])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-kbl1/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@kms_chamelium@hdmi-hpd-with-enabled-mode:
- shard-kbl: NOTRUN -> [SKIP][19] ([fdo#109271] / [fdo#111827]) +3 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-kbl1/igt@kms_chamelium@hdmi-hpd-with-enabled-mode.html
* igt@kms_chamelium@vga-frame-dump:
- shard-snb: NOTRUN -> [SKIP][20] ([fdo#109271] / [fdo#111827])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-snb4/igt@kms_chamelium@vga-frame-dump.html
* igt@kms_color@pipe-b-ctm-0-5:
- shard-skl: [PASS][21] -> [DMESG-WARN][22] ([i915#1982])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl6/igt@kms_color@pipe-b-ctm-0-5.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-skl9/igt@kms_color@pipe-b-ctm-0-5.html
* igt@kms_color_chamelium@pipe-a-ctm-green-to-red:
- shard-glk: NOTRUN -> [SKIP][23] ([fdo#109271] / [fdo#111827]) +2 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-glk5/igt@kms_color_chamelium@pipe-a-ctm-green-to-red.html
* igt@kms_color_chamelium@pipe-d-ctm-green-to-red:
- shard-skl: NOTRUN -> [SKIP][24] ([fdo#109271] / [fdo#111827]) +3 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-skl3/igt@kms_color_chamelium@pipe-d-ctm-green-to-red.html
* igt@kms_color_chamelium@pipe-d-ctm-max:
- shard-hsw: NOTRUN -> [SKIP][25] ([fdo#109271] / [fdo#111827]) +9 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-hsw5/igt@kms_color_chamelium@pipe-d-ctm-max.html
* igt@kms_cursor_crc@pipe-b-cursor-256x85-random:
- shard-skl: [PASS][26] -> [FAIL][27] ([i915#54]) +12 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl2/igt@kms_cursor_crc@pipe-b-cursor-256x85-random.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-skl5/igt@kms_cursor_crc@pipe-b-cursor-256x85-random.html
* igt@kms_cursor_edge_walk@pipe-a-64x64-top-edge:
- shard-glk: [PASS][28] -> [DMESG-WARN][29] ([i915#118] / [i915#95]) +2 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-glk8/igt@kms_cursor_edge_walk@pipe-a-64x64-top-edge.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-glk7/igt@kms_cursor_edge_walk@pipe-a-64x64-top-edge.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-skl: [PASS][30] -> [FAIL][31] ([i915#79])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl10/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-skl9/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite:
- shard-skl: NOTRUN -> [SKIP][32] ([fdo#109271]) +22 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-skl8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-pgflip-blt:
- shard-glk: NOTRUN -> [SKIP][33] ([fdo#109271]) +11 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-glk5/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-pgflip-blt.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [PASS][34] -> [FAIL][35] ([i915#1188])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl7/igt@kms_hdr@bpc-switch.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-skl4/igt@kms_hdr@bpc-switch.html
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence:
- shard-skl: NOTRUN -> [SKIP][36] ([fdo#109271] / [i915#533])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-skl4/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence.html
* igt@kms_pipe_crc_basic@read-crc-pipe-a:
- shard-glk: [PASS][37] -> [FAIL][38] ([i915#53])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-glk8/igt@kms_pipe_crc_basic@read-crc-pipe-a.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-glk7/igt@kms_pipe_crc_basic@read-crc-pipe-a.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: NOTRUN -> [FAIL][39] ([fdo#108145] / [i915#265])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-skl3/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [PASS][40] -> [FAIL][41] ([fdo#108145] / [i915#265])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][42] -> [SKIP][43] ([fdo#109441]) +1 similar issue
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-iclb7/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_vblank@pipe-d-wait-idle:
- shard-kbl: NOTRUN -> [SKIP][44] ([fdo#109271] / [i915#533])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-kbl1/igt@kms_vblank@pipe-d-wait-idle.html
#### Possible fixes ####
* igt@drm_import_export@prime:
- shard-kbl: [INCOMPLETE][45] -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-kbl7/igt@drm_import_export@prime.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-kbl1/igt@drm_import_export@prime.html
* igt@feature_discovery@psr2:
- shard-iclb: [SKIP][47] ([i915#658]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-iclb5/igt@feature_discovery@psr2.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-iclb2/igt@feature_discovery@psr2.html
* igt@gem_exec_capture@pi@vecs0:
- shard-skl: [INCOMPLETE][49] ([i915#198] / [i915#2624]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl3/igt@gem_exec_capture@pi@vecs0.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-skl2/igt@gem_exec_capture@pi@vecs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl: [FAIL][51] ([i915#2842]) -> [PASS][52] +1 similar issue
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-kbl6/igt@gem_exec_fair@basic-pace@vecs0.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-kbl7/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [FAIL][53] ([i915#2842]) -> [PASS][54] +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-glk3/igt@gem_exec_fair@basic-throttle@rcs0.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-glk8/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_schedule@u-fairslice@rcs0:
- shard-glk: [DMESG-WARN][55] ([i915#1610]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-glk9/igt@gem_exec_schedule@u-fairslice@rcs0.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-glk5/igt@gem_exec_schedule@u-fairslice@rcs0.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy@gtt:
- shard-hsw: [INCOMPLETE][57] -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-hsw8/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy@gtt.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-hsw5/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy@gtt.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-snb: [INCOMPLETE][59] ([i915#2880]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-snb7/igt@i915_module_load@reload-with-fault-injection.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-snb4/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_suspend@sysfs-reader:
- shard-skl: [INCOMPLETE][61] ([i915#146] / [i915#198]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl2/igt@i915_suspend@sysfs-reader.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-skl3/igt@i915_suspend@sysfs-reader.html
* igt@kms_cursor_crc@pipe-b-cursor-128x42-sliding:
- shard-skl: [FAIL][63] ([i915#54]) -> [PASS][64] +5 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl7/igt@kms_cursor_crc@pipe-b-cursor-128x42-sliding.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-skl4/igt@kms_cursor_crc@pipe-b-cursor-128x42-sliding.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
- shard-hsw: [FAIL][65] ([i915#96]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-hsw8/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-hsw8/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: [FAIL][67] ([i915#2346]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-skl: [FAIL][69] ([i915#79]) -> [PASS][70] +1 similar issue
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl10/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@kms_flip@plain-flip-fb-recreate@c-edp1:
- shard-skl: [FAIL][71] ([i915#2122]) -> [PASS][72] +2 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl10/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-skl9/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-cpu:
- shard-skl: [DMESG-WARN][73] ([i915#1982]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl10/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-cpu.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-skl9/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-cpu.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [SKIP][75] ([fdo#109441]) -> [PASS][76] +2 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-iclb6/igt@kms_psr@psr2_primary_mmap_cpu.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
#### Warnings ####
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-iclb: [WARN][77] ([i915#2684]) -> [WARN][78] ([i915#1804] / [i915#2684])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-iclb2/igt@i915_pm_rc6_residency@rc6-fence.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-iclb7/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][79] ([i915#1804] / [i915#2684]) -> [WARN][80] ([i915#2681] / [i915#2684])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-iclb4/igt@i915_pm_rc6_residency@rc6-idle.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-iclb8/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2:
- shard-iclb: [SKIP][81] ([i915#658]) -> [SKIP][82] ([i915#2920]) +2 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-iclb1/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4:
- shard-iclb: [SKIP][83] ([i915#2920]) -> [SKIP][84] ([i915#658]) +2 similar issues
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-iclb7/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][85], [FAIL][86]) ([i915#2295] / [i915#2505] / [i915#2722]) -> [FAIL][87] ([i915#2295])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-kbl6/igt@runner@aborted.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-kbl7/igt@runner@aborted.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-kbl3/igt@runner@aborted.html
- shard-glk: ([FAIL][88], [FAIL][89]) ([i915#2295] / [i915#2426] / [k.org#202321]) -> [FAIL][90] ([i915#2295] / [k.org#202321])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-glk4/igt@runner@aborted.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-glk9/igt@runner@aborted.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-glk4/igt@runner@aborted.html
- shard-skl: ([FAIL][91], [FAIL][92]) ([i915#1436] / [i915#2295]) -> ([FAIL][93], [FAIL][94], [FAIL][95]) ([i915#1436] / [i915#2295] / [i915#2426])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl9/igt@runner@aborted.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl4/igt@runner@aborted.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-skl7/igt@runner@aborted.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-skl5/igt@runner@aborted.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-skl10/igt@runner@aborted.html
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
[i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610
[i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2505]: https://gitlab.freedesktop.org/drm/intel/issues/2505
[i915#2624]: https://gitlab.freedesktop.org/drm/intel/issues/2624
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#2795]: https://gitlab.freedesktop.org/drm/intel/issues/2795
[i915#2803]: https://gitlab.freedesktop.org/drm/intel/issues/2803
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2880]: https://gitlab.freedesktop.org/drm/intel/issues/2880
[i915#2918]: https://gitlab.freedesktop.org/drm/intel/issues/2918
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#53]: https://gitlab.freedesktop.org/drm/intel/issues/53
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
[i915#96]: https://gitlab.freedesktop.org/drm/intel/issues/96
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_9650 -> Patchwork_19420
CI-20190529: 20190529
CI_DRM_9650: 3f989d1bb4cfd91e25549f9fd7a750412581dcc4 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5960: ace82fcd5f3623f8dde7c220a825873dc53dfae4 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19420: c56c8a0d76770a79728ee5f8fb534cc88d3070e9 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/index.html
[-- Attachment #1.2: Type: text/html, Size: 26887 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH 3/4] drm/i915/dp: abstract struct intel_dp pps members to a sub-struct
2021-01-20 10:18 ` [Intel-gfx] [PATCH 3/4] drm/i915/dp: abstract struct intel_dp pps members to a sub-struct Jani Nikula
@ 2021-01-20 17:30 ` Rodrigo Vivi
2021-01-20 19:25 ` Jani Nikula
0 siblings, 1 reply; 13+ messages in thread
From: Rodrigo Vivi @ 2021-01-20 17:30 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Wed, Jan 20, 2021 at 12:18:33PM +0200, Jani Nikula wrote:
> Add some namespacing to highlight what belongs where. No functional
> changes.
>
> Cc: Anshuman Gupta <anshuman.gupta@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> .../drm/i915/display/intel_display_debugfs.c | 8 +-
> .../drm/i915/display/intel_display_types.h | 61 +++---
> drivers/gpu/drm/i915/display/intel_dp.c | 14 +-
> drivers/gpu/drm/i915/display/intel_pps.c | 192 +++++++++---------
> 4 files changed, 140 insertions(+), 135 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index cd7e5519ee7d..885d2d3c91a3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -2155,13 +2155,13 @@ static int i915_panel_show(struct seq_file *m, void *data)
> return -ENODEV;
>
> seq_printf(m, "Panel power up delay: %d\n",
> - intel_dp->panel_power_up_delay);
> + intel_dp->pps.panel_power_up_delay);
> seq_printf(m, "Panel power down delay: %d\n",
> - intel_dp->panel_power_down_delay);
> + intel_dp->pps.panel_power_down_delay);
> seq_printf(m, "Backlight on delay: %d\n",
> - intel_dp->backlight_on_delay);
> + intel_dp->pps.backlight_on_delay);
> seq_printf(m, "Backlight off delay: %d\n",
> - intel_dp->backlight_off_delay);
> + intel_dp->pps.backlight_off_delay);
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index b601e804f854..1a9243426a25 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1369,6 +1369,38 @@ struct intel_dp_pcon_frl {
> int trained_rate_gbps;
> };
>
> +struct intel_pps {
PPS for Panel Power Something (Sequence? Struct?)
> + int panel_power_up_delay;
if we have panel power already could we remove panel_power_ from
here to simply use pps.up_delay ?
> + int panel_power_down_delay;
> + int panel_power_cycle_delay;
> + int backlight_on_delay;
> + int backlight_off_delay;
> + struct delayed_work panel_vdd_work;
> + bool want_panel_vdd;
> + unsigned long last_power_on;
> + unsigned long last_backlight_off;
> + ktime_t panel_power_off_time;
> + intel_wakeref_t vdd_wakeref;
> +
> + /*
> + * Pipe whose power sequencer is currently locked into
> + * this port. Only relevant on VLV/CHV.
> + */
> + enum pipe pps_pipe;
and pps.pipe
> + /*
> + * Pipe currently driving the port. Used for preventing
> + * the use of the PPS for any pipe currentrly driving
> + * external DP as that will mess things up on VLV.
> + */
> + enum pipe active_pipe;
> + /*
> + * Set if the sequencer may be reset due to a power transition,
> + * requiring a reinitialization. Only relevant on BXT.
> + */
> + bool pps_reset;
and pps.reset ?
> + struct edp_power_seq pps_delays;
> +};
> +
> struct intel_dp {
> i915_reg_t output_reg;
> u32 DP;
> @@ -1408,35 +1440,8 @@ struct intel_dp {
> struct drm_dp_aux aux;
> u32 aux_busy_last_status;
> u8 train_set[4];
> - int panel_power_up_delay;
> - int panel_power_down_delay;
> - int panel_power_cycle_delay;
> - int backlight_on_delay;
> - int backlight_off_delay;
> - struct delayed_work panel_vdd_work;
> - bool want_panel_vdd;
> - unsigned long last_power_on;
> - unsigned long last_backlight_off;
> - ktime_t panel_power_off_time;
> - intel_wakeref_t vdd_wakeref;
>
> - /*
> - * Pipe whose power sequencer is currently locked into
> - * this port. Only relevant on VLV/CHV.
> - */
> - enum pipe pps_pipe;
> - /*
> - * Pipe currently driving the port. Used for preventing
> - * the use of the PPS for any pipe currentrly driving
> - * external DP as that will mess things up on VLV.
> - */
> - enum pipe active_pipe;
> - /*
> - * Set if the sequencer may be reset due to a power transition,
> - * requiring a reinitialization. Only relevant on BXT.
> - */
> - bool pps_reset;
> - struct edp_power_seq pps_delays;
> + struct intel_pps pps;
>
> bool can_mst; /* this port supports mst */
> bool is_mst;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 8b9c20555f0e..d815087a26aa 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4129,7 +4129,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
> intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
> }
>
> - msleep(intel_dp->panel_power_down_delay);
> + msleep(intel_dp->pps.panel_power_down_delay);
>
> intel_dp->DP = DP;
>
> @@ -4137,7 +4137,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
> intel_wakeref_t wakeref;
>
> with_intel_pps_lock(intel_dp, wakeref)
> - intel_dp->active_pipe = INVALID_PIPE;
> + intel_dp->pps.active_pipe = INVALID_PIPE;
> }
> }
>
> @@ -6368,7 +6368,7 @@ void intel_dp_encoder_reset(struct drm_encoder *encoder)
> intel_wakeref_t wakeref;
>
> with_intel_pps_lock(intel_dp, wakeref)
> - intel_dp->active_pipe = vlv_active_pipe(intel_dp);
> + intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
> }
>
> intel_pps_encoder_reset(intel_dp);
> @@ -7139,7 +7139,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
> pipe = vlv_active_pipe(intel_dp);
>
> if (pipe != PIPE_A && pipe != PIPE_B)
> - pipe = intel_dp->pps_pipe;
> + pipe = intel_dp->pps.pps_pipe;
>
> if (pipe != PIPE_A && pipe != PIPE_B)
> pipe = PIPE_A;
> @@ -7216,8 +7216,8 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
> intel_dp_set_source_rates(intel_dp);
>
> intel_dp->reset_link_params = true;
> - intel_dp->pps_pipe = INVALID_PIPE;
> - intel_dp->active_pipe = INVALID_PIPE;
> + intel_dp->pps.pps_pipe = INVALID_PIPE;
> + intel_dp->pps.active_pipe = INVALID_PIPE;
>
> /* Preserve the current hw state. */
> intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
> @@ -7235,7 +7235,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
> }
>
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> - intel_dp->active_pipe = vlv_active_pipe(intel_dp);
> + intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
>
> /*
> * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
> index 69d9d41b6d22..c4867a8020a5 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.c
> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> @@ -44,7 +44,7 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> - enum pipe pipe = intel_dp->pps_pipe;
> + enum pipe pipe = intel_dp->pps.pps_pipe;
> bool pll_enabled, release_cl_override = false;
> enum dpio_phy phy = DPIO_PHY(pipe);
> enum dpio_channel ch = vlv_pipe_to_channel(pipe);
> @@ -130,18 +130,18 @@ static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
>
> if (encoder->type == INTEL_OUTPUT_EDP) {
> drm_WARN_ON(&dev_priv->drm,
> - intel_dp->active_pipe != INVALID_PIPE &&
> - intel_dp->active_pipe !=
> - intel_dp->pps_pipe);
> + intel_dp->pps.active_pipe != INVALID_PIPE &&
> + intel_dp->pps.active_pipe !=
> + intel_dp->pps.pps_pipe);
>
> - if (intel_dp->pps_pipe != INVALID_PIPE)
> - pipes &= ~(1 << intel_dp->pps_pipe);
> + if (intel_dp->pps.pps_pipe != INVALID_PIPE)
> + pipes &= ~(1 << intel_dp->pps.pps_pipe);
> } else {
> drm_WARN_ON(&dev_priv->drm,
> - intel_dp->pps_pipe != INVALID_PIPE);
> + intel_dp->pps.pps_pipe != INVALID_PIPE);
>
> - if (intel_dp->active_pipe != INVALID_PIPE)
> - pipes &= ~(1 << intel_dp->active_pipe);
> + if (intel_dp->pps.active_pipe != INVALID_PIPE)
> + pipes &= ~(1 << intel_dp->pps.active_pipe);
> }
> }
>
> @@ -163,11 +163,11 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
> /* We should never land here with regular DP ports */
> drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
>
> - drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE &&
> - intel_dp->active_pipe != intel_dp->pps_pipe);
> + drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE &&
> + intel_dp->pps.active_pipe != intel_dp->pps.pps_pipe);
>
> - if (intel_dp->pps_pipe != INVALID_PIPE)
> - return intel_dp->pps_pipe;
> + if (intel_dp->pps.pps_pipe != INVALID_PIPE)
> + return intel_dp->pps.pps_pipe;
>
> pipe = vlv_find_free_pps(dev_priv);
>
> @@ -179,11 +179,11 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
> pipe = PIPE_A;
>
> vlv_steal_power_sequencer(dev_priv, pipe);
> - intel_dp->pps_pipe = pipe;
> + intel_dp->pps.pps_pipe = pipe;
>
> drm_dbg_kms(&dev_priv->drm,
> "picked pipe %c power sequencer for [ENCODER:%d:%s]\n",
> - pipe_name(intel_dp->pps_pipe),
> + pipe_name(intel_dp->pps.pps_pipe),
> dig_port->base.base.base.id,
> dig_port->base.base.name);
>
> @@ -197,7 +197,7 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
> */
> vlv_power_sequencer_kick(intel_dp);
>
> - return intel_dp->pps_pipe;
> + return intel_dp->pps.pps_pipe;
> }
>
> static int
> @@ -211,10 +211,10 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp)
> /* We should never land here with regular DP ports */
> drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
>
> - if (!intel_dp->pps_reset)
> + if (!intel_dp->pps.pps_reset)
> return backlight_controller;
>
> - intel_dp->pps_reset = false;
> + intel_dp->pps.pps_reset = false;
>
> /*
> * Only the HW needs to be reprogrammed, the SW state is fixed and
> @@ -280,19 +280,19 @@ vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
>
> /* try to find a pipe with this port selected */
> /* first pick one where the panel is on */
> - intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
> - vlv_pipe_has_pp_on);
> + intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
> + vlv_pipe_has_pp_on);
> /* didn't find one? pick one where vdd is on */
> - if (intel_dp->pps_pipe == INVALID_PIPE)
> - intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
> - vlv_pipe_has_vdd_on);
> + if (intel_dp->pps.pps_pipe == INVALID_PIPE)
> + intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
> + vlv_pipe_has_vdd_on);
> /* didn't find one? pick one with just the correct port */
> - if (intel_dp->pps_pipe == INVALID_PIPE)
> - intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
> - vlv_pipe_any);
> + if (intel_dp->pps.pps_pipe == INVALID_PIPE)
> + intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
> + vlv_pipe_any);
>
> /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
> - if (intel_dp->pps_pipe == INVALID_PIPE) {
> + if (intel_dp->pps.pps_pipe == INVALID_PIPE) {
> drm_dbg_kms(&dev_priv->drm,
> "no initial power sequencer for [ENCODER:%d:%s]\n",
> dig_port->base.base.base.id,
> @@ -304,7 +304,7 @@ vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
> "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n",
> dig_port->base.base.base.id,
> dig_port->base.base.name,
> - pipe_name(intel_dp->pps_pipe));
> + pipe_name(intel_dp->pps.pps_pipe));
> }
>
> void intel_pps_reset_all(struct drm_i915_private *dev_priv)
> @@ -331,15 +331,15 @@ void intel_pps_reset_all(struct drm_i915_private *dev_priv)
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>
> drm_WARN_ON(&dev_priv->drm,
> - intel_dp->active_pipe != INVALID_PIPE);
> + intel_dp->pps.active_pipe != INVALID_PIPE);
>
> if (encoder->type != INTEL_OUTPUT_EDP)
> continue;
>
> if (IS_GEN9_LP(dev_priv))
> - intel_dp->pps_reset = true;
> + intel_dp->pps.pps_reset = true;
> else
> - intel_dp->pps_pipe = INVALID_PIPE;
> + intel_dp->pps.pps_pipe = INVALID_PIPE;
> }
> }
>
> @@ -403,7 +403,7 @@ static bool edp_have_panel_power(struct intel_dp *intel_dp)
> lockdep_assert_held(&dev_priv->pps_mutex);
>
> if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> - intel_dp->pps_pipe == INVALID_PIPE)
> + intel_dp->pps.pps_pipe == INVALID_PIPE)
> return false;
>
> return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON) != 0;
> @@ -416,7 +416,7 @@ static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
> lockdep_assert_held(&dev_priv->pps_mutex);
>
> if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> - intel_dp->pps_pipe == INVALID_PIPE)
> + intel_dp->pps.pps_pipe == INVALID_PIPE)
> return false;
>
> return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
> @@ -506,13 +506,13 @@ static void wait_panel_power_cycle(struct intel_dp *intel_dp)
> /* take the difference of currrent time and panel power off time
> * and then make panel wait for t11_t12 if needed. */
> panel_power_on_time = ktime_get_boottime();
> - panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
> + panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->pps.panel_power_off_time);
>
> /* When we disable the VDD override bit last we have to do the manual
> * wait. */
> - if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
> + if (panel_power_off_duration < (s64)intel_dp->pps.panel_power_cycle_delay)
> wait_remaining_ms_from_jiffies(jiffies,
> - intel_dp->panel_power_cycle_delay - panel_power_off_duration);
> + intel_dp->pps.panel_power_cycle_delay - panel_power_off_duration);
>
> wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
> }
> @@ -530,14 +530,14 @@ void intel_pps_wait_power_cycle(struct intel_dp *intel_dp)
>
> static void wait_backlight_on(struct intel_dp *intel_dp)
> {
> - wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
> - intel_dp->backlight_on_delay);
> + wait_remaining_ms_from_jiffies(intel_dp->pps.last_power_on,
> + intel_dp->pps.backlight_on_delay);
> }
>
> static void edp_wait_backlight_off(struct intel_dp *intel_dp)
> {
> - wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
> - intel_dp->backlight_off_delay);
> + wait_remaining_ms_from_jiffies(intel_dp->pps.last_backlight_off,
> + intel_dp->pps.backlight_off_delay);
> }
>
> /* Read the current pp_control value, unlocking the register if it
> @@ -571,22 +571,22 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp)
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> u32 pp;
> i915_reg_t pp_stat_reg, pp_ctrl_reg;
> - bool need_to_disable = !intel_dp->want_panel_vdd;
> + bool need_to_disable = !intel_dp->pps.want_panel_vdd;
>
> lockdep_assert_held(&dev_priv->pps_mutex);
>
> if (!intel_dp_is_edp(intel_dp))
> return false;
>
> - cancel_delayed_work(&intel_dp->panel_vdd_work);
> - intel_dp->want_panel_vdd = true;
> + cancel_delayed_work(&intel_dp->pps.panel_vdd_work);
> + intel_dp->pps.want_panel_vdd = true;
>
> if (edp_have_panel_vdd(intel_dp))
> return need_to_disable;
>
> - drm_WARN_ON(&dev_priv->drm, intel_dp->vdd_wakeref);
> - intel_dp->vdd_wakeref = intel_display_power_get(dev_priv,
> - intel_aux_power_domain(dig_port));
> + drm_WARN_ON(&dev_priv->drm, intel_dp->pps.vdd_wakeref);
> + intel_dp->pps.vdd_wakeref = intel_display_power_get(dev_priv,
> + intel_aux_power_domain(dig_port));
>
> drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD on\n",
> dig_port->base.base.base.id,
> @@ -614,7 +614,7 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp)
> "[ENCODER:%d:%s] panel power wasn't enabled\n",
> dig_port->base.base.base.id,
> dig_port->base.base.name);
> - msleep(intel_dp->panel_power_up_delay);
> + msleep(intel_dp->pps.panel_power_up_delay);
> }
>
> return need_to_disable;
> @@ -652,7 +652,7 @@ static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
>
> lockdep_assert_held(&dev_priv->pps_mutex);
>
> - drm_WARN_ON(&dev_priv->drm, intel_dp->want_panel_vdd);
> + drm_WARN_ON(&dev_priv->drm, intel_dp->pps.want_panel_vdd);
>
> if (!edp_have_panel_vdd(intel_dp))
> return;
> @@ -676,11 +676,11 @@ static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
> intel_de_read(dev_priv, pp_ctrl_reg));
>
> if ((pp & PANEL_POWER_ON) == 0)
> - intel_dp->panel_power_off_time = ktime_get_boottime();
> + intel_dp->pps.panel_power_off_time = ktime_get_boottime();
>
> intel_display_power_put(dev_priv,
> intel_aux_power_domain(dig_port),
> - fetch_and_zero(&intel_dp->vdd_wakeref));
> + fetch_and_zero(&intel_dp->pps.vdd_wakeref));
> }
>
> void intel_pps_vdd_off_sync(struct intel_dp *intel_dp)
> @@ -690,7 +690,7 @@ void intel_pps_vdd_off_sync(struct intel_dp *intel_dp)
> if (!intel_dp_is_edp(intel_dp))
> return;
>
> - cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
> + cancel_delayed_work_sync(&intel_dp->pps.panel_vdd_work);
> /*
> * vdd might still be enabled due to the delayed vdd off.
> * Make sure vdd is actually turned off here.
> @@ -701,13 +701,13 @@ void intel_pps_vdd_off_sync(struct intel_dp *intel_dp)
>
> static void edp_panel_vdd_work(struct work_struct *__work)
> {
> - struct intel_dp *intel_dp =
> - container_of(to_delayed_work(__work),
> - struct intel_dp, panel_vdd_work);
> + struct intel_pps *pps = container_of(to_delayed_work(__work),
> + struct intel_pps, panel_vdd_work);
> + struct intel_dp *intel_dp = container_of(pps, struct intel_dp, pps);
> intel_wakeref_t wakeref;
>
> with_intel_pps_lock(intel_dp, wakeref) {
> - if (!intel_dp->want_panel_vdd)
> + if (!intel_dp->pps.want_panel_vdd)
> intel_pps_vdd_off_sync_unlocked(intel_dp);
> }
> }
> @@ -721,8 +721,8 @@ static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
> * down delay) to keep the panel power up across a sequence of
> * operations.
> */
> - delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
> - schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
> + delay = msecs_to_jiffies(intel_dp->pps.panel_power_cycle_delay * 5);
> + schedule_delayed_work(&intel_dp->pps.panel_vdd_work, delay);
> }
>
> /*
> @@ -739,11 +739,11 @@ void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync)
> if (!intel_dp_is_edp(intel_dp))
> return;
>
> - I915_STATE_WARN(!intel_dp->want_panel_vdd, "[ENCODER:%d:%s] VDD not forced on",
> + I915_STATE_WARN(!intel_dp->pps.want_panel_vdd, "[ENCODER:%d:%s] VDD not forced on",
> dp_to_dig_port(intel_dp)->base.base.base.id,
> dp_to_dig_port(intel_dp)->base.base.name);
>
> - intel_dp->want_panel_vdd = false;
> + intel_dp->pps.want_panel_vdd = false;
>
> if (sync)
> intel_pps_vdd_off_sync_unlocked(intel_dp);
> @@ -791,7 +791,7 @@ void intel_pps_on_unlocked(struct intel_dp *intel_dp)
> intel_de_posting_read(dev_priv, pp_ctrl_reg);
>
> wait_panel_on(intel_dp);
> - intel_dp->last_power_on = jiffies;
> + intel_dp->pps.last_power_on = jiffies;
>
> if (IS_GEN(dev_priv, 5)) {
> pp |= PANEL_POWER_RESET; /* restore panel reset bit */
> @@ -826,7 +826,7 @@ void intel_pps_off_unlocked(struct intel_dp *intel_dp)
> drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power off\n",
> dig_port->base.base.base.id, dig_port->base.base.name);
>
> - drm_WARN(&dev_priv->drm, !intel_dp->want_panel_vdd,
> + drm_WARN(&dev_priv->drm, !intel_dp->pps.want_panel_vdd,
> "Need [ENCODER:%d:%s] VDD to turn off panel\n",
> dig_port->base.base.base.id, dig_port->base.base.name);
>
> @@ -838,18 +838,18 @@ void intel_pps_off_unlocked(struct intel_dp *intel_dp)
>
> pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
>
> - intel_dp->want_panel_vdd = false;
> + intel_dp->pps.want_panel_vdd = false;
>
> intel_de_write(dev_priv, pp_ctrl_reg, pp);
> intel_de_posting_read(dev_priv, pp_ctrl_reg);
>
> wait_panel_off(intel_dp);
> - intel_dp->panel_power_off_time = ktime_get_boottime();
> + intel_dp->pps.panel_power_off_time = ktime_get_boottime();
>
> /* We got a reference when we enabled the VDD. */
> intel_display_power_put(dev_priv,
> intel_aux_power_domain(dig_port),
> - fetch_and_zero(&intel_dp->vdd_wakeref));
> + fetch_and_zero(&intel_dp->pps.vdd_wakeref));
> }
>
> void intel_pps_off(struct intel_dp *intel_dp)
> @@ -909,7 +909,7 @@ void intel_pps_backlight_off(struct intel_dp *intel_dp)
> intel_de_posting_read(dev_priv, pp_ctrl_reg);
> }
>
> - intel_dp->last_backlight_off = jiffies;
> + intel_dp->pps.last_backlight_off = jiffies;
> edp_wait_backlight_off(intel_dp);
> }
>
> @@ -943,10 +943,10 @@ static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
> {
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> - enum pipe pipe = intel_dp->pps_pipe;
> + enum pipe pipe = intel_dp->pps.pps_pipe;
> i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
>
> - drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE);
> + drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE);
>
> if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B))
> return;
> @@ -969,7 +969,7 @@ static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
> intel_de_write(dev_priv, pp_on_reg, 0);
> intel_de_posting_read(dev_priv, pp_on_reg);
>
> - intel_dp->pps_pipe = INVALID_PIPE;
> + intel_dp->pps.pps_pipe = INVALID_PIPE;
> }
>
> static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
> @@ -982,12 +982,12 @@ static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
> for_each_intel_dp(&dev_priv->drm, encoder) {
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>
> - drm_WARN(&dev_priv->drm, intel_dp->active_pipe == pipe,
> + drm_WARN(&dev_priv->drm, intel_dp->pps.active_pipe == pipe,
> "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n",
> pipe_name(pipe), encoder->base.base.id,
> encoder->base.name);
>
> - if (intel_dp->pps_pipe != pipe)
> + if (intel_dp->pps.pps_pipe != pipe)
> continue;
>
> drm_dbg_kms(&dev_priv->drm,
> @@ -1009,10 +1009,10 @@ void vlv_pps_init(struct intel_encoder *encoder,
>
> lockdep_assert_held(&dev_priv->pps_mutex);
>
> - drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE);
> + drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE);
>
> - if (intel_dp->pps_pipe != INVALID_PIPE &&
> - intel_dp->pps_pipe != crtc->pipe) {
> + if (intel_dp->pps.pps_pipe != INVALID_PIPE &&
> + intel_dp->pps.pps_pipe != crtc->pipe) {
> /*
> * If another power sequencer was being used on this
> * port previously make sure to turn off vdd there while
> @@ -1027,17 +1027,17 @@ void vlv_pps_init(struct intel_encoder *encoder,
> */
> vlv_steal_power_sequencer(dev_priv, crtc->pipe);
>
> - intel_dp->active_pipe = crtc->pipe;
> + intel_dp->pps.active_pipe = crtc->pipe;
>
> if (!intel_dp_is_edp(intel_dp))
> return;
>
> /* now it's all ours */
> - intel_dp->pps_pipe = crtc->pipe;
> + intel_dp->pps.pps_pipe = crtc->pipe;
>
> drm_dbg_kms(&dev_priv->drm,
> "initializing pipe %c power sequencer for [ENCODER:%d:%s]\n",
> - pipe_name(intel_dp->pps_pipe), encoder->base.base.id,
> + pipe_name(intel_dp->pps.pps_pipe), encoder->base.base.id,
> encoder->base.name);
>
> /* init power sequencer on this pipe and port */
> @@ -1063,9 +1063,9 @@ static void intel_pps_vdd_sanitize(struct intel_dp *intel_dp)
> */
> drm_dbg_kms(&dev_priv->drm,
> "VDD left on by BIOS, adjusting state tracking\n");
> - drm_WARN_ON(&dev_priv->drm, intel_dp->vdd_wakeref);
> - intel_dp->vdd_wakeref = intel_display_power_get(dev_priv,
> - intel_aux_power_domain(dig_port));
> + drm_WARN_ON(&dev_priv->drm, intel_dp->pps.vdd_wakeref);
> + intel_dp->pps.vdd_wakeref = intel_display_power_get(dev_priv,
> + intel_aux_power_domain(dig_port));
>
> edp_panel_vdd_schedule_off(intel_dp);
> }
> @@ -1085,9 +1085,9 @@ bool intel_pps_have_power(struct intel_dp *intel_dp)
>
> static void pps_init_timestamps(struct intel_dp *intel_dp)
> {
> - intel_dp->panel_power_off_time = ktime_get_boottime();
> - intel_dp->last_power_on = jiffies;
> - intel_dp->last_backlight_off = jiffies;
> + intel_dp->pps.panel_power_off_time = ktime_get_boottime();
> + intel_dp->pps.last_power_on = jiffies;
> + intel_dp->pps.last_backlight_off = jiffies;
> }
>
> static void
> @@ -1137,7 +1137,7 @@ static void
> intel_pps_verify_state(struct intel_dp *intel_dp)
> {
> struct edp_power_seq hw;
> - struct edp_power_seq *sw = &intel_dp->pps_delays;
> + struct edp_power_seq *sw = &intel_dp->pps.pps_delays;
>
> intel_pps_readout_hw_state(intel_dp, &hw);
>
> @@ -1153,7 +1153,7 @@ static void pps_init_delays(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> struct edp_power_seq cur, vbt, spec,
> - *final = &intel_dp->pps_delays;
> + *final = &intel_dp->pps.pps_delays;
>
> lockdep_assert_held(&dev_priv->pps_mutex);
>
> @@ -1210,22 +1210,22 @@ static void pps_init_delays(struct intel_dp *intel_dp)
> #undef assign_final
>
> #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
> - intel_dp->panel_power_up_delay = get_delay(t1_t3);
> - intel_dp->backlight_on_delay = get_delay(t8);
> - intel_dp->backlight_off_delay = get_delay(t9);
> - intel_dp->panel_power_down_delay = get_delay(t10);
> - intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
> + intel_dp->pps.panel_power_up_delay = get_delay(t1_t3);
> + intel_dp->pps.backlight_on_delay = get_delay(t8);
> + intel_dp->pps.backlight_off_delay = get_delay(t9);
> + intel_dp->pps.panel_power_down_delay = get_delay(t10);
> + intel_dp->pps.panel_power_cycle_delay = get_delay(t11_t12);
> #undef get_delay
>
> drm_dbg_kms(&dev_priv->drm,
> "panel power up delay %d, power down delay %d, power cycle delay %d\n",
> - intel_dp->panel_power_up_delay,
> - intel_dp->panel_power_down_delay,
> - intel_dp->panel_power_cycle_delay);
> + intel_dp->pps.panel_power_up_delay,
> + intel_dp->pps.panel_power_down_delay,
> + intel_dp->pps.panel_power_cycle_delay);
>
> drm_dbg_kms(&dev_priv->drm, "backlight on delay %d, off delay %d\n",
> - intel_dp->backlight_on_delay,
> - intel_dp->backlight_off_delay);
> + intel_dp->pps.backlight_on_delay,
> + intel_dp->pps.backlight_off_delay);
>
> /*
> * We override the HW backlight delays to 1 because we do manual waits
> @@ -1251,7 +1251,7 @@ static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd
> int div = RUNTIME_INFO(dev_priv)->rawclk_freq / 1000;
> struct pps_registers regs;
> enum port port = dp_to_dig_port(intel_dp)->base.port;
> - const struct edp_power_seq *seq = &intel_dp->pps_delays;
> + const struct edp_power_seq *seq = &intel_dp->pps.pps_delays;
>
> lockdep_assert_held(&dev_priv->pps_mutex);
>
> @@ -1364,7 +1364,7 @@ void intel_pps_encoder_reset(struct intel_dp *intel_dp)
>
> void intel_pps_init(struct intel_dp *intel_dp)
> {
> - INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work);
> + INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work);
>
> pps_init_timestamps(intel_dp);
>
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH 4/4] drm/i915/dp: split out aux functionality to intel_dp_aux.c
2021-01-20 10:18 ` [Intel-gfx] [PATCH 4/4] drm/i915/dp: split out aux functionality to intel_dp_aux.c Jani Nikula
@ 2021-01-20 17:31 ` Rodrigo Vivi
0 siblings, 0 replies; 13+ messages in thread
From: Rodrigo Vivi @ 2021-01-20 17:31 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Wed, Jan 20, 2021 at 12:18:34PM +0200, Jani Nikula wrote:
> Split out the DP aux functionality to a new intel_dp_aux.[ch]. This is a
> surprisingly clean cut.
I had wondered about this split in the past... surprisingly clean cut indeed...
>
> v2:
> - Remove intel_dp_pack_aux declaration from intel_dp.h (Anshuman)
> - Fixed some whitespace/comment checkpatch warnings
>
> Cc: Anshuman Gupta <anshuman.gupta@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/display/intel_dp.c | 680 +------------------
> drivers/gpu/drm/i915/display/intel_dp.h | 1 -
> drivers/gpu/drm/i915/display/intel_dp_aux.c | 692 ++++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_dp_aux.h | 18 +
> drivers/gpu/drm/i915/display/intel_psr.c | 3 +-
> 6 files changed, 714 insertions(+), 681 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_dp_aux.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_dp_aux.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 006dec54408d..ea1cc5736049 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -243,6 +243,7 @@ i915-y += \
> display/intel_crt.o \
> display/intel_ddi.o \
> display/intel_dp.o \
> + display/intel_dp_aux.o \
> display/intel_dp_aux_backlight.o \
> display/intel_dp_hdcp.o \
> display/intel_dp_link_training.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index d815087a26aa..8979996f1747 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -41,13 +41,13 @@
>
> #include "i915_debugfs.h"
> #include "i915_drv.h"
> -#include "i915_trace.h"
> #include "intel_atomic.h"
> #include "intel_audio.h"
> #include "intel_connector.h"
> #include "intel_ddi.h"
> #include "intel_display_types.h"
> #include "intel_dp.h"
> +#include "intel_dp_aux.h"
> #include "intel_dp_link_training.h"
> #include "intel_dp_mst.h"
> #include "intel_dpio_phy.h"
> @@ -862,684 +862,6 @@ intel_dp_mode_valid(struct drm_connector *connector,
> return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
> }
>
> -u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
> -{
> - int i;
> - u32 v = 0;
> -
> - if (src_bytes > 4)
> - src_bytes = 4;
> - for (i = 0; i < src_bytes; i++)
> - v |= ((u32)src[i]) << ((3 - i) * 8);
> - return v;
> -}
> -
> -static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes)
> -{
> - int i;
> - if (dst_bytes > 4)
> - dst_bytes = 4;
> - for (i = 0; i < dst_bytes; i++)
> - dst[i] = src >> ((3-i) * 8);
> -}
> -
> -static u32
> -intel_dp_aux_wait_done(struct intel_dp *intel_dp)
> -{
> - struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> - i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
> - const unsigned int timeout_ms = 10;
> - u32 status;
> - bool done;
> -
> -#define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
> - done = wait_event_timeout(i915->gmbus_wait_queue, C,
> - msecs_to_jiffies_timeout(timeout_ms));
> -
> - /* just trace the final value */
> - trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
> -
> - if (!done)
> - drm_err(&i915->drm,
> - "%s: did not complete or timeout within %ums (status 0x%08x)\n",
> - intel_dp->aux.name, timeout_ms, status);
> -#undef C
> -
> - return status;
> -}
> -
> -static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
> -{
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> -
> - if (index)
> - return 0;
> -
> - /*
> - * The clock divider is based off the hrawclk, and would like to run at
> - * 2MHz. So, take the hrawclk value and divide by 2000 and use that
> - */
> - return DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq, 2000);
> -}
> -
> -static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
> -{
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> - u32 freq;
> -
> - if (index)
> - return 0;
> -
> - /*
> - * The clock divider is based off the cdclk or PCH rawclk, and would
> - * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
> - * divide by 2000 and use that
> - */
> - if (dig_port->aux_ch == AUX_CH_A)
> - freq = dev_priv->cdclk.hw.cdclk;
> - else
> - freq = RUNTIME_INFO(dev_priv)->rawclk_freq;
> - return DIV_ROUND_CLOSEST(freq, 2000);
> -}
> -
> -static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
> -{
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> -
> - if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
> - /* Workaround for non-ULT HSW */
> - switch (index) {
> - case 0: return 63;
> - case 1: return 72;
> - default: return 0;
> - }
> - }
> -
> - return ilk_get_aux_clock_divider(intel_dp, index);
> -}
> -
> -static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
> -{
> - /*
> - * SKL doesn't need us to program the AUX clock divider (Hardware will
> - * derive the clock from CDCLK automatically). We still implement the
> - * get_aux_clock_divider vfunc to plug-in into the existing code.
> - */
> - return index ? 0 : 1;
> -}
> -
> -static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
> - int send_bytes,
> - u32 aux_clock_divider)
> -{
> - struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> - struct drm_i915_private *dev_priv =
> - to_i915(dig_port->base.base.dev);
> - u32 precharge, timeout;
> -
> - if (IS_GEN(dev_priv, 6))
> - precharge = 3;
> - else
> - precharge = 5;
> -
> - if (IS_BROADWELL(dev_priv))
> - timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
> - else
> - timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
> -
> - return DP_AUX_CH_CTL_SEND_BUSY |
> - DP_AUX_CH_CTL_DONE |
> - DP_AUX_CH_CTL_INTERRUPT |
> - DP_AUX_CH_CTL_TIME_OUT_ERROR |
> - timeout |
> - DP_AUX_CH_CTL_RECEIVE_ERROR |
> - (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
> - (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
> - (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
> -}
> -
> -static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
> - int send_bytes,
> - u32 unused)
> -{
> - struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> - struct drm_i915_private *i915 =
> - to_i915(dig_port->base.base.dev);
> - enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
> - u32 ret;
> -
> - ret = DP_AUX_CH_CTL_SEND_BUSY |
> - DP_AUX_CH_CTL_DONE |
> - DP_AUX_CH_CTL_INTERRUPT |
> - DP_AUX_CH_CTL_TIME_OUT_ERROR |
> - DP_AUX_CH_CTL_TIME_OUT_MAX |
> - DP_AUX_CH_CTL_RECEIVE_ERROR |
> - (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
> - DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
> - DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
> -
> - if (intel_phy_is_tc(i915, phy) &&
> - dig_port->tc_mode == TC_PORT_TBT_ALT)
> - ret |= DP_AUX_CH_CTL_TBT_IO;
> -
> - return ret;
> -}
> -
> -static int
> -intel_dp_aux_xfer(struct intel_dp *intel_dp,
> - const u8 *send, int send_bytes,
> - u8 *recv, int recv_size,
> - u32 aux_send_ctl_flags)
> -{
> - struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> - struct drm_i915_private *i915 =
> - to_i915(dig_port->base.base.dev);
> - struct intel_uncore *uncore = &i915->uncore;
> - enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
> - bool is_tc_port = intel_phy_is_tc(i915, phy);
> - i915_reg_t ch_ctl, ch_data[5];
> - u32 aux_clock_divider;
> - enum intel_display_power_domain aux_domain;
> - intel_wakeref_t aux_wakeref;
> - intel_wakeref_t pps_wakeref;
> - int i, ret, recv_bytes;
> - int try, clock = 0;
> - u32 status;
> - bool vdd;
> -
> - ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
> - for (i = 0; i < ARRAY_SIZE(ch_data); i++)
> - ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
> -
> - if (is_tc_port)
> - intel_tc_port_lock(dig_port);
> -
> - aux_domain = intel_aux_power_domain(dig_port);
> -
> - aux_wakeref = intel_display_power_get(i915, aux_domain);
> - pps_wakeref = intel_pps_lock(intel_dp);
> -
> - /*
> - * We will be called with VDD already enabled for dpcd/edid/oui reads.
> - * In such cases we want to leave VDD enabled and it's up to upper layers
> - * to turn it off. But for eg. i2c-dev access we need to turn it on/off
> - * ourselves.
> - */
> - vdd = intel_pps_vdd_on_unlocked(intel_dp);
> -
> - /* dp aux is extremely sensitive to irq latency, hence request the
> - * lowest possible wakeup latency and so prevent the cpu from going into
> - * deep sleep states.
> - */
> - cpu_latency_qos_update_request(&intel_dp->pm_qos, 0);
> -
> - intel_pps_check_power_unlocked(intel_dp);
> -
> - /* Try to wait for any previous AUX channel activity */
> - for (try = 0; try < 3; try++) {
> - status = intel_uncore_read_notrace(uncore, ch_ctl);
> - if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
> - break;
> - msleep(1);
> - }
> - /* just trace the final value */
> - trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
> -
> - if (try == 3) {
> - const u32 status = intel_uncore_read(uncore, ch_ctl);
> -
> - if (status != intel_dp->aux_busy_last_status) {
> - drm_WARN(&i915->drm, 1,
> - "%s: not started (status 0x%08x)\n",
> - intel_dp->aux.name, status);
> - intel_dp->aux_busy_last_status = status;
> - }
> -
> - ret = -EBUSY;
> - goto out;
> - }
> -
> - /* Only 5 data registers! */
> - if (drm_WARN_ON(&i915->drm, send_bytes > 20 || recv_size > 20)) {
> - ret = -E2BIG;
> - goto out;
> - }
> -
> - while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
> - u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
> - send_bytes,
> - aux_clock_divider);
> -
> - send_ctl |= aux_send_ctl_flags;
> -
> - /* Must try at least 3 times according to DP spec */
> - for (try = 0; try < 5; try++) {
> - /* Load the send data into the aux channel data registers */
> - for (i = 0; i < send_bytes; i += 4)
> - intel_uncore_write(uncore,
> - ch_data[i >> 2],
> - intel_dp_pack_aux(send + i,
> - send_bytes - i));
> -
> - /* Send the command and wait for it to complete */
> - intel_uncore_write(uncore, ch_ctl, send_ctl);
> -
> - status = intel_dp_aux_wait_done(intel_dp);
> -
> - /* Clear done status and any errors */
> - intel_uncore_write(uncore,
> - ch_ctl,
> - status |
> - DP_AUX_CH_CTL_DONE |
> - DP_AUX_CH_CTL_TIME_OUT_ERROR |
> - DP_AUX_CH_CTL_RECEIVE_ERROR);
> -
> - /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
> - * 400us delay required for errors and timeouts
> - * Timeout errors from the HW already meet this
> - * requirement so skip to next iteration
> - */
> - if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
> - continue;
> -
> - if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
> - usleep_range(400, 500);
> - continue;
> - }
> - if (status & DP_AUX_CH_CTL_DONE)
> - goto done;
> - }
> - }
> -
> - if ((status & DP_AUX_CH_CTL_DONE) == 0) {
> - drm_err(&i915->drm, "%s: not done (status 0x%08x)\n",
> - intel_dp->aux.name, status);
> - ret = -EBUSY;
> - goto out;
> - }
> -
> -done:
> - /* Check for timeout or receive error.
> - * Timeouts occur when the sink is not connected
> - */
> - if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
> - drm_err(&i915->drm, "%s: receive error (status 0x%08x)\n",
> - intel_dp->aux.name, status);
> - ret = -EIO;
> - goto out;
> - }
> -
> - /* Timeouts occur when the device isn't connected, so they're
> - * "normal" -- don't fill the kernel log with these */
> - if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
> - drm_dbg_kms(&i915->drm, "%s: timeout (status 0x%08x)\n",
> - intel_dp->aux.name, status);
> - ret = -ETIMEDOUT;
> - goto out;
> - }
> -
> - /* Unload any bytes sent back from the other side */
> - recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
> - DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
> -
> - /*
> - * By BSpec: "Message sizes of 0 or >20 are not allowed."
> - * We have no idea of what happened so we return -EBUSY so
> - * drm layer takes care for the necessary retries.
> - */
> - if (recv_bytes == 0 || recv_bytes > 20) {
> - drm_dbg_kms(&i915->drm,
> - "%s: Forbidden recv_bytes = %d on aux transaction\n",
> - intel_dp->aux.name, recv_bytes);
> - ret = -EBUSY;
> - goto out;
> - }
> -
> - if (recv_bytes > recv_size)
> - recv_bytes = recv_size;
> -
> - for (i = 0; i < recv_bytes; i += 4)
> - intel_dp_unpack_aux(intel_uncore_read(uncore, ch_data[i >> 2]),
> - recv + i, recv_bytes - i);
> -
> - ret = recv_bytes;
> -out:
> - cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
> -
> - if (vdd)
> - intel_pps_vdd_off_unlocked(intel_dp, false);
> -
> - intel_pps_unlock(intel_dp, pps_wakeref);
> - intel_display_power_put_async(i915, aux_domain, aux_wakeref);
> -
> - if (is_tc_port)
> - intel_tc_port_unlock(dig_port);
> -
> - return ret;
> -}
> -
> -#define BARE_ADDRESS_SIZE 3
> -#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
> -
> -static void
> -intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
> - const struct drm_dp_aux_msg *msg)
> -{
> - txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
> - txbuf[1] = (msg->address >> 8) & 0xff;
> - txbuf[2] = msg->address & 0xff;
> - txbuf[3] = msg->size - 1;
> -}
> -
> -static u32 intel_dp_aux_xfer_flags(const struct drm_dp_aux_msg *msg)
> -{
> - /*
> - * If we're trying to send the HDCP Aksv, we need to set a the Aksv
> - * select bit to inform the hardware to send the Aksv after our header
> - * since we can't access that data from software.
> - */
> - if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_WRITE &&
> - msg->address == DP_AUX_HDCP_AKSV)
> - return DP_AUX_CH_CTL_AUX_AKSV_SELECT;
> -
> - return 0;
> -}
> -
> -static ssize_t
> -intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
> -{
> - struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
> - struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> - u8 txbuf[20], rxbuf[20];
> - size_t txsize, rxsize;
> - u32 flags = intel_dp_aux_xfer_flags(msg);
> - int ret;
> -
> - intel_dp_aux_header(txbuf, msg);
> -
> - switch (msg->request & ~DP_AUX_I2C_MOT) {
> - case DP_AUX_NATIVE_WRITE:
> - case DP_AUX_I2C_WRITE:
> - case DP_AUX_I2C_WRITE_STATUS_UPDATE:
> - txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
> - rxsize = 2; /* 0 or 1 data bytes */
> -
> - if (drm_WARN_ON(&i915->drm, txsize > 20))
> - return -E2BIG;
> -
> - drm_WARN_ON(&i915->drm, !msg->buffer != !msg->size);
> -
> - if (msg->buffer)
> - memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
> -
> - ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
> - rxbuf, rxsize, flags);
> - if (ret > 0) {
> - msg->reply = rxbuf[0] >> 4;
> -
> - if (ret > 1) {
> - /* Number of bytes written in a short write. */
> - ret = clamp_t(int, rxbuf[1], 0, msg->size);
> - } else {
> - /* Return payload size. */
> - ret = msg->size;
> - }
> - }
> - break;
> -
> - case DP_AUX_NATIVE_READ:
> - case DP_AUX_I2C_READ:
> - txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
> - rxsize = msg->size + 1;
> -
> - if (drm_WARN_ON(&i915->drm, rxsize > 20))
> - return -E2BIG;
> -
> - ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
> - rxbuf, rxsize, flags);
> - if (ret > 0) {
> - msg->reply = rxbuf[0] >> 4;
> - /*
> - * Assume happy day, and copy the data. The caller is
> - * expected to check msg->reply before touching it.
> - *
> - * Return payload size.
> - */
> - ret--;
> - memcpy(msg->buffer, rxbuf + 1, ret);
> - }
> - break;
> -
> - default:
> - ret = -EINVAL;
> - break;
> - }
> -
> - return ret;
> -}
> -
> -
> -static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
> -{
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> - enum aux_ch aux_ch = dig_port->aux_ch;
> -
> - switch (aux_ch) {
> - case AUX_CH_B:
> - case AUX_CH_C:
> - case AUX_CH_D:
> - return DP_AUX_CH_CTL(aux_ch);
> - default:
> - MISSING_CASE(aux_ch);
> - return DP_AUX_CH_CTL(AUX_CH_B);
> - }
> -}
> -
> -static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
> -{
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> - enum aux_ch aux_ch = dig_port->aux_ch;
> -
> - switch (aux_ch) {
> - case AUX_CH_B:
> - case AUX_CH_C:
> - case AUX_CH_D:
> - return DP_AUX_CH_DATA(aux_ch, index);
> - default:
> - MISSING_CASE(aux_ch);
> - return DP_AUX_CH_DATA(AUX_CH_B, index);
> - }
> -}
> -
> -static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
> -{
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> - enum aux_ch aux_ch = dig_port->aux_ch;
> -
> - switch (aux_ch) {
> - case AUX_CH_A:
> - return DP_AUX_CH_CTL(aux_ch);
> - case AUX_CH_B:
> - case AUX_CH_C:
> - case AUX_CH_D:
> - return PCH_DP_AUX_CH_CTL(aux_ch);
> - default:
> - MISSING_CASE(aux_ch);
> - return DP_AUX_CH_CTL(AUX_CH_A);
> - }
> -}
> -
> -static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
> -{
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> - enum aux_ch aux_ch = dig_port->aux_ch;
> -
> - switch (aux_ch) {
> - case AUX_CH_A:
> - return DP_AUX_CH_DATA(aux_ch, index);
> - case AUX_CH_B:
> - case AUX_CH_C:
> - case AUX_CH_D:
> - return PCH_DP_AUX_CH_DATA(aux_ch, index);
> - default:
> - MISSING_CASE(aux_ch);
> - return DP_AUX_CH_DATA(AUX_CH_A, index);
> - }
> -}
> -
> -static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
> -{
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> - enum aux_ch aux_ch = dig_port->aux_ch;
> -
> - switch (aux_ch) {
> - case AUX_CH_A:
> - case AUX_CH_B:
> - case AUX_CH_C:
> - case AUX_CH_D:
> - case AUX_CH_E:
> - case AUX_CH_F:
> - return DP_AUX_CH_CTL(aux_ch);
> - default:
> - MISSING_CASE(aux_ch);
> - return DP_AUX_CH_CTL(AUX_CH_A);
> - }
> -}
> -
> -static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
> -{
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> - enum aux_ch aux_ch = dig_port->aux_ch;
> -
> - switch (aux_ch) {
> - case AUX_CH_A:
> - case AUX_CH_B:
> - case AUX_CH_C:
> - case AUX_CH_D:
> - case AUX_CH_E:
> - case AUX_CH_F:
> - return DP_AUX_CH_DATA(aux_ch, index);
> - default:
> - MISSING_CASE(aux_ch);
> - return DP_AUX_CH_DATA(AUX_CH_A, index);
> - }
> -}
> -
> -static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp)
> -{
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> - enum aux_ch aux_ch = dig_port->aux_ch;
> -
> - switch (aux_ch) {
> - case AUX_CH_A:
> - case AUX_CH_B:
> - case AUX_CH_C:
> - case AUX_CH_USBC1:
> - case AUX_CH_USBC2:
> - case AUX_CH_USBC3:
> - case AUX_CH_USBC4:
> - case AUX_CH_USBC5:
> - case AUX_CH_USBC6:
> - return DP_AUX_CH_CTL(aux_ch);
> - default:
> - MISSING_CASE(aux_ch);
> - return DP_AUX_CH_CTL(AUX_CH_A);
> - }
> -}
> -
> -static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index)
> -{
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> - enum aux_ch aux_ch = dig_port->aux_ch;
> -
> - switch (aux_ch) {
> - case AUX_CH_A:
> - case AUX_CH_B:
> - case AUX_CH_C:
> - case AUX_CH_USBC1:
> - case AUX_CH_USBC2:
> - case AUX_CH_USBC3:
> - case AUX_CH_USBC4:
> - case AUX_CH_USBC5:
> - case AUX_CH_USBC6:
> - return DP_AUX_CH_DATA(aux_ch, index);
> - default:
> - MISSING_CASE(aux_ch);
> - return DP_AUX_CH_DATA(AUX_CH_A, index);
> - }
> -}
> -
> -static void
> -intel_dp_aux_fini(struct intel_dp *intel_dp)
> -{
> - if (cpu_latency_qos_request_active(&intel_dp->pm_qos))
> - cpu_latency_qos_remove_request(&intel_dp->pm_qos);
> -
> - kfree(intel_dp->aux.name);
> -}
> -
> -static void
> -intel_dp_aux_init(struct intel_dp *intel_dp)
> -{
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> - struct intel_encoder *encoder = &dig_port->base;
> - enum aux_ch aux_ch = dig_port->aux_ch;
> -
> - if (INTEL_GEN(dev_priv) >= 12) {
> - intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg;
> - intel_dp->aux_ch_data_reg = tgl_aux_data_reg;
> - } else if (INTEL_GEN(dev_priv) >= 9) {
> - intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
> - intel_dp->aux_ch_data_reg = skl_aux_data_reg;
> - } else if (HAS_PCH_SPLIT(dev_priv)) {
> - intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
> - intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
> - } else {
> - intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
> - intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
> - }
> -
> - if (INTEL_GEN(dev_priv) >= 9)
> - intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
> - else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> - intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
> - else if (HAS_PCH_SPLIT(dev_priv))
> - intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
> - else
> - intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
> -
> - if (INTEL_GEN(dev_priv) >= 9)
> - intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
> - else
> - intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
> -
> - drm_dp_aux_init(&intel_dp->aux);
> -
> - /* Failure to allocate our preferred name is not critical */
> - if (INTEL_GEN(dev_priv) >= 12 && aux_ch >= AUX_CH_USBC1)
> - intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX USBC%c/%s",
> - aux_ch - AUX_CH_USBC1 + '1',
> - encoder->base.name);
> - else
> - intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/%s",
> - aux_ch_name(aux_ch),
> - encoder->base.name);
> -
> - intel_dp->aux.transfer = intel_dp_aux_transfer;
> - cpu_latency_qos_add_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
> -}
> -
> bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
> {
> int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 40e70531296c..d80839139bfb 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -75,7 +75,6 @@ void intel_dp_mst_resume(struct drm_i915_private *dev_priv);
> int intel_dp_max_link_rate(struct intel_dp *intel_dp);
> int intel_dp_max_lane_count(struct intel_dp *intel_dp);
> int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
> -u32 intel_dp_pack_aux(const u8 *src, int src_bytes);
>
> void intel_edp_drrs_enable(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> new file mode 100644
> index 000000000000..c7c82a6cd63c
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> @@ -0,0 +1,692 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2020 Intel Corporation
2021?!
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> + */
> +
> +#include "i915_drv.h"
> +#include "i915_trace.h"
> +#include "intel_display_types.h"
> +#include "intel_dp_aux.h"
> +#include "intel_pps.h"
> +#include "intel_tc.h"
> +
> +u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
> +{
> + int i;
> + u32 v = 0;
> +
> + if (src_bytes > 4)
> + src_bytes = 4;
> + for (i = 0; i < src_bytes; i++)
> + v |= ((u32)src[i]) << ((3 - i) * 8);
> + return v;
> +}
> +
> +static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes)
> +{
> + int i;
> +
> + if (dst_bytes > 4)
> + dst_bytes = 4;
> + for (i = 0; i < dst_bytes; i++)
> + dst[i] = src >> ((3 - i) * 8);
> +}
> +
> +static u32
> +intel_dp_aux_wait_done(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> + i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
> + const unsigned int timeout_ms = 10;
> + u32 status;
> + bool done;
> +
> +#define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
> + done = wait_event_timeout(i915->gmbus_wait_queue, C,
> + msecs_to_jiffies_timeout(timeout_ms));
> +
> + /* just trace the final value */
> + trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
> +
> + if (!done)
> + drm_err(&i915->drm,
> + "%s: did not complete or timeout within %ums (status 0x%08x)\n",
> + intel_dp->aux.name, timeout_ms, status);
> +#undef C
> +
> + return status;
> +}
> +
> +static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> + if (index)
> + return 0;
> +
> + /*
> + * The clock divider is based off the hrawclk, and would like to run at
> + * 2MHz. So, take the hrawclk value and divide by 2000 and use that
> + */
> + return DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq, 2000);
> +}
> +
> +static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + u32 freq;
> +
> + if (index)
> + return 0;
> +
> + /*
> + * The clock divider is based off the cdclk or PCH rawclk, and would
> + * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
> + * divide by 2000 and use that
> + */
> + if (dig_port->aux_ch == AUX_CH_A)
> + freq = dev_priv->cdclk.hw.cdclk;
> + else
> + freq = RUNTIME_INFO(dev_priv)->rawclk_freq;
> + return DIV_ROUND_CLOSEST(freq, 2000);
> +}
> +
> +static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> +
> + if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
> + /* Workaround for non-ULT HSW */
> + switch (index) {
> + case 0: return 63;
> + case 1: return 72;
> + default: return 0;
> + }
> + }
> +
> + return ilk_get_aux_clock_divider(intel_dp, index);
> +}
> +
> +static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
> +{
> + /*
> + * SKL doesn't need us to program the AUX clock divider (Hardware will
> + * derive the clock from CDCLK automatically). We still implement the
> + * get_aux_clock_divider vfunc to plug-in into the existing code.
> + */
> + return index ? 0 : 1;
> +}
> +
> +static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
> + int send_bytes,
> + u32 aux_clock_divider)
> +{
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + struct drm_i915_private *dev_priv =
> + to_i915(dig_port->base.base.dev);
> + u32 precharge, timeout;
> +
> + if (IS_GEN(dev_priv, 6))
> + precharge = 3;
> + else
> + precharge = 5;
> +
> + if (IS_BROADWELL(dev_priv))
> + timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
> + else
> + timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
> +
> + return DP_AUX_CH_CTL_SEND_BUSY |
> + DP_AUX_CH_CTL_DONE |
> + DP_AUX_CH_CTL_INTERRUPT |
> + DP_AUX_CH_CTL_TIME_OUT_ERROR |
> + timeout |
> + DP_AUX_CH_CTL_RECEIVE_ERROR |
> + (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
> + (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
> + (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
> +}
> +
> +static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
> + int send_bytes,
> + u32 unused)
> +{
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + struct drm_i915_private *i915 =
> + to_i915(dig_port->base.base.dev);
> + enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
> + u32 ret;
> +
> + ret = DP_AUX_CH_CTL_SEND_BUSY |
> + DP_AUX_CH_CTL_DONE |
> + DP_AUX_CH_CTL_INTERRUPT |
> + DP_AUX_CH_CTL_TIME_OUT_ERROR |
> + DP_AUX_CH_CTL_TIME_OUT_MAX |
> + DP_AUX_CH_CTL_RECEIVE_ERROR |
> + (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
> + DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
> + DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
> +
> + if (intel_phy_is_tc(i915, phy) &&
> + dig_port->tc_mode == TC_PORT_TBT_ALT)
> + ret |= DP_AUX_CH_CTL_TBT_IO;
> +
> + return ret;
> +}
> +
> +static int
> +intel_dp_aux_xfer(struct intel_dp *intel_dp,
> + const u8 *send, int send_bytes,
> + u8 *recv, int recv_size,
> + u32 aux_send_ctl_flags)
> +{
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + struct drm_i915_private *i915 =
> + to_i915(dig_port->base.base.dev);
> + struct intel_uncore *uncore = &i915->uncore;
> + enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
> + bool is_tc_port = intel_phy_is_tc(i915, phy);
> + i915_reg_t ch_ctl, ch_data[5];
> + u32 aux_clock_divider;
> + enum intel_display_power_domain aux_domain;
> + intel_wakeref_t aux_wakeref;
> + intel_wakeref_t pps_wakeref;
> + int i, ret, recv_bytes;
> + int try, clock = 0;
> + u32 status;
> + bool vdd;
> +
> + ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
> + for (i = 0; i < ARRAY_SIZE(ch_data); i++)
> + ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
> +
> + if (is_tc_port)
> + intel_tc_port_lock(dig_port);
> +
> + aux_domain = intel_aux_power_domain(dig_port);
> +
> + aux_wakeref = intel_display_power_get(i915, aux_domain);
> + pps_wakeref = intel_pps_lock(intel_dp);
> +
> + /*
> + * We will be called with VDD already enabled for dpcd/edid/oui reads.
> + * In such cases we want to leave VDD enabled and it's up to upper layers
> + * to turn it off. But for eg. i2c-dev access we need to turn it on/off
> + * ourselves.
> + */
> + vdd = intel_pps_vdd_on_unlocked(intel_dp);
> +
> + /*
> + * dp aux is extremely sensitive to irq latency, hence request the
> + * lowest possible wakeup latency and so prevent the cpu from going into
> + * deep sleep states.
> + */
> + cpu_latency_qos_update_request(&intel_dp->pm_qos, 0);
> +
> + intel_pps_check_power_unlocked(intel_dp);
> +
> + /* Try to wait for any previous AUX channel activity */
> + for (try = 0; try < 3; try++) {
> + status = intel_uncore_read_notrace(uncore, ch_ctl);
> + if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
> + break;
> + msleep(1);
> + }
> + /* just trace the final value */
> + trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
> +
> + if (try == 3) {
> + const u32 status = intel_uncore_read(uncore, ch_ctl);
> +
> + if (status != intel_dp->aux_busy_last_status) {
> + drm_WARN(&i915->drm, 1,
> + "%s: not started (status 0x%08x)\n",
> + intel_dp->aux.name, status);
> + intel_dp->aux_busy_last_status = status;
> + }
> +
> + ret = -EBUSY;
> + goto out;
> + }
> +
> + /* Only 5 data registers! */
> + if (drm_WARN_ON(&i915->drm, send_bytes > 20 || recv_size > 20)) {
> + ret = -E2BIG;
> + goto out;
> + }
> +
> + while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
> + u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
> + send_bytes,
> + aux_clock_divider);
> +
> + send_ctl |= aux_send_ctl_flags;
> +
> + /* Must try at least 3 times according to DP spec */
> + for (try = 0; try < 5; try++) {
> + /* Load the send data into the aux channel data registers */
> + for (i = 0; i < send_bytes; i += 4)
> + intel_uncore_write(uncore,
> + ch_data[i >> 2],
> + intel_dp_pack_aux(send + i,
> + send_bytes - i));
> +
> + /* Send the command and wait for it to complete */
> + intel_uncore_write(uncore, ch_ctl, send_ctl);
> +
> + status = intel_dp_aux_wait_done(intel_dp);
> +
> + /* Clear done status and any errors */
> + intel_uncore_write(uncore,
> + ch_ctl,
> + status |
> + DP_AUX_CH_CTL_DONE |
> + DP_AUX_CH_CTL_TIME_OUT_ERROR |
> + DP_AUX_CH_CTL_RECEIVE_ERROR);
> +
> + /*
> + * DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
> + * 400us delay required for errors and timeouts
> + * Timeout errors from the HW already meet this
> + * requirement so skip to next iteration
> + */
> + if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
> + continue;
> +
> + if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
> + usleep_range(400, 500);
> + continue;
> + }
> + if (status & DP_AUX_CH_CTL_DONE)
> + goto done;
> + }
> + }
> +
> + if ((status & DP_AUX_CH_CTL_DONE) == 0) {
> + drm_err(&i915->drm, "%s: not done (status 0x%08x)\n",
> + intel_dp->aux.name, status);
> + ret = -EBUSY;
> + goto out;
> + }
> +
> +done:
> + /*
> + * Check for timeout or receive error. Timeouts occur when the sink is
> + * not connected.
> + */
> + if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
> + drm_err(&i915->drm, "%s: receive error (status 0x%08x)\n",
> + intel_dp->aux.name, status);
> + ret = -EIO;
> + goto out;
> + }
> +
> + /*
> + * Timeouts occur when the device isn't connected, so they're "normal"
> + * -- don't fill the kernel log with these
> + */
> + if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
> + drm_dbg_kms(&i915->drm, "%s: timeout (status 0x%08x)\n",
> + intel_dp->aux.name, status);
> + ret = -ETIMEDOUT;
> + goto out;
> + }
> +
> + /* Unload any bytes sent back from the other side */
> + recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
> + DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
> +
> + /*
> + * By BSpec: "Message sizes of 0 or >20 are not allowed."
> + * We have no idea of what happened so we return -EBUSY so
> + * drm layer takes care for the necessary retries.
> + */
> + if (recv_bytes == 0 || recv_bytes > 20) {
> + drm_dbg_kms(&i915->drm,
> + "%s: Forbidden recv_bytes = %d on aux transaction\n",
> + intel_dp->aux.name, recv_bytes);
> + ret = -EBUSY;
> + goto out;
> + }
> +
> + if (recv_bytes > recv_size)
> + recv_bytes = recv_size;
> +
> + for (i = 0; i < recv_bytes; i += 4)
> + intel_dp_unpack_aux(intel_uncore_read(uncore, ch_data[i >> 2]),
> + recv + i, recv_bytes - i);
> +
> + ret = recv_bytes;
> +out:
> + cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
> +
> + if (vdd)
> + intel_pps_vdd_off_unlocked(intel_dp, false);
> +
> + intel_pps_unlock(intel_dp, pps_wakeref);
> + intel_display_power_put_async(i915, aux_domain, aux_wakeref);
> +
> + if (is_tc_port)
> + intel_tc_port_unlock(dig_port);
> +
> + return ret;
> +}
> +
> +#define BARE_ADDRESS_SIZE 3
> +#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
> +
> +static void
> +intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
> + const struct drm_dp_aux_msg *msg)
> +{
> + txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
> + txbuf[1] = (msg->address >> 8) & 0xff;
> + txbuf[2] = msg->address & 0xff;
> + txbuf[3] = msg->size - 1;
> +}
> +
> +static u32 intel_dp_aux_xfer_flags(const struct drm_dp_aux_msg *msg)
> +{
> + /*
> + * If we're trying to send the HDCP Aksv, we need to set a the Aksv
> + * select bit to inform the hardware to send the Aksv after our header
> + * since we can't access that data from software.
> + */
> + if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_WRITE &&
> + msg->address == DP_AUX_HDCP_AKSV)
> + return DP_AUX_CH_CTL_AUX_AKSV_SELECT;
> +
> + return 0;
> +}
> +
> +static ssize_t
> +intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
> +{
> + struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
> + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> + u8 txbuf[20], rxbuf[20];
> + size_t txsize, rxsize;
> + u32 flags = intel_dp_aux_xfer_flags(msg);
> + int ret;
> +
> + intel_dp_aux_header(txbuf, msg);
> +
> + switch (msg->request & ~DP_AUX_I2C_MOT) {
> + case DP_AUX_NATIVE_WRITE:
> + case DP_AUX_I2C_WRITE:
> + case DP_AUX_I2C_WRITE_STATUS_UPDATE:
> + txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
> + rxsize = 2; /* 0 or 1 data bytes */
> +
> + if (drm_WARN_ON(&i915->drm, txsize > 20))
> + return -E2BIG;
> +
> + drm_WARN_ON(&i915->drm, !msg->buffer != !msg->size);
> +
> + if (msg->buffer)
> + memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
> +
> + ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
> + rxbuf, rxsize, flags);
> + if (ret > 0) {
> + msg->reply = rxbuf[0] >> 4;
> +
> + if (ret > 1) {
> + /* Number of bytes written in a short write. */
> + ret = clamp_t(int, rxbuf[1], 0, msg->size);
> + } else {
> + /* Return payload size. */
> + ret = msg->size;
> + }
> + }
> + break;
> +
> + case DP_AUX_NATIVE_READ:
> + case DP_AUX_I2C_READ:
> + txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
> + rxsize = msg->size + 1;
> +
> + if (drm_WARN_ON(&i915->drm, rxsize > 20))
> + return -E2BIG;
> +
> + ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
> + rxbuf, rxsize, flags);
> + if (ret > 0) {
> + msg->reply = rxbuf[0] >> 4;
> + /*
> + * Assume happy day, and copy the data. The caller is
> + * expected to check msg->reply before touching it.
> + *
> + * Return payload size.
> + */
> + ret--;
> + memcpy(msg->buffer, rxbuf + 1, ret);
> + }
> + break;
> +
> + default:
> + ret = -EINVAL;
> + break;
> + }
> +
> + return ret;
> +}
> +
> +static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + enum aux_ch aux_ch = dig_port->aux_ch;
> +
> + switch (aux_ch) {
> + case AUX_CH_B:
> + case AUX_CH_C:
> + case AUX_CH_D:
> + return DP_AUX_CH_CTL(aux_ch);
> + default:
> + MISSING_CASE(aux_ch);
> + return DP_AUX_CH_CTL(AUX_CH_B);
> + }
> +}
> +
> +static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + enum aux_ch aux_ch = dig_port->aux_ch;
> +
> + switch (aux_ch) {
> + case AUX_CH_B:
> + case AUX_CH_C:
> + case AUX_CH_D:
> + return DP_AUX_CH_DATA(aux_ch, index);
> + default:
> + MISSING_CASE(aux_ch);
> + return DP_AUX_CH_DATA(AUX_CH_B, index);
> + }
> +}
> +
> +static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + enum aux_ch aux_ch = dig_port->aux_ch;
> +
> + switch (aux_ch) {
> + case AUX_CH_A:
> + return DP_AUX_CH_CTL(aux_ch);
> + case AUX_CH_B:
> + case AUX_CH_C:
> + case AUX_CH_D:
> + return PCH_DP_AUX_CH_CTL(aux_ch);
> + default:
> + MISSING_CASE(aux_ch);
> + return DP_AUX_CH_CTL(AUX_CH_A);
> + }
> +}
> +
> +static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + enum aux_ch aux_ch = dig_port->aux_ch;
> +
> + switch (aux_ch) {
> + case AUX_CH_A:
> + return DP_AUX_CH_DATA(aux_ch, index);
> + case AUX_CH_B:
> + case AUX_CH_C:
> + case AUX_CH_D:
> + return PCH_DP_AUX_CH_DATA(aux_ch, index);
> + default:
> + MISSING_CASE(aux_ch);
> + return DP_AUX_CH_DATA(AUX_CH_A, index);
> + }
> +}
> +
> +static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + enum aux_ch aux_ch = dig_port->aux_ch;
> +
> + switch (aux_ch) {
> + case AUX_CH_A:
> + case AUX_CH_B:
> + case AUX_CH_C:
> + case AUX_CH_D:
> + case AUX_CH_E:
> + case AUX_CH_F:
> + return DP_AUX_CH_CTL(aux_ch);
> + default:
> + MISSING_CASE(aux_ch);
> + return DP_AUX_CH_CTL(AUX_CH_A);
> + }
> +}
> +
> +static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + enum aux_ch aux_ch = dig_port->aux_ch;
> +
> + switch (aux_ch) {
> + case AUX_CH_A:
> + case AUX_CH_B:
> + case AUX_CH_C:
> + case AUX_CH_D:
> + case AUX_CH_E:
> + case AUX_CH_F:
> + return DP_AUX_CH_DATA(aux_ch, index);
> + default:
> + MISSING_CASE(aux_ch);
> + return DP_AUX_CH_DATA(AUX_CH_A, index);
> + }
> +}
> +
> +static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + enum aux_ch aux_ch = dig_port->aux_ch;
> +
> + switch (aux_ch) {
> + case AUX_CH_A:
> + case AUX_CH_B:
> + case AUX_CH_C:
> + case AUX_CH_USBC1:
> + case AUX_CH_USBC2:
> + case AUX_CH_USBC3:
> + case AUX_CH_USBC4:
> + case AUX_CH_USBC5:
> + case AUX_CH_USBC6:
> + return DP_AUX_CH_CTL(aux_ch);
> + default:
> + MISSING_CASE(aux_ch);
> + return DP_AUX_CH_CTL(AUX_CH_A);
> + }
> +}
> +
> +static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + enum aux_ch aux_ch = dig_port->aux_ch;
> +
> + switch (aux_ch) {
> + case AUX_CH_A:
> + case AUX_CH_B:
> + case AUX_CH_C:
> + case AUX_CH_USBC1:
> + case AUX_CH_USBC2:
> + case AUX_CH_USBC3:
> + case AUX_CH_USBC4:
> + case AUX_CH_USBC5:
> + case AUX_CH_USBC6:
> + return DP_AUX_CH_DATA(aux_ch, index);
> + default:
> + MISSING_CASE(aux_ch);
> + return DP_AUX_CH_DATA(AUX_CH_A, index);
> + }
> +}
> +
> +void intel_dp_aux_fini(struct intel_dp *intel_dp)
> +{
> + if (cpu_latency_qos_request_active(&intel_dp->pm_qos))
> + cpu_latency_qos_remove_request(&intel_dp->pm_qos);
> +
> + kfree(intel_dp->aux.name);
> +}
> +
> +void intel_dp_aux_init(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + struct intel_encoder *encoder = &dig_port->base;
> + enum aux_ch aux_ch = dig_port->aux_ch;
> +
> + if (INTEL_GEN(dev_priv) >= 12) {
> + intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg;
> + intel_dp->aux_ch_data_reg = tgl_aux_data_reg;
> + } else if (INTEL_GEN(dev_priv) >= 9) {
> + intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
> + intel_dp->aux_ch_data_reg = skl_aux_data_reg;
> + } else if (HAS_PCH_SPLIT(dev_priv)) {
> + intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
> + intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
> + } else {
> + intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
> + intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
> + }
> +
> + if (INTEL_GEN(dev_priv) >= 9)
> + intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
> + else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> + intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
> + else if (HAS_PCH_SPLIT(dev_priv))
> + intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
> + else
> + intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
> +
> + if (INTEL_GEN(dev_priv) >= 9)
> + intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
> + else
> + intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
> +
> + drm_dp_aux_init(&intel_dp->aux);
> +
> + /* Failure to allocate our preferred name is not critical */
> + if (INTEL_GEN(dev_priv) >= 12 && aux_ch >= AUX_CH_USBC1)
> + intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX USBC%c/%s",
> + aux_ch - AUX_CH_USBC1 + '1',
> + encoder->base.name);
> + else
> + intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/%s",
> + aux_ch_name(aux_ch),
> + encoder->base.name);
> +
> + intel_dp->aux.transfer = intel_dp_aux_transfer;
> + cpu_latency_qos_add_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.h b/drivers/gpu/drm/i915/display/intel_dp_aux.h
> new file mode 100644
> index 000000000000..cea58dd86c49
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.h
> @@ -0,0 +1,18 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2020 Intel Corporation
> + */
> +
> +#ifndef __INTEL_DP_AUX_H__
> +#define __INTEL_DP_AUX_H__
> +
> +#include <linux/types.h>
> +
> +struct intel_dp;
> +
> +u32 intel_dp_pack_aux(const u8 *src, int src_bytes);
> +
> +void intel_dp_aux_fini(struct intel_dp *intel_dp);
> +void intel_dp_aux_init(struct intel_dp *intel_dp);
> +
> +#endif /* __INTEL_DP_AUX_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 1e6c1fa59d4a..72d4c61e142e 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -28,9 +28,10 @@
> #include "i915_drv.h"
> #include "intel_atomic.h"
> #include "intel_display_types.h"
> +#include "intel_dp_aux.h"
> +#include "intel_hdmi.h"
> #include "intel_psr.h"
> #include "intel_sprite.h"
> -#include "intel_hdmi.h"
>
> /**
> * DOC: Panel Self Refresh (PSR/SRD)
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH 3/4] drm/i915/dp: abstract struct intel_dp pps members to a sub-struct
2021-01-20 17:30 ` Rodrigo Vivi
@ 2021-01-20 19:25 ` Jani Nikula
2021-01-20 20:08 ` Rodrigo Vivi
0 siblings, 1 reply; 13+ messages in thread
From: Jani Nikula @ 2021-01-20 19:25 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
On Wed, 20 Jan 2021, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> On Wed, Jan 20, 2021 at 12:18:33PM +0200, Jani Nikula wrote:
>> Add some namespacing to highlight what belongs where. No functional
>> changes.
>>
>> Cc: Anshuman Gupta <anshuman.gupta@intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> .../drm/i915/display/intel_display_debugfs.c | 8 +-
>> .../drm/i915/display/intel_display_types.h | 61 +++---
>> drivers/gpu/drm/i915/display/intel_dp.c | 14 +-
>> drivers/gpu/drm/i915/display/intel_pps.c | 192 +++++++++---------
>> 4 files changed, 140 insertions(+), 135 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> index cd7e5519ee7d..885d2d3c91a3 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> @@ -2155,13 +2155,13 @@ static int i915_panel_show(struct seq_file *m, void *data)
>> return -ENODEV;
>>
>> seq_printf(m, "Panel power up delay: %d\n",
>> - intel_dp->panel_power_up_delay);
>> + intel_dp->pps.panel_power_up_delay);
>> seq_printf(m, "Panel power down delay: %d\n",
>> - intel_dp->panel_power_down_delay);
>> + intel_dp->pps.panel_power_down_delay);
>> seq_printf(m, "Backlight on delay: %d\n",
>> - intel_dp->backlight_on_delay);
>> + intel_dp->pps.backlight_on_delay);
>> seq_printf(m, "Backlight off delay: %d\n",
>> - intel_dp->backlight_off_delay);
>> + intel_dp->pps.backlight_off_delay);
>>
>> return 0;
>> }
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index b601e804f854..1a9243426a25 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -1369,6 +1369,38 @@ struct intel_dp_pcon_frl {
>> int trained_rate_gbps;
>> };
>>
>> +struct intel_pps {
>
> PPS for Panel Power Something (Sequence? Struct?)
Panel Power Sequencer.
>
>> + int panel_power_up_delay;
>
> if we have panel power already could we remove panel_power_ from
> here to simply use pps.up_delay ?
IIRC that's the name used in the specs.
Also didn't want to rename any of the fields in this patch because it's
much easier to review. Can be renamed afterwards.
BR,
Jani.
>
>> + int panel_power_down_delay;
>> + int panel_power_cycle_delay;
>> + int backlight_on_delay;
>> + int backlight_off_delay;
>> + struct delayed_work panel_vdd_work;
>> + bool want_panel_vdd;
>> + unsigned long last_power_on;
>> + unsigned long last_backlight_off;
>> + ktime_t panel_power_off_time;
>> + intel_wakeref_t vdd_wakeref;
>> +
>> + /*
>> + * Pipe whose power sequencer is currently locked into
>> + * this port. Only relevant on VLV/CHV.
>> + */
>> + enum pipe pps_pipe;
>
> and pps.pipe
>
>> + /*
>> + * Pipe currently driving the port. Used for preventing
>> + * the use of the PPS for any pipe currentrly driving
>> + * external DP as that will mess things up on VLV.
>> + */
>> + enum pipe active_pipe;
>> + /*
>> + * Set if the sequencer may be reset due to a power transition,
>> + * requiring a reinitialization. Only relevant on BXT.
>> + */
>> + bool pps_reset;
>
> and pps.reset ?
>
>> + struct edp_power_seq pps_delays;
>> +};
>> +
>> struct intel_dp {
>> i915_reg_t output_reg;
>> u32 DP;
>> @@ -1408,35 +1440,8 @@ struct intel_dp {
>> struct drm_dp_aux aux;
>> u32 aux_busy_last_status;
>> u8 train_set[4];
>> - int panel_power_up_delay;
>> - int panel_power_down_delay;
>> - int panel_power_cycle_delay;
>> - int backlight_on_delay;
>> - int backlight_off_delay;
>> - struct delayed_work panel_vdd_work;
>> - bool want_panel_vdd;
>> - unsigned long last_power_on;
>> - unsigned long last_backlight_off;
>> - ktime_t panel_power_off_time;
>> - intel_wakeref_t vdd_wakeref;
>>
>> - /*
>> - * Pipe whose power sequencer is currently locked into
>> - * this port. Only relevant on VLV/CHV.
>> - */
>> - enum pipe pps_pipe;
>> - /*
>> - * Pipe currently driving the port. Used for preventing
>> - * the use of the PPS for any pipe currentrly driving
>> - * external DP as that will mess things up on VLV.
>> - */
>> - enum pipe active_pipe;
>> - /*
>> - * Set if the sequencer may be reset due to a power transition,
>> - * requiring a reinitialization. Only relevant on BXT.
>> - */
>> - bool pps_reset;
>> - struct edp_power_seq pps_delays;
>> + struct intel_pps pps;
>>
>> bool can_mst; /* this port supports mst */
>> bool is_mst;
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 8b9c20555f0e..d815087a26aa 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -4129,7 +4129,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
>> intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
>> }
>>
>> - msleep(intel_dp->panel_power_down_delay);
>> + msleep(intel_dp->pps.panel_power_down_delay);
>>
>> intel_dp->DP = DP;
>>
>> @@ -4137,7 +4137,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
>> intel_wakeref_t wakeref;
>>
>> with_intel_pps_lock(intel_dp, wakeref)
>> - intel_dp->active_pipe = INVALID_PIPE;
>> + intel_dp->pps.active_pipe = INVALID_PIPE;
>> }
>> }
>>
>> @@ -6368,7 +6368,7 @@ void intel_dp_encoder_reset(struct drm_encoder *encoder)
>> intel_wakeref_t wakeref;
>>
>> with_intel_pps_lock(intel_dp, wakeref)
>> - intel_dp->active_pipe = vlv_active_pipe(intel_dp);
>> + intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
>> }
>>
>> intel_pps_encoder_reset(intel_dp);
>> @@ -7139,7 +7139,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
>> pipe = vlv_active_pipe(intel_dp);
>>
>> if (pipe != PIPE_A && pipe != PIPE_B)
>> - pipe = intel_dp->pps_pipe;
>> + pipe = intel_dp->pps.pps_pipe;
>>
>> if (pipe != PIPE_A && pipe != PIPE_B)
>> pipe = PIPE_A;
>> @@ -7216,8 +7216,8 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
>> intel_dp_set_source_rates(intel_dp);
>>
>> intel_dp->reset_link_params = true;
>> - intel_dp->pps_pipe = INVALID_PIPE;
>> - intel_dp->active_pipe = INVALID_PIPE;
>> + intel_dp->pps.pps_pipe = INVALID_PIPE;
>> + intel_dp->pps.active_pipe = INVALID_PIPE;
>>
>> /* Preserve the current hw state. */
>> intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
>> @@ -7235,7 +7235,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
>> }
>>
>> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>> - intel_dp->active_pipe = vlv_active_pipe(intel_dp);
>> + intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
>>
>> /*
>> * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
>> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
>> index 69d9d41b6d22..c4867a8020a5 100644
>> --- a/drivers/gpu/drm/i915/display/intel_pps.c
>> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
>> @@ -44,7 +44,7 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp)
>> {
>> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>> - enum pipe pipe = intel_dp->pps_pipe;
>> + enum pipe pipe = intel_dp->pps.pps_pipe;
>> bool pll_enabled, release_cl_override = false;
>> enum dpio_phy phy = DPIO_PHY(pipe);
>> enum dpio_channel ch = vlv_pipe_to_channel(pipe);
>> @@ -130,18 +130,18 @@ static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
>>
>> if (encoder->type == INTEL_OUTPUT_EDP) {
>> drm_WARN_ON(&dev_priv->drm,
>> - intel_dp->active_pipe != INVALID_PIPE &&
>> - intel_dp->active_pipe !=
>> - intel_dp->pps_pipe);
>> + intel_dp->pps.active_pipe != INVALID_PIPE &&
>> + intel_dp->pps.active_pipe !=
>> + intel_dp->pps.pps_pipe);
>>
>> - if (intel_dp->pps_pipe != INVALID_PIPE)
>> - pipes &= ~(1 << intel_dp->pps_pipe);
>> + if (intel_dp->pps.pps_pipe != INVALID_PIPE)
>> + pipes &= ~(1 << intel_dp->pps.pps_pipe);
>> } else {
>> drm_WARN_ON(&dev_priv->drm,
>> - intel_dp->pps_pipe != INVALID_PIPE);
>> + intel_dp->pps.pps_pipe != INVALID_PIPE);
>>
>> - if (intel_dp->active_pipe != INVALID_PIPE)
>> - pipes &= ~(1 << intel_dp->active_pipe);
>> + if (intel_dp->pps.active_pipe != INVALID_PIPE)
>> + pipes &= ~(1 << intel_dp->pps.active_pipe);
>> }
>> }
>>
>> @@ -163,11 +163,11 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
>> /* We should never land here with regular DP ports */
>> drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
>>
>> - drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE &&
>> - intel_dp->active_pipe != intel_dp->pps_pipe);
>> + drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE &&
>> + intel_dp->pps.active_pipe != intel_dp->pps.pps_pipe);
>>
>> - if (intel_dp->pps_pipe != INVALID_PIPE)
>> - return intel_dp->pps_pipe;
>> + if (intel_dp->pps.pps_pipe != INVALID_PIPE)
>> + return intel_dp->pps.pps_pipe;
>>
>> pipe = vlv_find_free_pps(dev_priv);
>>
>> @@ -179,11 +179,11 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
>> pipe = PIPE_A;
>>
>> vlv_steal_power_sequencer(dev_priv, pipe);
>> - intel_dp->pps_pipe = pipe;
>> + intel_dp->pps.pps_pipe = pipe;
>>
>> drm_dbg_kms(&dev_priv->drm,
>> "picked pipe %c power sequencer for [ENCODER:%d:%s]\n",
>> - pipe_name(intel_dp->pps_pipe),
>> + pipe_name(intel_dp->pps.pps_pipe),
>> dig_port->base.base.base.id,
>> dig_port->base.base.name);
>>
>> @@ -197,7 +197,7 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
>> */
>> vlv_power_sequencer_kick(intel_dp);
>>
>> - return intel_dp->pps_pipe;
>> + return intel_dp->pps.pps_pipe;
>> }
>>
>> static int
>> @@ -211,10 +211,10 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp)
>> /* We should never land here with regular DP ports */
>> drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
>>
>> - if (!intel_dp->pps_reset)
>> + if (!intel_dp->pps.pps_reset)
>> return backlight_controller;
>>
>> - intel_dp->pps_reset = false;
>> + intel_dp->pps.pps_reset = false;
>>
>> /*
>> * Only the HW needs to be reprogrammed, the SW state is fixed and
>> @@ -280,19 +280,19 @@ vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
>>
>> /* try to find a pipe with this port selected */
>> /* first pick one where the panel is on */
>> - intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
>> - vlv_pipe_has_pp_on);
>> + intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
>> + vlv_pipe_has_pp_on);
>> /* didn't find one? pick one where vdd is on */
>> - if (intel_dp->pps_pipe == INVALID_PIPE)
>> - intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
>> - vlv_pipe_has_vdd_on);
>> + if (intel_dp->pps.pps_pipe == INVALID_PIPE)
>> + intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
>> + vlv_pipe_has_vdd_on);
>> /* didn't find one? pick one with just the correct port */
>> - if (intel_dp->pps_pipe == INVALID_PIPE)
>> - intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
>> - vlv_pipe_any);
>> + if (intel_dp->pps.pps_pipe == INVALID_PIPE)
>> + intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
>> + vlv_pipe_any);
>>
>> /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
>> - if (intel_dp->pps_pipe == INVALID_PIPE) {
>> + if (intel_dp->pps.pps_pipe == INVALID_PIPE) {
>> drm_dbg_kms(&dev_priv->drm,
>> "no initial power sequencer for [ENCODER:%d:%s]\n",
>> dig_port->base.base.base.id,
>> @@ -304,7 +304,7 @@ vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
>> "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n",
>> dig_port->base.base.base.id,
>> dig_port->base.base.name,
>> - pipe_name(intel_dp->pps_pipe));
>> + pipe_name(intel_dp->pps.pps_pipe));
>> }
>>
>> void intel_pps_reset_all(struct drm_i915_private *dev_priv)
>> @@ -331,15 +331,15 @@ void intel_pps_reset_all(struct drm_i915_private *dev_priv)
>> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>>
>> drm_WARN_ON(&dev_priv->drm,
>> - intel_dp->active_pipe != INVALID_PIPE);
>> + intel_dp->pps.active_pipe != INVALID_PIPE);
>>
>> if (encoder->type != INTEL_OUTPUT_EDP)
>> continue;
>>
>> if (IS_GEN9_LP(dev_priv))
>> - intel_dp->pps_reset = true;
>> + intel_dp->pps.pps_reset = true;
>> else
>> - intel_dp->pps_pipe = INVALID_PIPE;
>> + intel_dp->pps.pps_pipe = INVALID_PIPE;
>> }
>> }
>>
>> @@ -403,7 +403,7 @@ static bool edp_have_panel_power(struct intel_dp *intel_dp)
>> lockdep_assert_held(&dev_priv->pps_mutex);
>>
>> if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
>> - intel_dp->pps_pipe == INVALID_PIPE)
>> + intel_dp->pps.pps_pipe == INVALID_PIPE)
>> return false;
>>
>> return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON) != 0;
>> @@ -416,7 +416,7 @@ static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
>> lockdep_assert_held(&dev_priv->pps_mutex);
>>
>> if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
>> - intel_dp->pps_pipe == INVALID_PIPE)
>> + intel_dp->pps.pps_pipe == INVALID_PIPE)
>> return false;
>>
>> return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
>> @@ -506,13 +506,13 @@ static void wait_panel_power_cycle(struct intel_dp *intel_dp)
>> /* take the difference of currrent time and panel power off time
>> * and then make panel wait for t11_t12 if needed. */
>> panel_power_on_time = ktime_get_boottime();
>> - panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
>> + panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->pps.panel_power_off_time);
>>
>> /* When we disable the VDD override bit last we have to do the manual
>> * wait. */
>> - if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
>> + if (panel_power_off_duration < (s64)intel_dp->pps.panel_power_cycle_delay)
>> wait_remaining_ms_from_jiffies(jiffies,
>> - intel_dp->panel_power_cycle_delay - panel_power_off_duration);
>> + intel_dp->pps.panel_power_cycle_delay - panel_power_off_duration);
>>
>> wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
>> }
>> @@ -530,14 +530,14 @@ void intel_pps_wait_power_cycle(struct intel_dp *intel_dp)
>>
>> static void wait_backlight_on(struct intel_dp *intel_dp)
>> {
>> - wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
>> - intel_dp->backlight_on_delay);
>> + wait_remaining_ms_from_jiffies(intel_dp->pps.last_power_on,
>> + intel_dp->pps.backlight_on_delay);
>> }
>>
>> static void edp_wait_backlight_off(struct intel_dp *intel_dp)
>> {
>> - wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
>> - intel_dp->backlight_off_delay);
>> + wait_remaining_ms_from_jiffies(intel_dp->pps.last_backlight_off,
>> + intel_dp->pps.backlight_off_delay);
>> }
>>
>> /* Read the current pp_control value, unlocking the register if it
>> @@ -571,22 +571,22 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp)
>> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>> u32 pp;
>> i915_reg_t pp_stat_reg, pp_ctrl_reg;
>> - bool need_to_disable = !intel_dp->want_panel_vdd;
>> + bool need_to_disable = !intel_dp->pps.want_panel_vdd;
>>
>> lockdep_assert_held(&dev_priv->pps_mutex);
>>
>> if (!intel_dp_is_edp(intel_dp))
>> return false;
>>
>> - cancel_delayed_work(&intel_dp->panel_vdd_work);
>> - intel_dp->want_panel_vdd = true;
>> + cancel_delayed_work(&intel_dp->pps.panel_vdd_work);
>> + intel_dp->pps.want_panel_vdd = true;
>>
>> if (edp_have_panel_vdd(intel_dp))
>> return need_to_disable;
>>
>> - drm_WARN_ON(&dev_priv->drm, intel_dp->vdd_wakeref);
>> - intel_dp->vdd_wakeref = intel_display_power_get(dev_priv,
>> - intel_aux_power_domain(dig_port));
>> + drm_WARN_ON(&dev_priv->drm, intel_dp->pps.vdd_wakeref);
>> + intel_dp->pps.vdd_wakeref = intel_display_power_get(dev_priv,
>> + intel_aux_power_domain(dig_port));
>>
>> drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD on\n",
>> dig_port->base.base.base.id,
>> @@ -614,7 +614,7 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp)
>> "[ENCODER:%d:%s] panel power wasn't enabled\n",
>> dig_port->base.base.base.id,
>> dig_port->base.base.name);
>> - msleep(intel_dp->panel_power_up_delay);
>> + msleep(intel_dp->pps.panel_power_up_delay);
>> }
>>
>> return need_to_disable;
>> @@ -652,7 +652,7 @@ static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
>>
>> lockdep_assert_held(&dev_priv->pps_mutex);
>>
>> - drm_WARN_ON(&dev_priv->drm, intel_dp->want_panel_vdd);
>> + drm_WARN_ON(&dev_priv->drm, intel_dp->pps.want_panel_vdd);
>>
>> if (!edp_have_panel_vdd(intel_dp))
>> return;
>> @@ -676,11 +676,11 @@ static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
>> intel_de_read(dev_priv, pp_ctrl_reg));
>>
>> if ((pp & PANEL_POWER_ON) == 0)
>> - intel_dp->panel_power_off_time = ktime_get_boottime();
>> + intel_dp->pps.panel_power_off_time = ktime_get_boottime();
>>
>> intel_display_power_put(dev_priv,
>> intel_aux_power_domain(dig_port),
>> - fetch_and_zero(&intel_dp->vdd_wakeref));
>> + fetch_and_zero(&intel_dp->pps.vdd_wakeref));
>> }
>>
>> void intel_pps_vdd_off_sync(struct intel_dp *intel_dp)
>> @@ -690,7 +690,7 @@ void intel_pps_vdd_off_sync(struct intel_dp *intel_dp)
>> if (!intel_dp_is_edp(intel_dp))
>> return;
>>
>> - cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
>> + cancel_delayed_work_sync(&intel_dp->pps.panel_vdd_work);
>> /*
>> * vdd might still be enabled due to the delayed vdd off.
>> * Make sure vdd is actually turned off here.
>> @@ -701,13 +701,13 @@ void intel_pps_vdd_off_sync(struct intel_dp *intel_dp)
>>
>> static void edp_panel_vdd_work(struct work_struct *__work)
>> {
>> - struct intel_dp *intel_dp =
>> - container_of(to_delayed_work(__work),
>> - struct intel_dp, panel_vdd_work);
>> + struct intel_pps *pps = container_of(to_delayed_work(__work),
>> + struct intel_pps, panel_vdd_work);
>> + struct intel_dp *intel_dp = container_of(pps, struct intel_dp, pps);
>> intel_wakeref_t wakeref;
>>
>> with_intel_pps_lock(intel_dp, wakeref) {
>> - if (!intel_dp->want_panel_vdd)
>> + if (!intel_dp->pps.want_panel_vdd)
>> intel_pps_vdd_off_sync_unlocked(intel_dp);
>> }
>> }
>> @@ -721,8 +721,8 @@ static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
>> * down delay) to keep the panel power up across a sequence of
>> * operations.
>> */
>> - delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
>> - schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
>> + delay = msecs_to_jiffies(intel_dp->pps.panel_power_cycle_delay * 5);
>> + schedule_delayed_work(&intel_dp->pps.panel_vdd_work, delay);
>> }
>>
>> /*
>> @@ -739,11 +739,11 @@ void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync)
>> if (!intel_dp_is_edp(intel_dp))
>> return;
>>
>> - I915_STATE_WARN(!intel_dp->want_panel_vdd, "[ENCODER:%d:%s] VDD not forced on",
>> + I915_STATE_WARN(!intel_dp->pps.want_panel_vdd, "[ENCODER:%d:%s] VDD not forced on",
>> dp_to_dig_port(intel_dp)->base.base.base.id,
>> dp_to_dig_port(intel_dp)->base.base.name);
>>
>> - intel_dp->want_panel_vdd = false;
>> + intel_dp->pps.want_panel_vdd = false;
>>
>> if (sync)
>> intel_pps_vdd_off_sync_unlocked(intel_dp);
>> @@ -791,7 +791,7 @@ void intel_pps_on_unlocked(struct intel_dp *intel_dp)
>> intel_de_posting_read(dev_priv, pp_ctrl_reg);
>>
>> wait_panel_on(intel_dp);
>> - intel_dp->last_power_on = jiffies;
>> + intel_dp->pps.last_power_on = jiffies;
>>
>> if (IS_GEN(dev_priv, 5)) {
>> pp |= PANEL_POWER_RESET; /* restore panel reset bit */
>> @@ -826,7 +826,7 @@ void intel_pps_off_unlocked(struct intel_dp *intel_dp)
>> drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power off\n",
>> dig_port->base.base.base.id, dig_port->base.base.name);
>>
>> - drm_WARN(&dev_priv->drm, !intel_dp->want_panel_vdd,
>> + drm_WARN(&dev_priv->drm, !intel_dp->pps.want_panel_vdd,
>> "Need [ENCODER:%d:%s] VDD to turn off panel\n",
>> dig_port->base.base.base.id, dig_port->base.base.name);
>>
>> @@ -838,18 +838,18 @@ void intel_pps_off_unlocked(struct intel_dp *intel_dp)
>>
>> pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
>>
>> - intel_dp->want_panel_vdd = false;
>> + intel_dp->pps.want_panel_vdd = false;
>>
>> intel_de_write(dev_priv, pp_ctrl_reg, pp);
>> intel_de_posting_read(dev_priv, pp_ctrl_reg);
>>
>> wait_panel_off(intel_dp);
>> - intel_dp->panel_power_off_time = ktime_get_boottime();
>> + intel_dp->pps.panel_power_off_time = ktime_get_boottime();
>>
>> /* We got a reference when we enabled the VDD. */
>> intel_display_power_put(dev_priv,
>> intel_aux_power_domain(dig_port),
>> - fetch_and_zero(&intel_dp->vdd_wakeref));
>> + fetch_and_zero(&intel_dp->pps.vdd_wakeref));
>> }
>>
>> void intel_pps_off(struct intel_dp *intel_dp)
>> @@ -909,7 +909,7 @@ void intel_pps_backlight_off(struct intel_dp *intel_dp)
>> intel_de_posting_read(dev_priv, pp_ctrl_reg);
>> }
>>
>> - intel_dp->last_backlight_off = jiffies;
>> + intel_dp->pps.last_backlight_off = jiffies;
>> edp_wait_backlight_off(intel_dp);
>> }
>>
>> @@ -943,10 +943,10 @@ static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
>> {
>> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>> struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
>> - enum pipe pipe = intel_dp->pps_pipe;
>> + enum pipe pipe = intel_dp->pps.pps_pipe;
>> i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
>>
>> - drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE);
>> + drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE);
>>
>> if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B))
>> return;
>> @@ -969,7 +969,7 @@ static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
>> intel_de_write(dev_priv, pp_on_reg, 0);
>> intel_de_posting_read(dev_priv, pp_on_reg);
>>
>> - intel_dp->pps_pipe = INVALID_PIPE;
>> + intel_dp->pps.pps_pipe = INVALID_PIPE;
>> }
>>
>> static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
>> @@ -982,12 +982,12 @@ static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
>> for_each_intel_dp(&dev_priv->drm, encoder) {
>> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>>
>> - drm_WARN(&dev_priv->drm, intel_dp->active_pipe == pipe,
>> + drm_WARN(&dev_priv->drm, intel_dp->pps.active_pipe == pipe,
>> "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n",
>> pipe_name(pipe), encoder->base.base.id,
>> encoder->base.name);
>>
>> - if (intel_dp->pps_pipe != pipe)
>> + if (intel_dp->pps.pps_pipe != pipe)
>> continue;
>>
>> drm_dbg_kms(&dev_priv->drm,
>> @@ -1009,10 +1009,10 @@ void vlv_pps_init(struct intel_encoder *encoder,
>>
>> lockdep_assert_held(&dev_priv->pps_mutex);
>>
>> - drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE);
>> + drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE);
>>
>> - if (intel_dp->pps_pipe != INVALID_PIPE &&
>> - intel_dp->pps_pipe != crtc->pipe) {
>> + if (intel_dp->pps.pps_pipe != INVALID_PIPE &&
>> + intel_dp->pps.pps_pipe != crtc->pipe) {
>> /*
>> * If another power sequencer was being used on this
>> * port previously make sure to turn off vdd there while
>> @@ -1027,17 +1027,17 @@ void vlv_pps_init(struct intel_encoder *encoder,
>> */
>> vlv_steal_power_sequencer(dev_priv, crtc->pipe);
>>
>> - intel_dp->active_pipe = crtc->pipe;
>> + intel_dp->pps.active_pipe = crtc->pipe;
>>
>> if (!intel_dp_is_edp(intel_dp))
>> return;
>>
>> /* now it's all ours */
>> - intel_dp->pps_pipe = crtc->pipe;
>> + intel_dp->pps.pps_pipe = crtc->pipe;
>>
>> drm_dbg_kms(&dev_priv->drm,
>> "initializing pipe %c power sequencer for [ENCODER:%d:%s]\n",
>> - pipe_name(intel_dp->pps_pipe), encoder->base.base.id,
>> + pipe_name(intel_dp->pps.pps_pipe), encoder->base.base.id,
>> encoder->base.name);
>>
>> /* init power sequencer on this pipe and port */
>> @@ -1063,9 +1063,9 @@ static void intel_pps_vdd_sanitize(struct intel_dp *intel_dp)
>> */
>> drm_dbg_kms(&dev_priv->drm,
>> "VDD left on by BIOS, adjusting state tracking\n");
>> - drm_WARN_ON(&dev_priv->drm, intel_dp->vdd_wakeref);
>> - intel_dp->vdd_wakeref = intel_display_power_get(dev_priv,
>> - intel_aux_power_domain(dig_port));
>> + drm_WARN_ON(&dev_priv->drm, intel_dp->pps.vdd_wakeref);
>> + intel_dp->pps.vdd_wakeref = intel_display_power_get(dev_priv,
>> + intel_aux_power_domain(dig_port));
>>
>> edp_panel_vdd_schedule_off(intel_dp);
>> }
>> @@ -1085,9 +1085,9 @@ bool intel_pps_have_power(struct intel_dp *intel_dp)
>>
>> static void pps_init_timestamps(struct intel_dp *intel_dp)
>> {
>> - intel_dp->panel_power_off_time = ktime_get_boottime();
>> - intel_dp->last_power_on = jiffies;
>> - intel_dp->last_backlight_off = jiffies;
>> + intel_dp->pps.panel_power_off_time = ktime_get_boottime();
>> + intel_dp->pps.last_power_on = jiffies;
>> + intel_dp->pps.last_backlight_off = jiffies;
>> }
>>
>> static void
>> @@ -1137,7 +1137,7 @@ static void
>> intel_pps_verify_state(struct intel_dp *intel_dp)
>> {
>> struct edp_power_seq hw;
>> - struct edp_power_seq *sw = &intel_dp->pps_delays;
>> + struct edp_power_seq *sw = &intel_dp->pps.pps_delays;
>>
>> intel_pps_readout_hw_state(intel_dp, &hw);
>>
>> @@ -1153,7 +1153,7 @@ static void pps_init_delays(struct intel_dp *intel_dp)
>> {
>> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>> struct edp_power_seq cur, vbt, spec,
>> - *final = &intel_dp->pps_delays;
>> + *final = &intel_dp->pps.pps_delays;
>>
>> lockdep_assert_held(&dev_priv->pps_mutex);
>>
>> @@ -1210,22 +1210,22 @@ static void pps_init_delays(struct intel_dp *intel_dp)
>> #undef assign_final
>>
>> #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
>> - intel_dp->panel_power_up_delay = get_delay(t1_t3);
>> - intel_dp->backlight_on_delay = get_delay(t8);
>> - intel_dp->backlight_off_delay = get_delay(t9);
>> - intel_dp->panel_power_down_delay = get_delay(t10);
>> - intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
>> + intel_dp->pps.panel_power_up_delay = get_delay(t1_t3);
>> + intel_dp->pps.backlight_on_delay = get_delay(t8);
>> + intel_dp->pps.backlight_off_delay = get_delay(t9);
>> + intel_dp->pps.panel_power_down_delay = get_delay(t10);
>> + intel_dp->pps.panel_power_cycle_delay = get_delay(t11_t12);
>> #undef get_delay
>>
>> drm_dbg_kms(&dev_priv->drm,
>> "panel power up delay %d, power down delay %d, power cycle delay %d\n",
>> - intel_dp->panel_power_up_delay,
>> - intel_dp->panel_power_down_delay,
>> - intel_dp->panel_power_cycle_delay);
>> + intel_dp->pps.panel_power_up_delay,
>> + intel_dp->pps.panel_power_down_delay,
>> + intel_dp->pps.panel_power_cycle_delay);
>>
>> drm_dbg_kms(&dev_priv->drm, "backlight on delay %d, off delay %d\n",
>> - intel_dp->backlight_on_delay,
>> - intel_dp->backlight_off_delay);
>> + intel_dp->pps.backlight_on_delay,
>> + intel_dp->pps.backlight_off_delay);
>>
>> /*
>> * We override the HW backlight delays to 1 because we do manual waits
>> @@ -1251,7 +1251,7 @@ static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd
>> int div = RUNTIME_INFO(dev_priv)->rawclk_freq / 1000;
>> struct pps_registers regs;
>> enum port port = dp_to_dig_port(intel_dp)->base.port;
>> - const struct edp_power_seq *seq = &intel_dp->pps_delays;
>> + const struct edp_power_seq *seq = &intel_dp->pps.pps_delays;
>>
>> lockdep_assert_held(&dev_priv->pps_mutex);
>>
>> @@ -1364,7 +1364,7 @@ void intel_pps_encoder_reset(struct intel_dp *intel_dp)
>>
>> void intel_pps_init(struct intel_dp *intel_dp)
>> {
>> - INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work);
>> + INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work);
>>
>> pps_init_timestamps(intel_dp);
>>
>> --
>> 2.20.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH 3/4] drm/i915/dp: abstract struct intel_dp pps members to a sub-struct
2021-01-20 19:25 ` Jani Nikula
@ 2021-01-20 20:08 ` Rodrigo Vivi
2021-01-21 11:47 ` Jani Nikula
0 siblings, 1 reply; 13+ messages in thread
From: Rodrigo Vivi @ 2021-01-20 20:08 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Wed, Jan 20, 2021 at 09:25:10PM +0200, Jani Nikula wrote:
> On Wed, 20 Jan 2021, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> > On Wed, Jan 20, 2021 at 12:18:33PM +0200, Jani Nikula wrote:
> >> Add some namespacing to highlight what belongs where. No functional
> >> changes.
> >>
> >> Cc: Anshuman Gupta <anshuman.gupta@intel.com>
> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >> ---
> >> .../drm/i915/display/intel_display_debugfs.c | 8 +-
> >> .../drm/i915/display/intel_display_types.h | 61 +++---
> >> drivers/gpu/drm/i915/display/intel_dp.c | 14 +-
> >> drivers/gpu/drm/i915/display/intel_pps.c | 192 +++++++++---------
> >> 4 files changed, 140 insertions(+), 135 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> >> index cd7e5519ee7d..885d2d3c91a3 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> >> @@ -2155,13 +2155,13 @@ static int i915_panel_show(struct seq_file *m, void *data)
> >> return -ENODEV;
> >>
> >> seq_printf(m, "Panel power up delay: %d\n",
> >> - intel_dp->panel_power_up_delay);
> >> + intel_dp->pps.panel_power_up_delay);
> >> seq_printf(m, "Panel power down delay: %d\n",
> >> - intel_dp->panel_power_down_delay);
> >> + intel_dp->pps.panel_power_down_delay);
> >> seq_printf(m, "Backlight on delay: %d\n",
> >> - intel_dp->backlight_on_delay);
> >> + intel_dp->pps.backlight_on_delay);
> >> seq_printf(m, "Backlight off delay: %d\n",
> >> - intel_dp->backlight_off_delay);
> >> + intel_dp->pps.backlight_off_delay);
> >>
> >> return 0;
> >> }
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> >> index b601e804f854..1a9243426a25 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> >> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> >> @@ -1369,6 +1369,38 @@ struct intel_dp_pcon_frl {
> >> int trained_rate_gbps;
> >> };
> >>
> >> +struct intel_pps {
> >
> > PPS for Panel Power Something (Sequence? Struct?)
>
> Panel Power Sequencer.
7>
> >
> >> + int panel_power_up_delay;
> >
> > if we have panel power already could we remove panel_power_ from
> > here to simply use pps.up_delay ?
>
> IIRC that's the name used in the specs.
>
> Also didn't want to rename any of the fields in this patch because it's
> much easier to review. Can be renamed afterwards.
That's very true.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> BR,
> Jani.
>
> >
> >> + int panel_power_down_delay;
> >> + int panel_power_cycle_delay;
> >> + int backlight_on_delay;
> >> + int backlight_off_delay;
> >> + struct delayed_work panel_vdd_work;
> >> + bool want_panel_vdd;
> >> + unsigned long last_power_on;
> >> + unsigned long last_backlight_off;
> >> + ktime_t panel_power_off_time;
> >> + intel_wakeref_t vdd_wakeref;
> >> +
> >> + /*
> >> + * Pipe whose power sequencer is currently locked into
> >> + * this port. Only relevant on VLV/CHV.
> >> + */
> >> + enum pipe pps_pipe;
> >
> > and pps.pipe
> >
> >> + /*
> >> + * Pipe currently driving the port. Used for preventing
> >> + * the use of the PPS for any pipe currentrly driving
> >> + * external DP as that will mess things up on VLV.
> >> + */
> >> + enum pipe active_pipe;
> >> + /*
> >> + * Set if the sequencer may be reset due to a power transition,
> >> + * requiring a reinitialization. Only relevant on BXT.
> >> + */
> >> + bool pps_reset;
> >
> > and pps.reset ?
> >
> >> + struct edp_power_seq pps_delays;
> >> +};
> >> +
> >> struct intel_dp {
> >> i915_reg_t output_reg;
> >> u32 DP;
> >> @@ -1408,35 +1440,8 @@ struct intel_dp {
> >> struct drm_dp_aux aux;
> >> u32 aux_busy_last_status;
> >> u8 train_set[4];
> >> - int panel_power_up_delay;
> >> - int panel_power_down_delay;
> >> - int panel_power_cycle_delay;
> >> - int backlight_on_delay;
> >> - int backlight_off_delay;
> >> - struct delayed_work panel_vdd_work;
> >> - bool want_panel_vdd;
> >> - unsigned long last_power_on;
> >> - unsigned long last_backlight_off;
> >> - ktime_t panel_power_off_time;
> >> - intel_wakeref_t vdd_wakeref;
> >>
> >> - /*
> >> - * Pipe whose power sequencer is currently locked into
> >> - * this port. Only relevant on VLV/CHV.
> >> - */
> >> - enum pipe pps_pipe;
> >> - /*
> >> - * Pipe currently driving the port. Used for preventing
> >> - * the use of the PPS for any pipe currentrly driving
> >> - * external DP as that will mess things up on VLV.
> >> - */
> >> - enum pipe active_pipe;
> >> - /*
> >> - * Set if the sequencer may be reset due to a power transition,
> >> - * requiring a reinitialization. Only relevant on BXT.
> >> - */
> >> - bool pps_reset;
> >> - struct edp_power_seq pps_delays;
> >> + struct intel_pps pps;
> >>
> >> bool can_mst; /* this port supports mst */
> >> bool is_mst;
> >> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> >> index 8b9c20555f0e..d815087a26aa 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> >> @@ -4129,7 +4129,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
> >> intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
> >> }
> >>
> >> - msleep(intel_dp->panel_power_down_delay);
> >> + msleep(intel_dp->pps.panel_power_down_delay);
> >>
> >> intel_dp->DP = DP;
> >>
> >> @@ -4137,7 +4137,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
> >> intel_wakeref_t wakeref;
> >>
> >> with_intel_pps_lock(intel_dp, wakeref)
> >> - intel_dp->active_pipe = INVALID_PIPE;
> >> + intel_dp->pps.active_pipe = INVALID_PIPE;
> >> }
> >> }
> >>
> >> @@ -6368,7 +6368,7 @@ void intel_dp_encoder_reset(struct drm_encoder *encoder)
> >> intel_wakeref_t wakeref;
> >>
> >> with_intel_pps_lock(intel_dp, wakeref)
> >> - intel_dp->active_pipe = vlv_active_pipe(intel_dp);
> >> + intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
> >> }
> >>
> >> intel_pps_encoder_reset(intel_dp);
> >> @@ -7139,7 +7139,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
> >> pipe = vlv_active_pipe(intel_dp);
> >>
> >> if (pipe != PIPE_A && pipe != PIPE_B)
> >> - pipe = intel_dp->pps_pipe;
> >> + pipe = intel_dp->pps.pps_pipe;
> >>
> >> if (pipe != PIPE_A && pipe != PIPE_B)
> >> pipe = PIPE_A;
> >> @@ -7216,8 +7216,8 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
> >> intel_dp_set_source_rates(intel_dp);
> >>
> >> intel_dp->reset_link_params = true;
> >> - intel_dp->pps_pipe = INVALID_PIPE;
> >> - intel_dp->active_pipe = INVALID_PIPE;
> >> + intel_dp->pps.pps_pipe = INVALID_PIPE;
> >> + intel_dp->pps.active_pipe = INVALID_PIPE;
> >>
> >> /* Preserve the current hw state. */
> >> intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
> >> @@ -7235,7 +7235,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
> >> }
> >>
> >> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> >> - intel_dp->active_pipe = vlv_active_pipe(intel_dp);
> >> + intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
> >>
> >> /*
> >> * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
> >> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
> >> index 69d9d41b6d22..c4867a8020a5 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_pps.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> >> @@ -44,7 +44,7 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp)
> >> {
> >> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> >> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> >> - enum pipe pipe = intel_dp->pps_pipe;
> >> + enum pipe pipe = intel_dp->pps.pps_pipe;
> >> bool pll_enabled, release_cl_override = false;
> >> enum dpio_phy phy = DPIO_PHY(pipe);
> >> enum dpio_channel ch = vlv_pipe_to_channel(pipe);
> >> @@ -130,18 +130,18 @@ static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
> >>
> >> if (encoder->type == INTEL_OUTPUT_EDP) {
> >> drm_WARN_ON(&dev_priv->drm,
> >> - intel_dp->active_pipe != INVALID_PIPE &&
> >> - intel_dp->active_pipe !=
> >> - intel_dp->pps_pipe);
> >> + intel_dp->pps.active_pipe != INVALID_PIPE &&
> >> + intel_dp->pps.active_pipe !=
> >> + intel_dp->pps.pps_pipe);
> >>
> >> - if (intel_dp->pps_pipe != INVALID_PIPE)
> >> - pipes &= ~(1 << intel_dp->pps_pipe);
> >> + if (intel_dp->pps.pps_pipe != INVALID_PIPE)
> >> + pipes &= ~(1 << intel_dp->pps.pps_pipe);
> >> } else {
> >> drm_WARN_ON(&dev_priv->drm,
> >> - intel_dp->pps_pipe != INVALID_PIPE);
> >> + intel_dp->pps.pps_pipe != INVALID_PIPE);
> >>
> >> - if (intel_dp->active_pipe != INVALID_PIPE)
> >> - pipes &= ~(1 << intel_dp->active_pipe);
> >> + if (intel_dp->pps.active_pipe != INVALID_PIPE)
> >> + pipes &= ~(1 << intel_dp->pps.active_pipe);
> >> }
> >> }
> >>
> >> @@ -163,11 +163,11 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
> >> /* We should never land here with regular DP ports */
> >> drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
> >>
> >> - drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE &&
> >> - intel_dp->active_pipe != intel_dp->pps_pipe);
> >> + drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE &&
> >> + intel_dp->pps.active_pipe != intel_dp->pps.pps_pipe);
> >>
> >> - if (intel_dp->pps_pipe != INVALID_PIPE)
> >> - return intel_dp->pps_pipe;
> >> + if (intel_dp->pps.pps_pipe != INVALID_PIPE)
> >> + return intel_dp->pps.pps_pipe;
> >>
> >> pipe = vlv_find_free_pps(dev_priv);
> >>
> >> @@ -179,11 +179,11 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
> >> pipe = PIPE_A;
> >>
> >> vlv_steal_power_sequencer(dev_priv, pipe);
> >> - intel_dp->pps_pipe = pipe;
> >> + intel_dp->pps.pps_pipe = pipe;
> >>
> >> drm_dbg_kms(&dev_priv->drm,
> >> "picked pipe %c power sequencer for [ENCODER:%d:%s]\n",
> >> - pipe_name(intel_dp->pps_pipe),
> >> + pipe_name(intel_dp->pps.pps_pipe),
> >> dig_port->base.base.base.id,
> >> dig_port->base.base.name);
> >>
> >> @@ -197,7 +197,7 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
> >> */
> >> vlv_power_sequencer_kick(intel_dp);
> >>
> >> - return intel_dp->pps_pipe;
> >> + return intel_dp->pps.pps_pipe;
> >> }
> >>
> >> static int
> >> @@ -211,10 +211,10 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp)
> >> /* We should never land here with regular DP ports */
> >> drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
> >>
> >> - if (!intel_dp->pps_reset)
> >> + if (!intel_dp->pps.pps_reset)
> >> return backlight_controller;
> >>
> >> - intel_dp->pps_reset = false;
> >> + intel_dp->pps.pps_reset = false;
> >>
> >> /*
> >> * Only the HW needs to be reprogrammed, the SW state is fixed and
> >> @@ -280,19 +280,19 @@ vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
> >>
> >> /* try to find a pipe with this port selected */
> >> /* first pick one where the panel is on */
> >> - intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
> >> - vlv_pipe_has_pp_on);
> >> + intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
> >> + vlv_pipe_has_pp_on);
> >> /* didn't find one? pick one where vdd is on */
> >> - if (intel_dp->pps_pipe == INVALID_PIPE)
> >> - intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
> >> - vlv_pipe_has_vdd_on);
> >> + if (intel_dp->pps.pps_pipe == INVALID_PIPE)
> >> + intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
> >> + vlv_pipe_has_vdd_on);
> >> /* didn't find one? pick one with just the correct port */
> >> - if (intel_dp->pps_pipe == INVALID_PIPE)
> >> - intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
> >> - vlv_pipe_any);
> >> + if (intel_dp->pps.pps_pipe == INVALID_PIPE)
> >> + intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
> >> + vlv_pipe_any);
> >>
> >> /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
> >> - if (intel_dp->pps_pipe == INVALID_PIPE) {
> >> + if (intel_dp->pps.pps_pipe == INVALID_PIPE) {
> >> drm_dbg_kms(&dev_priv->drm,
> >> "no initial power sequencer for [ENCODER:%d:%s]\n",
> >> dig_port->base.base.base.id,
> >> @@ -304,7 +304,7 @@ vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
> >> "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n",
> >> dig_port->base.base.base.id,
> >> dig_port->base.base.name,
> >> - pipe_name(intel_dp->pps_pipe));
> >> + pipe_name(intel_dp->pps.pps_pipe));
> >> }
> >>
> >> void intel_pps_reset_all(struct drm_i915_private *dev_priv)
> >> @@ -331,15 +331,15 @@ void intel_pps_reset_all(struct drm_i915_private *dev_priv)
> >> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> >>
> >> drm_WARN_ON(&dev_priv->drm,
> >> - intel_dp->active_pipe != INVALID_PIPE);
> >> + intel_dp->pps.active_pipe != INVALID_PIPE);
> >>
> >> if (encoder->type != INTEL_OUTPUT_EDP)
> >> continue;
> >>
> >> if (IS_GEN9_LP(dev_priv))
> >> - intel_dp->pps_reset = true;
> >> + intel_dp->pps.pps_reset = true;
> >> else
> >> - intel_dp->pps_pipe = INVALID_PIPE;
> >> + intel_dp->pps.pps_pipe = INVALID_PIPE;
> >> }
> >> }
> >>
> >> @@ -403,7 +403,7 @@ static bool edp_have_panel_power(struct intel_dp *intel_dp)
> >> lockdep_assert_held(&dev_priv->pps_mutex);
> >>
> >> if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> >> - intel_dp->pps_pipe == INVALID_PIPE)
> >> + intel_dp->pps.pps_pipe == INVALID_PIPE)
> >> return false;
> >>
> >> return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON) != 0;
> >> @@ -416,7 +416,7 @@ static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
> >> lockdep_assert_held(&dev_priv->pps_mutex);
> >>
> >> if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> >> - intel_dp->pps_pipe == INVALID_PIPE)
> >> + intel_dp->pps.pps_pipe == INVALID_PIPE)
> >> return false;
> >>
> >> return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
> >> @@ -506,13 +506,13 @@ static void wait_panel_power_cycle(struct intel_dp *intel_dp)
> >> /* take the difference of currrent time and panel power off time
> >> * and then make panel wait for t11_t12 if needed. */
> >> panel_power_on_time = ktime_get_boottime();
> >> - panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
> >> + panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->pps.panel_power_off_time);
> >>
> >> /* When we disable the VDD override bit last we have to do the manual
> >> * wait. */
> >> - if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
> >> + if (panel_power_off_duration < (s64)intel_dp->pps.panel_power_cycle_delay)
> >> wait_remaining_ms_from_jiffies(jiffies,
> >> - intel_dp->panel_power_cycle_delay - panel_power_off_duration);
> >> + intel_dp->pps.panel_power_cycle_delay - panel_power_off_duration);
> >>
> >> wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
> >> }
> >> @@ -530,14 +530,14 @@ void intel_pps_wait_power_cycle(struct intel_dp *intel_dp)
> >>
> >> static void wait_backlight_on(struct intel_dp *intel_dp)
> >> {
> >> - wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
> >> - intel_dp->backlight_on_delay);
> >> + wait_remaining_ms_from_jiffies(intel_dp->pps.last_power_on,
> >> + intel_dp->pps.backlight_on_delay);
> >> }
> >>
> >> static void edp_wait_backlight_off(struct intel_dp *intel_dp)
> >> {
> >> - wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
> >> - intel_dp->backlight_off_delay);
> >> + wait_remaining_ms_from_jiffies(intel_dp->pps.last_backlight_off,
> >> + intel_dp->pps.backlight_off_delay);
> >> }
> >>
> >> /* Read the current pp_control value, unlocking the register if it
> >> @@ -571,22 +571,22 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp)
> >> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> >> u32 pp;
> >> i915_reg_t pp_stat_reg, pp_ctrl_reg;
> >> - bool need_to_disable = !intel_dp->want_panel_vdd;
> >> + bool need_to_disable = !intel_dp->pps.want_panel_vdd;
> >>
> >> lockdep_assert_held(&dev_priv->pps_mutex);
> >>
> >> if (!intel_dp_is_edp(intel_dp))
> >> return false;
> >>
> >> - cancel_delayed_work(&intel_dp->panel_vdd_work);
> >> - intel_dp->want_panel_vdd = true;
> >> + cancel_delayed_work(&intel_dp->pps.panel_vdd_work);
> >> + intel_dp->pps.want_panel_vdd = true;
> >>
> >> if (edp_have_panel_vdd(intel_dp))
> >> return need_to_disable;
> >>
> >> - drm_WARN_ON(&dev_priv->drm, intel_dp->vdd_wakeref);
> >> - intel_dp->vdd_wakeref = intel_display_power_get(dev_priv,
> >> - intel_aux_power_domain(dig_port));
> >> + drm_WARN_ON(&dev_priv->drm, intel_dp->pps.vdd_wakeref);
> >> + intel_dp->pps.vdd_wakeref = intel_display_power_get(dev_priv,
> >> + intel_aux_power_domain(dig_port));
> >>
> >> drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD on\n",
> >> dig_port->base.base.base.id,
> >> @@ -614,7 +614,7 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp)
> >> "[ENCODER:%d:%s] panel power wasn't enabled\n",
> >> dig_port->base.base.base.id,
> >> dig_port->base.base.name);
> >> - msleep(intel_dp->panel_power_up_delay);
> >> + msleep(intel_dp->pps.panel_power_up_delay);
> >> }
> >>
> >> return need_to_disable;
> >> @@ -652,7 +652,7 @@ static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
> >>
> >> lockdep_assert_held(&dev_priv->pps_mutex);
> >>
> >> - drm_WARN_ON(&dev_priv->drm, intel_dp->want_panel_vdd);
> >> + drm_WARN_ON(&dev_priv->drm, intel_dp->pps.want_panel_vdd);
> >>
> >> if (!edp_have_panel_vdd(intel_dp))
> >> return;
> >> @@ -676,11 +676,11 @@ static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
> >> intel_de_read(dev_priv, pp_ctrl_reg));
> >>
> >> if ((pp & PANEL_POWER_ON) == 0)
> >> - intel_dp->panel_power_off_time = ktime_get_boottime();
> >> + intel_dp->pps.panel_power_off_time = ktime_get_boottime();
> >>
> >> intel_display_power_put(dev_priv,
> >> intel_aux_power_domain(dig_port),
> >> - fetch_and_zero(&intel_dp->vdd_wakeref));
> >> + fetch_and_zero(&intel_dp->pps.vdd_wakeref));
> >> }
> >>
> >> void intel_pps_vdd_off_sync(struct intel_dp *intel_dp)
> >> @@ -690,7 +690,7 @@ void intel_pps_vdd_off_sync(struct intel_dp *intel_dp)
> >> if (!intel_dp_is_edp(intel_dp))
> >> return;
> >>
> >> - cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
> >> + cancel_delayed_work_sync(&intel_dp->pps.panel_vdd_work);
> >> /*
> >> * vdd might still be enabled due to the delayed vdd off.
> >> * Make sure vdd is actually turned off here.
> >> @@ -701,13 +701,13 @@ void intel_pps_vdd_off_sync(struct intel_dp *intel_dp)
> >>
> >> static void edp_panel_vdd_work(struct work_struct *__work)
> >> {
> >> - struct intel_dp *intel_dp =
> >> - container_of(to_delayed_work(__work),
> >> - struct intel_dp, panel_vdd_work);
> >> + struct intel_pps *pps = container_of(to_delayed_work(__work),
> >> + struct intel_pps, panel_vdd_work);
> >> + struct intel_dp *intel_dp = container_of(pps, struct intel_dp, pps);
> >> intel_wakeref_t wakeref;
> >>
> >> with_intel_pps_lock(intel_dp, wakeref) {
> >> - if (!intel_dp->want_panel_vdd)
> >> + if (!intel_dp->pps.want_panel_vdd)
> >> intel_pps_vdd_off_sync_unlocked(intel_dp);
> >> }
> >> }
> >> @@ -721,8 +721,8 @@ static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
> >> * down delay) to keep the panel power up across a sequence of
> >> * operations.
> >> */
> >> - delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
> >> - schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
> >> + delay = msecs_to_jiffies(intel_dp->pps.panel_power_cycle_delay * 5);
> >> + schedule_delayed_work(&intel_dp->pps.panel_vdd_work, delay);
> >> }
> >>
> >> /*
> >> @@ -739,11 +739,11 @@ void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync)
> >> if (!intel_dp_is_edp(intel_dp))
> >> return;
> >>
> >> - I915_STATE_WARN(!intel_dp->want_panel_vdd, "[ENCODER:%d:%s] VDD not forced on",
> >> + I915_STATE_WARN(!intel_dp->pps.want_panel_vdd, "[ENCODER:%d:%s] VDD not forced on",
> >> dp_to_dig_port(intel_dp)->base.base.base.id,
> >> dp_to_dig_port(intel_dp)->base.base.name);
> >>
> >> - intel_dp->want_panel_vdd = false;
> >> + intel_dp->pps.want_panel_vdd = false;
> >>
> >> if (sync)
> >> intel_pps_vdd_off_sync_unlocked(intel_dp);
> >> @@ -791,7 +791,7 @@ void intel_pps_on_unlocked(struct intel_dp *intel_dp)
> >> intel_de_posting_read(dev_priv, pp_ctrl_reg);
> >>
> >> wait_panel_on(intel_dp);
> >> - intel_dp->last_power_on = jiffies;
> >> + intel_dp->pps.last_power_on = jiffies;
> >>
> >> if (IS_GEN(dev_priv, 5)) {
> >> pp |= PANEL_POWER_RESET; /* restore panel reset bit */
> >> @@ -826,7 +826,7 @@ void intel_pps_off_unlocked(struct intel_dp *intel_dp)
> >> drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power off\n",
> >> dig_port->base.base.base.id, dig_port->base.base.name);
> >>
> >> - drm_WARN(&dev_priv->drm, !intel_dp->want_panel_vdd,
> >> + drm_WARN(&dev_priv->drm, !intel_dp->pps.want_panel_vdd,
> >> "Need [ENCODER:%d:%s] VDD to turn off panel\n",
> >> dig_port->base.base.base.id, dig_port->base.base.name);
> >>
> >> @@ -838,18 +838,18 @@ void intel_pps_off_unlocked(struct intel_dp *intel_dp)
> >>
> >> pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
> >>
> >> - intel_dp->want_panel_vdd = false;
> >> + intel_dp->pps.want_panel_vdd = false;
> >>
> >> intel_de_write(dev_priv, pp_ctrl_reg, pp);
> >> intel_de_posting_read(dev_priv, pp_ctrl_reg);
> >>
> >> wait_panel_off(intel_dp);
> >> - intel_dp->panel_power_off_time = ktime_get_boottime();
> >> + intel_dp->pps.panel_power_off_time = ktime_get_boottime();
> >>
> >> /* We got a reference when we enabled the VDD. */
> >> intel_display_power_put(dev_priv,
> >> intel_aux_power_domain(dig_port),
> >> - fetch_and_zero(&intel_dp->vdd_wakeref));
> >> + fetch_and_zero(&intel_dp->pps.vdd_wakeref));
> >> }
> >>
> >> void intel_pps_off(struct intel_dp *intel_dp)
> >> @@ -909,7 +909,7 @@ void intel_pps_backlight_off(struct intel_dp *intel_dp)
> >> intel_de_posting_read(dev_priv, pp_ctrl_reg);
> >> }
> >>
> >> - intel_dp->last_backlight_off = jiffies;
> >> + intel_dp->pps.last_backlight_off = jiffies;
> >> edp_wait_backlight_off(intel_dp);
> >> }
> >>
> >> @@ -943,10 +943,10 @@ static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
> >> {
> >> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> >> struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> >> - enum pipe pipe = intel_dp->pps_pipe;
> >> + enum pipe pipe = intel_dp->pps.pps_pipe;
> >> i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
> >>
> >> - drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE);
> >> + drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE);
> >>
> >> if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B))
> >> return;
> >> @@ -969,7 +969,7 @@ static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
> >> intel_de_write(dev_priv, pp_on_reg, 0);
> >> intel_de_posting_read(dev_priv, pp_on_reg);
> >>
> >> - intel_dp->pps_pipe = INVALID_PIPE;
> >> + intel_dp->pps.pps_pipe = INVALID_PIPE;
> >> }
> >>
> >> static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
> >> @@ -982,12 +982,12 @@ static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
> >> for_each_intel_dp(&dev_priv->drm, encoder) {
> >> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> >>
> >> - drm_WARN(&dev_priv->drm, intel_dp->active_pipe == pipe,
> >> + drm_WARN(&dev_priv->drm, intel_dp->pps.active_pipe == pipe,
> >> "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n",
> >> pipe_name(pipe), encoder->base.base.id,
> >> encoder->base.name);
> >>
> >> - if (intel_dp->pps_pipe != pipe)
> >> + if (intel_dp->pps.pps_pipe != pipe)
> >> continue;
> >>
> >> drm_dbg_kms(&dev_priv->drm,
> >> @@ -1009,10 +1009,10 @@ void vlv_pps_init(struct intel_encoder *encoder,
> >>
> >> lockdep_assert_held(&dev_priv->pps_mutex);
> >>
> >> - drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE);
> >> + drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE);
> >>
> >> - if (intel_dp->pps_pipe != INVALID_PIPE &&
> >> - intel_dp->pps_pipe != crtc->pipe) {
> >> + if (intel_dp->pps.pps_pipe != INVALID_PIPE &&
> >> + intel_dp->pps.pps_pipe != crtc->pipe) {
> >> /*
> >> * If another power sequencer was being used on this
> >> * port previously make sure to turn off vdd there while
> >> @@ -1027,17 +1027,17 @@ void vlv_pps_init(struct intel_encoder *encoder,
> >> */
> >> vlv_steal_power_sequencer(dev_priv, crtc->pipe);
> >>
> >> - intel_dp->active_pipe = crtc->pipe;
> >> + intel_dp->pps.active_pipe = crtc->pipe;
> >>
> >> if (!intel_dp_is_edp(intel_dp))
> >> return;
> >>
> >> /* now it's all ours */
> >> - intel_dp->pps_pipe = crtc->pipe;
> >> + intel_dp->pps.pps_pipe = crtc->pipe;
> >>
> >> drm_dbg_kms(&dev_priv->drm,
> >> "initializing pipe %c power sequencer for [ENCODER:%d:%s]\n",
> >> - pipe_name(intel_dp->pps_pipe), encoder->base.base.id,
> >> + pipe_name(intel_dp->pps.pps_pipe), encoder->base.base.id,
> >> encoder->base.name);
> >>
> >> /* init power sequencer on this pipe and port */
> >> @@ -1063,9 +1063,9 @@ static void intel_pps_vdd_sanitize(struct intel_dp *intel_dp)
> >> */
> >> drm_dbg_kms(&dev_priv->drm,
> >> "VDD left on by BIOS, adjusting state tracking\n");
> >> - drm_WARN_ON(&dev_priv->drm, intel_dp->vdd_wakeref);
> >> - intel_dp->vdd_wakeref = intel_display_power_get(dev_priv,
> >> - intel_aux_power_domain(dig_port));
> >> + drm_WARN_ON(&dev_priv->drm, intel_dp->pps.vdd_wakeref);
> >> + intel_dp->pps.vdd_wakeref = intel_display_power_get(dev_priv,
> >> + intel_aux_power_domain(dig_port));
> >>
> >> edp_panel_vdd_schedule_off(intel_dp);
> >> }
> >> @@ -1085,9 +1085,9 @@ bool intel_pps_have_power(struct intel_dp *intel_dp)
> >>
> >> static void pps_init_timestamps(struct intel_dp *intel_dp)
> >> {
> >> - intel_dp->panel_power_off_time = ktime_get_boottime();
> >> - intel_dp->last_power_on = jiffies;
> >> - intel_dp->last_backlight_off = jiffies;
> >> + intel_dp->pps.panel_power_off_time = ktime_get_boottime();
> >> + intel_dp->pps.last_power_on = jiffies;
> >> + intel_dp->pps.last_backlight_off = jiffies;
> >> }
> >>
> >> static void
> >> @@ -1137,7 +1137,7 @@ static void
> >> intel_pps_verify_state(struct intel_dp *intel_dp)
> >> {
> >> struct edp_power_seq hw;
> >> - struct edp_power_seq *sw = &intel_dp->pps_delays;
> >> + struct edp_power_seq *sw = &intel_dp->pps.pps_delays;
> >>
> >> intel_pps_readout_hw_state(intel_dp, &hw);
> >>
> >> @@ -1153,7 +1153,7 @@ static void pps_init_delays(struct intel_dp *intel_dp)
> >> {
> >> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> >> struct edp_power_seq cur, vbt, spec,
> >> - *final = &intel_dp->pps_delays;
> >> + *final = &intel_dp->pps.pps_delays;
> >>
> >> lockdep_assert_held(&dev_priv->pps_mutex);
> >>
> >> @@ -1210,22 +1210,22 @@ static void pps_init_delays(struct intel_dp *intel_dp)
> >> #undef assign_final
> >>
> >> #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
> >> - intel_dp->panel_power_up_delay = get_delay(t1_t3);
> >> - intel_dp->backlight_on_delay = get_delay(t8);
> >> - intel_dp->backlight_off_delay = get_delay(t9);
> >> - intel_dp->panel_power_down_delay = get_delay(t10);
> >> - intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
> >> + intel_dp->pps.panel_power_up_delay = get_delay(t1_t3);
> >> + intel_dp->pps.backlight_on_delay = get_delay(t8);
> >> + intel_dp->pps.backlight_off_delay = get_delay(t9);
> >> + intel_dp->pps.panel_power_down_delay = get_delay(t10);
> >> + intel_dp->pps.panel_power_cycle_delay = get_delay(t11_t12);
> >> #undef get_delay
> >>
> >> drm_dbg_kms(&dev_priv->drm,
> >> "panel power up delay %d, power down delay %d, power cycle delay %d\n",
> >> - intel_dp->panel_power_up_delay,
> >> - intel_dp->panel_power_down_delay,
> >> - intel_dp->panel_power_cycle_delay);
> >> + intel_dp->pps.panel_power_up_delay,
> >> + intel_dp->pps.panel_power_down_delay,
> >> + intel_dp->pps.panel_power_cycle_delay);
> >>
> >> drm_dbg_kms(&dev_priv->drm, "backlight on delay %d, off delay %d\n",
> >> - intel_dp->backlight_on_delay,
> >> - intel_dp->backlight_off_delay);
> >> + intel_dp->pps.backlight_on_delay,
> >> + intel_dp->pps.backlight_off_delay);
> >>
> >> /*
> >> * We override the HW backlight delays to 1 because we do manual waits
> >> @@ -1251,7 +1251,7 @@ static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd
> >> int div = RUNTIME_INFO(dev_priv)->rawclk_freq / 1000;
> >> struct pps_registers regs;
> >> enum port port = dp_to_dig_port(intel_dp)->base.port;
> >> - const struct edp_power_seq *seq = &intel_dp->pps_delays;
> >> + const struct edp_power_seq *seq = &intel_dp->pps.pps_delays;
> >>
> >> lockdep_assert_held(&dev_priv->pps_mutex);
> >>
> >> @@ -1364,7 +1364,7 @@ void intel_pps_encoder_reset(struct intel_dp *intel_dp)
> >>
> >> void intel_pps_init(struct intel_dp *intel_dp)
> >> {
> >> - INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work);
> >> + INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work);
> >>
> >> pps_init_timestamps(intel_dp);
> >>
> >> --
> >> 2.20.1
> >>
> >> _______________________________________________
> >> Intel-gfx mailing list
> >> Intel-gfx@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Jani Nikula, Intel Open Source Graphics Center
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH 3/4] drm/i915/dp: abstract struct intel_dp pps members to a sub-struct
2021-01-20 20:08 ` Rodrigo Vivi
@ 2021-01-21 11:47 ` Jani Nikula
0 siblings, 0 replies; 13+ messages in thread
From: Jani Nikula @ 2021-01-21 11:47 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
On Wed, 20 Jan 2021, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> On Wed, Jan 20, 2021 at 09:25:10PM +0200, Jani Nikula wrote:
>> On Wed, 20 Jan 2021, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
>> > On Wed, Jan 20, 2021 at 12:18:33PM +0200, Jani Nikula wrote:
>> >> Add some namespacing to highlight what belongs where. No functional
>> >> changes.
>> >>
>> >> Cc: Anshuman Gupta <anshuman.gupta@intel.com>
>> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> >> ---
>> >> .../drm/i915/display/intel_display_debugfs.c | 8 +-
>> >> .../drm/i915/display/intel_display_types.h | 61 +++---
>> >> drivers/gpu/drm/i915/display/intel_dp.c | 14 +-
>> >> drivers/gpu/drm/i915/display/intel_pps.c | 192 +++++++++---------
>> >> 4 files changed, 140 insertions(+), 135 deletions(-)
>> >>
>> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> >> index cd7e5519ee7d..885d2d3c91a3 100644
>> >> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> >> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> >> @@ -2155,13 +2155,13 @@ static int i915_panel_show(struct seq_file *m, void *data)
>> >> return -ENODEV;
>> >>
>> >> seq_printf(m, "Panel power up delay: %d\n",
>> >> - intel_dp->panel_power_up_delay);
>> >> + intel_dp->pps.panel_power_up_delay);
>> >> seq_printf(m, "Panel power down delay: %d\n",
>> >> - intel_dp->panel_power_down_delay);
>> >> + intel_dp->pps.panel_power_down_delay);
>> >> seq_printf(m, "Backlight on delay: %d\n",
>> >> - intel_dp->backlight_on_delay);
>> >> + intel_dp->pps.backlight_on_delay);
>> >> seq_printf(m, "Backlight off delay: %d\n",
>> >> - intel_dp->backlight_off_delay);
>> >> + intel_dp->pps.backlight_off_delay);
>> >>
>> >> return 0;
>> >> }
>> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>> >> index b601e804f854..1a9243426a25 100644
>> >> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> >> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> >> @@ -1369,6 +1369,38 @@ struct intel_dp_pcon_frl {
>> >> int trained_rate_gbps;
>> >> };
>> >>
>> >> +struct intel_pps {
>> >
>> > PPS for Panel Power Something (Sequence? Struct?)
>>
>> Panel Power Sequencer.
> 7>
>> >
>> >> + int panel_power_up_delay;
>> >
>> > if we have panel power already could we remove panel_power_ from
>> > here to simply use pps.up_delay ?
>>
>> IIRC that's the name used in the specs.
>>
>> Also didn't want to rename any of the fields in this patch because it's
>> much easier to review. Can be renamed afterwards.
>
> That's very true.
>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Thanks for the reviews, pushed to drm-intel-next.
BR,
Jani.
>
>
>
>>
>> BR,
>> Jani.
>>
>> >
>> >> + int panel_power_down_delay;
>> >> + int panel_power_cycle_delay;
>> >> + int backlight_on_delay;
>> >> + int backlight_off_delay;
>> >> + struct delayed_work panel_vdd_work;
>> >> + bool want_panel_vdd;
>> >> + unsigned long last_power_on;
>> >> + unsigned long last_backlight_off;
>> >> + ktime_t panel_power_off_time;
>> >> + intel_wakeref_t vdd_wakeref;
>> >> +
>> >> + /*
>> >> + * Pipe whose power sequencer is currently locked into
>> >> + * this port. Only relevant on VLV/CHV.
>> >> + */
>> >> + enum pipe pps_pipe;
>> >
>> > and pps.pipe
>> >
>> >> + /*
>> >> + * Pipe currently driving the port. Used for preventing
>> >> + * the use of the PPS for any pipe currentrly driving
>> >> + * external DP as that will mess things up on VLV.
>> >> + */
>> >> + enum pipe active_pipe;
>> >> + /*
>> >> + * Set if the sequencer may be reset due to a power transition,
>> >> + * requiring a reinitialization. Only relevant on BXT.
>> >> + */
>> >> + bool pps_reset;
>> >
>> > and pps.reset ?
>> >
>> >> + struct edp_power_seq pps_delays;
>> >> +};
>> >> +
>> >> struct intel_dp {
>> >> i915_reg_t output_reg;
>> >> u32 DP;
>> >> @@ -1408,35 +1440,8 @@ struct intel_dp {
>> >> struct drm_dp_aux aux;
>> >> u32 aux_busy_last_status;
>> >> u8 train_set[4];
>> >> - int panel_power_up_delay;
>> >> - int panel_power_down_delay;
>> >> - int panel_power_cycle_delay;
>> >> - int backlight_on_delay;
>> >> - int backlight_off_delay;
>> >> - struct delayed_work panel_vdd_work;
>> >> - bool want_panel_vdd;
>> >> - unsigned long last_power_on;
>> >> - unsigned long last_backlight_off;
>> >> - ktime_t panel_power_off_time;
>> >> - intel_wakeref_t vdd_wakeref;
>> >>
>> >> - /*
>> >> - * Pipe whose power sequencer is currently locked into
>> >> - * this port. Only relevant on VLV/CHV.
>> >> - */
>> >> - enum pipe pps_pipe;
>> >> - /*
>> >> - * Pipe currently driving the port. Used for preventing
>> >> - * the use of the PPS for any pipe currentrly driving
>> >> - * external DP as that will mess things up on VLV.
>> >> - */
>> >> - enum pipe active_pipe;
>> >> - /*
>> >> - * Set if the sequencer may be reset due to a power transition,
>> >> - * requiring a reinitialization. Only relevant on BXT.
>> >> - */
>> >> - bool pps_reset;
>> >> - struct edp_power_seq pps_delays;
>> >> + struct intel_pps pps;
>> >>
>> >> bool can_mst; /* this port supports mst */
>> >> bool is_mst;
>> >> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> >> index 8b9c20555f0e..d815087a26aa 100644
>> >> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> >> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> >> @@ -4129,7 +4129,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
>> >> intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
>> >> }
>> >>
>> >> - msleep(intel_dp->panel_power_down_delay);
>> >> + msleep(intel_dp->pps.panel_power_down_delay);
>> >>
>> >> intel_dp->DP = DP;
>> >>
>> >> @@ -4137,7 +4137,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
>> >> intel_wakeref_t wakeref;
>> >>
>> >> with_intel_pps_lock(intel_dp, wakeref)
>> >> - intel_dp->active_pipe = INVALID_PIPE;
>> >> + intel_dp->pps.active_pipe = INVALID_PIPE;
>> >> }
>> >> }
>> >>
>> >> @@ -6368,7 +6368,7 @@ void intel_dp_encoder_reset(struct drm_encoder *encoder)
>> >> intel_wakeref_t wakeref;
>> >>
>> >> with_intel_pps_lock(intel_dp, wakeref)
>> >> - intel_dp->active_pipe = vlv_active_pipe(intel_dp);
>> >> + intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
>> >> }
>> >>
>> >> intel_pps_encoder_reset(intel_dp);
>> >> @@ -7139,7 +7139,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
>> >> pipe = vlv_active_pipe(intel_dp);
>> >>
>> >> if (pipe != PIPE_A && pipe != PIPE_B)
>> >> - pipe = intel_dp->pps_pipe;
>> >> + pipe = intel_dp->pps.pps_pipe;
>> >>
>> >> if (pipe != PIPE_A && pipe != PIPE_B)
>> >> pipe = PIPE_A;
>> >> @@ -7216,8 +7216,8 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
>> >> intel_dp_set_source_rates(intel_dp);
>> >>
>> >> intel_dp->reset_link_params = true;
>> >> - intel_dp->pps_pipe = INVALID_PIPE;
>> >> - intel_dp->active_pipe = INVALID_PIPE;
>> >> + intel_dp->pps.pps_pipe = INVALID_PIPE;
>> >> + intel_dp->pps.active_pipe = INVALID_PIPE;
>> >>
>> >> /* Preserve the current hw state. */
>> >> intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
>> >> @@ -7235,7 +7235,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
>> >> }
>> >>
>> >> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>> >> - intel_dp->active_pipe = vlv_active_pipe(intel_dp);
>> >> + intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
>> >>
>> >> /*
>> >> * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
>> >> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
>> >> index 69d9d41b6d22..c4867a8020a5 100644
>> >> --- a/drivers/gpu/drm/i915/display/intel_pps.c
>> >> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
>> >> @@ -44,7 +44,7 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp)
>> >> {
>> >> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>> >> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>> >> - enum pipe pipe = intel_dp->pps_pipe;
>> >> + enum pipe pipe = intel_dp->pps.pps_pipe;
>> >> bool pll_enabled, release_cl_override = false;
>> >> enum dpio_phy phy = DPIO_PHY(pipe);
>> >> enum dpio_channel ch = vlv_pipe_to_channel(pipe);
>> >> @@ -130,18 +130,18 @@ static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
>> >>
>> >> if (encoder->type == INTEL_OUTPUT_EDP) {
>> >> drm_WARN_ON(&dev_priv->drm,
>> >> - intel_dp->active_pipe != INVALID_PIPE &&
>> >> - intel_dp->active_pipe !=
>> >> - intel_dp->pps_pipe);
>> >> + intel_dp->pps.active_pipe != INVALID_PIPE &&
>> >> + intel_dp->pps.active_pipe !=
>> >> + intel_dp->pps.pps_pipe);
>> >>
>> >> - if (intel_dp->pps_pipe != INVALID_PIPE)
>> >> - pipes &= ~(1 << intel_dp->pps_pipe);
>> >> + if (intel_dp->pps.pps_pipe != INVALID_PIPE)
>> >> + pipes &= ~(1 << intel_dp->pps.pps_pipe);
>> >> } else {
>> >> drm_WARN_ON(&dev_priv->drm,
>> >> - intel_dp->pps_pipe != INVALID_PIPE);
>> >> + intel_dp->pps.pps_pipe != INVALID_PIPE);
>> >>
>> >> - if (intel_dp->active_pipe != INVALID_PIPE)
>> >> - pipes &= ~(1 << intel_dp->active_pipe);
>> >> + if (intel_dp->pps.active_pipe != INVALID_PIPE)
>> >> + pipes &= ~(1 << intel_dp->pps.active_pipe);
>> >> }
>> >> }
>> >>
>> >> @@ -163,11 +163,11 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
>> >> /* We should never land here with regular DP ports */
>> >> drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
>> >>
>> >> - drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE &&
>> >> - intel_dp->active_pipe != intel_dp->pps_pipe);
>> >> + drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE &&
>> >> + intel_dp->pps.active_pipe != intel_dp->pps.pps_pipe);
>> >>
>> >> - if (intel_dp->pps_pipe != INVALID_PIPE)
>> >> - return intel_dp->pps_pipe;
>> >> + if (intel_dp->pps.pps_pipe != INVALID_PIPE)
>> >> + return intel_dp->pps.pps_pipe;
>> >>
>> >> pipe = vlv_find_free_pps(dev_priv);
>> >>
>> >> @@ -179,11 +179,11 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
>> >> pipe = PIPE_A;
>> >>
>> >> vlv_steal_power_sequencer(dev_priv, pipe);
>> >> - intel_dp->pps_pipe = pipe;
>> >> + intel_dp->pps.pps_pipe = pipe;
>> >>
>> >> drm_dbg_kms(&dev_priv->drm,
>> >> "picked pipe %c power sequencer for [ENCODER:%d:%s]\n",
>> >> - pipe_name(intel_dp->pps_pipe),
>> >> + pipe_name(intel_dp->pps.pps_pipe),
>> >> dig_port->base.base.base.id,
>> >> dig_port->base.base.name);
>> >>
>> >> @@ -197,7 +197,7 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
>> >> */
>> >> vlv_power_sequencer_kick(intel_dp);
>> >>
>> >> - return intel_dp->pps_pipe;
>> >> + return intel_dp->pps.pps_pipe;
>> >> }
>> >>
>> >> static int
>> >> @@ -211,10 +211,10 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp)
>> >> /* We should never land here with regular DP ports */
>> >> drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
>> >>
>> >> - if (!intel_dp->pps_reset)
>> >> + if (!intel_dp->pps.pps_reset)
>> >> return backlight_controller;
>> >>
>> >> - intel_dp->pps_reset = false;
>> >> + intel_dp->pps.pps_reset = false;
>> >>
>> >> /*
>> >> * Only the HW needs to be reprogrammed, the SW state is fixed and
>> >> @@ -280,19 +280,19 @@ vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
>> >>
>> >> /* try to find a pipe with this port selected */
>> >> /* first pick one where the panel is on */
>> >> - intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
>> >> - vlv_pipe_has_pp_on);
>> >> + intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
>> >> + vlv_pipe_has_pp_on);
>> >> /* didn't find one? pick one where vdd is on */
>> >> - if (intel_dp->pps_pipe == INVALID_PIPE)
>> >> - intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
>> >> - vlv_pipe_has_vdd_on);
>> >> + if (intel_dp->pps.pps_pipe == INVALID_PIPE)
>> >> + intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
>> >> + vlv_pipe_has_vdd_on);
>> >> /* didn't find one? pick one with just the correct port */
>> >> - if (intel_dp->pps_pipe == INVALID_PIPE)
>> >> - intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
>> >> - vlv_pipe_any);
>> >> + if (intel_dp->pps.pps_pipe == INVALID_PIPE)
>> >> + intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
>> >> + vlv_pipe_any);
>> >>
>> >> /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
>> >> - if (intel_dp->pps_pipe == INVALID_PIPE) {
>> >> + if (intel_dp->pps.pps_pipe == INVALID_PIPE) {
>> >> drm_dbg_kms(&dev_priv->drm,
>> >> "no initial power sequencer for [ENCODER:%d:%s]\n",
>> >> dig_port->base.base.base.id,
>> >> @@ -304,7 +304,7 @@ vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
>> >> "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n",
>> >> dig_port->base.base.base.id,
>> >> dig_port->base.base.name,
>> >> - pipe_name(intel_dp->pps_pipe));
>> >> + pipe_name(intel_dp->pps.pps_pipe));
>> >> }
>> >>
>> >> void intel_pps_reset_all(struct drm_i915_private *dev_priv)
>> >> @@ -331,15 +331,15 @@ void intel_pps_reset_all(struct drm_i915_private *dev_priv)
>> >> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>> >>
>> >> drm_WARN_ON(&dev_priv->drm,
>> >> - intel_dp->active_pipe != INVALID_PIPE);
>> >> + intel_dp->pps.active_pipe != INVALID_PIPE);
>> >>
>> >> if (encoder->type != INTEL_OUTPUT_EDP)
>> >> continue;
>> >>
>> >> if (IS_GEN9_LP(dev_priv))
>> >> - intel_dp->pps_reset = true;
>> >> + intel_dp->pps.pps_reset = true;
>> >> else
>> >> - intel_dp->pps_pipe = INVALID_PIPE;
>> >> + intel_dp->pps.pps_pipe = INVALID_PIPE;
>> >> }
>> >> }
>> >>
>> >> @@ -403,7 +403,7 @@ static bool edp_have_panel_power(struct intel_dp *intel_dp)
>> >> lockdep_assert_held(&dev_priv->pps_mutex);
>> >>
>> >> if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
>> >> - intel_dp->pps_pipe == INVALID_PIPE)
>> >> + intel_dp->pps.pps_pipe == INVALID_PIPE)
>> >> return false;
>> >>
>> >> return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON) != 0;
>> >> @@ -416,7 +416,7 @@ static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
>> >> lockdep_assert_held(&dev_priv->pps_mutex);
>> >>
>> >> if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
>> >> - intel_dp->pps_pipe == INVALID_PIPE)
>> >> + intel_dp->pps.pps_pipe == INVALID_PIPE)
>> >> return false;
>> >>
>> >> return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
>> >> @@ -506,13 +506,13 @@ static void wait_panel_power_cycle(struct intel_dp *intel_dp)
>> >> /* take the difference of currrent time and panel power off time
>> >> * and then make panel wait for t11_t12 if needed. */
>> >> panel_power_on_time = ktime_get_boottime();
>> >> - panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
>> >> + panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->pps.panel_power_off_time);
>> >>
>> >> /* When we disable the VDD override bit last we have to do the manual
>> >> * wait. */
>> >> - if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
>> >> + if (panel_power_off_duration < (s64)intel_dp->pps.panel_power_cycle_delay)
>> >> wait_remaining_ms_from_jiffies(jiffies,
>> >> - intel_dp->panel_power_cycle_delay - panel_power_off_duration);
>> >> + intel_dp->pps.panel_power_cycle_delay - panel_power_off_duration);
>> >>
>> >> wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
>> >> }
>> >> @@ -530,14 +530,14 @@ void intel_pps_wait_power_cycle(struct intel_dp *intel_dp)
>> >>
>> >> static void wait_backlight_on(struct intel_dp *intel_dp)
>> >> {
>> >> - wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
>> >> - intel_dp->backlight_on_delay);
>> >> + wait_remaining_ms_from_jiffies(intel_dp->pps.last_power_on,
>> >> + intel_dp->pps.backlight_on_delay);
>> >> }
>> >>
>> >> static void edp_wait_backlight_off(struct intel_dp *intel_dp)
>> >> {
>> >> - wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
>> >> - intel_dp->backlight_off_delay);
>> >> + wait_remaining_ms_from_jiffies(intel_dp->pps.last_backlight_off,
>> >> + intel_dp->pps.backlight_off_delay);
>> >> }
>> >>
>> >> /* Read the current pp_control value, unlocking the register if it
>> >> @@ -571,22 +571,22 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp)
>> >> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>> >> u32 pp;
>> >> i915_reg_t pp_stat_reg, pp_ctrl_reg;
>> >> - bool need_to_disable = !intel_dp->want_panel_vdd;
>> >> + bool need_to_disable = !intel_dp->pps.want_panel_vdd;
>> >>
>> >> lockdep_assert_held(&dev_priv->pps_mutex);
>> >>
>> >> if (!intel_dp_is_edp(intel_dp))
>> >> return false;
>> >>
>> >> - cancel_delayed_work(&intel_dp->panel_vdd_work);
>> >> - intel_dp->want_panel_vdd = true;
>> >> + cancel_delayed_work(&intel_dp->pps.panel_vdd_work);
>> >> + intel_dp->pps.want_panel_vdd = true;
>> >>
>> >> if (edp_have_panel_vdd(intel_dp))
>> >> return need_to_disable;
>> >>
>> >> - drm_WARN_ON(&dev_priv->drm, intel_dp->vdd_wakeref);
>> >> - intel_dp->vdd_wakeref = intel_display_power_get(dev_priv,
>> >> - intel_aux_power_domain(dig_port));
>> >> + drm_WARN_ON(&dev_priv->drm, intel_dp->pps.vdd_wakeref);
>> >> + intel_dp->pps.vdd_wakeref = intel_display_power_get(dev_priv,
>> >> + intel_aux_power_domain(dig_port));
>> >>
>> >> drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD on\n",
>> >> dig_port->base.base.base.id,
>> >> @@ -614,7 +614,7 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp)
>> >> "[ENCODER:%d:%s] panel power wasn't enabled\n",
>> >> dig_port->base.base.base.id,
>> >> dig_port->base.base.name);
>> >> - msleep(intel_dp->panel_power_up_delay);
>> >> + msleep(intel_dp->pps.panel_power_up_delay);
>> >> }
>> >>
>> >> return need_to_disable;
>> >> @@ -652,7 +652,7 @@ static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
>> >>
>> >> lockdep_assert_held(&dev_priv->pps_mutex);
>> >>
>> >> - drm_WARN_ON(&dev_priv->drm, intel_dp->want_panel_vdd);
>> >> + drm_WARN_ON(&dev_priv->drm, intel_dp->pps.want_panel_vdd);
>> >>
>> >> if (!edp_have_panel_vdd(intel_dp))
>> >> return;
>> >> @@ -676,11 +676,11 @@ static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
>> >> intel_de_read(dev_priv, pp_ctrl_reg));
>> >>
>> >> if ((pp & PANEL_POWER_ON) == 0)
>> >> - intel_dp->panel_power_off_time = ktime_get_boottime();
>> >> + intel_dp->pps.panel_power_off_time = ktime_get_boottime();
>> >>
>> >> intel_display_power_put(dev_priv,
>> >> intel_aux_power_domain(dig_port),
>> >> - fetch_and_zero(&intel_dp->vdd_wakeref));
>> >> + fetch_and_zero(&intel_dp->pps.vdd_wakeref));
>> >> }
>> >>
>> >> void intel_pps_vdd_off_sync(struct intel_dp *intel_dp)
>> >> @@ -690,7 +690,7 @@ void intel_pps_vdd_off_sync(struct intel_dp *intel_dp)
>> >> if (!intel_dp_is_edp(intel_dp))
>> >> return;
>> >>
>> >> - cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
>> >> + cancel_delayed_work_sync(&intel_dp->pps.panel_vdd_work);
>> >> /*
>> >> * vdd might still be enabled due to the delayed vdd off.
>> >> * Make sure vdd is actually turned off here.
>> >> @@ -701,13 +701,13 @@ void intel_pps_vdd_off_sync(struct intel_dp *intel_dp)
>> >>
>> >> static void edp_panel_vdd_work(struct work_struct *__work)
>> >> {
>> >> - struct intel_dp *intel_dp =
>> >> - container_of(to_delayed_work(__work),
>> >> - struct intel_dp, panel_vdd_work);
>> >> + struct intel_pps *pps = container_of(to_delayed_work(__work),
>> >> + struct intel_pps, panel_vdd_work);
>> >> + struct intel_dp *intel_dp = container_of(pps, struct intel_dp, pps);
>> >> intel_wakeref_t wakeref;
>> >>
>> >> with_intel_pps_lock(intel_dp, wakeref) {
>> >> - if (!intel_dp->want_panel_vdd)
>> >> + if (!intel_dp->pps.want_panel_vdd)
>> >> intel_pps_vdd_off_sync_unlocked(intel_dp);
>> >> }
>> >> }
>> >> @@ -721,8 +721,8 @@ static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
>> >> * down delay) to keep the panel power up across a sequence of
>> >> * operations.
>> >> */
>> >> - delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
>> >> - schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
>> >> + delay = msecs_to_jiffies(intel_dp->pps.panel_power_cycle_delay * 5);
>> >> + schedule_delayed_work(&intel_dp->pps.panel_vdd_work, delay);
>> >> }
>> >>
>> >> /*
>> >> @@ -739,11 +739,11 @@ void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync)
>> >> if (!intel_dp_is_edp(intel_dp))
>> >> return;
>> >>
>> >> - I915_STATE_WARN(!intel_dp->want_panel_vdd, "[ENCODER:%d:%s] VDD not forced on",
>> >> + I915_STATE_WARN(!intel_dp->pps.want_panel_vdd, "[ENCODER:%d:%s] VDD not forced on",
>> >> dp_to_dig_port(intel_dp)->base.base.base.id,
>> >> dp_to_dig_port(intel_dp)->base.base.name);
>> >>
>> >> - intel_dp->want_panel_vdd = false;
>> >> + intel_dp->pps.want_panel_vdd = false;
>> >>
>> >> if (sync)
>> >> intel_pps_vdd_off_sync_unlocked(intel_dp);
>> >> @@ -791,7 +791,7 @@ void intel_pps_on_unlocked(struct intel_dp *intel_dp)
>> >> intel_de_posting_read(dev_priv, pp_ctrl_reg);
>> >>
>> >> wait_panel_on(intel_dp);
>> >> - intel_dp->last_power_on = jiffies;
>> >> + intel_dp->pps.last_power_on = jiffies;
>> >>
>> >> if (IS_GEN(dev_priv, 5)) {
>> >> pp |= PANEL_POWER_RESET; /* restore panel reset bit */
>> >> @@ -826,7 +826,7 @@ void intel_pps_off_unlocked(struct intel_dp *intel_dp)
>> >> drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power off\n",
>> >> dig_port->base.base.base.id, dig_port->base.base.name);
>> >>
>> >> - drm_WARN(&dev_priv->drm, !intel_dp->want_panel_vdd,
>> >> + drm_WARN(&dev_priv->drm, !intel_dp->pps.want_panel_vdd,
>> >> "Need [ENCODER:%d:%s] VDD to turn off panel\n",
>> >> dig_port->base.base.base.id, dig_port->base.base.name);
>> >>
>> >> @@ -838,18 +838,18 @@ void intel_pps_off_unlocked(struct intel_dp *intel_dp)
>> >>
>> >> pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
>> >>
>> >> - intel_dp->want_panel_vdd = false;
>> >> + intel_dp->pps.want_panel_vdd = false;
>> >>
>> >> intel_de_write(dev_priv, pp_ctrl_reg, pp);
>> >> intel_de_posting_read(dev_priv, pp_ctrl_reg);
>> >>
>> >> wait_panel_off(intel_dp);
>> >> - intel_dp->panel_power_off_time = ktime_get_boottime();
>> >> + intel_dp->pps.panel_power_off_time = ktime_get_boottime();
>> >>
>> >> /* We got a reference when we enabled the VDD. */
>> >> intel_display_power_put(dev_priv,
>> >> intel_aux_power_domain(dig_port),
>> >> - fetch_and_zero(&intel_dp->vdd_wakeref));
>> >> + fetch_and_zero(&intel_dp->pps.vdd_wakeref));
>> >> }
>> >>
>> >> void intel_pps_off(struct intel_dp *intel_dp)
>> >> @@ -909,7 +909,7 @@ void intel_pps_backlight_off(struct intel_dp *intel_dp)
>> >> intel_de_posting_read(dev_priv, pp_ctrl_reg);
>> >> }
>> >>
>> >> - intel_dp->last_backlight_off = jiffies;
>> >> + intel_dp->pps.last_backlight_off = jiffies;
>> >> edp_wait_backlight_off(intel_dp);
>> >> }
>> >>
>> >> @@ -943,10 +943,10 @@ static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
>> >> {
>> >> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>> >> struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
>> >> - enum pipe pipe = intel_dp->pps_pipe;
>> >> + enum pipe pipe = intel_dp->pps.pps_pipe;
>> >> i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
>> >>
>> >> - drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE);
>> >> + drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE);
>> >>
>> >> if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B))
>> >> return;
>> >> @@ -969,7 +969,7 @@ static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
>> >> intel_de_write(dev_priv, pp_on_reg, 0);
>> >> intel_de_posting_read(dev_priv, pp_on_reg);
>> >>
>> >> - intel_dp->pps_pipe = INVALID_PIPE;
>> >> + intel_dp->pps.pps_pipe = INVALID_PIPE;
>> >> }
>> >>
>> >> static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
>> >> @@ -982,12 +982,12 @@ static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
>> >> for_each_intel_dp(&dev_priv->drm, encoder) {
>> >> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>> >>
>> >> - drm_WARN(&dev_priv->drm, intel_dp->active_pipe == pipe,
>> >> + drm_WARN(&dev_priv->drm, intel_dp->pps.active_pipe == pipe,
>> >> "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n",
>> >> pipe_name(pipe), encoder->base.base.id,
>> >> encoder->base.name);
>> >>
>> >> - if (intel_dp->pps_pipe != pipe)
>> >> + if (intel_dp->pps.pps_pipe != pipe)
>> >> continue;
>> >>
>> >> drm_dbg_kms(&dev_priv->drm,
>> >> @@ -1009,10 +1009,10 @@ void vlv_pps_init(struct intel_encoder *encoder,
>> >>
>> >> lockdep_assert_held(&dev_priv->pps_mutex);
>> >>
>> >> - drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE);
>> >> + drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE);
>> >>
>> >> - if (intel_dp->pps_pipe != INVALID_PIPE &&
>> >> - intel_dp->pps_pipe != crtc->pipe) {
>> >> + if (intel_dp->pps.pps_pipe != INVALID_PIPE &&
>> >> + intel_dp->pps.pps_pipe != crtc->pipe) {
>> >> /*
>> >> * If another power sequencer was being used on this
>> >> * port previously make sure to turn off vdd there while
>> >> @@ -1027,17 +1027,17 @@ void vlv_pps_init(struct intel_encoder *encoder,
>> >> */
>> >> vlv_steal_power_sequencer(dev_priv, crtc->pipe);
>> >>
>> >> - intel_dp->active_pipe = crtc->pipe;
>> >> + intel_dp->pps.active_pipe = crtc->pipe;
>> >>
>> >> if (!intel_dp_is_edp(intel_dp))
>> >> return;
>> >>
>> >> /* now it's all ours */
>> >> - intel_dp->pps_pipe = crtc->pipe;
>> >> + intel_dp->pps.pps_pipe = crtc->pipe;
>> >>
>> >> drm_dbg_kms(&dev_priv->drm,
>> >> "initializing pipe %c power sequencer for [ENCODER:%d:%s]\n",
>> >> - pipe_name(intel_dp->pps_pipe), encoder->base.base.id,
>> >> + pipe_name(intel_dp->pps.pps_pipe), encoder->base.base.id,
>> >> encoder->base.name);
>> >>
>> >> /* init power sequencer on this pipe and port */
>> >> @@ -1063,9 +1063,9 @@ static void intel_pps_vdd_sanitize(struct intel_dp *intel_dp)
>> >> */
>> >> drm_dbg_kms(&dev_priv->drm,
>> >> "VDD left on by BIOS, adjusting state tracking\n");
>> >> - drm_WARN_ON(&dev_priv->drm, intel_dp->vdd_wakeref);
>> >> - intel_dp->vdd_wakeref = intel_display_power_get(dev_priv,
>> >> - intel_aux_power_domain(dig_port));
>> >> + drm_WARN_ON(&dev_priv->drm, intel_dp->pps.vdd_wakeref);
>> >> + intel_dp->pps.vdd_wakeref = intel_display_power_get(dev_priv,
>> >> + intel_aux_power_domain(dig_port));
>> >>
>> >> edp_panel_vdd_schedule_off(intel_dp);
>> >> }
>> >> @@ -1085,9 +1085,9 @@ bool intel_pps_have_power(struct intel_dp *intel_dp)
>> >>
>> >> static void pps_init_timestamps(struct intel_dp *intel_dp)
>> >> {
>> >> - intel_dp->panel_power_off_time = ktime_get_boottime();
>> >> - intel_dp->last_power_on = jiffies;
>> >> - intel_dp->last_backlight_off = jiffies;
>> >> + intel_dp->pps.panel_power_off_time = ktime_get_boottime();
>> >> + intel_dp->pps.last_power_on = jiffies;
>> >> + intel_dp->pps.last_backlight_off = jiffies;
>> >> }
>> >>
>> >> static void
>> >> @@ -1137,7 +1137,7 @@ static void
>> >> intel_pps_verify_state(struct intel_dp *intel_dp)
>> >> {
>> >> struct edp_power_seq hw;
>> >> - struct edp_power_seq *sw = &intel_dp->pps_delays;
>> >> + struct edp_power_seq *sw = &intel_dp->pps.pps_delays;
>> >>
>> >> intel_pps_readout_hw_state(intel_dp, &hw);
>> >>
>> >> @@ -1153,7 +1153,7 @@ static void pps_init_delays(struct intel_dp *intel_dp)
>> >> {
>> >> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>> >> struct edp_power_seq cur, vbt, spec,
>> >> - *final = &intel_dp->pps_delays;
>> >> + *final = &intel_dp->pps.pps_delays;
>> >>
>> >> lockdep_assert_held(&dev_priv->pps_mutex);
>> >>
>> >> @@ -1210,22 +1210,22 @@ static void pps_init_delays(struct intel_dp *intel_dp)
>> >> #undef assign_final
>> >>
>> >> #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
>> >> - intel_dp->panel_power_up_delay = get_delay(t1_t3);
>> >> - intel_dp->backlight_on_delay = get_delay(t8);
>> >> - intel_dp->backlight_off_delay = get_delay(t9);
>> >> - intel_dp->panel_power_down_delay = get_delay(t10);
>> >> - intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
>> >> + intel_dp->pps.panel_power_up_delay = get_delay(t1_t3);
>> >> + intel_dp->pps.backlight_on_delay = get_delay(t8);
>> >> + intel_dp->pps.backlight_off_delay = get_delay(t9);
>> >> + intel_dp->pps.panel_power_down_delay = get_delay(t10);
>> >> + intel_dp->pps.panel_power_cycle_delay = get_delay(t11_t12);
>> >> #undef get_delay
>> >>
>> >> drm_dbg_kms(&dev_priv->drm,
>> >> "panel power up delay %d, power down delay %d, power cycle delay %d\n",
>> >> - intel_dp->panel_power_up_delay,
>> >> - intel_dp->panel_power_down_delay,
>> >> - intel_dp->panel_power_cycle_delay);
>> >> + intel_dp->pps.panel_power_up_delay,
>> >> + intel_dp->pps.panel_power_down_delay,
>> >> + intel_dp->pps.panel_power_cycle_delay);
>> >>
>> >> drm_dbg_kms(&dev_priv->drm, "backlight on delay %d, off delay %d\n",
>> >> - intel_dp->backlight_on_delay,
>> >> - intel_dp->backlight_off_delay);
>> >> + intel_dp->pps.backlight_on_delay,
>> >> + intel_dp->pps.backlight_off_delay);
>> >>
>> >> /*
>> >> * We override the HW backlight delays to 1 because we do manual waits
>> >> @@ -1251,7 +1251,7 @@ static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd
>> >> int div = RUNTIME_INFO(dev_priv)->rawclk_freq / 1000;
>> >> struct pps_registers regs;
>> >> enum port port = dp_to_dig_port(intel_dp)->base.port;
>> >> - const struct edp_power_seq *seq = &intel_dp->pps_delays;
>> >> + const struct edp_power_seq *seq = &intel_dp->pps.pps_delays;
>> >>
>> >> lockdep_assert_held(&dev_priv->pps_mutex);
>> >>
>> >> @@ -1364,7 +1364,7 @@ void intel_pps_encoder_reset(struct intel_dp *intel_dp)
>> >>
>> >> void intel_pps_init(struct intel_dp *intel_dp)
>> >> {
>> >> - INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work);
>> >> + INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work);
>> >>
>> >> pps_init_timestamps(intel_dp);
>> >>
>> >> --
>> >> 2.20.1
>> >>
>> >> _______________________________________________
>> >> Intel-gfx mailing list
>> >> Intel-gfx@lists.freedesktop.org
>> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>
>> --
>> Jani Nikula, Intel Open Source Graphics Center
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2021-01-21 11:48 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-01-20 10:18 [Intel-gfx] [PATCH 1/4] drm/i915/pps: refactor init abstractions Jani Nikula
2021-01-20 10:18 ` [Intel-gfx] [PATCH 2/4] drm/i915/pps: move pps code over from intel_display.c and refactor Jani Nikula
2021-01-20 10:18 ` [Intel-gfx] [PATCH 3/4] drm/i915/dp: abstract struct intel_dp pps members to a sub-struct Jani Nikula
2021-01-20 17:30 ` Rodrigo Vivi
2021-01-20 19:25 ` Jani Nikula
2021-01-20 20:08 ` Rodrigo Vivi
2021-01-21 11:47 ` Jani Nikula
2021-01-20 10:18 ` [Intel-gfx] [PATCH 4/4] drm/i915/dp: split out aux functionality to intel_dp_aux.c Jani Nikula
2021-01-20 17:31 ` Rodrigo Vivi
2021-01-20 14:17 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915/pps: refactor init abstractions Patchwork
2021-01-20 14:19 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-01-20 14:46 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-01-20 16:08 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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