[Intel-gfx] linux-next: manual merge of the drm-intel tree with the drm tree

[Intel-gfx] linux-next: manual merge of the drm-intel tree with the drm tree

[Stephen Rothwell]

[-- Attachment #1.1: Type: text/plain, Size: 1315 bytes --]

Hi all,

Today's linux-next merge of the drm-intel tree got a conflict in:

  drivers/gpu/drm/i915/gem/i915_gem_object.h

between commit:

  41a9c75d0acf ("drm/i915/gem: Move stolen node into GEM object union")

from the drm tree and commit:

  5fbc2c2bfa5c ("drm/i915/gem: Add a helper to read data from a GEM object page")

from the drm-intel tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

-- 
Cheers,
Stephen Rothwell

diff --cc drivers/gpu/drm/i915/gem/i915_gem_object.h
index 5274e9d139b4,ae83737f1d48..000000000000
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@@ -548,6 -546,6 +554,8 @@@ i915_gem_object_invalidate_frontbuffer(
  		__i915_gem_object_invalidate_frontbuffer(obj, origin);
  }
  
 +bool i915_gem_object_is_shmem(const struct drm_i915_gem_object *obj);
 +
+ int i915_gem_object_read_from_page(struct drm_i915_gem_object *obj, u64 offset, void *dst, int size);
+ 
  #endif

[-- Attachment #1.2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] linux-next: manual merge of the drm-intel tree with the drm tree

[Stephen Rothwell]

[-- Attachment #1: Type: text/plain, Size: 3060 bytes --]

Hi all,

Today's linux-next merge of the drm-intel tree got a conflict in:

  drivers/gpu/drm/i915/i915_drv.h

between commits:

  c9517783060a ("drm/i915/dg2: Drop Wa_16011777198")
  5a213086a025 ("drm/i915: Eliminate IS_MTL_GRAPHICS_STEP")
  81af8abe6513 ("drm/i915: Eliminate IS_MTL_MEDIA_STEP")

from the drm tree and commits:

  e50086f3d313 ("drm/i915/dg2: Drop pre-production display workarounds")
  213454b3af2e ("drm/i915: Eliminate IS_MTL_DISPLAY_STEP")

from the drm-intel tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

-- 
Cheers,
Stephen Rothwell

diff --cc drivers/gpu/drm/i915/i915_drv.h
index e994bd2d69db,cc229f08dfdb..000000000000
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@@ -647,21 -653,33 +649,6 @@@ IS_SUBPLATFORM(const struct drm_i915_pr
  #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
  	(IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
  
- #define IS_MTL_DISPLAY_STEP(__i915, since, until) \
 -#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
 -	(IS_SUBPLATFORM(__i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_##variant) && \
 -	 IS_GRAPHICS_STEP(__i915, since, until))
 -
 -#define IS_MTL_MEDIA_STEP(__i915, since, until) \
--	(IS_METEORLAKE(__i915) && \
- 	 IS_DISPLAY_STEP(__i915, since, until))
 -	 IS_MEDIA_STEP(__i915, since, until))
--
- #define IS_DG2_DISPLAY_STEP(__i915, since, until) \
- 	(IS_DG2(__i915) && \
- 	 IS_DISPLAY_STEP(__i915, since, until))
 -/*
 - * DG2 hardware steppings are a bit unusual.  The hardware design was forked to
 - * create three variants (G10, G11, and G12) which each have distinct
 - * workaround sets.  The G11 and G12 forks of the DG2 design reset the GT
 - * stepping back to "A0" for their first iterations, even though they're more
 - * similar to a G10 B0 stepping and G10 C0 stepping respectively in terms of
 - * functionality and workarounds.  However the display stepping does not reset
 - * in the same manner --- a specific stepping like "B0" has a consistent
 - * meaning regardless of whether it belongs to a G10, G11, or G12 DG2.
 - *
 - * TLDR:  All GT workarounds and stepping-specific logic must be applied in
 - * relation to a specific subplatform (G10/G11/G12), whereas display workarounds
 - * and stepping-specific logic will be applied with a general DG2-wide stepping
 - * number.
 - */
 -#define IS_DG2_GRAPHICS_STEP(__i915, variant, since, until) \
 -	(IS_SUBPLATFORM(__i915, INTEL_DG2, INTEL_SUBPLATFORM_##variant) && \
 -	 IS_GRAPHICS_STEP(__i915, since, until))
--
  #define IS_PVC_BD_STEP(__i915, since, until) \
  	(IS_PONTEVECCHIO(__i915) && \
  	 IS_BASEDIE_STEP(__i915, since, until))

[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

Re: [Intel-gfx] linux-next: manual merge of the drm-intel tree with the drm tree

[Stephen Rothwell]

[-- Attachment #1: Type: text/plain, Size: 1495 bytes --]

Hi all,

On Tue, 30 May 2023 11:57:52 +1000 Stephen Rothwell <sfr@canb.auug.org.au> wrote:
>
> @@@ -920,33 -587,8 +640,9 @@@ static const struct intel_device_info j
>   #define GEN12_FEATURES \
>   	GEN11_FEATURES, \
>   	GEN(12), \
> - 	.display.abox_mask = GENMASK(2, 1), \
> - 	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
> - 	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> - 		BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
> - 		BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
> - 	.display.pipe_offsets = { \
> - 		[TRANSCODER_A] = PIPE_A_OFFSET, \
> - 		[TRANSCODER_B] = PIPE_B_OFFSET, \
> - 		[TRANSCODER_C] = PIPE_C_OFFSET, \
> - 		[TRANSCODER_D] = PIPE_D_OFFSET, \
> - 		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
> - 		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
> - 	}, \
> - 	.display.trans_offsets = { \
> - 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> - 		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> - 		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
> - 		[TRANSCODER_D] = TRANSCODER_D_OFFSET, \
> - 		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
> - 		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
> - 	}, \
> - 	TGL_CURSOR_OFFSETS, \
> - 	TGL_CACHELEVEL, \
> ++	.max_pat_index = 3 \

I fixed the above up to have a ',' after the '3'

>   	.has_global_mocs = 1, \
> - 	.has_pxp = 1, \
> - 	.display.has_dsb = 1, \
> - 	.max_pat_index = 3
> + 	.has_pxp = 1
-- 
Cheers,
Stephen Rothwell

[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

[Intel-gfx] linux-next: manual merge of the drm-intel tree with the drm tree

[Stephen Rothwell]

[-- Attachment #1: Type: text/plain, Size: 12447 bytes --]

Hi all,

Today's linux-next merge of the drm-intel tree got a conflict in:

  drivers/gpu/drm/i915/i915_drv.h

between commit:

  66ca1d8f222b ("drm/i915/i915_drv: Use i915 instead of dev_priv insied the file_priv structure")

from the drm tree and commits:

  5af5169d7582 ("drm/i915: Convert INTEL_INFO()->display to a pointer")
  18e0deeed8c8 ("drm/i915/display: Move display runtime info to display structure")
  95c08508e237 ("drm/i915/display: Move feature test macros to intel_display_device.h")

from the drm-intel tree.

I fixed it up (see below) and can carry the fix as necessary. This is
now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your
tree is submitted for merging.  You may also want to consider
cooperating with the maintainer of the conflicting tree to minimise any
particularly complex conflicts.

-- 
Cheers,
Stephen Rothwell

diff --cc drivers/gpu/drm/i915/i915_drv.h
index f23b030aaf09,e9c403def9c9..000000000000
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@@ -407,11 -408,13 +408,13 @@@ static inline struct intel_gt *to_gt(st
  	     (engine__) && (engine__)->uabi_class == (class__); \
  	     (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
  
 -#define INTEL_INFO(dev_priv)	(&(dev_priv)->__info)
 +#define INTEL_INFO(i915)	(&(i915)->__info)
+ #define DISPLAY_INFO(i915)	(INTEL_INFO(i915)->display)
 -#define RUNTIME_INFO(dev_priv)	(&(dev_priv)->__runtime)
 +#define RUNTIME_INFO(i915)	(&(i915)->__runtime)
+ #define DISPLAY_RUNTIME_INFO(i915)	(&(i915)->__display_runtime)
 -#define DRIVER_CAPS(dev_priv)	(&(dev_priv)->caps)
 +#define DRIVER_CAPS(i915)	(&(i915)->caps)
  
 -#define INTEL_DEVID(dev_priv)	(RUNTIME_INFO(dev_priv)->device_id)
 +#define INTEL_DEVID(i915)	(RUNTIME_INFO(i915)->device_id)
  
  #define IP_VER(ver, rel)		((ver) << 8 | (rel))
  
@@@ -753,125 -756,82 +756,82 @@@ IS_SUBPLATFORM(const struct drm_i915_pr
   * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
   * All later gens can run the final buffer from the ppgtt
   */
 -#define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
 +#define CMDPARSER_USES_GGTT(i915) (GRAPHICS_VER(i915) == 7)
  
 -#define HAS_LLC(dev_priv)	(INTEL_INFO(dev_priv)->has_llc)
 -#define HAS_4TILE(dev_priv)	(INTEL_INFO(dev_priv)->has_4tile)
 -#define HAS_SNOOP(dev_priv)	(INTEL_INFO(dev_priv)->has_snoop)
 -#define HAS_EDRAM(dev_priv)	((dev_priv)->edram_size_mb)
 -#define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
 -#define HAS_WT(dev_priv)	HAS_EDRAM(dev_priv)
 +#define HAS_LLC(i915)	(INTEL_INFO(i915)->has_llc)
 +#define HAS_4TILE(i915)	(INTEL_INFO(i915)->has_4tile)
 +#define HAS_SNOOP(i915)	(INTEL_INFO(i915)->has_snoop)
 +#define HAS_EDRAM(i915)	((i915)->edram_size_mb)
 +#define HAS_SECURE_BATCHES(i915) (GRAPHICS_VER(i915) < 6)
 +#define HAS_WT(i915)	HAS_EDRAM(i915)
  
 -#define HWS_NEEDS_PHYSICAL(dev_priv)	(INTEL_INFO(dev_priv)->hws_needs_physical)
 +#define HWS_NEEDS_PHYSICAL(i915)	(INTEL_INFO(i915)->hws_needs_physical)
  
 -#define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
 -		(INTEL_INFO(dev_priv)->has_logical_ring_contexts)
 -#define HAS_LOGICAL_RING_ELSQ(dev_priv) \
 -		(INTEL_INFO(dev_priv)->has_logical_ring_elsq)
 +#define HAS_LOGICAL_RING_CONTEXTS(i915) \
 +		(INTEL_INFO(i915)->has_logical_ring_contexts)
 +#define HAS_LOGICAL_RING_ELSQ(i915) \
 +		(INTEL_INFO(i915)->has_logical_ring_elsq)
  
 -#define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
 +#define HAS_EXECLISTS(i915) HAS_LOGICAL_RING_CONTEXTS(i915)
  
 -#define INTEL_PPGTT(dev_priv) (RUNTIME_INFO(dev_priv)->ppgtt_type)
 -#define HAS_PPGTT(dev_priv) \
 -	(INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
 -#define HAS_FULL_PPGTT(dev_priv) \
 -	(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
 +#define INTEL_PPGTT(i915) (RUNTIME_INFO(i915)->ppgtt_type)
 +#define HAS_PPGTT(i915) \
 +	(INTEL_PPGTT(i915) != INTEL_PPGTT_NONE)
 +#define HAS_FULL_PPGTT(i915) \
 +	(INTEL_PPGTT(i915) >= INTEL_PPGTT_FULL)
  
 -#define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
 +#define HAS_PAGE_SIZES(i915, sizes) ({ \
  	GEM_BUG_ON((sizes) == 0); \
 -	((sizes) & ~RUNTIME_INFO(dev_priv)->page_sizes) == 0; \
 +	((sizes) & ~RUNTIME_INFO(i915)->page_sizes) == 0; \
  })
  
- #define HAS_OVERLAY(i915)		 (INTEL_INFO(i915)->display.has_overlay)
- #define OVERLAY_NEEDS_PHYSICAL(i915) \
- 		(INTEL_INFO(i915)->display.overlay_needs_physical)
- 
  /* Early gen2 have a totally busted CS tlb and require pinned batches. */
 -#define HAS_BROKEN_CS_TLB(dev_priv)	(IS_I830(dev_priv) || IS_I845G(dev_priv))
 +#define HAS_BROKEN_CS_TLB(i915)	(IS_I830(i915) || IS_I845G(i915))
  
 -#define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv)	\
 -	(IS_BROADWELL(dev_priv) || GRAPHICS_VER(dev_priv) == 9)
 +#define NEEDS_RC6_CTX_CORRUPTION_WA(i915)	\
 +	(IS_BROADWELL(i915) || GRAPHICS_VER(i915) == 9)
  
  /* WaRsDisableCoarsePowerGating:skl,cnl */
 -#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv)			\
 -	(IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
 +#define NEEDS_WaRsDisableCoarsePowerGating(i915)			\
 +	(IS_SKL_GT3(i915) || IS_SKL_GT4(i915))
  
- #define HAS_GMBUS_IRQ(i915) (DISPLAY_VER(i915) >= 4)
- #define HAS_GMBUS_BURST_READ(i915) (DISPLAY_VER(i915) >= 11 || \
- 					IS_GEMINILAKE(i915) || \
- 					IS_KABYLAKE(i915))
- 
  /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
   * rows, which changed the alignment requirements and fence programming.
   */
 -#define HAS_128_BYTE_Y_TILING(dev_priv) (GRAPHICS_VER(dev_priv) != 2 && \
 -					 !(IS_I915G(dev_priv) || IS_I915GM(dev_priv)))
 +#define HAS_128_BYTE_Y_TILING(i915) (GRAPHICS_VER(i915) != 2 && \
 +					 !(IS_I915G(i915) || IS_I915GM(i915)))
- #define SUPPORTS_TV(i915)		(INTEL_INFO(i915)->display.supports_tv)
- #define I915_HAS_HOTPLUG(i915)	(INTEL_INFO(i915)->display.has_hotplug)
  
- #define HAS_FW_BLC(i915)	(DISPLAY_VER(i915) > 2)
- #define HAS_FBC(i915)	(RUNTIME_INFO(i915)->fbc_mask != 0)
- #define HAS_CUR_FBC(i915)	(!HAS_GMCH(i915) && DISPLAY_VER(i915) >= 7)
- 
- #define HAS_DPT(i915)	(DISPLAY_VER(i915) >= 13)
- 
- #define HAS_IPS(i915)	(IS_HSW_ULT(i915) || IS_BROADWELL(i915))
- 
- #define HAS_DP_MST(i915)	(INTEL_INFO(i915)->display.has_dp_mst)
- #define HAS_DP20(i915)	(IS_DG2(i915) || DISPLAY_VER(i915) >= 14)
- 
- #define HAS_DOUBLE_BUFFERED_M_N(i915)	(DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915))
- 
- #define HAS_CDCLK_CRAWL(i915)	 (INTEL_INFO(i915)->display.has_cdclk_crawl)
- #define HAS_CDCLK_SQUASH(i915)	 (INTEL_INFO(i915)->display.has_cdclk_squash)
- #define HAS_DDI(i915)		 (INTEL_INFO(i915)->display.has_ddi)
- #define HAS_FPGA_DBG_UNCLAIMED(i915) (INTEL_INFO(i915)->display.has_fpga_dbg)
- #define HAS_PSR(i915)		 (INTEL_INFO(i915)->display.has_psr)
- #define HAS_PSR_HW_TRACKING(i915) \
- 	(INTEL_INFO(i915)->display.has_psr_hw_tracking)
- #define HAS_PSR2_SEL_FETCH(i915)	 (DISPLAY_VER(i915) >= 12)
- #define HAS_TRANSCODER(i915, trans)	 ((RUNTIME_INFO(i915)->cpu_transcoder_mask & BIT(trans)) != 0)
  
 -#define HAS_RC6(dev_priv)		 (INTEL_INFO(dev_priv)->has_rc6)
 -#define HAS_RC6p(dev_priv)		 (INTEL_INFO(dev_priv)->has_rc6p)
 -#define HAS_RC6pp(dev_priv)		 (false) /* HW was never validated */
 +#define HAS_RC6(i915)		 (INTEL_INFO(i915)->has_rc6)
 +#define HAS_RC6p(i915)		 (INTEL_INFO(i915)->has_rc6p)
 +#define HAS_RC6pp(i915)		 (false) /* HW was never validated */
  
 -#define HAS_RPS(dev_priv)	(INTEL_INFO(dev_priv)->has_rps)
 +#define HAS_RPS(i915)	(INTEL_INFO(i915)->has_rps)
  
- #define HAS_DMC(i915)	(RUNTIME_INFO(i915)->has_dmc)
- #define HAS_DSB(i915)	(INTEL_INFO(i915)->display.has_dsb)
- #define HAS_DSC(__i915)		(RUNTIME_INFO(__i915)->has_dsc)
- #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
- 
 -#define HAS_HECI_PXP(dev_priv) \
 -	(INTEL_INFO(dev_priv)->has_heci_pxp)
 +#define HAS_HECI_PXP(i915) \
 +	(INTEL_INFO(i915)->has_heci_pxp)
  
 -#define HAS_HECI_GSCFI(dev_priv) \
 -	(INTEL_INFO(dev_priv)->has_heci_gscfi)
 +#define HAS_HECI_GSCFI(i915) \
 +	(INTEL_INFO(i915)->has_heci_gscfi)
  
 -#define HAS_HECI_GSC(dev_priv) (HAS_HECI_PXP(dev_priv) || HAS_HECI_GSCFI(dev_priv))
 +#define HAS_HECI_GSC(i915) (HAS_HECI_PXP(i915) || HAS_HECI_GSCFI(i915))
  
- #define HAS_MSO(i915)		(DISPLAY_VER(i915) >= 12)
- 
 -#define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
 -#define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
 +#define HAS_RUNTIME_PM(i915) (INTEL_INFO(i915)->has_runtime_pm)
 +#define HAS_64BIT_RELOC(i915) (INTEL_INFO(i915)->has_64bit_reloc)
  
 -#define HAS_OA_BPC_REPORTING(dev_priv) \
 -	(INTEL_INFO(dev_priv)->has_oa_bpc_reporting)
 -#define HAS_OA_SLICE_CONTRIB_LIMITS(dev_priv) \
 -	(INTEL_INFO(dev_priv)->has_oa_slice_contrib_limits)
 -#define HAS_OAM(dev_priv) \
 -	(INTEL_INFO(dev_priv)->has_oam)
 +#define HAS_OA_BPC_REPORTING(i915) \
 +	(INTEL_INFO(i915)->has_oa_bpc_reporting)
 +#define HAS_OA_SLICE_CONTRIB_LIMITS(i915) \
 +	(INTEL_INFO(i915)->has_oa_slice_contrib_limits)
 +#define HAS_OAM(i915) \
 +	(INTEL_INFO(i915)->has_oam)
  
  /*
   * Set this flag, when platform requires 64K GTT page sizes or larger for
   * device local memory access.
   */
 -#define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)
 +#define HAS_64K_PAGES(i915) (INTEL_INFO(i915)->has_64k_pages)
  
- #define HAS_IPC(i915)		(INTEL_INFO(i915)->display.has_ipc)
- #define HAS_SAGV(i915)		(DISPLAY_VER(i915) >= 9 && !IS_LP(i915))
- 
  #define HAS_REGION(i915, i) (RUNTIME_INFO(i915)->memory_regions & (i))
  #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
  
@@@ -881,49 -841,32 +841,32 @@@
   * Platform has the dedicated compression control state for each lmem surfaces
   * stored in lmem to support the 3D and media compression formats.
   */
 -#define HAS_FLAT_CCS(dev_priv)   (INTEL_INFO(dev_priv)->has_flat_ccs)
 +#define HAS_FLAT_CCS(i915)   (INTEL_INFO(i915)->has_flat_ccs)
  
 -#define HAS_GT_UC(dev_priv)	(INTEL_INFO(dev_priv)->has_gt_uc)
 +#define HAS_GT_UC(i915)	(INTEL_INFO(i915)->has_gt_uc)
  
 -#define HAS_POOLED_EU(dev_priv)	(RUNTIME_INFO(dev_priv)->has_pooled_eu)
 +#define HAS_POOLED_EU(i915)	(RUNTIME_INFO(i915)->has_pooled_eu)
  
 -#define HAS_GLOBAL_MOCS_REGISTERS(dev_priv)	(INTEL_INFO(dev_priv)->has_global_mocs)
 +#define HAS_GLOBAL_MOCS_REGISTERS(i915)	(INTEL_INFO(i915)->has_global_mocs)
  
- #define HAS_GMCH(i915) (INTEL_INFO(i915)->display.has_gmch)
- 
  #define HAS_GMD_ID(i915)	(INTEL_INFO(i915)->has_gmd_id)
  
- #define HAS_LSPCON(i915) (IS_DISPLAY_VER(i915, 9, 10))
- 
  #define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
  
  /* DPF == dynamic parity feature */
 -#define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
 -#define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
 -				 2 : HAS_L3_DPF(dev_priv))
 +#define HAS_L3_DPF(i915) (INTEL_INFO(i915)->has_l3_dpf)
 +#define NUM_L3_SLICES(i915) (IS_HSW_GT3(i915) ? \
 +				 2 : HAS_L3_DPF(i915))
  
- #define INTEL_NUM_PIPES(i915) (hweight8(RUNTIME_INFO(i915)->pipe_mask))
- 
- #define HAS_DISPLAY(i915) (RUNTIME_INFO(i915)->pipe_mask != 0)
- 
- #define HAS_VRR(i915)	(DISPLAY_VER(i915) >= 11)
- 
- #define HAS_ASYNC_FLIPS(i915)		(DISPLAY_VER(i915) >= 5)
- 
  /* Only valid when HAS_DISPLAY() is true */
 -#define INTEL_DISPLAY_ENABLED(dev_priv) \
 -	(drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)),		\
 -	 !(dev_priv)->params.disable_display &&				\
 -	 !intel_opregion_headless_sku(dev_priv))
 +#define INTEL_DISPLAY_ENABLED(i915) \
 +	(drm_WARN_ON(&(i915)->drm, !HAS_DISPLAY(i915)),		\
 +	 !(i915)->params.disable_display &&				\
 +	 !intel_opregion_headless_sku(i915))
  
 -#define HAS_GUC_DEPRIVILEGE(dev_priv) \
 -	(INTEL_INFO(dev_priv)->has_guc_deprivilege)
 +#define HAS_GUC_DEPRIVILEGE(i915) \
 +	(INTEL_INFO(i915)->has_guc_deprivilege)
  
- #define HAS_D12_PLANE_MINIMIZATION(i915) (IS_ROCKETLAKE(i915) || \
- 					      IS_ALDERLAKE_S(i915))
- 
- #define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
- 
  #define HAS_3D_PIPELINE(i915)	(INTEL_INFO(i915)->has_3d_pipeline)
  
  #define HAS_ONE_EU_PER_FUSE_BIT(i915)	(INTEL_INFO(i915)->has_one_eu_per_fuse_bit)

[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

[Intel-gfx] linux-next: manual merge of the drm-intel tree with the drm tree

[Stephen Rothwell]

[-- Attachment #1: Type: text/plain, Size: 13039 bytes --]

Hi all,

Today's linux-next merge of the drm-intel tree got a conflict in:

  drivers/gpu/drm/i915/i915_pci.c

between commit:

  5e352e32aec2 ("drm/i915: preparation for using PAT index")

from the drm tree and commits:

  5af5169d7582 ("drm/i915: Convert INTEL_INFO()->display to a pointer")
  18e0deeed8c8 ("drm/i915/display: Move display runtime info to display structure")

from the drm-intel tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

-- 
Cheers,
Stephen Rothwell

diff --cc drivers/gpu/drm/i915/i915_pci.c
index 75cbccd1a441,34bc732a6375..000000000000
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@@ -27,9 -27,9 +27,10 @@@
  #include <drm/i915_pciids.h>
  
  #include "display/intel_display.h"
+ #include "display/intel_display_driver.h"
  #include "gt/intel_gt_regs.h"
  #include "gt/intel_sa_media.h"
 +#include "gem/i915_gem_object_types.h"
  
  #include "i915_driver.h"
  #include "i915_drv.h"
@@@ -40,162 -40,8 +41,40 @@@
  #define PLATFORM(x) .platform = (x)
  #define GEN(x) \
  	.__runtime.graphics.ip.ver = (x), \
- 	.__runtime.media.ip.ver = (x), \
- 	.__runtime.display.ip.ver = (x)
- 
- #define NO_DISPLAY .__runtime.pipe_mask = 0
- 
- #define I845_PIPE_OFFSETS \
- 	.display.pipe_offsets = { \
- 		[TRANSCODER_A] = PIPE_A_OFFSET,	\
- 	}, \
- 	.display.trans_offsets = { \
- 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
- 	}
- 
- #define I9XX_PIPE_OFFSETS \
- 	.display.pipe_offsets = { \
- 		[TRANSCODER_A] = PIPE_A_OFFSET,	\
- 		[TRANSCODER_B] = PIPE_B_OFFSET, \
- 	}, \
- 	.display.trans_offsets = { \
- 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
- 		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
- 	}
- 
- #define IVB_PIPE_OFFSETS \
- 	.display.pipe_offsets = { \
- 		[TRANSCODER_A] = PIPE_A_OFFSET,	\
- 		[TRANSCODER_B] = PIPE_B_OFFSET, \
- 		[TRANSCODER_C] = PIPE_C_OFFSET, \
- 	}, \
- 	.display.trans_offsets = { \
- 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
- 		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
- 		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
- 	}
- 
- #define HSW_PIPE_OFFSETS \
- 	.display.pipe_offsets = { \
- 		[TRANSCODER_A] = PIPE_A_OFFSET,	\
- 		[TRANSCODER_B] = PIPE_B_OFFSET, \
- 		[TRANSCODER_C] = PIPE_C_OFFSET, \
- 		[TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
- 	}, \
- 	.display.trans_offsets = { \
- 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
- 		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
- 		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
- 		[TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
- 	}
- 
- #define CHV_PIPE_OFFSETS \
- 	.display.pipe_offsets = { \
- 		[TRANSCODER_A] = PIPE_A_OFFSET, \
- 		[TRANSCODER_B] = PIPE_B_OFFSET, \
- 		[TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
- 	}, \
- 	.display.trans_offsets = { \
- 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
- 		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
- 		[TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
- 	}
- 
- #define I845_CURSOR_OFFSETS \
- 	.display.cursor_offsets = { \
- 		[PIPE_A] = CURSOR_A_OFFSET, \
- 	}
- 
- #define I9XX_CURSOR_OFFSETS \
- 	.display.cursor_offsets = { \
- 		[PIPE_A] = CURSOR_A_OFFSET, \
- 		[PIPE_B] = CURSOR_B_OFFSET, \
- 	}
- 
- #define CHV_CURSOR_OFFSETS \
- 	.display.cursor_offsets = { \
- 		[PIPE_A] = CURSOR_A_OFFSET, \
- 		[PIPE_B] = CURSOR_B_OFFSET, \
- 		[PIPE_C] = CHV_CURSOR_C_OFFSET, \
- 	}
- 
- #define IVB_CURSOR_OFFSETS \
- 	.display.cursor_offsets = { \
- 		[PIPE_A] = CURSOR_A_OFFSET, \
- 		[PIPE_B] = IVB_CURSOR_B_OFFSET, \
- 		[PIPE_C] = IVB_CURSOR_C_OFFSET, \
- 	}
- 
- #define TGL_CURSOR_OFFSETS \
- 	.display.cursor_offsets = { \
- 		[PIPE_A] = CURSOR_A_OFFSET, \
- 		[PIPE_B] = IVB_CURSOR_B_OFFSET, \
- 		[PIPE_C] = IVB_CURSOR_C_OFFSET, \
- 		[PIPE_D] = TGL_CURSOR_D_OFFSET, \
- 	}
- 
- #define I845_COLORS \
- 	.display.color = { .gamma_lut_size = 256 }
- #define I9XX_COLORS \
- 	.display.color = { .gamma_lut_size = 129, \
- 		   .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
- 	}
- #define ILK_COLORS \
- 	.display.color = { .gamma_lut_size = 1024 }
- #define IVB_COLORS \
- 	.display.color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
- #define CHV_COLORS \
- 	.display.color = { \
- 		.degamma_lut_size = 65, .gamma_lut_size = 257, \
- 		.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
- 		.gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
- 	}
- #define GLK_COLORS \
- 	.display.color = { \
- 		.degamma_lut_size = 33, .gamma_lut_size = 1024, \
- 		.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
- 				     DRM_COLOR_LUT_EQUAL_CHANNELS, \
- 	}
- #define ICL_COLORS \
- 	.display.color = { \
- 		.degamma_lut_size = 33, .gamma_lut_size = 262145, \
- 		.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
- 				     DRM_COLOR_LUT_EQUAL_CHANNELS, \
- 		.gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
- 	}
+ 	.__runtime.media.ip.ver = (x)
  
 +#define LEGACY_CACHELEVEL \
 +	.cachelevel_to_pat = { \
 +		[I915_CACHE_NONE]   = 0, \
 +		[I915_CACHE_LLC]    = 1, \
 +		[I915_CACHE_L3_LLC] = 2, \
 +		[I915_CACHE_WT]     = 3, \
 +	}
 +
 +#define TGL_CACHELEVEL \
 +	.cachelevel_to_pat = { \
 +		[I915_CACHE_NONE]   = 3, \
 +		[I915_CACHE_LLC]    = 0, \
 +		[I915_CACHE_L3_LLC] = 0, \
 +		[I915_CACHE_WT]     = 2, \
 +	}
 +
 +#define PVC_CACHELEVEL \
 +	.cachelevel_to_pat = { \
 +		[I915_CACHE_NONE]   = 0, \
 +		[I915_CACHE_LLC]    = 3, \
 +		[I915_CACHE_L3_LLC] = 3, \
 +		[I915_CACHE_WT]     = 2, \
 +	}
 +
 +#define MTL_CACHELEVEL \
 +	.cachelevel_to_pat = { \
 +		[I915_CACHE_NONE]   = 2, \
 +		[I915_CACHE_LLC]    = 3, \
 +		[I915_CACHE_L3_LLC] = 3, \
 +		[I915_CACHE_WT]     = 1, \
 +	}
 +
  /* Keep in gen based order, and chronological order within a gen */
  
  #define GEN_DEFAULT_PAGE_SIZES \
@@@ -221,13 -61,8 +94,10 @@@
  	.has_snoop = true, \
  	.has_coherent_ggtt = false, \
  	.dma_mask_size = 32, \
 +	.max_pat_index = 3, \
- 	I9XX_PIPE_OFFSETS, \
- 	I9XX_CURSOR_OFFSETS, \
- 	I9XX_COLORS, \
  	GEN_DEFAULT_PAGE_SIZES, \
 -	GEN_DEFAULT_REGIONS
 +	GEN_DEFAULT_REGIONS, \
 +	LEGACY_CACHELEVEL
  
  #define I845_FEATURES \
  	GEN(2), \
@@@ -244,13 -74,8 +109,10 @@@
  	.has_snoop = true, \
  	.has_coherent_ggtt = false, \
  	.dma_mask_size = 32, \
 +	.max_pat_index = 3, \
- 	I845_PIPE_OFFSETS, \
- 	I845_CURSOR_OFFSETS, \
- 	I845_COLORS, \
  	GEN_DEFAULT_PAGE_SIZES, \
 -	GEN_DEFAULT_REGIONS
 +	GEN_DEFAULT_REGIONS, \
 +	LEGACY_CACHELEVEL
  
  static const struct intel_device_info i830_info = {
  	I830_FEATURES,
@@@ -285,13 -105,8 +142,10 @@@ static const struct intel_device_info i
  	.has_snoop = true, \
  	.has_coherent_ggtt = true, \
  	.dma_mask_size = 32, \
 +	.max_pat_index = 3, \
- 	I9XX_PIPE_OFFSETS, \
- 	I9XX_CURSOR_OFFSETS, \
- 	I9XX_COLORS, \
  	GEN_DEFAULT_PAGE_SIZES, \
 -	GEN_DEFAULT_REGIONS
 +	GEN_DEFAULT_REGIONS, \
 +	LEGACY_CACHELEVEL
  
  static const struct intel_device_info i915g_info = {
  	GEN3_FEATURES,
@@@ -379,13 -166,8 +205,10 @@@ static const struct intel_device_info p
  	.has_snoop = true, \
  	.has_coherent_ggtt = true, \
  	.dma_mask_size = 36, \
 +	.max_pat_index = 3, \
- 	I9XX_PIPE_OFFSETS, \
- 	I9XX_CURSOR_OFFSETS, \
- 	I9XX_COLORS, \
  	GEN_DEFAULT_PAGE_SIZES, \
 -	GEN_DEFAULT_REGIONS
 +	GEN_DEFAULT_REGIONS, \
 +	LEGACY_CACHELEVEL
  
  static const struct intel_device_info i965g_info = {
  	GEN4_FEATURES,
@@@ -435,13 -208,8 +249,10 @@@ static const struct intel_device_info g
  	/* ilk does support rc6, but we do not implement [power] contexts */ \
  	.has_rc6 = 0, \
  	.dma_mask_size = 36, \
 +	.max_pat_index = 3, \
- 	I9XX_PIPE_OFFSETS, \
- 	I9XX_CURSOR_OFFSETS, \
- 	ILK_COLORS, \
  	GEN_DEFAULT_PAGE_SIZES, \
 -	GEN_DEFAULT_REGIONS
 +	GEN_DEFAULT_REGIONS, \
 +	LEGACY_CACHELEVEL
  
  static const struct intel_device_info ilk_d_info = {
  	GEN5_FEATURES,
@@@ -471,15 -234,10 +277,12 @@@ static const struct intel_device_info i
  	.has_rc6p = 0, \
  	.has_rps = true, \
  	.dma_mask_size = 40, \
 +	.max_pat_index = 3, \
  	.__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \
  	.__runtime.ppgtt_size = 31, \
- 	I9XX_PIPE_OFFSETS, \
- 	I9XX_CURSOR_OFFSETS, \
- 	ILK_COLORS, \
  	GEN_DEFAULT_PAGE_SIZES, \
 -	GEN_DEFAULT_REGIONS
 +	GEN_DEFAULT_REGIONS, \
 +	LEGACY_CACHELEVEL
  
  #define SNB_D_PLATFORM \
  	GEN6_FEATURES, \
@@@ -526,15 -280,10 +325,12 @@@ static const struct intel_device_info s
  	.has_reset_engine = true, \
  	.has_rps = true, \
  	.dma_mask_size = 40, \
 +	.max_pat_index = 3, \
  	.__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \
  	.__runtime.ppgtt_size = 31, \
- 	IVB_PIPE_OFFSETS, \
- 	IVB_CURSOR_OFFSETS, \
- 	IVB_COLORS, \
  	GEN_DEFAULT_PAGE_SIZES, \
 -	GEN_DEFAULT_REGIONS
 +	GEN_DEFAULT_REGIONS, \
 +	LEGACY_CACHELEVEL
  
  #define IVB_D_PLATFORM \
  	GEN7_FEATURES, \
@@@ -585,22 -331,14 +378,16 @@@ static const struct intel_device_info v
  	.has_rc6 = 1,
  	.has_reset_engine = true,
  	.has_rps = true,
- 	.display.has_gmch = 1,
- 	.display.has_hotplug = 1,
  	.dma_mask_size = 40,
 +	.max_pat_index = 3,
  	.__runtime.ppgtt_type = INTEL_PPGTT_ALIASING,
  	.__runtime.ppgtt_size = 31,
  	.has_snoop = true,
  	.has_coherent_ggtt = false,
  	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
- 	.display.mmio_offset = VLV_DISPLAY_BASE,
- 	I9XX_PIPE_OFFSETS,
- 	I9XX_CURSOR_OFFSETS,
- 	I9XX_COLORS,
  	GEN_DEFAULT_PAGE_SIZES,
  	GEN_DEFAULT_REGIONS,
 +	LEGACY_CACHELEVEL,
  };
  
  #define G75_FEATURES  \
@@@ -686,21 -415,14 +464,16 @@@ static const struct intel_device_info c
  	.has_rc6 = 1,
  	.has_rps = true,
  	.has_logical_ring_contexts = 1,
- 	.display.has_gmch = 1,
  	.dma_mask_size = 39,
 +	.max_pat_index = 3,
  	.__runtime.ppgtt_type = INTEL_PPGTT_FULL,
  	.__runtime.ppgtt_size = 32,
  	.has_reset_engine = 1,
  	.has_snoop = true,
  	.has_coherent_ggtt = false,
- 	.display.mmio_offset = VLV_DISPLAY_BASE,
- 	CHV_PIPE_OFFSETS,
- 	CHV_CURSOR_OFFSETS,
- 	CHV_COLORS,
  	GEN_DEFAULT_PAGE_SIZES,
  	GEN_DEFAULT_REGIONS,
 +	LEGACY_CACHELEVEL,
  };
  
  #define GEN9_DEFAULT_PAGE_SIZES \
@@@ -781,14 -482,8 +533,10 @@@ static const struct intel_device_info s
  	.has_reset_engine = 1, \
  	.has_snoop = true, \
  	.has_coherent_ggtt = false, \
- 	.display.has_ipc = 1, \
 +	.max_pat_index = 3, \
- 	HSW_PIPE_OFFSETS, \
- 	IVB_CURSOR_OFFSETS, \
- 	IVB_COLORS, \
  	GEN9_DEFAULT_PAGE_SIZES, \
 -	GEN_DEFAULT_REGIONS
 +	GEN_DEFAULT_REGIONS, \
 +	LEGACY_CACHELEVEL
  
  static const struct intel_device_info bxt_info = {
  	GEN9_LP_FEATURES,
@@@ -920,33 -587,8 +640,9 @@@ static const struct intel_device_info j
  #define GEN12_FEATURES \
  	GEN11_FEATURES, \
  	GEN(12), \
- 	.display.abox_mask = GENMASK(2, 1), \
- 	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
- 	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
- 		BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
- 		BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
- 	.display.pipe_offsets = { \
- 		[TRANSCODER_A] = PIPE_A_OFFSET, \
- 		[TRANSCODER_B] = PIPE_B_OFFSET, \
- 		[TRANSCODER_C] = PIPE_C_OFFSET, \
- 		[TRANSCODER_D] = PIPE_D_OFFSET, \
- 		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
- 		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
- 	}, \
- 	.display.trans_offsets = { \
- 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
- 		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
- 		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
- 		[TRANSCODER_D] = TRANSCODER_D_OFFSET, \
- 		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
- 		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
- 	}, \
- 	TGL_CURSOR_OFFSETS, \
- 	TGL_CACHELEVEL, \
++	.max_pat_index = 3 \
  	.has_global_mocs = 1, \
- 	.has_pxp = 1, \
- 	.display.has_dsb = 1, \
- 	.max_pat_index = 3
+ 	.has_pxp = 1
  
  static const struct intel_device_info tgl_info = {
  	GEN12_FEATURES,
@@@ -1162,24 -739,14 +795,16 @@@ static const struct intel_device_info p
  	.__runtime.graphics.ip.rel = 60,
  	.__runtime.media.ip.rel = 60,
  	PLATFORM(INTEL_PONTEVECCHIO),
- 	NO_DISPLAY,
  	.has_flat_ccs = 0,
 +	.max_pat_index = 7,
  	.__runtime.platform_engine_mask =
  		BIT(BCS0) |
  		BIT(VCS0) |
  		BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
  	.require_force_probe = 1,
 +	PVC_CACHELEVEL,
  };
  
- #define XE_LPDP_FEATURES	\
- 	XE_LPD_FEATURES,	\
- 	.__runtime.display.ip.ver = 14,	\
- 	.display.has_cdclk_crawl = 1, \
- 	.display.has_cdclk_squash = 1, \
- 	.__runtime.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B)
- 
  static const struct intel_gt_definition xelpmp_extra_gt[] = {
  	{
  		.type = GT_MEDIA,

[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

[Intel-gfx] linux-next: manual merge of the drm-intel tree with the drm tree

[Stephen Rothwell]

[-- Attachment #1: Type: text/plain, Size: 2974 bytes --]

Hi all,

Today's linux-next merge of the drm-intel tree got a conflict in:

  drivers/gpu/drm/i915/i915_drv.h

between commit:

  f67986b0119c ("drm/i915/pxp: Promote pxp subsystem to top-level of i915")

from the drm tree and commit:

  a3f839762ceb ("drm/i915: move pch_ssc_use to display sub-struct under dpll")

from the drm-intel tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

-- 
Cheers,
Stephen Rothwell

diff --cc drivers/gpu/drm/i915/i915_drv.h
index 48fd82722f12,ac4c3c6f5541..000000000000
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@@ -65,26 -65,40 +65,41 @@@
  #include "intel_uncore.h"
  
  struct drm_i915_clock_gating_funcs;
- struct drm_i915_gem_object;
- struct drm_i915_private;
- struct intel_connector;
- struct intel_dp;
- struct intel_encoder;
- struct intel_limit;
- struct intel_overlay_error_state;
  struct vlv_s0ix_state;
 +struct intel_pxp;
  
- #define I915_GEM_GPU_DOMAINS \
- 	(I915_GEM_DOMAIN_RENDER | \
- 	 I915_GEM_DOMAIN_SAMPLER | \
- 	 I915_GEM_DOMAIN_COMMAND | \
- 	 I915_GEM_DOMAIN_INSTRUCTION | \
- 	 I915_GEM_DOMAIN_VERTEX)
+ #define GEM_QUIRK_PIN_SWIZZLED_PAGES	BIT(0)
  
- #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
+ /* Data Stolen Memory (DSM) aka "i915 stolen memory" */
+ struct i915_dsm {
+ 	/*
+ 	 * The start and end of DSM which we can optionally use to create GEM
+ 	 * objects backed by stolen memory.
+ 	 *
+ 	 * Note that usable_size tells us exactly how much of this we are
+ 	 * actually allowed to use, given that some portion of it is in fact
+ 	 * reserved for use by hardware functions.
+ 	 */
+ 	struct resource stolen;
  
- #define GEM_QUIRK_PIN_SWIZZLED_PAGES	BIT(0)
+ 	/*
+ 	 * Reserved portion of DSM.
+ 	 */
+ 	struct resource reserved;
+ 
+ 	/*
+ 	 * Total size minus reserved ranges.
+ 	 *
+ 	 * DSM is segmented in hardware with different portions offlimits to
+ 	 * certain functions.
+ 	 *
+ 	 * The drm_mm is initialised to the total accessible range, as found
+ 	 * from the PCI config. On Broadwell+, this is further restricted to
+ 	 * avoid the first page! The upper end of DSM is reserved for hardware
+ 	 * functions and similarly removed from the accessible range.
+ 	 */
+ 	resource_size_t usable_size;
+ };
  
  struct i915_suspend_saved_registers {
  	u32 saveDSPARB;
@@@ -366,10 -337,6 +338,8 @@@ struct drm_i915_private 
  		struct file *mmap_singleton;
  	} gem;
  
 +	struct intel_pxp *pxp;
 +
- 	u8 pch_ssc_use;
- 
  	/* For i915gm/i945gm vblank irq workaround */
  	u8 vblank_enabled;
  

[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

[Intel-gfx] linux-next: manual merge of the drm-intel tree with the drm tree

[Stephen Rothwell]

[-- Attachment #1: Type: text/plain, Size: 2231 bytes --]

Hi all,

Today's linux-next merge of the drm-intel tree got a conflict in:

  drivers/gpu/drm/i915/i915_drv.h

between commit:

  3bb6a44251b4 ("drm/i915: Rename ggtt_view as gtt_view")

from the drm tree and commit:

  5fd5cc73e449 ("drm/i915: split out i915_gem.c declarations to i915_gem.h")

from the drm-intel tree.

I fixed it up (I used the latter version of this file and applied the
merge fix below) and can carry the fix as necessary. This is now fixed
as far as linux-next is concerned, but any non trivial conflicts should
be mentioned to your upstream maintainer when your tree is submitted for
merging.  You may also want to consider cooperating with the maintainer
of the conflicting tree to minimise any particularly complex conflicts.

From: Stephen Rothwell <sfr@canb.auug.org.au>
Date: Tue, 13 Sep 2022 12:06:57 +1000
Subject: [PATCH] drm/i915: fix up for "drm/i915: Rename ggtt_view as gtt_view"

Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
 drivers/gpu/drm/i915/i915_gem.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.h b/drivers/gpu/drm/i915/i915_gem.h
index 2fccb19ed9f7..a5cdf6662d01 100644
--- a/drivers/gpu/drm/i915/i915_gem.h
+++ b/drivers/gpu/drm/i915/i915_gem.h
@@ -36,7 +36,7 @@ struct drm_file;
 struct drm_i915_gem_object;
 struct drm_i915_private;
 struct i915_gem_ww_ctx;
-struct i915_ggtt_view;
+struct i915_gtt_view;
 struct i915_vma;
 
 void i915_gem_init_early(struct drm_i915_private *i915);
@@ -48,12 +48,12 @@ void i915_gem_drain_workqueue(struct drm_i915_private *i915);
 struct i915_vma * __must_check
 i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object *obj,
 			    struct i915_gem_ww_ctx *ww,
-			    const struct i915_ggtt_view *view,
+			    const struct i915_gtt_view *view,
 			    u64 size, u64 alignment, u64 flags);
 
 struct i915_vma * __must_check
 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
-			 const struct i915_ggtt_view *view,
+			 const struct i915_gtt_view *view,
 			 u64 size, u64 alignment, u64 flags);
 
 int i915_gem_object_unbind(struct drm_i915_gem_object *obj,
-- 
2.35.1

-- 
Cheers,
Stephen Rothwell

[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

[Intel-gfx] linux-next: manual merge of the drm-intel tree with the drm tree

[Stephen Rothwell]

[-- Attachment #1: Type: text/plain, Size: 774 bytes --]

Hi all,

Today's linux-next merge of the drm-intel tree got a conflict in:

  drivers/gpu/drm/i915/intel_pm.c

between commit:

  254e5e8829a9 ("drm: Remove unnecessary include statements of drm_plane_helper.h")

from the drm tree and commit:

  42a0d256496f ("drm/i915: Extract skl_watermark.c")

from the drm-intel tree.

I fixed it up (they both removed the same include) and can carry the fix
as necessary. This is now fixed as far as linux-next is concerned, but
any non trivial conflicts should be mentioned to your upstream maintainer
when your tree is submitted for merging.  You may also want to consider
cooperating with the maintainer of the conflicting tree to minimise any
particularly complex conflicts.

-- 
Cheers,
Stephen Rothwell

[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

[Intel-gfx] linux-next: manual merge of the drm-intel tree with the drm tree

[Stephen Rothwell]

[-- Attachment #1: Type: text/plain, Size: 1202 bytes --]

Hi all,

Today's linux-next merge of the drm-intel tree got a conflict in:

  drivers/gpu/drm/i915/i915_module.c

between commit:

  6387a3c4b0c4 ("drm: move the buddy allocator from i915 into common drm")

from the drm tree and commit:

  24524e3f43cf ("drm/i915: move the DRIVER_* macros to i915_driver.[ch]")

from the drm-intel tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

-- 
Cheers,
Stephen Rothwell

diff --cc drivers/gpu/drm/i915/i915_module.c
index 8451822637f0,5d6fdf37fb5a..000000000000
--- a/drivers/gpu/drm/i915/i915_module.c
+++ b/drivers/gpu/drm/i915/i915_module.c
@@@ -9,6 -9,8 +9,7 @@@
  #include "gem/i915_gem_context.h"
  #include "gem/i915_gem_object.h"
  #include "i915_active.h"
 -#include "i915_buddy.h"
+ #include "i915_driver.h"
  #include "i915_params.h"
  #include "i915_pci.h"
  #include "i915_perf.h"

[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

[Intel-gfx] linux-next: manual merge of the drm-intel tree with the drm tree

[Stephen Rothwell]

[-- Attachment #1: Type: text/plain, Size: 793 bytes --]

Hi all,

Today's linux-next merge of the drm-intel tree got a conflict in:

  include/linux/dma-buf-map.h

between commit:

  e8c1f36157ce ("dma-buf-map: Fix dot vs comma in example")

from the drm tree and commit:

  7938f4218168 ("dma-buf-map: Rename to iosys-map")

from the drm-intel tree.

I fixed it up (I just removed the file - the changes from the former
commit are only on comments) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

-- 
Cheers,
Stephen Rothwell

[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

[Intel-gfx] linux-next: manual merge of the drm-intel tree with the drm tree

[Stephen Rothwell]

[-- Attachment #1: Type: text/plain, Size: 1212 bytes --]

Hi all,

Today's linux-next merge of the drm-intel tree got a conflict in:

  drivers/gpu/drm/i915/intel_device_info.h

between commit:

  3ffe82d701a4 ("drm/i915/xehp: handle new steering options")

from the drm tree and commit:

  22e26af76903 ("drm/i915: Fork DG1 interrupt handler")

from the drm-intel tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

-- 
Cheers,
Stephen Rothwell

diff --cc drivers/gpu/drm/i915/intel_device_info.h
index f88be11a3570,ef1eecd259e0..000000000000
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@@ -133,8 -131,6 +131,7 @@@ enum intel_ppgtt_type 
  	func(has_llc); \
  	func(has_logical_ring_contexts); \
  	func(has_logical_ring_elsq); \
- 	func(has_master_unit_irq); \
 +	func(has_mslices); \
  	func(has_pooled_eu); \
  	func(has_rc6); \
  	func(has_rc6p); \

[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

Re: [Intel-gfx] linux-next: manual merge of the drm-intel tree with the drm tree

[Thomas Zimmermann]

[-- Attachment #1.1.1: Type: text/plain, Size: 3402 bytes --]

Hi

Am 14.05.21 um 03:53 schrieb Stephen Rothwell:
> Hi all,
> 
> On Fri, 30 Apr 2021 08:23:21 +1000 Stephen Rothwell <sfr@canb.auug.org.au> wrote:
>>
>> On Thu, 18 Mar 2021 12:52:41 +1100 Stephen Rothwell <sfr@canb.auug.org.au> wrote:
>>>
>>> On Wed, 17 Mar 2021 14:08:24 +1100 Stephen Rothwell <sfr@canb.auug.org.au> wrote:
>>>>
>>>> Today's linux-next merge of the drm-intel tree got a conflict in:
>>>>
>>>>    drivers/gpu/drm/i915/display/intel_sprite.c
>>>>
>>>> between commit:
>>>>
>>>>    92f1d09ca4ed ("drm: Switch to %p4cc format modifier")
>>>>
>>>> from the drm tree and commit:
>>>>
>>>>    46d12f911821 ("drm/i915: migrate skl planes code new file (v5)")
>>>>
>>>> from the drm-intel tree.
>>>>
>>>> I fixed it up (I used the latter version of the file and applied the
>>>> following patch) and can carry the fix as necessary. This is now fixed
>>>> as far as linux-next is concerned, but any non trivial conflicts should
>>>> be mentioned to your upstream maintainer when your tree is submitted 
for
>>>> merging.  You may also want to consider cooperating with the maintainer
>>>> of the conflicting tree to minimise any particularly complex conflicts.
>>>>
>>>> From: Stephen Rothwell <sfr@canb.auug.org.au>
>>>> Date: Wed, 17 Mar 2021 14:05:42 +1100
>>>> Subject: [PATCH] merge fix for "drm: Switch to %p4cc format modifier"
>>>>
>>>> Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
>>>> ---
>>>>   drivers/gpu/drm/i915/display/skl_universal_plane.c | 6 ++----
>>>>   1 file changed, 2 insertions(+), 4 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>>>> index 1f335cb09149..45ceff436bf7 100644
>>>> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
>>>> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>>>> @@ -1120,7 +1120,6 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
>>>>   	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>>>>   	const struct drm_framebuffer *fb = plane_state->hw.fb;
>>>>   	unsigned int rotation = plane_state->hw.rotation;
>>>> -	struct drm_format_name_buf format_name;
>>>>   
>>>>   	if (!fb)
>>>>   		return 0;
>>>> @@ -1168,9 +1167,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
>>>>   		case DRM_FORMAT_XVYU12_16161616:
>>>>   		case DRM_FORMAT_XVYU16161616:
>>>>   			drm_dbg_kms(&dev_priv->drm,
>>>> -				    "Unsupported pixel format %s for 90/270!\n",
>>>> -				    drm_get_format_name(fb->format->format,
>>>> -							&format_name));
>>>> +				    "Unsupported pixel format %p4cc for 90/270!\n",
>>>> +				    &fb->format->format);
>>>>   			return -EINVAL;
>>>>   		default:
>>>>   			break;
>>>> -- 
>>>> 2.30.0
>>>
>>> The above fix up patch now needs to be applied to the drm tree.
>>
>> I am still applying the above patch, but it applies to Linus' tree now.
> 
> I am going to stop applying this.  You guys can apply it if you want to
> some time.
> 

Sorry, this got lost several times. I've applied your patch to 
drm-misc-next now. Thanks a lot.

Best regards
Thomas


-- 
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Maxfeldstr. 5, 90409 Nürnberg, Germany
(HRB 36809, AG Nürnberg)
Geschäftsführer: Felix Imendörffer


[-- Attachment #1.2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 840 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] linux-next: manual merge of the drm-intel tree with the drm tree

[Stephen Rothwell]

[-- Attachment #1.1: Type: text/plain, Size: 3099 bytes --]

Hi all,

On Fri, 30 Apr 2021 08:23:21 +1000 Stephen Rothwell <sfr@canb.auug.org.au> wrote:
>
> On Thu, 18 Mar 2021 12:52:41 +1100 Stephen Rothwell <sfr@canb.auug.org.au> wrote:
> > 
> > On Wed, 17 Mar 2021 14:08:24 +1100 Stephen Rothwell <sfr@canb.auug.org.au> wrote:  
> > >
> > > Today's linux-next merge of the drm-intel tree got a conflict in:
> > > 
> > >   drivers/gpu/drm/i915/display/intel_sprite.c
> > > 
> > > between commit:
> > > 
> > >   92f1d09ca4ed ("drm: Switch to %p4cc format modifier")
> > > 
> > > from the drm tree and commit:
> > > 
> > >   46d12f911821 ("drm/i915: migrate skl planes code new file (v5)")
> > > 
> > > from the drm-intel tree.
> > > 
> > > I fixed it up (I used the latter version of the file and applied the
> > > following patch) and can carry the fix as necessary. This is now fixed
> > > as far as linux-next is concerned, but any non trivial conflicts should
> > > be mentioned to your upstream maintainer when your tree is submitted for
> > > merging.  You may also want to consider cooperating with the maintainer
> > > of the conflicting tree to minimise any particularly complex conflicts.
> > > 
> > > From: Stephen Rothwell <sfr@canb.auug.org.au>
> > > Date: Wed, 17 Mar 2021 14:05:42 +1100
> > > Subject: [PATCH] merge fix for "drm: Switch to %p4cc format modifier"
> > > 
> > > Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
> > > ---
> > >  drivers/gpu/drm/i915/display/skl_universal_plane.c | 6 ++----
> > >  1 file changed, 2 insertions(+), 4 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > index 1f335cb09149..45ceff436bf7 100644
> > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > @@ -1120,7 +1120,6 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
> > >  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > >  	const struct drm_framebuffer *fb = plane_state->hw.fb;
> > >  	unsigned int rotation = plane_state->hw.rotation;
> > > -	struct drm_format_name_buf format_name;
> > >  
> > >  	if (!fb)
> > >  		return 0;
> > > @@ -1168,9 +1167,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
> > >  		case DRM_FORMAT_XVYU12_16161616:
> > >  		case DRM_FORMAT_XVYU16161616:
> > >  			drm_dbg_kms(&dev_priv->drm,
> > > -				    "Unsupported pixel format %s for 90/270!\n",
> > > -				    drm_get_format_name(fb->format->format,
> > > -							&format_name));
> > > +				    "Unsupported pixel format %p4cc for 90/270!\n",
> > > +				    &fb->format->format);
> > >  			return -EINVAL;
> > >  		default:
> > >  			break;
> > > -- 
> > > 2.30.0    
> > 
> > The above fix up patch now needs to be applied to the drm tree.  
> 
> I am still applying the above patch, but it applies to Linus' tree now.

I am going to stop applying this.  You guys can apply it if you want to
some time.

-- 
Cheers,
Stephen Rothwell

[-- Attachment #1.2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] linux-next: manual merge of the drm-intel tree with the drm tree

[Stephen Rothwell]

[-- Attachment #1.1: Type: text/plain, Size: 2792 bytes --]

Hi all,

On Thu, 18 Mar 2021 12:52:41 +1100 Stephen Rothwell <sfr@canb.auug.org.au> wrote:
> 
> On Wed, 17 Mar 2021 14:08:24 +1100 Stephen Rothwell <sfr@canb.auug.org.au> wrote:
> >
> > Today's linux-next merge of the drm-intel tree got a conflict in:
> > 
> >   drivers/gpu/drm/i915/display/intel_sprite.c
> > 
> > between commit:
> > 
> >   92f1d09ca4ed ("drm: Switch to %p4cc format modifier")
> > 
> > from the drm tree and commit:
> > 
> >   46d12f911821 ("drm/i915: migrate skl planes code new file (v5)")
> > 
> > from the drm-intel tree.
> > 
> > I fixed it up (I used the latter version of the file and applied the
> > following patch) and can carry the fix as necessary. This is now fixed
> > as far as linux-next is concerned, but any non trivial conflicts should
> > be mentioned to your upstream maintainer when your tree is submitted for
> > merging.  You may also want to consider cooperating with the maintainer
> > of the conflicting tree to minimise any particularly complex conflicts.
> > 
> > From: Stephen Rothwell <sfr@canb.auug.org.au>
> > Date: Wed, 17 Mar 2021 14:05:42 +1100
> > Subject: [PATCH] merge fix for "drm: Switch to %p4cc format modifier"
> > 
> > Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
> > ---
> >  drivers/gpu/drm/i915/display/skl_universal_plane.c | 6 ++----
> >  1 file changed, 2 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > index 1f335cb09149..45ceff436bf7 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > @@ -1120,7 +1120,6 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
> >  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> >  	const struct drm_framebuffer *fb = plane_state->hw.fb;
> >  	unsigned int rotation = plane_state->hw.rotation;
> > -	struct drm_format_name_buf format_name;
> >  
> >  	if (!fb)
> >  		return 0;
> > @@ -1168,9 +1167,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
> >  		case DRM_FORMAT_XVYU12_16161616:
> >  		case DRM_FORMAT_XVYU16161616:
> >  			drm_dbg_kms(&dev_priv->drm,
> > -				    "Unsupported pixel format %s for 90/270!\n",
> > -				    drm_get_format_name(fb->format->format,
> > -							&format_name));
> > +				    "Unsupported pixel format %p4cc for 90/270!\n",
> > +				    &fb->format->format);
> >  			return -EINVAL;
> >  		default:
> >  			break;
> > -- 
> > 2.30.0  
> 
> The above fix up patch now needs to be applied to the drm tree.

I am still applying the above patch, but it applies to Linus' tree now.

-- 
Cheers,
Stephen Rothwell

[-- Attachment #1.2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] linux-next: manual merge of the drm-intel tree with the drm tree

[Stephen Rothwell]

[-- Attachment #1.1: Type: text/plain, Size: 2372 bytes --]

Hi all,

Today's linux-next merge of the drm-intel tree got a conflict in:

  drivers/gpu/drm/i915/display/intel_display.c

between commit:

  1b321026e213 ("drm/i915: Pass ww ctx to intel_pin_to_display_plane")

from the drm tree and commit:

  61169987c4d9 ("drm/i915: Unify the FB and plane state view information into one struct")

from the drm-intel tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

-- 
Cheers,
Stephen Rothwell

diff --cc drivers/gpu/drm/i915/display/intel_display.c
index aa524eff20e1,bdb2adb4d748..000000000000
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@@ -1185,13 -1094,13 +1112,13 @@@ retry
  		 * mode that matches the user configuration.
  		 */
  		ret = i915_vma_pin_fence(vma);
- 		if (ret != 0 && INTEL_GEN(dev_priv) < 4) {
+ 		if (ret != 0 && DISPLAY_VER(dev_priv) < 4) {
  			i915_vma_unpin(vma);
 -			vma = ERR_PTR(ret);
 -			goto err;
 +			goto err_unpin;
  		}
 +		ret = 0;
  
 -		if (ret == 0 && vma->fence)
 +		if (vma->fence)
  			*out_flags |= PLANE_HAS_FENCE;
  	}
  
@@@ -11363,12 -10508,20 +10536,12 @@@ int intel_plane_pin_fb(struct intel_pla
  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
  	struct drm_framebuffer *fb = plane_state->hw.fb;
  	struct i915_vma *vma;
 +	bool phys_cursor =
 +		plane->id == PLANE_CURSOR &&
 +		INTEL_INFO(dev_priv)->display.cursor_needs_physical;
  
 -	if (plane->id == PLANE_CURSOR &&
 -	    INTEL_INFO(dev_priv)->display.cursor_needs_physical) {
 -		struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 -		const int align = intel_cursor_alignment(dev_priv);
 -		int err;
 -
 -		err = i915_gem_object_attach_phys(obj, align);
 -		if (err)
 -			return err;
 -	}
 -
 -	vma = intel_pin_and_fence_fb_obj(fb,
 +	vma = intel_pin_and_fence_fb_obj(fb, phys_cursor,
- 					 &plane_state->view,
+ 					 &plane_state->view.gtt,
  					 intel_plane_uses_fence(plane_state),
  					 &plane_state->flags);
  	if (IS_ERR(vma))

[-- Attachment #1.2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] linux-next: manual merge of the drm-intel tree with the drm tree

[Stephen Rothwell]

[-- Attachment #1.1: Type: text/plain, Size: 2508 bytes --]

Hi all,

On Wed, 17 Mar 2021 14:08:24 +1100 Stephen Rothwell <sfr@canb.auug.org.au> wrote:
>
> Today's linux-next merge of the drm-intel tree got a conflict in:
> 
>   drivers/gpu/drm/i915/display/intel_sprite.c
> 
> between commit:
> 
>   92f1d09ca4ed ("drm: Switch to %p4cc format modifier")
> 
> from the drm tree and commit:
> 
>   46d12f911821 ("drm/i915: migrate skl planes code new file (v5)")
> 
> from the drm-intel tree.
> 
> I fixed it up (I used the latter version of the file and applied the
> following patch) and can carry the fix as necessary. This is now fixed
> as far as linux-next is concerned, but any non trivial conflicts should
> be mentioned to your upstream maintainer when your tree is submitted for
> merging.  You may also want to consider cooperating with the maintainer
> of the conflicting tree to minimise any particularly complex conflicts.
> 
> From: Stephen Rothwell <sfr@canb.auug.org.au>
> Date: Wed, 17 Mar 2021 14:05:42 +1100
> Subject: [PATCH] merge fix for "drm: Switch to %p4cc format modifier"
> 
> Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
> ---
>  drivers/gpu/drm/i915/display/skl_universal_plane.c | 6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 1f335cb09149..45ceff436bf7 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -1120,7 +1120,6 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
>  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>  	const struct drm_framebuffer *fb = plane_state->hw.fb;
>  	unsigned int rotation = plane_state->hw.rotation;
> -	struct drm_format_name_buf format_name;
>  
>  	if (!fb)
>  		return 0;
> @@ -1168,9 +1167,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
>  		case DRM_FORMAT_XVYU12_16161616:
>  		case DRM_FORMAT_XVYU16161616:
>  			drm_dbg_kms(&dev_priv->drm,
> -				    "Unsupported pixel format %s for 90/270!\n",
> -				    drm_get_format_name(fb->format->format,
> -							&format_name));
> +				    "Unsupported pixel format %p4cc for 90/270!\n",
> +				    &fb->format->format);
>  			return -EINVAL;
>  		default:
>  			break;
> -- 
> 2.30.0

The above fix up patch now needs to be applied to the drm tree.

-- 
Cheers,
Stephen Rothwell

[-- Attachment #1.2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] linux-next: manual merge of the drm-intel tree with the drm tree

[Stephen Rothwell]

[-- Attachment #1.1: Type: text/plain, Size: 2243 bytes --]

Hi all,

Today's linux-next merge of the drm-intel tree got a conflict in:

  drivers/gpu/drm/i915/display/intel_sprite.c

between commit:

  92f1d09ca4ed ("drm: Switch to %p4cc format modifier")

from the drm tree and commit:

  46d12f911821 ("drm/i915: migrate skl planes code new file (v5)")

from the drm-intel tree.

I fixed it up (I used the latter version of the file and applied the
following patch) and can carry the fix as necessary. This is now fixed
as far as linux-next is concerned, but any non trivial conflicts should
be mentioned to your upstream maintainer when your tree is submitted for
merging.  You may also want to consider cooperating with the maintainer
of the conflicting tree to minimise any particularly complex conflicts.

From: Stephen Rothwell <sfr@canb.auug.org.au>
Date: Wed, 17 Mar 2021 14:05:42 +1100
Subject: [PATCH] merge fix for "drm: Switch to %p4cc format modifier"

Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
 drivers/gpu/drm/i915/display/skl_universal_plane.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 1f335cb09149..45ceff436bf7 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1120,7 +1120,6 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	unsigned int rotation = plane_state->hw.rotation;
-	struct drm_format_name_buf format_name;
 
 	if (!fb)
 		return 0;
@@ -1168,9 +1167,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
 		case DRM_FORMAT_XVYU12_16161616:
 		case DRM_FORMAT_XVYU16161616:
 			drm_dbg_kms(&dev_priv->drm,
-				    "Unsupported pixel format %s for 90/270!\n",
-				    drm_get_format_name(fb->format->format,
-							&format_name));
+				    "Unsupported pixel format %p4cc for 90/270!\n",
+				    &fb->format->format);
 			return -EINVAL;
 		default:
 			break;
-- 
2.30.0

-- 
Cheers,
Stephen Rothwell

[-- Attachment #1.2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] linux-next: manual merge of the drm-intel tree with the drm tree

[Stephen Rothwell]

[-- Attachment #1.1: Type: text/plain, Size: 1533 bytes --]

Hi all,

Today's linux-next merge of the drm-intel tree got a conflict in:

  drivers/gpu/drm/drm_probe_helper.c

between commit:

  12c683e12cd8 ("drm: bridge: Pass drm_display_info to drm_bridge_funcs .mode_valid()")

from the drm tree and commit:

  1c26b8e09004 ("drm/probe_helper: Add drm_connector_helper_funcs.mode_valid_ctx")

from the drm-intel tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

-- 
Cheers,
Stephen Rothwell

diff --cc drivers/gpu/drm/drm_probe_helper.c
index 09e872e61315,601a4f25bb47..000000000000
--- a/drivers/gpu/drm/drm_probe_helper.c
+++ b/drivers/gpu/drm/drm_probe_helper.c
@@@ -114,10 -116,8 +116,10 @@@ drm_mode_validate_pipeline(struct drm_d
  		}
  
  		bridge = drm_bridge_chain_get_first_bridge(encoder);
- 		ret = drm_bridge_chain_mode_valid(bridge,
- 						  &connector->display_info,
- 						  mode);
- 		if (ret != MODE_OK) {
 -		*status = drm_bridge_chain_mode_valid(bridge, mode);
++		*status = drm_bridge_chain_mode_valid(bridge,
++						      &connector->display_info,
++						      mode);
+ 		if (*status != MODE_OK) {
  			/* There is also no point in continuing for crtc check
  			 * here. */
  			continue;

[-- Attachment #1.2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx