[Intel-gfx] [PATCH] drm/i915/gen9bc: Handle TGP PCH during suspend/resume

[Intel-gfx] [PATCH] drm/i915/gen9bc: Handle TGP PCH during suspend/resume

[Tejas Upadhyay]

For Legacy S3 suspend/resume GEN9 BC needs to enable and
setup TGP PCH.

Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 36 ++++++++++++++++++++++++---------
 1 file changed, 27 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index a31980f69120..6dcefc3e24ac 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3026,8 +3026,20 @@ static void gen8_irq_reset(struct drm_i915_private *dev_priv)
 	GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
 	GEN3_IRQ_RESET(uncore, GEN8_PCU_);
 
-	if (HAS_PCH_SPLIT(dev_priv))
+	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+		GEN3_IRQ_RESET(uncore, SDE);
+	else if (HAS_PCH_SPLIT(dev_priv))
 		ibx_irq_reset(dev_priv);
+
+	/* Wa_14010685332:cnp/cmp,tgp,adp */
+	if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
+	    (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
+	    INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
+		intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
+				 SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
+		intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
+				 SBCLK_RUN_REFCLK_DIS, 0);
+	}
 }
 
 static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
@@ -3442,6 +3454,9 @@ static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
 	ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
 
 	spt_hpd_detection_setup(dev_priv);
+
+	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+		icp_hpd_irq_setup(dev_priv);
 }
 
 static u32 ilk_hotplug_enables(struct drm_i915_private *i915,
@@ -3729,9 +3744,19 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 	}
 }
 
+static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
+{
+	struct intel_uncore *uncore = &dev_priv->uncore;
+	u32 mask = SDE_GMBUS_ICP;
+
+	GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
+}
+
 static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
 {
-	if (HAS_PCH_SPLIT(dev_priv))
+	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+		icp_irq_postinstall(dev_priv);
+	else if (HAS_PCH_SPLIT(dev_priv))
 		ibx_irq_postinstall(dev_priv);
 
 	gen8_gt_irq_postinstall(&dev_priv->gt);
@@ -3740,13 +3765,6 @@ static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
 	gen8_master_intr_enable(dev_priv->uncore.regs);
 }
 
-static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
-{
-	struct intel_uncore *uncore = &dev_priv->uncore;
-	u32 mask = SDE_GMBUS_ICP;
-
-	GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
-}
 
 static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
 {
-- 
2.30.0

_______________________________________________
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gen9bc: Handle TGP PCH during suspend/resume

[Patchwork]

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== Series Details ==

Series: drm/i915/gen9bc: Handle TGP PCH during suspend/resume
URL   : https://patchwork.freedesktop.org/series/86346/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9688 -> Patchwork_19518
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_19518:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_flip@basic-flip-vs-dpms@c-edp1:
    - {fi-cml-drallion}:  NOTRUN -> [INCOMPLETE][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/fi-cml-drallion/igt@kms_flip@basic-flip-vs-dpms@c-edp1.html

  
Known issues
------------

  Here are the changes found in Patchwork_19518 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_hotunplug@unbind-rebind:
    - fi-kbl-7500u:       [PASS][2] -> [DMESG-WARN][3] ([i915#2605])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/fi-kbl-7500u/igt@core_hotunplug@unbind-rebind.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/fi-kbl-7500u/igt@core_hotunplug@unbind-rebind.html

  * igt@debugfs_test@read_all_entries:
    - fi-tgl-y:           [PASS][4] -> [DMESG-WARN][5] ([i915#402])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/fi-tgl-y/igt@debugfs_test@read_all_entries.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/fi-tgl-y/igt@debugfs_test@read_all_entries.html

  * igt@gem_exec_suspend@basic-s3:
    - fi-tgl-y:           [PASS][6] -> [DMESG-WARN][7] ([i915#2411] / [i915#402])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/fi-tgl-y/igt@gem_exec_suspend@basic-s3.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/fi-tgl-y/igt@gem_exec_suspend@basic-s3.html

  * igt@gem_huc_copy@huc-copy:
    - fi-byt-j1900:       NOTRUN -> [SKIP][8] ([fdo#109271]) +27 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/fi-byt-j1900/igt@gem_huc_copy@huc-copy.html

  * igt@kms_chamelium@hdmi-crc-fast:
    - fi-byt-j1900:       NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/fi-byt-j1900/igt@kms_chamelium@hdmi-crc-fast.html

  
#### Possible fixes ####

  * igt@gem_basic@bad-close:
    - fi-tgl-y:           [DMESG-WARN][10] ([i915#402]) -> [PASS][11]
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/fi-tgl-y/igt@gem_basic@bad-close.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/fi-tgl-y/igt@gem_basic@bad-close.html

  * igt@gem_exec_suspend@basic-s0:
    - {fi-cml-drallion}:  [INCOMPLETE][12] ([i915#1614]) -> [PASS][13]
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/fi-cml-drallion/igt@gem_exec_suspend@basic-s0.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/fi-cml-drallion/igt@gem_exec_suspend@basic-s0.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1614]: https://gitlab.freedesktop.org/drm/intel/issues/1614
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
  [i915#2605]: https://gitlab.freedesktop.org/drm/intel/issues/2605
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (45 -> 40)
------------------------------

  Additional (1): fi-byt-j1900 
  Missing    (6): fi-jsl-1 fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_9688 -> Patchwork_19518

  CI-20190529: 20190529
  CI_DRM_9688: 43295c2b7bc37446a480bb5d42b03675baed171a @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5974: a85398dcae50930c0e27548cf8c9575ad0bf69d1 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19518: f7ab96d28d4a9215cc9c8ede76fc27dac7f79fef @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

f7ab96d28d4a drm/i915/gen9bc: Handle TGP PCH during suspend/resume

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/index.html

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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gen9bc: Handle TGP PCH during suspend/resume

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 18879 bytes --]

== Series Details ==

Series: drm/i915/gen9bc: Handle TGP PCH during suspend/resume
URL   : https://patchwork.freedesktop.org/series/86346/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9688_full -> Patchwork_19518_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_19518_full:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@gem_ctx_persistence@many-contexts}:
    - shard-tglb:         [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-tglb1/igt@gem_ctx_persistence@many-contexts.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-tglb8/igt@gem_ctx_persistence@many-contexts.html

  
Known issues
------------

  Here are the changes found in Patchwork_19518_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_fair@basic-none@vcs1:
    - shard-iclb:         NOTRUN -> [FAIL][3] ([i915#2842])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-iclb4/igt@gem_exec_fair@basic-none@vcs1.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-tglb:         [PASS][4] -> [FAIL][5] ([i915#2842]) +1 similar issue
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-tglb8/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-tglb2/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-glk:          [PASS][6] -> [FAIL][7] ([i915#2842])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-glk6/igt@gem_exec_fair@basic-throttle@rcs0.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-glk4/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@gem_exec_params@no-vebox:
    - shard-iclb:         NOTRUN -> [SKIP][8] ([fdo#109283])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-iclb1/igt@gem_exec_params@no-vebox.html

  * igt@gen7_exec_parse@basic-allowed:
    - shard-skl:          NOTRUN -> [SKIP][9] ([fdo#109271]) +9 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-skl10/igt@gen7_exec_parse@basic-allowed.html

  * igt@i915_pm_rpm@system-suspend-modeset:
    - shard-kbl:          [PASS][10] -> [INCOMPLETE][11] ([i915#151])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-kbl7/igt@i915_pm_rpm@system-suspend-modeset.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-kbl6/igt@i915_pm_rpm@system-suspend-modeset.html

  * igt@kms_chamelium@hdmi-cmp-planar-formats:
    - shard-glk:          NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +1 similar issue
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-glk7/igt@kms_chamelium@hdmi-cmp-planar-formats.html

  * igt@kms_color@pipe-a-ctm-0-5:
    - shard-skl:          [PASS][13] -> [DMESG-WARN][14] ([i915#1982])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-skl10/igt@kms_color@pipe-a-ctm-0-5.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-skl8/igt@kms_color@pipe-a-ctm-0-5.html

  * igt@kms_color_chamelium@pipe-invalid-ctm-matrix-sizes:
    - shard-skl:          NOTRUN -> [SKIP][15] ([fdo#109271] / [fdo#111827]) +2 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-skl10/igt@kms_color_chamelium@pipe-invalid-ctm-matrix-sizes.html

  * igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen:
    - shard-skl:          [PASS][16] -> [FAIL][17] ([i915#54]) +4 similar issues
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-skl9/igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-skl6/igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen.html

  * igt@kms_cursor_crc@pipe-b-cursor-128x128-onscreen:
    - shard-skl:          NOTRUN -> [FAIL][18] ([i915#54])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-skl7/igt@kms_cursor_crc@pipe-b-cursor-128x128-onscreen.html

  * igt@kms_cursor_crc@pipe-d-cursor-128x42-random:
    - shard-glk:          NOTRUN -> [SKIP][19] ([fdo#109271]) +3 similar issues
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-glk7/igt@kms_cursor_crc@pipe-d-cursor-128x42-random.html

  * igt@kms_cursor_crc@pipe-d-cursor-256x256-sliding:
    - shard-kbl:          NOTRUN -> [SKIP][20] ([fdo#109271]) +4 similar issues
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-kbl7/igt@kms_cursor_crc@pipe-d-cursor-256x256-sliding.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
    - shard-glk:          [PASS][21] -> [FAIL][22] ([i915#72])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-glk9/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-glk6/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
    - shard-tglb:         [PASS][23] -> [FAIL][24] ([i915#2598])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-tglb3/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-tglb5/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html

  * igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1:
    - shard-skl:          [PASS][25] -> [FAIL][26] ([i915#2122]) +2 similar issues
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-skl2/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-skl3/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt:
    - shard-iclb:         NOTRUN -> [SKIP][27] ([fdo#109280]) +1 similar issue
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-kbl:          [PASS][28] -> [DMESG-WARN][29] ([i915#180])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-kbl1/igt@kms_hdr@bpc-switch-suspend.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-kbl4/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
    - shard-skl:          NOTRUN -> [FAIL][30] ([fdo#108145] / [i915#265])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html

  * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
    - shard-skl:          [PASS][31] -> [FAIL][32] ([fdo#108145] / [i915#265])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-skl8/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html

  * igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-a-scaler-with-clipping-clamping:
    - shard-iclb:         [PASS][33] -> [DMESG-WARN][34] ([i915#1226])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-iclb1/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-a-scaler-with-clipping-clamping.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-iclb2/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-a-scaler-with-clipping-clamping.html

  * igt@kms_psr@psr2_basic:
    - shard-iclb:         [PASS][35] -> [SKIP][36] ([fdo#109441]) +4 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-iclb2/igt@kms_psr@psr2_basic.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-iclb6/igt@kms_psr@psr2_basic.html

  
#### Possible fixes ####

  * igt@gem_exec_fair@basic-deadline:
    - shard-kbl:          [FAIL][37] ([i915#2846]) -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-kbl4/igt@gem_exec_fair@basic-deadline.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-kbl6/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
    - shard-glk:          [FAIL][39] ([i915#2842]) -> [PASS][40] +2 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-glk5/igt@gem_exec_fair@basic-none-rrul@rcs0.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-glk5/igt@gem_exec_fair@basic-none-rrul@rcs0.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
    - shard-iclb:         [FAIL][41] ([i915#2842]) -> [PASS][42] +1 similar issue
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-iclb8/igt@gem_exec_fair@basic-none-share@rcs0.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-iclb1/igt@gem_exec_fair@basic-none-share@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs0:
    - shard-kbl:          [FAIL][43] ([i915#2842]) -> [PASS][44] +3 similar issues
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-kbl7/igt@gem_exec_fair@basic-none@vcs0.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-kbl6/igt@gem_exec_fair@basic-none@vcs0.html

  * igt@gem_exec_fair@basic-pace@vcs0:
    - shard-tglb:         [FAIL][45] ([i915#2842]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-tglb1/igt@gem_exec_fair@basic-pace@vcs0.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-tglb8/igt@gem_exec_fair@basic-pace@vcs0.html

  * igt@gem_shrink@reclaim:
    - shard-iclb:         [INCOMPLETE][47] -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-iclb4/igt@gem_shrink@reclaim.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-iclb1/igt@gem_shrink@reclaim.html

  * igt@gem_softpin@noreloc-s3:
    - shard-kbl:          [INCOMPLETE][49] ([i915#2405]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-kbl2/igt@gem_softpin@noreloc-s3.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-kbl7/igt@gem_softpin@noreloc-s3.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-glk:          [DMESG-WARN][51] ([i915#1436] / [i915#716]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-glk7/igt@gen9_exec_parse@allowed-all.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-glk7/igt@gen9_exec_parse@allowed-all.html

  * igt@kms_cursor_crc@pipe-c-cursor-64x21-offscreen:
    - shard-skl:          [FAIL][53] ([i915#54]) -> [PASS][54] +6 similar issues
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-skl4/igt@kms_cursor_crc@pipe-c-cursor-64x21-offscreen.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-skl9/igt@kms_cursor_crc@pipe-c-cursor-64x21-offscreen.html

  * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
    - shard-hsw:          [FAIL][55] ([i915#96]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-hsw1/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-hsw7/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html

  * igt@kms_cursor_legacy@flip-vs-cursor-varying-size:
    - shard-tglb:         [FAIL][57] ([i915#2346]) -> [PASS][58] +1 similar issue
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-tglb5/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-tglb2/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html

  * igt@kms_draw_crc@draw-method-xrgb8888-mmap-wc-ytiled:
    - shard-skl:          [DMESG-WARN][59] ([i915#1982]) -> [PASS][60] +1 similar issue
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-skl4/igt@kms_draw_crc@draw-method-xrgb8888-mmap-wc-ytiled.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-skl2/igt@kms_draw_crc@draw-method-xrgb8888-mmap-wc-ytiled.html

  * igt@kms_flip@flip-vs-suspend@c-hdmi-a1:
    - shard-hsw:          [INCOMPLETE][61] ([i915#2055]) -> [PASS][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-hsw4/igt@kms_flip@flip-vs-suspend@c-hdmi-a1.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-hsw8/igt@kms_flip@flip-vs-suspend@c-hdmi-a1.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
    - shard-skl:          [FAIL][63] ([i915#2122]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-skl8/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-skl10/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          [FAIL][65] ([fdo#108145] / [i915#265]) -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html

  * igt@kms_psr@psr2_cursor_mmap_gtt:
    - shard-iclb:         [SKIP][67] ([fdo#109441]) -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-iclb4/igt@kms_psr@psr2_cursor_mmap_gtt.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_gtt.html

  
#### Warnings ####

  * igt@i915_pm_rc6_residency@rc6-fence:
    - shard-iclb:         [WARN][69] ([i915#1804] / [i915#2684]) -> [WARN][70] ([i915#2684])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-iclb4/igt@i915_pm_rc6_residency@rc6-fence.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-iclb2/igt@i915_pm_rc6_residency@rc6-fence.html

  * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4:
    - shard-iclb:         [SKIP][71] ([i915#2920]) -> [SKIP][72] ([i915#658]) +2 similar issues
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-iclb6/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1:
    - shard-iclb:         [SKIP][73] ([i915#658]) -> [SKIP][74] ([i915#2920]) +2 similar issues
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-iclb1/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html

  * igt@runner@aborted:
    - shard-kbl:          ([FAIL][75], [FAIL][76], [FAIL][77]) ([i915#2295] / [i915#2505]) -> ([FAIL][78], [FAIL][79], [FAIL][80]) ([i915#1814] / [i915#2295])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-kbl6/igt@runner@aborted.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-kbl1/igt@runner@aborted.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-kbl6/igt@runner@aborted.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-kbl4/igt@runner@aborted.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-kbl4/igt@runner@aborted.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/shard-kbl2/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1226]: https://gitlab.freedesktop.org/drm/intel/issues/1226
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804
  [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2055]: https://gitlab.freedesktop.org/drm/intel/issues/2055
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2405]: https://gitlab.freedesktop.org/drm/intel/issues/2405
  [i915#2505]: https://gitlab.freedesktop.org/drm/intel/issues/2505
  [i915#2598]: https://gitlab.freedesktop.org/drm/intel/issues/2598
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
  [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
  [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
  [i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
  [i915#96]: https://gitlab.freedesktop.org/drm/intel/issues/96


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_9688 -> Patchwork_19518

  CI-20190529: 20190529
  CI_DRM_9688: 43295c2b7bc37446a480bb5d42b03675baed171a @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5974: a85398dcae50930c0e27548cf8c9575ad0bf69d1 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19518: f7ab96d28d4a9215cc9c8ede76fc27dac7f79fef @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19518/index.html

[-- Attachment #1.2: Type: text/html, Size: 22467 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915/gen9bc: Handle TGP PCH during suspend/resume

[Ville Syrjälä]

On Wed, Jan 27, 2021 at 03:38:30PM +0530, Tejas Upadhyay wrote:
> For Legacy S3 suspend/resume GEN9 BC needs to enable and
> setup TGP PCH.
> 
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 36 ++++++++++++++++++++++++---------
>  1 file changed, 27 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index a31980f69120..6dcefc3e24ac 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3026,8 +3026,20 @@ static void gen8_irq_reset(struct drm_i915_private *dev_priv)
>  	GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
>  	GEN3_IRQ_RESET(uncore, GEN8_PCU_);
>  
> -	if (HAS_PCH_SPLIT(dev_priv))
> +	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> +		GEN3_IRQ_RESET(uncore, SDE);
> +	else if (HAS_PCH_SPLIT(dev_priv))
>  		ibx_irq_reset(dev_priv);
> +
> +	/* Wa_14010685332:cnp/cmp,tgp,adp */
> +	if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> +	    (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> +	    INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> +		intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> +				 SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
> +		intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> +				 SBCLK_RUN_REFCLK_DIS, 0);
> +	}

Time to refactor instead of copypasta.

>  }
>  
>  static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> @@ -3442,6 +3454,9 @@ static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
>  	ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
>  
>  	spt_hpd_detection_setup(dev_priv);
> +
> +	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> +		icp_hpd_irq_setup(dev_priv);
>  }
>  
>  static u32 ilk_hotplug_enables(struct drm_i915_private *i915,
> @@ -3729,9 +3744,19 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
>  	}
>  }
>  
> +static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> +{
> +	struct intel_uncore *uncore = &dev_priv->uncore;
> +	u32 mask = SDE_GMBUS_ICP;
> +
> +	GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> +}
> +
>  static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
>  {
> -	if (HAS_PCH_SPLIT(dev_priv))
> +	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> +		icp_irq_postinstall(dev_priv);
> +	else if (HAS_PCH_SPLIT(dev_priv))
>  		ibx_irq_postinstall(dev_priv);
>  
>  	gen8_gt_irq_postinstall(&dev_priv->gt);
> @@ -3740,13 +3765,6 @@ static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
>  	gen8_master_intr_enable(dev_priv->uncore.regs);
>  }
>  
> -static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> -{
> -	struct intel_uncore *uncore = &dev_priv->uncore;
> -	u32 mask = SDE_GMBUS_ICP;
> -
> -	GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> -}
>  
>  static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
>  {
> -- 
> 2.30.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH] drm/i915/gen9bc: Handle TGP PCH during suspend/resume

[Surendrakumar Upadhyay, TejaskumarX]

> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: 28 January 2021 04:46
> To: Surendrakumar Upadhyay, TejaskumarX
> <tejaskumarx.surendrakumar.upadhyay@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Pandey, Hariom
> <hariom.pandey@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/gen9bc: Handle TGP PCH during
> suspend/resume
> 
> On Wed, Jan 27, 2021 at 03:38:30PM +0530, Tejas Upadhyay wrote:
> > For Legacy S3 suspend/resume GEN9 BC needs to enable and setup TGP
> > PCH.
> >
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Tejas Upadhyay
> > <tejaskumarx.surendrakumar.upadhyay@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_irq.c | 36
> > ++++++++++++++++++++++++---------
> >  1 file changed, 27 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > b/drivers/gpu/drm/i915/i915_irq.c index a31980f69120..6dcefc3e24ac
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -3026,8 +3026,20 @@ static void gen8_irq_reset(struct
> drm_i915_private *dev_priv)
> >  	GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
> >  	GEN3_IRQ_RESET(uncore, GEN8_PCU_);
> >
> > -	if (HAS_PCH_SPLIT(dev_priv))
> > +	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > +		GEN3_IRQ_RESET(uncore, SDE);
> > +	else if (HAS_PCH_SPLIT(dev_priv))
> >  		ibx_irq_reset(dev_priv);
> > +
> > +	/* Wa_14010685332:cnp/cmp,tgp,adp */
> > +	if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> > +	    (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> > +	    INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> > +		intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > +				 SBCLK_RUN_REFCLK_DIS,
> SBCLK_RUN_REFCLK_DIS);
> > +		intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > +				 SBCLK_RUN_REFCLK_DIS, 0);
> > +	}
> 
> Time to refactor instead of copypasta.
Do you expect below? :

If ((INTEL_PCH_TYPE(dev_priv) == PCH_TGP) {
	intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
				 SBCLK_RUN_REFCLK_DIS,
SBCLK_RUN_REFCLK_DIS);
		intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
				 SBCLK_RUN_REFCLK_DIS, 0);
}
> 
> >  }
> >
> >  static void gen11_display_irq_reset(struct drm_i915_private
> > *dev_priv) @@ -3442,6 +3454,9 @@ static void spt_hpd_irq_setup(struct
> drm_i915_private *dev_priv)
> >  	ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
> >
> >  	spt_hpd_detection_setup(dev_priv);
> > +
> > +	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > +		icp_hpd_irq_setup(dev_priv);
> >  }
> >
> >  static u32 ilk_hotplug_enables(struct drm_i915_private *i915, @@
> > -3729,9 +3744,19 @@ static void gen8_de_irq_postinstall(struct
> drm_i915_private *dev_priv)
> >  	}
> >  }
> >
> > +static void icp_irq_postinstall(struct drm_i915_private *dev_priv) {
> > +	struct intel_uncore *uncore = &dev_priv->uncore;
> > +	u32 mask = SDE_GMBUS_ICP;
> > +
> > +	GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff); }
> > +
> >  static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
> > {
> > -	if (HAS_PCH_SPLIT(dev_priv))
> > +	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > +		icp_irq_postinstall(dev_priv);
> > +	else if (HAS_PCH_SPLIT(dev_priv))
> >  		ibx_irq_postinstall(dev_priv);
> >
> >  	gen8_gt_irq_postinstall(&dev_priv->gt);
> > @@ -3740,13 +3765,6 @@ static void gen8_irq_postinstall(struct
> drm_i915_private *dev_priv)
> >  	gen8_master_intr_enable(dev_priv->uncore.regs);
> >  }
> >
> > -static void icp_irq_postinstall(struct drm_i915_private *dev_priv) -{
> > -	struct intel_uncore *uncore = &dev_priv->uncore;
> > -	u32 mask = SDE_GMBUS_ICP;
> > -
> > -	GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> > -}
> >
> >  static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
> > {
> > --
> > 2.30.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> --
> Ville Syrjälä
> Intel
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Re: [Intel-gfx] [PATCH] drm/i915/gen9bc: Handle TGP PCH during suspend/resume

[Ville Syrjälä]

On Tue, Feb 02, 2021 at 05:52:28AM +0000, Surendrakumar Upadhyay, TejaskumarX wrote:
> 
> 
> > -----Original Message-----
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Sent: 28 January 2021 04:46
> > To: Surendrakumar Upadhyay, TejaskumarX
> > <tejaskumarx.surendrakumar.upadhyay@intel.com>
> > Cc: intel-gfx@lists.freedesktop.org; Pandey, Hariom
> > <hariom.pandey@intel.com>; Roper, Matthew D
> > <matthew.d.roper@intel.com>
> > Subject: Re: [Intel-gfx] [PATCH] drm/i915/gen9bc: Handle TGP PCH during
> > suspend/resume
> > 
> > On Wed, Jan 27, 2021 at 03:38:30PM +0530, Tejas Upadhyay wrote:
> > > For Legacy S3 suspend/resume GEN9 BC needs to enable and setup TGP
> > > PCH.
> > >
> > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > Signed-off-by: Tejas Upadhyay
> > > <tejaskumarx.surendrakumar.upadhyay@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/i915_irq.c | 36
> > > ++++++++++++++++++++++++---------
> > >  1 file changed, 27 insertions(+), 9 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > b/drivers/gpu/drm/i915/i915_irq.c index a31980f69120..6dcefc3e24ac
> > > 100644
> > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > @@ -3026,8 +3026,20 @@ static void gen8_irq_reset(struct
> > drm_i915_private *dev_priv)
> > >  	GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
> > >  	GEN3_IRQ_RESET(uncore, GEN8_PCU_);
> > >
> > > -	if (HAS_PCH_SPLIT(dev_priv))
> > > +	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > > +		GEN3_IRQ_RESET(uncore, SDE);
> > > +	else if (HAS_PCH_SPLIT(dev_priv))
> > >  		ibx_irq_reset(dev_priv);
> > > +
> > > +	/* Wa_14010685332:cnp/cmp,tgp,adp */
> > > +	if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> > > +	    (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> > > +	    INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> > > +		intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > +				 SBCLK_RUN_REFCLK_DIS,
> > SBCLK_RUN_REFCLK_DIS);
> > > +		intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > +				 SBCLK_RUN_REFCLK_DIS, 0);
> > > +	}
> > 
> > Time to refactor instead of copypasta.
> Do you expect below? :
> 
> If ((INTEL_PCH_TYPE(dev_priv) == PCH_TGP) {
> 	intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> 				 SBCLK_RUN_REFCLK_DIS,
> SBCLK_RUN_REFCLK_DIS);
> 		intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> 				 SBCLK_RUN_REFCLK_DIS, 0);
> }

I expect a new function instead of copy pasting this whole thing
into multiple places.

That said even the current code doesn't make any sense to me.
Take for instance this part:
        if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
	                GEN3_IRQ_RESET(uncore, SDE);
What is that PCH type check doing there? What weird PCH
type are we supposed to have that doesn't need this?

Also the Wa_14010685332 part looks a bit odd. Is it
correct that icp doesn't need that, but cnp and tgp
both do somehow? Can we even have cnp on icl+?

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH] drm/i915/gen9bc: Handle TGP PCH during suspend/resume

[Ville Syrjälä]

On Tue, Feb 02, 2021 at 08:31:48AM +0200, Ville Syrjälä wrote:
> On Tue, Feb 02, 2021 at 05:52:28AM +0000, Surendrakumar Upadhyay, TejaskumarX wrote:
> > 
> > 
> > > -----Original Message-----
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Sent: 28 January 2021 04:46
> > > To: Surendrakumar Upadhyay, TejaskumarX
> > > <tejaskumarx.surendrakumar.upadhyay@intel.com>
> > > Cc: intel-gfx@lists.freedesktop.org; Pandey, Hariom
> > > <hariom.pandey@intel.com>; Roper, Matthew D
> > > <matthew.d.roper@intel.com>
> > > Subject: Re: [Intel-gfx] [PATCH] drm/i915/gen9bc: Handle TGP PCH during
> > > suspend/resume
> > > 
> > > On Wed, Jan 27, 2021 at 03:38:30PM +0530, Tejas Upadhyay wrote:
> > > > For Legacy S3 suspend/resume GEN9 BC needs to enable and setup TGP
> > > > PCH.
> > > >
> > > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > > Signed-off-by: Tejas Upadhyay
> > > > <tejaskumarx.surendrakumar.upadhyay@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/i915_irq.c | 36
> > > > ++++++++++++++++++++++++---------
> > > >  1 file changed, 27 insertions(+), 9 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > > b/drivers/gpu/drm/i915/i915_irq.c index a31980f69120..6dcefc3e24ac
> > > > 100644
> > > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > > @@ -3026,8 +3026,20 @@ static void gen8_irq_reset(struct
> > > drm_i915_private *dev_priv)
> > > >  	GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
> > > >  	GEN3_IRQ_RESET(uncore, GEN8_PCU_);
> > > >
> > > > -	if (HAS_PCH_SPLIT(dev_priv))
> > > > +	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > > > +		GEN3_IRQ_RESET(uncore, SDE);
> > > > +	else if (HAS_PCH_SPLIT(dev_priv))
> > > >  		ibx_irq_reset(dev_priv);
> > > > +
> > > > +	/* Wa_14010685332:cnp/cmp,tgp,adp */
> > > > +	if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> > > > +	    (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> > > > +	    INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> > > > +		intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > > +				 SBCLK_RUN_REFCLK_DIS,
> > > SBCLK_RUN_REFCLK_DIS);
> > > > +		intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > > +				 SBCLK_RUN_REFCLK_DIS, 0);
> > > > +	}
> > > 
> > > Time to refactor instead of copypasta.
> > Do you expect below? :
> > 
> > If ((INTEL_PCH_TYPE(dev_priv) == PCH_TGP) {
> > 	intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > 				 SBCLK_RUN_REFCLK_DIS,
> > SBCLK_RUN_REFCLK_DIS);
> > 		intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > 				 SBCLK_RUN_REFCLK_DIS, 0);
> > }
> 
> I expect a new function instead of copy pasting this whole thing
> into multiple places.
> 
> That said even the current code doesn't make any sense to me.
> Take for instance this part:
>         if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> 	                GEN3_IRQ_RESET(uncore, SDE);
> What is that PCH type check doing there? What weird PCH
> type are we supposed to have that doesn't need this?
> 
> Also the Wa_14010685332 part looks a bit odd. Is it
> correct that icp doesn't need that, but cnp and tgp
> both do somehow? Can we even have cnp on icl+?

Hmm. Looking at it a bit more, that w/a seems to have something to do
with suspend/resume, so seems rather misplaced in irq_reset(). Should
probably just move the whole thing into a more appropriate place.

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH] drm/i915/gen9bc: Handle TGP PCH during suspend/resume

[Surendrakumar Upadhyay, TejaskumarX]

> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: 02 February 2021 12:42
> To: Surendrakumar Upadhyay, TejaskumarX
> <tejaskumarx.surendrakumar.upadhyay@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Pandey, Hariom
> <hariom.pandey@intel.com>
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/gen9bc: Handle TGP PCH during
> suspend/resume
> 
> On Tue, Feb 02, 2021 at 08:31:48AM +0200, Ville Syrjälä wrote:
> > On Tue, Feb 02, 2021 at 05:52:28AM +0000, Surendrakumar Upadhyay,
> TejaskumarX wrote:
> > >
> > >
> > > > -----Original Message-----
> > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > Sent: 28 January 2021 04:46
> > > > To: Surendrakumar Upadhyay, TejaskumarX
> > > > <tejaskumarx.surendrakumar.upadhyay@intel.com>
> > > > Cc: intel-gfx@lists.freedesktop.org; Pandey, Hariom
> > > > <hariom.pandey@intel.com>; Roper, Matthew D
> > > > <matthew.d.roper@intel.com>
> > > > Subject: Re: [Intel-gfx] [PATCH] drm/i915/gen9bc: Handle TGP PCH
> > > > during suspend/resume
> > > >
> > > > On Wed, Jan 27, 2021 at 03:38:30PM +0530, Tejas Upadhyay wrote:
> > > > > For Legacy S3 suspend/resume GEN9 BC needs to enable and setup
> > > > > TGP PCH.
> > > > >
> > > > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > > > Signed-off-by: Tejas Upadhyay
> > > > > <tejaskumarx.surendrakumar.upadhyay@intel.com>
> > > > > ---
> > > > >  drivers/gpu/drm/i915/i915_irq.c | 36
> > > > > ++++++++++++++++++++++++---------
> > > > >  1 file changed, 27 insertions(+), 9 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > > > b/drivers/gpu/drm/i915/i915_irq.c index
> > > > > a31980f69120..6dcefc3e24ac
> > > > > 100644
> > > > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > > > @@ -3026,8 +3026,20 @@ static void gen8_irq_reset(struct
> > > > drm_i915_private *dev_priv)
> > > > >  	GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
> > > > >  	GEN3_IRQ_RESET(uncore, GEN8_PCU_);
> > > > >
> > > > > -	if (HAS_PCH_SPLIT(dev_priv))
> > > > > +	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > > > > +		GEN3_IRQ_RESET(uncore, SDE);
> > > > > +	else if (HAS_PCH_SPLIT(dev_priv))
> > > > >  		ibx_irq_reset(dev_priv);
> > > > > +
> > > > > +	/* Wa_14010685332:cnp/cmp,tgp,adp */
> > > > > +	if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> > > > > +	    (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> > > > > +	    INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> > > > > +		intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > > > +				 SBCLK_RUN_REFCLK_DIS,
> > > > SBCLK_RUN_REFCLK_DIS);
> > > > > +		intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > > > +				 SBCLK_RUN_REFCLK_DIS, 0);
> > > > > +	}
> > > >
> > > > Time to refactor instead of copypasta.
> > > Do you expect below? :
> > >
> > > If ((INTEL_PCH_TYPE(dev_priv) == PCH_TGP) {
> > > 	intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > 				 SBCLK_RUN_REFCLK_DIS,
> > > SBCLK_RUN_REFCLK_DIS);
> > > 		intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > 				 SBCLK_RUN_REFCLK_DIS, 0);
> > > }
> >
> > I expect a new function instead of copy pasting this whole thing into
> > multiple places.
> >
> > That said even the current code doesn't make any sense to me.
> > Take for instance this part:
> >         if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > 	                GEN3_IRQ_RESET(uncore, SDE); What is that PCH type
> > check doing there? What weird PCH type are we supposed to have that
> > doesn't need this?
> >
> > Also the Wa_14010685332 part looks a bit odd. Is it correct that icp
> > doesn't need that, but cnp and tgp both do somehow? Can we even have
> > cnp on icl+?
> 
> Hmm. Looking at it a bit more, that w/a seems to have something to do with
> suspend/resume, so seems rather misplaced in irq_reset(). Should probably
> just move the whole thing into a more appropriate place.
> 
GEN11+ needs these checks in irq_reset(). Please check irq_reset for GEN11. Now that customer like dell are expecting TGP PCH with gen9bc platforms, I have done similar PCH checking in irq_reset() for gen9bc. You mean these checks are at wrong place for GEN11 irq_reset() as well? Or you want one function doing these checks and calling it everywhere!
> --
> Ville Syrjälä
> Intel
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Re: [Intel-gfx] [PATCH] drm/i915/gen9bc: Handle TGP PCH during suspend/resume

[Imre Deak]

On Tue, Feb 02, 2021 at 08:59:20AM +0000, Surendrakumar Upadhyay, TejaskumarX wrote:
> 
> 
> > -----Original Message-----
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Sent: 02 February 2021 12:42
> > To: Surendrakumar Upadhyay, TejaskumarX
> > <tejaskumarx.surendrakumar.upadhyay@intel.com>
> > Cc: intel-gfx@lists.freedesktop.org; Pandey, Hariom
> > <hariom.pandey@intel.com>
> > Subject: Re: [Intel-gfx] [PATCH] drm/i915/gen9bc: Handle TGP PCH during
> > suspend/resume
> > 
> > On Tue, Feb 02, 2021 at 08:31:48AM +0200, Ville Syrjälä wrote:
> > > On Tue, Feb 02, 2021 at 05:52:28AM +0000, Surendrakumar Upadhyay,
> > TejaskumarX wrote:
> > > >
> > > >
> > > > > -----Original Message-----
> > > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > > Sent: 28 January 2021 04:46
> > > > > To: Surendrakumar Upadhyay, TejaskumarX
> > > > > <tejaskumarx.surendrakumar.upadhyay@intel.com>
> > > > > Cc: intel-gfx@lists.freedesktop.org; Pandey, Hariom
> > > > > <hariom.pandey@intel.com>; Roper, Matthew D
> > > > > <matthew.d.roper@intel.com>
> > > > > Subject: Re: [Intel-gfx] [PATCH] drm/i915/gen9bc: Handle TGP PCH
> > > > > during suspend/resume
> > > > >
> > > > > On Wed, Jan 27, 2021 at 03:38:30PM +0530, Tejas Upadhyay wrote:
> > > > > > For Legacy S3 suspend/resume GEN9 BC needs to enable and setup
> > > > > > TGP PCH.
> > > > > >
> > > > > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > > > > Signed-off-by: Tejas Upadhyay
> > > > > > <tejaskumarx.surendrakumar.upadhyay@intel.com>
> > > > > > ---
> > > > > >  drivers/gpu/drm/i915/i915_irq.c | 36
> > > > > > ++++++++++++++++++++++++---------
> > > > > >  1 file changed, 27 insertions(+), 9 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > > > > b/drivers/gpu/drm/i915/i915_irq.c index
> > > > > > a31980f69120..6dcefc3e24ac
> > > > > > 100644
> > > > > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > > > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > > > > @@ -3026,8 +3026,20 @@ static void gen8_irq_reset(struct drm_i915_private *dev_priv)
> > > > > >  	GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
> > > > > >  	GEN3_IRQ_RESET(uncore, GEN8_PCU_);
> > > > > >
> > > > > > -	if (HAS_PCH_SPLIT(dev_priv))
> > > > > > +	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > > > > > +		GEN3_IRQ_RESET(uncore, SDE);
> > > > > > +	else if (HAS_PCH_SPLIT(dev_priv))
> > > > > >  		ibx_irq_reset(dev_priv);
> > > > > > +
> > > > > > +	/* Wa_14010685332:cnp/cmp,tgp,adp */
> > > > > > +	if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> > > > > > +	    (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> > > > > > +	    INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> > > > > > +		intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > > > > +				 SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
> > > > > > +		intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > > > > +				 SBCLK_RUN_REFCLK_DIS, 0);
> > > > > > +	}
> > > > >
> > > > > Time to refactor instead of copypasta.
> > > > Do you expect below? :
> > > >
> > > > If ((INTEL_PCH_TYPE(dev_priv) == PCH_TGP) {
> > > > 	intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > > 				 SBCLK_RUN_REFCLK_DIS,
> > > > SBCLK_RUN_REFCLK_DIS);
> > > > 		intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > > 				 SBCLK_RUN_REFCLK_DIS, 0);
> > > > }
> > >
> > > I expect a new function instead of copy pasting this whole thing into
> > > multiple places.
> > >
> > > That said even the current code doesn't make any sense to me.
> > > Take for instance this part:
> > >         if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > > 	                GEN3_IRQ_RESET(uncore, SDE); What is that PCH type
> > > check doing there? What weird PCH type are we supposed to have that
> > > doesn't need this?
> > >
> > > Also the Wa_14010685332 part looks a bit odd. Is it correct that icp
> > > doesn't need that, but cnp and tgp both do somehow? Can we even have
> > > cnp on icl+?
> > 
> > Hmm. Looking at it a bit more, that w/a seems to have something to do with
> > suspend/resume, so seems rather misplaced in irq_reset(). Should probably
> > just move the whole thing into a more appropriate place.
> > 
> GEN11+ needs these checks in irq_reset(). Please check irq_reset for
> GEN11. Now that customer like dell are expecting TGP PCH with gen9bc
> platforms, I have done similar PCH checking in irq_reset() for gen9bc.
> You mean these checks are at wrong place for GEN11 irq_reset() as
> well? Or you want one function doing these checks and calling it
> everywhere!

BSpec says about this WA for both ICL and TGL:
"""
Display driver should set and clear register offset 0xC2000 bit #7 as
last step in programming south display registers in preparation for
entering S0ix state, or set 0xC2000 bit #7 on S0ix entry and clear it on
S0ix exit.

"""

This means to me the WA is only relevant for S0ix and we can implement
it by setting/clearing 0xC2000 bit #7 right before entering/right after
exiting S0ix. This is done atm on PCH_ICP..PCH_MCC in
intel_display_power_suspend_late()/intel_display_power_resume_early(),
so I'd move the WA for all platforms there.

I assume the current code in irq_reset() was the first alternative to
implement the WA, but it wasn't enough. Not sure why, maybe there is a
south display register access after irq_reset() during suspend. Adding
Anshuman for an idea on that.

--Imre
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Re: [Intel-gfx] [PATCH] drm/i915/gen9bc: Handle TGP PCH during suspend/resume

[Lyude Paul]

..snip.. (comments down below)

On Tue, 2021-02-02 at 18:14 +0200, Imre Deak wrote:
> 
> BSpec says about this WA for both ICL and TGL:
> """
> Display driver should set and clear register offset 0xC2000 bit #7 as
> last step in programming south display registers in preparation for
> entering S0ix state, or set 0xC2000 bit #7 on S0ix entry and clear it on
> S0ix exit.
> 
> """
> 
> This means to me the WA is only relevant for S0ix and we can implement
> it by setting/clearing 0xC2000 bit #7 right before entering/right after
> exiting S0ix. This is done atm on PCH_ICP..PCH_MCC in
> intel_display_power_suspend_late()/intel_display_power_resume_early(),
> so I'd move the WA for all platforms there.
> 
> I assume the current code in irq_reset() was the first alternative to
> implement the WA, but it wasn't enough. Not sure why, maybe there is a
> south display register access after irq_reset() during suspend. Adding
> Anshuman for an idea on that.
> 

Poking Anshuman here, is there any update on this? I'm looking to push these
patches forward as some of Red Hat's hardware partners are very eager for this
to get upstream asap as we're running out of time from our end. If you can
answer this, I can handle respinning this patch as needed.

> --Imre
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 

-- 
Sincerely,
   Lyude Paul (she/her)
   Software Engineer at Red Hat
   
Note: I deal with a lot of emails and have a lot of bugs on my plate. If you've
asked me a question, are waiting for a review/merge on a patch, etc. and I
haven't responded in a while, please feel free to send me another email to check
on my status. I don't bite!

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Re: [Intel-gfx] [PATCH] drm/i915/gen9bc: Handle TGP PCH during suspend/resume

[Gupta, Anshuman]

> -----Original Message-----
> From: Lyude Paul <lyude@redhat.com>
> Sent: Wednesday, February 10, 2021 1:34 AM
> To: Deak, Imre <imre.deak@intel.com>; Surendrakumar Upadhyay, TejaskumarX
> <tejaskumarx.surendrakumar.upadhyay@intel.com>; Gupta, Anshuman
> <anshuman.gupta@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Pandey, Hariom
> <hariom.pandey@intel.com>
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/gen9bc: Handle TGP PCH during
> suspend/resume
> 
> ..snip.. (comments down below)
> 
> On Tue, 2021-02-02 at 18:14 +0200, Imre Deak wrote:
> >
> > BSpec says about this WA for both ICL and TGL:
> > """
> > Display driver should set and clear register offset 0xC2000 bit #7 as
> > last step in programming south display registers in preparation for
> > entering S0ix state, or set 0xC2000 bit #7 on S0ix entry and clear it
> > on S0ix exit.
> >
> > """
> >
> > This means to me the WA is only relevant for S0ix and we can implement
> > it by setting/clearing 0xC2000 bit #7 right before entering/right
> > after exiting S0ix. This is done atm on PCH_ICP..PCH_MCC in
> > intel_display_power_suspend_late()/intel_display_power_resume_early(),
> > so I'd move the WA for all platforms there.
> >
> > I assume the current code in irq_reset() was the first alternative to
> > implement the WA, but it wasn't enough. Not sure why, maybe there is a
> > south display register access after irq_reset() during suspend. Adding
> > Anshuman for an idea on that.
> >
> 
> Poking Anshuman here, is there any update on this? I'm looking to push these
> patches forward as some of Red Hat's hardware partners are very eager for this
> to get upstream asap as we're running out of time from our end. If you can
> answer this, I can handle respinning this patch as needed.
My sincere apology, I had missed this thread.
We have decided to keep the alternative WA i.e  setting/clearing 0xC2000 bit #7 
before entering after exiting s0ix to fix the deeper s0ix power consumption issues on ICL_PCH
families platforms. This alternative WA  was added to B.Spec on our request.
But on TGL_PCH first alternative WA logic i.e  in irq_reset() was working to attain deeper s0ix residencies so
we haven't changed that.

Thanks,
Anshuman Gupta
> 
> > --Imre
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> 
> --
> Sincerely,
>    Lyude Paul (she/her)
>    Software Engineer at Red Hat
> 
> Note: I deal with a lot of emails and have a lot of bugs on my plate. If you've
> asked me a question, are waiting for a review/merge on a patch, etc. and I
> haven't responded in a while, please feel free to send me another email to check
> on my status. I don't bite!

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Re: [Intel-gfx] [PATCH] drm/i915/gen9bc: Handle TGP PCH during suspend/resume

[Imre Deak]

On Wed, Feb 10, 2021 at 06:33:20AM +0200, Gupta, Anshuman wrote:
> > On Tue, 2021-02-02 at 18:14 +0200, Imre Deak wrote:
> > >
> > > BSpec says about this WA for both ICL and TGL:
> > > """
> > > Display driver should set and clear register offset 0xC2000 bit #7 as
> > > last step in programming south display registers in preparation for
> > > entering S0ix state, or set 0xC2000 bit #7 on S0ix entry and clear it
> > > on S0ix exit.
> > >
> > > """
> > >
> > > This means to me the WA is only relevant for S0ix and we can implement
> > > it by setting/clearing 0xC2000 bit #7 right before entering/right
> > > after exiting S0ix. This is done atm on PCH_ICP..PCH_MCC in
> > > intel_display_power_suspend_late()/intel_display_power_resume_early(),
> > > so I'd move the WA for all platforms there.
> > >
> > > I assume the current code in irq_reset() was the first alternative to
> > > implement the WA, but it wasn't enough. Not sure why, maybe there is a
> > > south display register access after irq_reset() during suspend. Adding
> > > Anshuman for an idea on that.
> > >
> > 
> > Poking Anshuman here, is there any update on this? I'm looking to push these
> > patches forward as some of Red Hat's hardware partners are very eager for this
> > to get upstream asap as we're running out of time from our end. If you can
> > answer this, I can handle respinning this patch as needed.
>
> My sincere apology, I had missed this thread.  We have decided to keep
> the alternative WA i.e  setting/clearing 0xC2000 bit #7 before
> entering after exiting s0ix to fix the deeper s0ix power consumption
> issues on ICL_PCH families platforms. This alternative WA  was added
> to B.Spec on our request.  But on TGL_PCH first alternative WA logic
> i.e  in irq_reset() was working to attain deeper s0ix residencies so
> we haven't changed that.

Ok, thanks for the explanation. For now I'd just ask to add a TODO: in
this patch to check if the WA can be applied in the s0ix suspend/resume
handlers as on earlier platforms and whether the WA is also needed for
runtime s/r.

--Imre
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Re: [Intel-gfx] [PATCH] drm/i915/gen9bc: Handle TGP PCH during suspend/resume

[Lyude Paul]

On Wed, 2021-02-10 at 04:33 +0000, Gupta, Anshuman wrote:
> My sincere apology, I had missed this thread.

No problem! Happens all the time to me :)

> We have decided to keep the alternative WA i.e  setting/clearing 0xC2000 bit
> #7 
> before entering after exiting s0ix to fix the deeper s0ix power consumption
> issues on ICL_PCH
> families platforms. This alternative WA  was added to B.Spec on our request.
> But on TGL_PCH first alternative WA logic i.e  in irq_reset() was working to
> attain deeper s0ix residencies so
> we haven't changed that.

Awesome, thanks for the info!

-- 
Sincerely,
   Lyude Paul (she/her)
   Software Engineer at Red Hat
   
Note: I deal with a lot of emails and have a lot of bugs on my plate. If you've
asked me a question, are waiting for a review/merge on a patch, etc. and I
haven't responded in a while, please feel free to send me another email to check
on my status. I don't bite!

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx