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From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 09/18] drm/i915/display13: Handle new location of outputs D and E
Date: Thu, 28 Jan 2021 11:24:04 -0800	[thread overview]
Message-ID: <20210128192413.1715802-10-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20210128192413.1715802-1-matthew.d.roper@intel.com>

The DDI naming template for Display12 went A-C, TC1-TC6.  With
Display13, that naming scheme for DDI's has now changed to A-E, TC1-TC4.

The Display13 design keeps the register offsets and bitfields relating
to the TC outputs in the same location they were on Display12.  The new
"D" and "E" outputs now take the locations that were previously used by
Display12's TC5 and TC6 outputs, or what we would have considered to be
outputs "H" and "I" under the legacy lettering scheme.

For the most part everything will just work as long as we initialize the
output with the proper 'enum port' value.  However we do need to take
care to pick the correct AUX channel when parsing the VBT (e.g., a
reference to 'AUX D' is actually asking us to use the 8th aux channel,
not the fourth).  We should also make sure that our encoders and aux
channels are named appropriately so that it's easier to correlate driver
debug messages with the bspec instructions.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c    |  8 ++++++--
 drivers/gpu/drm/i915/display/intel_ddi.c     |  8 +++++++-
 drivers/gpu/drm/i915/display/intel_display.c |  6 +++++-
 drivers/gpu/drm/i915/display/intel_display.h |  8 ++++++++
 drivers/gpu/drm/i915/display/intel_dp_aux.c  | 14 +++++++++-----
 5 files changed, 35 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 04337ac6f8c4..b9e00fc3715d 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2716,7 +2716,9 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv,
 			aux_ch = AUX_CH_C;
 		break;
 	case DP_AUX_D:
-		if (IS_ALDERLAKE_S(dev_priv))
+		if (HAS_DISPLAY13(dev_priv))
+			aux_ch = AUX_CH_D_D13;
+		else if (IS_ALDERLAKE_S(dev_priv))
 			aux_ch = AUX_CH_USBC3;
 		else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
 			aux_ch = AUX_CH_USBC2;
@@ -2724,7 +2726,9 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv,
 			aux_ch = AUX_CH_D;
 		break;
 	case DP_AUX_E:
-		if (IS_ALDERLAKE_S(dev_priv))
+		if (HAS_DISPLAY13(dev_priv))
+			aux_ch = AUX_CH_E_D13;
+		else if (IS_ALDERLAKE_S(dev_priv))
 			aux_ch = AUX_CH_USBC4;
 		else
 			aux_ch = AUX_CH_E;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 9506b8048530..68e58e94f2a5 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -5520,7 +5520,13 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 
 	encoder = &dig_port->base;
 
-	if (INTEL_GEN(dev_priv) >= 12) {
+	if (HAS_DISPLAY13(dev_priv) && port >= PORT_D_D13) {
+		drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
+				 DRM_MODE_ENCODER_TMDS,
+				 "DDI %c/PHY %c",
+				 port_name(port - PORT_D_D13 + PORT_D),
+				 phy_name(phy));
+	} else if (INTEL_GEN(dev_priv) >= 12) {
 		enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
 
 		drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f56237aaa7b5..4dc4b1be0809 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5699,7 +5699,11 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
 
 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
 {
-	if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1)
+	if (HAS_DISPLAY13(i915) && port >= PORT_D_D13)
+		return PHY_D + port - PORT_D_D13;
+	else if (HAS_DISPLAY13(i915) && port >= PORT_TC1)
+		return PHY_F + port - PORT_TC1;
+	else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1)
 		return PHY_B + port - PORT_TC1;
 	else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
 		return PHY_C + port - PORT_TC1;
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 64ffa34544a7..b102ec0d5390 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -216,6 +216,10 @@ enum port {
 	PORT_TC5,
 	PORT_TC6,
 
+	/* Display13 repositions D/E offsets and bitfields */
+	PORT_D_D13 = PORT_TC5,
+	PORT_E_D13,
+
 	I915_MAX_PORTS
 };
 
@@ -299,6 +303,10 @@ enum aux_ch {
 	AUX_CH_USBC4,
 	AUX_CH_USBC5,
 	AUX_CH_USBC6,
+
+	/* Display13 repositions D/E offsets and bitfields */
+	AUX_CH_D_D13 = AUX_CH_USBC5,
+	AUX_CH_E_D13,
 };
 
 #define aux_ch_name(a) ((a) + 'A')
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index eaebf123310a..355680ace6f9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -600,8 +600,8 @@ static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp)
 	case AUX_CH_USBC2:
 	case AUX_CH_USBC3:
 	case AUX_CH_USBC4:
-	case AUX_CH_USBC5:
-	case AUX_CH_USBC6:
+	case AUX_CH_USBC5:  /* aka AUX_CH_D_D13 */
+	case AUX_CH_USBC6:  /* aka AUX_CH_E_D13 */
 		return DP_AUX_CH_CTL(aux_ch);
 	default:
 		MISSING_CASE(aux_ch);
@@ -623,8 +623,8 @@ static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index)
 	case AUX_CH_USBC2:
 	case AUX_CH_USBC3:
 	case AUX_CH_USBC4:
-	case AUX_CH_USBC5:
-	case AUX_CH_USBC6:
+	case AUX_CH_USBC5:  /* aka AUX_CH_D_D13 */
+	case AUX_CH_USBC6:  /* aka AUX_CH_E_D13 */
 		return DP_AUX_CH_DATA(aux_ch, index);
 	default:
 		MISSING_CASE(aux_ch);
@@ -678,7 +678,11 @@ void intel_dp_aux_init(struct intel_dp *intel_dp)
 	drm_dp_aux_init(&intel_dp->aux);
 
 	/* Failure to allocate our preferred name is not critical */
-	if (INTEL_GEN(dev_priv) >= 12 && aux_ch >= AUX_CH_USBC1)
+	if (HAS_DISPLAY13(dev_priv) && aux_ch >= AUX_CH_D_D13)
+		intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/%s",
+					       aux_ch_name(aux_ch - AUX_CH_D_D13 + AUX_CH_D),
+					       encoder->base.name);
+	else if (INTEL_GEN(dev_priv) >= 12 && aux_ch >= AUX_CH_USBC1)
 		intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX USBC%c/%s",
 					       aux_ch - AUX_CH_USBC1 + '1',
 					       encoder->base.name);
-- 
2.25.4

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  parent reply	other threads:[~2021-01-28 19:25 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-28 19:23 [Intel-gfx] [PATCH 00/18] Preliminary Display13 support Matt Roper
2021-01-28 19:23 ` [Intel-gfx] [PATCH 01/18] drm/i915/display13: add Display13 characteristics Matt Roper
2021-02-11  0:03   ` Lucas De Marchi
2021-01-28 19:23 ` [Intel-gfx] [PATCH 02/18] drm/i915/display13: Handle proper AUX interrupt bits Matt Roper
2021-02-11  0:10   ` Lucas De Marchi
2021-01-28 19:23 ` [Intel-gfx] [PATCH 03/18] drm/i915/display13: Enhanced pipe underrun reporting Matt Roper
2021-02-11  0:31   ` Lucas De Marchi
2021-02-11 12:25   ` Ville Syrjälä
2021-01-28 19:23 ` [Intel-gfx] [PATCH 04/18] drm/i915/display13: Define plane capabilities Matt Roper
2021-02-11  1:05   ` Lucas De Marchi
2021-01-28 19:24 ` [Intel-gfx] [PATCH 05/18] drm/i915/display13: Support 128k plane stride Matt Roper
2021-02-11  1:17   ` Lucas De Marchi
2021-01-28 19:24 ` [Intel-gfx] [PATCH 06/18] drm/i915/display13: Only enable legacy gamma for now Matt Roper
2021-02-11  1:19   ` Lucas De Marchi
2021-01-28 19:24 ` [Intel-gfx] [PATCH 07/18] drm/i915/display13: Add Display13 power wells Matt Roper
2021-02-11  1:33   ` Lucas De Marchi
2021-01-28 19:24 ` [Intel-gfx] [PATCH 08/18] drm/i915/display13: Handle LPSP for Display 13 Matt Roper
2021-02-11  1:36   ` Lucas De Marchi
2021-01-28 19:24 ` Matt Roper [this message]
2021-01-28 19:24 ` [Intel-gfx] [PATCH 10/18] drm/i915/display13: Increase maximum watermark lines to 255 Matt Roper
2021-01-28 19:24 ` [Intel-gfx] [PATCH 11/18] drm/i915/display13: Required bandwidth increases when VT-d is active Matt Roper
2021-01-28 19:24 ` [Intel-gfx] [PATCH 12/18] drm/i915/display13: Add Wa_14011503030:d13 Matt Roper
2021-01-28 19:24 ` [Intel-gfx] [PATCH 13/18] drm/i915/display/dsc: Refactor intel_dp_dsc_compute_bpp Matt Roper
2021-01-28 19:24 ` [Intel-gfx] [PATCH 14/18] drm/i915/display13: Support DP1.4 compression BPPs Matt Roper
2021-01-28 19:24 ` [Intel-gfx] [PATCH 15/18] drm/i915/display13: Get slice height before computing rc params Matt Roper
2021-01-28 19:24 ` [Intel-gfx] [PATCH 16/18] drm/i915/display13: Calculate VDSC RC parameters Matt Roper
2021-01-28 19:24 ` [Intel-gfx] [PATCH 17/18] drm/i915/display13: Add rc_qp_table for rcparams calculation Matt Roper
2021-01-29 11:12   ` Jani Nikula
2021-01-29 11:15     ` Chris Wilson
2021-01-29 12:01       ` Jani Nikula
2021-02-10 22:24         ` Lucas De Marchi
2021-01-28 19:24 ` [Intel-gfx] [PATCH 18/18] drm/i915/display13: Enabling dithering after the CC1 pipe Matt Roper
2021-02-11 12:29   ` Ville Syrjälä
2021-02-19  3:22     ` Mario Kleiner
2021-02-19  5:44       ` Mario Kleiner
2021-03-01  4:57         ` Varide, Nischal
2021-03-01  5:43           ` Ilia Mirkin
2021-01-28 19:25 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Preliminary Display13 support Patchwork

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