From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Matt Roper <matthew.d.roper@intel.com>
Cc: intel-gfx@lists.freedesktop.org,
Lucas De Marchi <lucas.demarchi@intel.com>
Subject: Re: [Intel-gfx] [PATCH 03/18] drm/i915/display13: Enhanced pipe underrun reporting
Date: Thu, 11 Feb 2021 14:25:47 +0200 [thread overview]
Message-ID: <YCUiSx3qpFE9uGhl@intel.com> (raw)
In-Reply-To: <20210128192413.1715802-4-matthew.d.roper@intel.com>
On Thu, Jan 28, 2021 at 11:23:58AM -0800, Matt Roper wrote:
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 10fd0e3af2d4..a57593f7d7b1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6039,14 +6039,18 @@ enum {
> #define PIPECONF_DITHER_TYPE_ST2 (2 << 2)
> #define PIPECONF_DITHER_TYPE_TEMP (3 << 2)
> #define _PIPEASTAT 0x70024
> +#define _PIPEASTAT_ICL 0x70058
PIPESTAT is a gmch thing. This is not that for sure.
> #define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31)
> #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30)
> #define PIPE_CRC_ERROR_ENABLE (1UL << 29)
> #define PIPE_CRC_DONE_ENABLE (1UL << 28)
> +#define PIPE_STAT_SOFT_UNDERRUN_D13 (1UL << 28)
> #define PERF_COUNTER2_INTERRUPT_EN (1UL << 27)
> #define PIPE_GMBUS_EVENT_ENABLE (1UL << 27)
> +#define PIPE_STAT_HARD_UNDERRUN_D13 (1UL << 27)
> #define PLANE_FLIP_DONE_INT_EN_VLV (1UL << 26)
> #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL << 26)
> +#define PIPE_STAT_PORT_UNDERRUN_D13 (1UL << 26)
> #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL << 25)
> #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL << 24)
> #define PIPE_DPST_EVENT_ENABLE (1UL << 23)
> @@ -6111,6 +6115,7 @@ enum {
> #define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
> #define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL)
> #define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT)
> +#define ICL_PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT_ICL)
>
> #define _PIPEAGCMAX 0x70010
> #define _PIPEBGCMAX 0x71010
> @@ -7789,6 +7794,8 @@ enum {
> #define GEN8_PIPE_FIFO_UNDERRUN (1 << 31)
> #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29)
> #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28)
> +#define D13_PIPE_SOFT_UNDERRUN (1 << 22)
> +#define D13_PIPE_HARD_UNDERRUN (1 << 21)
> #define GEN8_PIPE_CURSOR_FAULT (1 << 10)
> #define GEN8_PIPE_SPRITE_FAULT (1 << 9)
> #define GEN8_PIPE_PRIMARY_FAULT (1 << 8)
> --
> 2.25.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
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next prev parent reply other threads:[~2021-02-11 12:25 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-28 19:23 [Intel-gfx] [PATCH 00/18] Preliminary Display13 support Matt Roper
2021-01-28 19:23 ` [Intel-gfx] [PATCH 01/18] drm/i915/display13: add Display13 characteristics Matt Roper
2021-02-11 0:03 ` Lucas De Marchi
2021-01-28 19:23 ` [Intel-gfx] [PATCH 02/18] drm/i915/display13: Handle proper AUX interrupt bits Matt Roper
2021-02-11 0:10 ` Lucas De Marchi
2021-01-28 19:23 ` [Intel-gfx] [PATCH 03/18] drm/i915/display13: Enhanced pipe underrun reporting Matt Roper
2021-02-11 0:31 ` Lucas De Marchi
2021-02-11 12:25 ` Ville Syrjälä [this message]
2021-01-28 19:23 ` [Intel-gfx] [PATCH 04/18] drm/i915/display13: Define plane capabilities Matt Roper
2021-02-11 1:05 ` Lucas De Marchi
2021-01-28 19:24 ` [Intel-gfx] [PATCH 05/18] drm/i915/display13: Support 128k plane stride Matt Roper
2021-02-11 1:17 ` Lucas De Marchi
2021-01-28 19:24 ` [Intel-gfx] [PATCH 06/18] drm/i915/display13: Only enable legacy gamma for now Matt Roper
2021-02-11 1:19 ` Lucas De Marchi
2021-01-28 19:24 ` [Intel-gfx] [PATCH 07/18] drm/i915/display13: Add Display13 power wells Matt Roper
2021-02-11 1:33 ` Lucas De Marchi
2021-01-28 19:24 ` [Intel-gfx] [PATCH 08/18] drm/i915/display13: Handle LPSP for Display 13 Matt Roper
2021-02-11 1:36 ` Lucas De Marchi
2021-01-28 19:24 ` [Intel-gfx] [PATCH 09/18] drm/i915/display13: Handle new location of outputs D and E Matt Roper
2021-01-28 19:24 ` [Intel-gfx] [PATCH 10/18] drm/i915/display13: Increase maximum watermark lines to 255 Matt Roper
2021-01-28 19:24 ` [Intel-gfx] [PATCH 11/18] drm/i915/display13: Required bandwidth increases when VT-d is active Matt Roper
2021-01-28 19:24 ` [Intel-gfx] [PATCH 12/18] drm/i915/display13: Add Wa_14011503030:d13 Matt Roper
2021-01-28 19:24 ` [Intel-gfx] [PATCH 13/18] drm/i915/display/dsc: Refactor intel_dp_dsc_compute_bpp Matt Roper
2021-01-28 19:24 ` [Intel-gfx] [PATCH 14/18] drm/i915/display13: Support DP1.4 compression BPPs Matt Roper
2021-01-28 19:24 ` [Intel-gfx] [PATCH 15/18] drm/i915/display13: Get slice height before computing rc params Matt Roper
2021-01-28 19:24 ` [Intel-gfx] [PATCH 16/18] drm/i915/display13: Calculate VDSC RC parameters Matt Roper
2021-01-28 19:24 ` [Intel-gfx] [PATCH 17/18] drm/i915/display13: Add rc_qp_table for rcparams calculation Matt Roper
2021-01-29 11:12 ` Jani Nikula
2021-01-29 11:15 ` Chris Wilson
2021-01-29 12:01 ` Jani Nikula
2021-02-10 22:24 ` Lucas De Marchi
2021-01-28 19:24 ` [Intel-gfx] [PATCH 18/18] drm/i915/display13: Enabling dithering after the CC1 pipe Matt Roper
2021-02-11 12:29 ` Ville Syrjälä
2021-02-19 3:22 ` Mario Kleiner
2021-02-19 5:44 ` Mario Kleiner
2021-03-01 4:57 ` Varide, Nischal
2021-03-01 5:43 ` Ilia Mirkin
2021-01-28 19:25 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Preliminary Display13 support Patchwork
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